Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
2830 |
0 |
0 |
T85 |
10110 |
2 |
0 |
0 |
T86 |
29041 |
5 |
0 |
0 |
T87 |
4148 |
10 |
0 |
0 |
T88 |
11738 |
10 |
0 |
0 |
T89 |
27887 |
3 |
0 |
0 |
T90 |
29822 |
6 |
0 |
0 |
T91 |
7602 |
85 |
0 |
0 |
T101 |
11725 |
157 |
0 |
0 |
T103 |
12207 |
9 |
0 |
0 |
T106 |
27711 |
1 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1599 |
0 |
0 |
T85 |
10110 |
6 |
0 |
0 |
T88 |
11738 |
11 |
0 |
0 |
T111 |
6983 |
12 |
0 |
0 |
T113 |
271285 |
687 |
0 |
0 |
T114 |
10344 |
8 |
0 |
0 |
T127 |
7336 |
4 |
0 |
0 |
T140 |
3978 |
7 |
0 |
0 |
T141 |
4936 |
4 |
0 |
0 |
T142 |
6410 |
17 |
0 |
0 |
T143 |
3933 |
7 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1697 |
0 |
0 |
T85 |
10110 |
7 |
0 |
0 |
T88 |
11738 |
12 |
0 |
0 |
T111 |
6983 |
5 |
0 |
0 |
T113 |
271285 |
658 |
0 |
0 |
T114 |
10344 |
9 |
0 |
0 |
T127 |
7336 |
8 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
10 |
0 |
0 |
T142 |
6410 |
46 |
0 |
0 |
T143 |
3933 |
1 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1913 |
0 |
0 |
T85 |
10110 |
30 |
0 |
0 |
T88 |
11738 |
24 |
0 |
0 |
T111 |
6983 |
29 |
0 |
0 |
T113 |
271285 |
667 |
0 |
0 |
T114 |
10344 |
25 |
0 |
0 |
T117 |
10602 |
30 |
0 |
0 |
T127 |
7336 |
8 |
0 |
0 |
T141 |
4936 |
14 |
0 |
0 |
T142 |
6410 |
36 |
0 |
0 |
T143 |
3933 |
12 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6118 |
0 |
0 |
T85 |
10110 |
226 |
0 |
0 |
T88 |
11738 |
139 |
0 |
0 |
T111 |
6983 |
201 |
0 |
0 |
T113 |
271285 |
686 |
0 |
0 |
T114 |
10344 |
9 |
0 |
0 |
T117 |
10602 |
202 |
0 |
0 |
T140 |
3978 |
85 |
0 |
0 |
T141 |
4936 |
10 |
0 |
0 |
T143 |
3933 |
5 |
0 |
0 |
T144 |
13989 |
50 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6301 |
0 |
0 |
T85 |
10110 |
17 |
0 |
0 |
T88 |
11738 |
272 |
0 |
0 |
T111 |
6983 |
107 |
0 |
0 |
T113 |
271285 |
640 |
0 |
0 |
T114 |
10344 |
108 |
0 |
0 |
T127 |
7336 |
159 |
0 |
0 |
T140 |
3978 |
160 |
0 |
0 |
T141 |
4936 |
124 |
0 |
0 |
T142 |
6410 |
2 |
0 |
0 |
T143 |
3933 |
3 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6859 |
0 |
0 |
T85 |
10110 |
10 |
0 |
0 |
T88 |
11738 |
131 |
0 |
0 |
T111 |
6983 |
117 |
0 |
0 |
T113 |
271285 |
691 |
0 |
0 |
T114 |
10344 |
330 |
0 |
0 |
T127 |
7336 |
148 |
0 |
0 |
T140 |
3978 |
125 |
0 |
0 |
T141 |
4936 |
123 |
0 |
0 |
T142 |
6410 |
7 |
0 |
0 |
T143 |
3933 |
5 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6313 |
0 |
0 |
T85 |
10110 |
123 |
0 |
0 |
T88 |
11738 |
131 |
0 |
0 |
T111 |
6983 |
135 |
0 |
0 |
T113 |
271285 |
649 |
0 |
0 |
T114 |
10344 |
160 |
0 |
0 |
T117 |
10602 |
117 |
0 |
0 |
T127 |
7336 |
31 |
0 |
0 |
T140 |
3978 |
8 |
0 |
0 |
T141 |
4936 |
132 |
0 |
0 |
T143 |
3933 |
1 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6277 |
0 |
0 |
T85 |
10110 |
291 |
0 |
0 |
T88 |
11738 |
132 |
0 |
0 |
T111 |
6983 |
9 |
0 |
0 |
T113 |
271285 |
691 |
0 |
0 |
T114 |
10344 |
105 |
0 |
0 |
T117 |
10602 |
138 |
0 |
0 |
T127 |
7336 |
9 |
0 |
0 |
T140 |
3978 |
4 |
0 |
0 |
T142 |
6410 |
24 |
0 |
0 |
T143 |
3933 |
166 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6798 |
0 |
0 |
T85 |
10110 |
137 |
0 |
0 |
T88 |
11738 |
184 |
0 |
0 |
T111 |
6983 |
116 |
0 |
0 |
T113 |
271285 |
717 |
0 |
0 |
T114 |
10344 |
260 |
0 |
0 |
T127 |
7336 |
147 |
0 |
0 |
T140 |
3978 |
5 |
0 |
0 |
T141 |
4936 |
7 |
0 |
0 |
T142 |
6410 |
8 |
0 |
0 |
T143 |
3933 |
111 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6905 |
0 |
0 |
T85 |
10110 |
124 |
0 |
0 |
T88 |
11738 |
111 |
0 |
0 |
T111 |
6983 |
107 |
0 |
0 |
T113 |
271285 |
695 |
0 |
0 |
T114 |
10344 |
131 |
0 |
0 |
T127 |
7336 |
141 |
0 |
0 |
T140 |
3978 |
1 |
0 |
0 |
T141 |
4936 |
124 |
0 |
0 |
T142 |
6410 |
8 |
0 |
0 |
T143 |
3933 |
3 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
6080 |
0 |
0 |
T85 |
10110 |
137 |
0 |
0 |
T88 |
11738 |
16 |
0 |
0 |
T111 |
6983 |
96 |
0 |
0 |
T113 |
271285 |
649 |
0 |
0 |
T114 |
10344 |
103 |
0 |
0 |
T117 |
10602 |
138 |
0 |
0 |
T140 |
3978 |
117 |
0 |
0 |
T141 |
4936 |
128 |
0 |
0 |
T143 |
3933 |
136 |
0 |
0 |
T144 |
13989 |
24 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3644 |
0 |
0 |
T85 |
10110 |
90 |
0 |
0 |
T88 |
11738 |
52 |
0 |
0 |
T111 |
6983 |
30 |
0 |
0 |
T113 |
271285 |
707 |
0 |
0 |
T114 |
10344 |
97 |
0 |
0 |
T127 |
7336 |
27 |
0 |
0 |
T140 |
3978 |
6 |
0 |
0 |
T141 |
4936 |
51 |
0 |
0 |
T142 |
6410 |
9 |
0 |
0 |
T143 |
3933 |
5 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3394 |
0 |
0 |
T85 |
10110 |
53 |
0 |
0 |
T88 |
11738 |
63 |
0 |
0 |
T111 |
6983 |
67 |
0 |
0 |
T113 |
271285 |
617 |
0 |
0 |
T114 |
10344 |
124 |
0 |
0 |
T117 |
10602 |
145 |
0 |
0 |
T127 |
7336 |
51 |
0 |
0 |
T141 |
4936 |
1 |
0 |
0 |
T142 |
6410 |
2 |
0 |
0 |
T143 |
3933 |
48 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3655 |
0 |
0 |
T85 |
10110 |
11 |
0 |
0 |
T88 |
11738 |
62 |
0 |
0 |
T111 |
6983 |
49 |
0 |
0 |
T113 |
271285 |
700 |
0 |
0 |
T114 |
10344 |
89 |
0 |
0 |
T127 |
7336 |
47 |
0 |
0 |
T140 |
3978 |
8 |
0 |
0 |
T141 |
4936 |
49 |
0 |
0 |
T142 |
6410 |
15 |
0 |
0 |
T143 |
3933 |
1 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3701 |
0 |
0 |
T85 |
10110 |
67 |
0 |
0 |
T88 |
11738 |
57 |
0 |
0 |
T111 |
6983 |
39 |
0 |
0 |
T113 |
271285 |
630 |
0 |
0 |
T114 |
10344 |
109 |
0 |
0 |
T127 |
7336 |
45 |
0 |
0 |
T140 |
3978 |
59 |
0 |
0 |
T141 |
4936 |
53 |
0 |
0 |
T142 |
6410 |
27 |
0 |
0 |
T143 |
3933 |
7 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3851 |
0 |
0 |
T85 |
10110 |
100 |
0 |
0 |
T88 |
11738 |
63 |
0 |
0 |
T111 |
6983 |
12 |
0 |
0 |
T113 |
271285 |
658 |
0 |
0 |
T114 |
10344 |
139 |
0 |
0 |
T127 |
7336 |
46 |
0 |
0 |
T140 |
3978 |
65 |
0 |
0 |
T141 |
4936 |
46 |
0 |
0 |
T142 |
6410 |
7 |
0 |
0 |
T143 |
3933 |
1 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3332 |
0 |
0 |
T85 |
10110 |
68 |
0 |
0 |
T88 |
11738 |
8 |
0 |
0 |
T111 |
6983 |
7 |
0 |
0 |
T113 |
271285 |
710 |
0 |
0 |
T114 |
10344 |
48 |
0 |
0 |
T127 |
7336 |
43 |
0 |
0 |
T140 |
3978 |
3 |
0 |
0 |
T141 |
4936 |
8 |
0 |
0 |
T142 |
6410 |
4 |
0 |
0 |
T143 |
3933 |
1 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3377 |
0 |
0 |
T85 |
10110 |
62 |
0 |
0 |
T88 |
11738 |
20 |
0 |
0 |
T111 |
6983 |
88 |
0 |
0 |
T113 |
271285 |
656 |
0 |
0 |
T114 |
10344 |
98 |
0 |
0 |
T127 |
7336 |
14 |
0 |
0 |
T140 |
3978 |
1 |
0 |
0 |
T141 |
4936 |
48 |
0 |
0 |
T142 |
6410 |
30 |
0 |
0 |
T143 |
3933 |
4 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3612 |
0 |
0 |
T85 |
10110 |
70 |
0 |
0 |
T88 |
11738 |
89 |
0 |
0 |
T111 |
6983 |
35 |
0 |
0 |
T113 |
271285 |
683 |
0 |
0 |
T114 |
10344 |
95 |
0 |
0 |
T117 |
10602 |
101 |
0 |
0 |
T140 |
3978 |
50 |
0 |
0 |
T141 |
4936 |
5 |
0 |
0 |
T143 |
3933 |
49 |
0 |
0 |
T144 |
13989 |
26 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3848 |
0 |
0 |
T85 |
10110 |
6 |
0 |
0 |
T88 |
11738 |
107 |
0 |
0 |
T111 |
6983 |
86 |
0 |
0 |
T113 |
271285 |
642 |
0 |
0 |
T114 |
10344 |
115 |
0 |
0 |
T117 |
10602 |
99 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
45 |
0 |
0 |
T142 |
6410 |
10 |
0 |
0 |
T143 |
3933 |
47 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3421 |
0 |
0 |
T85 |
10110 |
106 |
0 |
0 |
T88 |
11738 |
120 |
0 |
0 |
T111 |
6983 |
31 |
0 |
0 |
T113 |
271285 |
665 |
0 |
0 |
T114 |
10344 |
14 |
0 |
0 |
T117 |
10602 |
87 |
0 |
0 |
T141 |
4936 |
50 |
0 |
0 |
T143 |
3933 |
8 |
0 |
0 |
T144 |
13989 |
31 |
0 |
0 |
T145 |
78956 |
125 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3407 |
0 |
0 |
T85 |
10110 |
63 |
0 |
0 |
T88 |
11738 |
74 |
0 |
0 |
T111 |
6983 |
112 |
0 |
0 |
T113 |
271285 |
676 |
0 |
0 |
T114 |
10344 |
115 |
0 |
0 |
T127 |
7336 |
2 |
0 |
0 |
T140 |
3978 |
9 |
0 |
0 |
T141 |
4936 |
8 |
0 |
0 |
T142 |
6410 |
1 |
0 |
0 |
T143 |
3933 |
49 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3382 |
0 |
0 |
T85 |
10110 |
71 |
0 |
0 |
T88 |
11738 |
67 |
0 |
0 |
T111 |
6983 |
11 |
0 |
0 |
T113 |
271285 |
591 |
0 |
0 |
T114 |
10344 |
15 |
0 |
0 |
T127 |
7336 |
36 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
43 |
0 |
0 |
T142 |
6410 |
8 |
0 |
0 |
T143 |
3933 |
6 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3307 |
0 |
0 |
T85 |
10110 |
61 |
0 |
0 |
T88 |
11738 |
23 |
0 |
0 |
T111 |
6983 |
32 |
0 |
0 |
T113 |
271285 |
638 |
0 |
0 |
T114 |
10344 |
105 |
0 |
0 |
T127 |
7336 |
35 |
0 |
0 |
T140 |
3978 |
4 |
0 |
0 |
T141 |
4936 |
5 |
0 |
0 |
T142 |
6410 |
7 |
0 |
0 |
T143 |
3933 |
5 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3731 |
0 |
0 |
T85 |
10110 |
70 |
0 |
0 |
T88 |
11738 |
64 |
0 |
0 |
T111 |
6983 |
88 |
0 |
0 |
T113 |
271285 |
725 |
0 |
0 |
T114 |
10344 |
80 |
0 |
0 |
T127 |
7336 |
89 |
0 |
0 |
T140 |
3978 |
45 |
0 |
0 |
T141 |
4936 |
49 |
0 |
0 |
T142 |
6410 |
15 |
0 |
0 |
T143 |
3933 |
38 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3764 |
0 |
0 |
T85 |
10110 |
63 |
0 |
0 |
T88 |
11738 |
61 |
0 |
0 |
T111 |
6983 |
9 |
0 |
0 |
T113 |
271285 |
674 |
0 |
0 |
T114 |
10344 |
15 |
0 |
0 |
T127 |
7336 |
46 |
0 |
0 |
T140 |
3978 |
5 |
0 |
0 |
T141 |
4936 |
60 |
0 |
0 |
T142 |
6410 |
20 |
0 |
0 |
T143 |
3933 |
7 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3990 |
0 |
0 |
T85 |
10110 |
104 |
0 |
0 |
T88 |
11738 |
97 |
0 |
0 |
T111 |
6983 |
93 |
0 |
0 |
T113 |
271285 |
706 |
0 |
0 |
T114 |
10344 |
158 |
0 |
0 |
T127 |
7336 |
10 |
0 |
0 |
T140 |
3978 |
3 |
0 |
0 |
T141 |
4936 |
6 |
0 |
0 |
T142 |
6410 |
9 |
0 |
0 |
T143 |
3933 |
48 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3760 |
0 |
0 |
T85 |
10110 |
14 |
0 |
0 |
T88 |
11738 |
55 |
0 |
0 |
T111 |
6983 |
49 |
0 |
0 |
T113 |
271285 |
690 |
0 |
0 |
T114 |
10344 |
89 |
0 |
0 |
T127 |
7336 |
5 |
0 |
0 |
T140 |
3978 |
55 |
0 |
0 |
T141 |
4936 |
3 |
0 |
0 |
T142 |
6410 |
9 |
0 |
0 |
T143 |
3933 |
39 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3178 |
0 |
0 |
T85 |
10110 |
15 |
0 |
0 |
T88 |
11738 |
80 |
0 |
0 |
T111 |
6983 |
5 |
0 |
0 |
T113 |
271285 |
624 |
0 |
0 |
T114 |
10344 |
73 |
0 |
0 |
T127 |
7336 |
57 |
0 |
0 |
T140 |
3978 |
9 |
0 |
0 |
T141 |
4936 |
3 |
0 |
0 |
T142 |
6410 |
8 |
0 |
0 |
T143 |
3933 |
58 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3293 |
0 |
0 |
T85 |
10110 |
119 |
0 |
0 |
T88 |
11738 |
92 |
0 |
0 |
T111 |
6983 |
49 |
0 |
0 |
T113 |
271285 |
646 |
0 |
0 |
T114 |
10344 |
97 |
0 |
0 |
T127 |
7336 |
32 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
38 |
0 |
0 |
T142 |
6410 |
11 |
0 |
0 |
T143 |
3933 |
7 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3425 |
0 |
0 |
T85 |
10110 |
54 |
0 |
0 |
T88 |
11738 |
116 |
0 |
0 |
T111 |
6983 |
50 |
0 |
0 |
T113 |
271285 |
663 |
0 |
0 |
T114 |
10344 |
87 |
0 |
0 |
T127 |
7336 |
41 |
0 |
0 |
T140 |
3978 |
5 |
0 |
0 |
T141 |
4936 |
5 |
0 |
0 |
T142 |
6410 |
4 |
0 |
0 |
T143 |
3933 |
5 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3409 |
0 |
0 |
T85 |
10110 |
46 |
0 |
0 |
T88 |
11738 |
68 |
0 |
0 |
T111 |
6983 |
38 |
0 |
0 |
T113 |
271285 |
656 |
0 |
0 |
T114 |
10344 |
78 |
0 |
0 |
T117 |
10602 |
57 |
0 |
0 |
T127 |
7336 |
57 |
0 |
0 |
T141 |
4936 |
2 |
0 |
0 |
T142 |
6410 |
1 |
0 |
0 |
T143 |
3933 |
2 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3599 |
0 |
0 |
T85 |
10110 |
82 |
0 |
0 |
T88 |
11738 |
12 |
0 |
0 |
T111 |
6983 |
39 |
0 |
0 |
T113 |
271285 |
697 |
0 |
0 |
T114 |
10344 |
110 |
0 |
0 |
T117 |
10602 |
13 |
0 |
0 |
T127 |
7336 |
17 |
0 |
0 |
T140 |
3978 |
3 |
0 |
0 |
T141 |
4936 |
34 |
0 |
0 |
T142 |
6410 |
7 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3780 |
0 |
0 |
T85 |
10110 |
112 |
0 |
0 |
T88 |
11738 |
68 |
0 |
0 |
T111 |
6983 |
25 |
0 |
0 |
T113 |
271285 |
686 |
0 |
0 |
T114 |
10344 |
105 |
0 |
0 |
T127 |
7336 |
6 |
0 |
0 |
T140 |
3978 |
36 |
0 |
0 |
T141 |
4936 |
69 |
0 |
0 |
T142 |
6410 |
13 |
0 |
0 |
T143 |
3933 |
2 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3459 |
0 |
0 |
T85 |
10110 |
65 |
0 |
0 |
T88 |
11738 |
55 |
0 |
0 |
T111 |
6983 |
43 |
0 |
0 |
T113 |
271285 |
633 |
0 |
0 |
T114 |
10344 |
48 |
0 |
0 |
T127 |
7336 |
8 |
0 |
0 |
T140 |
3978 |
37 |
0 |
0 |
T141 |
4936 |
3 |
0 |
0 |
T142 |
6410 |
8 |
0 |
0 |
T143 |
3933 |
58 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1648 |
0 |
0 |
T85 |
10110 |
19 |
0 |
0 |
T88 |
11738 |
22 |
0 |
0 |
T111 |
6983 |
11 |
0 |
0 |
T113 |
271285 |
640 |
0 |
0 |
T114 |
10344 |
9 |
0 |
0 |
T127 |
7336 |
7 |
0 |
0 |
T140 |
3978 |
5 |
0 |
0 |
T141 |
4936 |
2 |
0 |
0 |
T142 |
6410 |
8 |
0 |
0 |
T143 |
3933 |
6 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1652 |
0 |
0 |
T85 |
10110 |
19 |
0 |
0 |
T88 |
11738 |
18 |
0 |
0 |
T111 |
6983 |
18 |
0 |
0 |
T113 |
271285 |
612 |
0 |
0 |
T114 |
10344 |
15 |
0 |
0 |
T117 |
10602 |
13 |
0 |
0 |
T127 |
7336 |
10 |
0 |
0 |
T140 |
3978 |
8 |
0 |
0 |
T141 |
4936 |
8 |
0 |
0 |
T142 |
6410 |
5 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1794 |
0 |
0 |
T85 |
10110 |
6 |
0 |
0 |
T88 |
11738 |
15 |
0 |
0 |
T111 |
6983 |
5 |
0 |
0 |
T113 |
271285 |
704 |
0 |
0 |
T114 |
10344 |
1 |
0 |
0 |
T127 |
7336 |
14 |
0 |
0 |
T140 |
3978 |
10 |
0 |
0 |
T141 |
4936 |
3 |
0 |
0 |
T142 |
6410 |
14 |
0 |
0 |
T143 |
3933 |
3 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1721 |
0 |
0 |
T85 |
10110 |
11 |
0 |
0 |
T88 |
11738 |
23 |
0 |
0 |
T111 |
6983 |
7 |
0 |
0 |
T113 |
271285 |
647 |
0 |
0 |
T114 |
10344 |
12 |
0 |
0 |
T117 |
10602 |
19 |
0 |
0 |
T127 |
7336 |
12 |
0 |
0 |
T140 |
3978 |
1 |
0 |
0 |
T141 |
4936 |
6 |
0 |
0 |
T143 |
3933 |
10 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
2040 |
0 |
0 |
T85 |
10110 |
30 |
0 |
0 |
T88 |
11738 |
36 |
0 |
0 |
T111 |
6983 |
19 |
0 |
0 |
T113 |
271285 |
699 |
0 |
0 |
T114 |
10344 |
5 |
0 |
0 |
T127 |
7336 |
1 |
0 |
0 |
T140 |
3978 |
5 |
0 |
0 |
T141 |
4936 |
2 |
0 |
0 |
T142 |
6410 |
6 |
0 |
0 |
T143 |
3933 |
4 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
3603 |
0 |
0 |
T17 |
5041 |
17 |
0 |
0 |
T72 |
233722 |
0 |
0 |
0 |
T122 |
799000 |
0 |
0 |
0 |
T136 |
343456 |
0 |
0 |
0 |
T146 |
0 |
61 |
0 |
0 |
T147 |
0 |
21 |
0 |
0 |
T148 |
0 |
17 |
0 |
0 |
T149 |
0 |
56 |
0 |
0 |
T150 |
0 |
7 |
0 |
0 |
T151 |
0 |
49 |
0 |
0 |
T152 |
0 |
22 |
0 |
0 |
T153 |
0 |
33 |
0 |
0 |
T154 |
0 |
22 |
0 |
0 |
T155 |
71644 |
0 |
0 |
0 |
T156 |
397187 |
0 |
0 |
0 |
T157 |
124216 |
0 |
0 |
0 |
T158 |
270131 |
0 |
0 |
0 |
T159 |
5735 |
0 |
0 |
0 |
T160 |
37797 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1743 |
0 |
0 |
T85 |
10110 |
26 |
0 |
0 |
T88 |
11738 |
20 |
0 |
0 |
T111 |
6983 |
13 |
0 |
0 |
T113 |
271285 |
698 |
0 |
0 |
T114 |
10344 |
10 |
0 |
0 |
T117 |
10602 |
18 |
0 |
0 |
T127 |
7336 |
8 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
9 |
0 |
0 |
T142 |
6410 |
2 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1797 |
0 |
0 |
T85 |
10110 |
24 |
0 |
0 |
T88 |
11738 |
30 |
0 |
0 |
T111 |
6983 |
4 |
0 |
0 |
T113 |
271285 |
692 |
0 |
0 |
T114 |
10344 |
13 |
0 |
0 |
T127 |
7336 |
6 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
6 |
0 |
0 |
T142 |
6410 |
2 |
0 |
0 |
T143 |
3933 |
2 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1610 |
0 |
0 |
T85 |
10110 |
18 |
0 |
0 |
T88 |
11738 |
14 |
0 |
0 |
T111 |
6983 |
9 |
0 |
0 |
T113 |
271285 |
623 |
0 |
0 |
T114 |
10344 |
5 |
0 |
0 |
T127 |
7336 |
6 |
0 |
0 |
T140 |
3978 |
9 |
0 |
0 |
T141 |
4936 |
2 |
0 |
0 |
T142 |
6410 |
12 |
0 |
0 |
T143 |
3933 |
7 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1663 |
0 |
0 |
T85 |
10110 |
18 |
0 |
0 |
T88 |
11738 |
22 |
0 |
0 |
T111 |
6983 |
15 |
0 |
0 |
T113 |
271285 |
736 |
0 |
0 |
T114 |
10344 |
10 |
0 |
0 |
T127 |
7336 |
11 |
0 |
0 |
T140 |
3978 |
5 |
0 |
0 |
T141 |
4936 |
2 |
0 |
0 |
T142 |
6410 |
10 |
0 |
0 |
T143 |
3933 |
3 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1648 |
0 |
0 |
T85 |
10110 |
12 |
0 |
0 |
T88 |
11738 |
18 |
0 |
0 |
T111 |
6983 |
4 |
0 |
0 |
T113 |
271285 |
650 |
0 |
0 |
T114 |
10344 |
15 |
0 |
0 |
T117 |
10602 |
11 |
0 |
0 |
T127 |
7336 |
2 |
0 |
0 |
T140 |
3978 |
5 |
0 |
0 |
T141 |
4936 |
9 |
0 |
0 |
T142 |
6410 |
11 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1570 |
0 |
0 |
T85 |
10110 |
14 |
0 |
0 |
T88 |
11738 |
6 |
0 |
0 |
T111 |
6983 |
11 |
0 |
0 |
T113 |
271285 |
660 |
0 |
0 |
T114 |
10344 |
14 |
0 |
0 |
T117 |
10602 |
6 |
0 |
0 |
T140 |
3978 |
8 |
0 |
0 |
T141 |
4936 |
8 |
0 |
0 |
T142 |
6410 |
1 |
0 |
0 |
T143 |
3933 |
8 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
2056 |
0 |
0 |
T85 |
10110 |
10 |
0 |
0 |
T88 |
11738 |
45 |
0 |
0 |
T111 |
6983 |
14 |
0 |
0 |
T113 |
271285 |
686 |
0 |
0 |
T114 |
10344 |
36 |
0 |
0 |
T117 |
10602 |
19 |
0 |
0 |
T141 |
4936 |
6 |
0 |
0 |
T142 |
6410 |
16 |
0 |
0 |
T143 |
3933 |
23 |
0 |
0 |
T144 |
13989 |
34 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1454 |
0 |
0 |
T85 |
10110 |
14 |
0 |
0 |
T88 |
11738 |
7 |
0 |
0 |
T111 |
6983 |
5 |
0 |
0 |
T113 |
271285 |
630 |
0 |
0 |
T114 |
10344 |
5 |
0 |
0 |
T127 |
7336 |
6 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
3 |
0 |
0 |
T142 |
6410 |
6 |
0 |
0 |
T143 |
3933 |
2 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
2365 |
0 |
0 |
T85 |
10110 |
32 |
0 |
0 |
T88 |
11738 |
31 |
0 |
0 |
T111 |
6983 |
7 |
0 |
0 |
T113 |
271285 |
714 |
0 |
0 |
T114 |
10344 |
47 |
0 |
0 |
T127 |
7336 |
20 |
0 |
0 |
T140 |
3978 |
6 |
0 |
0 |
T141 |
4936 |
16 |
0 |
0 |
T142 |
6410 |
14 |
0 |
0 |
T143 |
3933 |
18 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1626 |
0 |
0 |
T85 |
10110 |
29 |
0 |
0 |
T88 |
11738 |
36 |
0 |
0 |
T111 |
6983 |
11 |
0 |
0 |
T113 |
271285 |
607 |
0 |
0 |
T114 |
10344 |
12 |
0 |
0 |
T117 |
10602 |
21 |
0 |
0 |
T140 |
3978 |
9 |
0 |
0 |
T141 |
4936 |
8 |
0 |
0 |
T142 |
6410 |
10 |
0 |
0 |
T143 |
3933 |
4 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1478 |
0 |
0 |
T85 |
10110 |
7 |
0 |
0 |
T88 |
11738 |
14 |
0 |
0 |
T111 |
6983 |
4 |
0 |
0 |
T113 |
271285 |
666 |
0 |
0 |
T114 |
10344 |
5 |
0 |
0 |
T127 |
7336 |
4 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
4 |
0 |
0 |
T142 |
6410 |
20 |
0 |
0 |
T143 |
3933 |
2 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1546 |
0 |
0 |
T85 |
10110 |
11 |
0 |
0 |
T88 |
11738 |
11 |
0 |
0 |
T111 |
6983 |
10 |
0 |
0 |
T113 |
271285 |
667 |
0 |
0 |
T114 |
10344 |
11 |
0 |
0 |
T127 |
7336 |
2 |
0 |
0 |
T140 |
3978 |
10 |
0 |
0 |
T141 |
4936 |
1 |
0 |
0 |
T142 |
6410 |
3 |
0 |
0 |
T143 |
3933 |
3 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1643 |
0 |
0 |
T85 |
10110 |
27 |
0 |
0 |
T88 |
11738 |
10 |
0 |
0 |
T111 |
6983 |
11 |
0 |
0 |
T113 |
271285 |
622 |
0 |
0 |
T114 |
10344 |
24 |
0 |
0 |
T117 |
10602 |
12 |
0 |
0 |
T140 |
3978 |
2 |
0 |
0 |
T141 |
4936 |
8 |
0 |
0 |
T142 |
6410 |
3 |
0 |
0 |
T143 |
3933 |
3 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1675 |
0 |
0 |
T85 |
10110 |
18 |
0 |
0 |
T88 |
11738 |
11 |
0 |
0 |
T111 |
6983 |
6 |
0 |
0 |
T113 |
271285 |
632 |
0 |
0 |
T114 |
10344 |
7 |
0 |
0 |
T127 |
7336 |
7 |
0 |
0 |
T140 |
3978 |
3 |
0 |
0 |
T141 |
4936 |
5 |
0 |
0 |
T142 |
6410 |
5 |
0 |
0 |
T143 |
3933 |
6 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1668 |
0 |
0 |
T85 |
10110 |
9 |
0 |
0 |
T88 |
11738 |
15 |
0 |
0 |
T111 |
6983 |
5 |
0 |
0 |
T113 |
271285 |
615 |
0 |
0 |
T114 |
10344 |
25 |
0 |
0 |
T127 |
7336 |
14 |
0 |
0 |
T140 |
3978 |
3 |
0 |
0 |
T141 |
4936 |
6 |
0 |
0 |
T142 |
6410 |
14 |
0 |
0 |
T143 |
3933 |
6 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
372991443 |
1539 |
0 |
0 |
T85 |
10110 |
19 |
0 |
0 |
T88 |
11738 |
13 |
0 |
0 |
T111 |
6983 |
15 |
0 |
0 |
T113 |
271285 |
665 |
0 |
0 |
T114 |
10344 |
10 |
0 |
0 |
T117 |
10602 |
12 |
0 |
0 |
T140 |
3978 |
1 |
0 |
0 |
T141 |
4936 |
1 |
0 |
0 |
T142 |
6410 |
12 |
0 |
0 |
T143 |
3933 |
1 |
0 |
0 |