Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3960857	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4108570

1

T1

3173

T2

875

T3

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4605807	1			T1	4733		T2	2		T3	9
values[0x0]	1731122	1			T1	460		T2	414		T3	8
values[0x1]	1732498	1			T1	437		T2	462		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2795970	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5273457

1

T1

3637

T2

876

T3

22

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27841	1			T1	21		T2	8		T8	5
valid_sources[0x01]	31900	1			T1	27		T2	2		T4	2
valid_sources[0x02]	32776	1			T1	2		T2	5		T4	2
valid_sources[0x03]	29514	1			T1	35		T2	4		T4	2
valid_sources[0x04]	30942	1			T1	14		T2	2		T4	1
valid_sources[0x05]	28047	1			T1	63		T2	1		T4	1
valid_sources[0x06]	31232	1			T1	5		T2	5		T4	3
valid_sources[0x07]	32268	1			T1	19		T2	1		T4	1
valid_sources[0x08]	64475	1			T1	10		T4	2		T10	3
valid_sources[0x09]	31670	1			T1	30		T2	4		T8	4
valid_sources[0x0a]	29341	1			T1	8		T2	4		T4	2
valid_sources[0x0b]	31068	1			T1	4		T2	1		T3	1
valid_sources[0x0c]	29761	1			T1	12		T2	2		T4	3
valid_sources[0x0d]	28283	1			T1	18		T2	2		T4	1
valid_sources[0x0e]	32260	1			T1	20		T2	3		T4	3
valid_sources[0x0f]	30895	1			T1	11		T2	2		T4	5
valid_sources[0x10]	29983	1			T1	25		T2	3		T4	4
valid_sources[0x11]	31807	1			T1	9		T2	7		T7	997
valid_sources[0x12]	30737	1			T1	35		T2	1		T4	3
valid_sources[0x13]	32786	1			T1	40		T2	3		T4	1
valid_sources[0x14]	29582	1			T1	17		T2	9		T8	8
valid_sources[0x15]	29605	1			T1	15		T2	2		T4	2
valid_sources[0x16]	31941	1			T1	14		T2	3		T4	2
valid_sources[0x17]	29812	1			T1	10		T2	4		T4	1
valid_sources[0x18]	30051	1			T1	4		T2	4		T4	2
valid_sources[0x19]	28008	1			T1	10		T2	3		T4	2
valid_sources[0x1a]	28341	1			T1	14		T2	7		T4	1
valid_sources[0x1b]	32980	1			T1	14		T2	1		T8	6
valid_sources[0x1c]	29143	1			T1	8		T2	5		T10	1
valid_sources[0x1d]	31283	1			T1	20		T2	4		T4	1
valid_sources[0x1e]	31716	1			T1	13		T2	2		T4	3
valid_sources[0x1f]	29692	1			T1	11		T2	2		T4	2
valid_sources[0x20]	28425	1			T1	26		T4	1		T8	6
valid_sources[0x21]	29051	1			T1	34		T2	4		T4	1
valid_sources[0x22]	29277	1			T1	19		T2	2		T4	1
valid_sources[0x23]	30259	1			T1	34		T2	3		T4	2
valid_sources[0x24]	30623	1			T1	43		T2	1		T4	2
valid_sources[0x25]	30509	1			T1	7		T2	5		T3	4
valid_sources[0x26]	29559	1			T1	14		T2	8		T3	1
valid_sources[0x27]	29192	1			T1	5		T2	6		T4	2
valid_sources[0x28]	27683	1			T1	13		T2	5		T4	2
valid_sources[0x29]	33294	1			T1	48		T2	5		T4	3
valid_sources[0x2a]	27527	1			T1	22		T2	4		T4	4
valid_sources[0x2b]	29473	1			T1	70		T2	1		T4	3
valid_sources[0x2c]	30187	1			T1	17		T2	12		T4	6
valid_sources[0x2d]	28073	1			T1	3		T2	8		T8	4
valid_sources[0x2e]	30702	1			T1	17		T2	2		T10	7
valid_sources[0x2f]	31190	1			T1	18		T2	1		T4	3
valid_sources[0x30]	29880	1			T1	21		T2	9		T4	3
valid_sources[0x31]	28815	1			T1	21		T2	3		T4	1
valid_sources[0x32]	30674	1			T1	20		T2	5		T4	5
valid_sources[0x33]	30809	1			T1	31		T2	7		T4	2
valid_sources[0x34]	31602	1			T1	43		T2	2		T8	8
valid_sources[0x35]	29381	1			T1	8		T2	3		T4	1
valid_sources[0x36]	31627	1			T1	9		T2	3		T4	2
valid_sources[0x37]	33171	1			T1	22		T2	5		T4	2
valid_sources[0x38]	30586	1			T1	19		T2	1		T4	2
valid_sources[0x39]	34304	1			T1	5		T2	3		T4	6
valid_sources[0x3a]	29025	1			T1	12		T2	5		T4	4
valid_sources[0x3b]	32640	1			T1	35		T2	2		T3	6
valid_sources[0x3c]	28779	1			T1	32		T2	5		T3	4
valid_sources[0x3d]	31802	1			T1	9		T2	3		T4	4
valid_sources[0x3e]	28896	1			T1	2		T2	2		T4	3
valid_sources[0x3f]	30527	1			T1	10		T2	3		T4	3
valid_sources[0x40]	30534	1			T1	19		T2	4		T4	4
valid_sources[0x41]	31332	1			T1	21		T2	2		T4	1
valid_sources[0x42]	28750	1			T1	21		T2	3		T4	1
valid_sources[0x43]	32424	1			T1	13		T2	5		T4	2
valid_sources[0x44]	29372	1			T1	8		T8	5		T10	5
valid_sources[0x45]	30910	1			T1	11		T2	9		T4	3
valid_sources[0x46]	33043	1			T1	37		T8	14		T10	1
valid_sources[0x47]	31692	1			T1	44		T2	2		T4	3
valid_sources[0x48]	28159	1			T1	27		T2	3		T8	3
valid_sources[0x49]	28654	1			T1	42		T2	2		T4	4
valid_sources[0x4a]	32889	1			T1	18		T2	6		T4	3
valid_sources[0x4b]	29775	1			T1	29		T2	8		T4	3
valid_sources[0x4c]	29565	1			T1	51		T2	5		T4	2
valid_sources[0x4d]	33431	1			T1	28		T2	7		T4	2
valid_sources[0x4e]	29391	1			T1	8		T2	2		T4	3
valid_sources[0x4f]	30628	1			T1	22		T2	5		T4	1
valid_sources[0x50]	29691	1			T1	11		T2	5		T4	4
valid_sources[0x51]	31666	1			T1	69		T2	2		T8	1
valid_sources[0x52]	28910	1			T1	47		T2	2		T4	2
valid_sources[0x53]	30694	1			T1	26		T2	9		T4	2
valid_sources[0x54]	32600	1			T1	8		T2	2		T3	1
valid_sources[0x55]	30088	1			T1	9		T2	2		T4	2
valid_sources[0x56]	32342	1			T1	4		T2	5		T4	4
valid_sources[0x57]	31489	1			T1	14		T2	1		T4	2
valid_sources[0x58]	29572	1			T1	33		T2	5		T8	2
valid_sources[0x59]	31114	1			T1	24		T2	4		T4	3
valid_sources[0x5a]	29190	1			T1	6		T2	5		T4	3
valid_sources[0x5b]	29839	1			T1	16		T2	7		T4	3
valid_sources[0x5c]	32084	1			T1	34		T4	2		T8	5
valid_sources[0x5d]	30918	1			T1	11		T2	2		T4	2
valid_sources[0x5e]	38704	1			T1	5		T2	2		T8	2
valid_sources[0x5f]	30159	1			T1	14		T2	4		T4	1
valid_sources[0x60]	32238	1			T1	7		T2	5		T4	2
valid_sources[0x61]	35258	1			T1	24		T2	1		T4	2
valid_sources[0x62]	34919	1			T1	20		T2	2		T4	2
valid_sources[0x63]	28944	1			T1	31		T2	3		T4	2
valid_sources[0x64]	27930	1			T1	5		T2	3		T4	1
valid_sources[0x65]	31158	1			T1	4		T2	2		T4	1
valid_sources[0x66]	29470	1			T1	14		T2	1		T4	1
valid_sources[0x67]	27551	1			T1	8		T2	2		T4	2
valid_sources[0x68]	28065	1			T1	17		T2	2		T4	4
valid_sources[0x69]	30485	1			T1	18		T4	2		T6	1
valid_sources[0x6a]	29931	1			T1	20		T2	2		T4	4
valid_sources[0x6b]	29415	1			T1	23		T2	5		T4	1
valid_sources[0x6c]	29939	1			T1	40		T2	2		T4	1
valid_sources[0x6d]	32128	1			T1	34		T2	3		T4	3
valid_sources[0x6e]	30255	1			T1	14		T2	8		T8	8
valid_sources[0x6f]	29745	1			T1	23		T2	3		T4	1
valid_sources[0x70]	28581	1			T1	22		T4	7		T6	1
valid_sources[0x71]	31536	1			T1	38		T2	4		T4	3
valid_sources[0x72]	33795	1			T1	17		T2	1		T4	1
valid_sources[0x73]	28122	1			T1	19		T2	8		T8	5
valid_sources[0x74]	29261	1			T1	30		T2	2		T4	2
valid_sources[0x75]	32953	1			T1	23		T2	5		T8	4
valid_sources[0x76]	31508	1			T1	16		T2	3		T4	4
valid_sources[0x77]	28283	1			T1	1		T2	2		T4	1
valid_sources[0x78]	33444	1			T1	20		T2	3		T4	1
valid_sources[0x79]	30105	1			T1	28		T2	3		T4	2
valid_sources[0x7a]	30954	1			T1	33		T2	5		T4	1
valid_sources[0x7b]	30970	1			T1	16		T2	2		T4	4
valid_sources[0x7c]	29845	1			T1	10		T2	3		T4	4
valid_sources[0x7d]	69175	1			T1	32		T2	2		T4	3
valid_sources[0x7e]	32749	1			T1	13		T2	1		T4	3
valid_sources[0x7f]	30389	1			T1	6		T2	5		T6	1
valid_sources[0x80]	30990	1			T1	3		T2	4		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1016438

1

T1

2281

T4

88

T5

114

values[0x0]

all_enables

biggest_size

1558363

1

T1

459

T2

414

T3

6

values[0x1]

all_enables

biggest_size

1533769

1

T1

433

T2

461

T3

11