Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3980095

1

T1

2457

T2

3

T3

11

full_word

4107550

1

T1

3173

T2

875

T3

17

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8087255	1			T1	5630		T2	878		T3	28
auto[TlIntgErrCmd]	134	1			T98	13		T100	4		T101	5
auto[TlIntgErrData]	132	1			T98	6		T100	5		T186	10
auto[TlIntgErrBoth]	124	1			T98	11		T100	1		T101	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4607355

1

T1

4733

T2

2

T3

9

auto[1]

3480290

1

T1

897

T2

876

T3

19

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3590669	1			T1	2452		T2	2		T3	9
auto[TlIntgErrNone]	partial	auto[1]	389073	1			T1	5		T2	1		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1016489	1			T1	2281		T4	88		T5	114
auto[TlIntgErrNone]	full_word	auto[1]	3091024	1			T1	892		T2	875		T3	17
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T98	4		T100	2		T101	3
auto[TlIntgErrCmd]	partial	auto[1]	61	1			T98	5		T100	2		T101	2
auto[TlIntgErrCmd]	full_word	auto[0]	9	1			T98	2		T187	2		T188	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T98	2		T186	1		T182	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T98	6		T100	2		T186	4
auto[TlIntgErrData]	partial	auto[1]	61	1			T100	3		T186	6		T182	4
auto[TlIntgErrData]	full_word	auto[0]	3	1			T185	1		T189	1		T190	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T188	1		T189	2		-	-
auto[TlIntgErrBoth]	partial	auto[0]	59	1			T98	6		T101	2		T186	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T98	5		T100	1		T101	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T101	1		T186	1		T183	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T101	1		T186	1		T182	1