Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.63	93.89	84.31	97.00		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.63	93.89	84.31	97.00		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T5,T7,T12
1	0	Covered	T5,T7,T12
1	1	Covered	T5,T7,T12

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T7,T12
1	0	Covered	T5,T7,T12
1	1	Covered	T5,T7,T12

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1252805232	2233	0	0
SrcPulseCheck_M	395336676	2233	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1252805232	2233	0	0
T5	20244	7	0	0
T6	3298	0	0	0
T7	500640	4	0	0
T8	1580385	0	0	0
T9	370419	0	0	0
T10	170037	0	0	0
T11	421809	0	0	0
T12	1131549	3	0	0
T13	38109	0	0	0
T14	0	3	0	0
T17	0	18	0	0
T23	64941	0	0	0
T24	51461	0	0	0
T25	57684	0	0	0
T38	0	9	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	9	0	0
T51	0	1	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	13	0	0
T146	0	1	0	0
T147	0	8	0	0
T148	0	4	0	0
T149	0	7	0	0
T150	0	7	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	395336676	2233	0	0
T5	49932	7	0	0
T7	465930	4	0	0
T8	262995	0	0	0
T9	120381	0	0	0
T10	157350	0	0	0
T11	1033602	0	0	0
T12	1101135	3	0	0
T13	23526	0	0	0
T14	0	3	0	0
T17	0	18	0	0
T23	13893	0	0	0
T24	372297	0	0	0
T25	61069	0	0	0
T38	0	9	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	9	0	0
T51	0	1	0	0
T52	0	5	0	0
T53	0	3	0	0
T54	0	13	0	0
T146	0	1	0	0
T147	0	8	0	0
T148	0	4	0	0
T149	0	7	0	0
T150	0	7	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T5,T51,T52
1	0	Covered	T5,T51,T52
1	1	Covered	T5,T52,T53

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T51,T52
1	0	Covered	T5,T52,T53
1	1	Covered	T5,T51,T52

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	417601744	189	0	0
SrcPulseCheck_M	131778892	189	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	189	0	0
T5	10122	2	0	0
T6	1649	0	0	0
T7	166880	0	0	0
T8	526795	0	0	0
T9	123473	0	0	0
T10	56679	0	0	0
T11	140603	0	0	0
T12	377183	0	0	0
T13	12703	0	0	0
T23	21647	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	189	0	0
T5	24966	2	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	0	0	0
T13	7842	0	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T53	0	2	0	0
T146	0	1	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T5,T52,T53
1	0	Covered	T5,T52,T53
1	1	Covered	T5,T52,T147

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T52,T53
1	0	Covered	T5,T52,T147
1	1	Covered	T5,T52,T53

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	417601744	338	0	0
SrcPulseCheck_M	131778892	338	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	338	0	0
T5	10122	5	0	0
T6	1649	0	0	0
T7	166880	0	0	0
T8	526795	0	0	0
T9	123473	0	0	0
T10	56679	0	0	0
T11	140603	0	0	0
T12	377183	0	0	0
T13	12703	0	0	0
T23	21647	0	0	0
T52	0	2	0	0
T53	0	1	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	338	0	0
T5	24966	5	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	0	0	0
T13	7842	0	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T52	0	2	0	0
T53	0	1	0	0
T147	0	4	0	0
T148	0	2	0	0
T149	0	5	0	0
T150	0	5	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T7,T12,T14
1	0	Covered	T7,T12,T14
1	1	Covered	T7,T12,T14

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T14
1	0	Covered	T7,T12,T14
1	1	Covered	T7,T12,T14

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	417601744	1706	0	0
SrcPulseCheck_M	131778892	1706	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1706	0	0
T7	166880	4	0	0
T8	526795	0	0	0
T9	123473	0	0	0
T10	56679	0	0	0
T11	140603	0	0	0
T12	377183	3	0	0
T13	12703	0	0	0
T14	0	3	0	0
T17	0	18	0	0
T23	21647	0	0	0
T24	51461	0	0	0
T25	57684	0	0	0
T38	0	9	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	9	0	0
T54	0	13	0	0
T69	0	18	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	1706	0	0
T7	155310	4	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	3	0	0
T13	7842	0	0	0
T14	0	3	0	0
T17	0	18	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	9	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	9	0	0
T54	0	13	0	0
T69	0	18	0	0