Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Total | Covered | Percent |
Conditions | 22 | 16 | 72.73 |
Logical | 22 | 16 | 72.73 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T5,T7 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T8 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T5,T7 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T5,T7,T8 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T7,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T5,T7,T8 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T8 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T8 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T5,T7 |
0 |
0 |
Covered |
T1,T5,T7 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
19384161 |
0 |
0 |
T5 |
24966 |
23745 |
0 |
0 |
T7 |
155310 |
20738 |
0 |
0 |
T8 |
87665 |
128 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
42 |
0 |
0 |
T11 |
344534 |
11150 |
0 |
0 |
T12 |
367045 |
105907 |
0 |
0 |
T13 |
7842 |
2340 |
0 |
0 |
T14 |
0 |
17513 |
0 |
0 |
T23 |
4631 |
0 |
0 |
0 |
T24 |
124099 |
0 |
0 |
0 |
T43 |
0 |
2004 |
0 |
0 |
T55 |
0 |
12688 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
19384161 |
0 |
0 |
T5 |
24966 |
23745 |
0 |
0 |
T7 |
155310 |
20738 |
0 |
0 |
T8 |
87665 |
128 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
42 |
0 |
0 |
T11 |
344534 |
11150 |
0 |
0 |
T12 |
367045 |
105907 |
0 |
0 |
T13 |
7842 |
2340 |
0 |
0 |
T14 |
0 |
17513 |
0 |
0 |
T23 |
4631 |
0 |
0 |
0 |
T24 |
124099 |
0 |
0 |
0 |
T43 |
0 |
2004 |
0 |
0 |
T55 |
0 |
12688 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
130 |
1 |
1 |
131 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Total | Covered | Percent |
Conditions | 22 | 18 | 81.82 |
Logical | 22 | 18 | 81.82 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T5,T7 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T7 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T5,T7,T8 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T5,T7 |
1 | 0 | 1 | Covered | T5,T7,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T5,T7,T8 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T5,T7,T8 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T5,T7,T8 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T7,T8 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T5,T7,T8 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T7,T8 |
1 | 0 | Covered | T5,T7,T8 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T5,T7 |
0 |
0 |
Covered |
T1,T5,T7 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T7,T8 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
20391861 |
0 |
0 |
T5 |
24966 |
24694 |
0 |
0 |
T7 |
155310 |
21626 |
0 |
0 |
T8 |
87665 |
128 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
40 |
0 |
0 |
T11 |
344534 |
11532 |
0 |
0 |
T12 |
367045 |
110782 |
0 |
0 |
T13 |
7842 |
2522 |
0 |
0 |
T14 |
0 |
18736 |
0 |
0 |
T23 |
4631 |
0 |
0 |
0 |
T24 |
124099 |
0 |
0 |
0 |
T43 |
0 |
2064 |
0 |
0 |
T55 |
0 |
13530 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
20391861 |
0 |
0 |
T5 |
24966 |
24694 |
0 |
0 |
T7 |
155310 |
21626 |
0 |
0 |
T8 |
87665 |
128 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
40 |
0 |
0 |
T11 |
344534 |
11532 |
0 |
0 |
T12 |
367045 |
110782 |
0 |
0 |
T13 |
7842 |
2522 |
0 |
0 |
T14 |
0 |
18736 |
0 |
0 |
T23 |
4631 |
0 |
0 |
0 |
T24 |
124099 |
0 |
0 |
0 |
T43 |
0 |
2064 |
0 |
0 |
T55 |
0 |
13530 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 12 | 85.71 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 1 | 50.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
0 |
1 |
|
|
|
MISSING_ELSE |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Total | Covered | Percent |
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T5,T7 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T5,T7 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T5,T7 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T5,T7 |
0 |
0 |
Covered |
T1,T5,T7 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
102074643 |
0 |
0 |
T1 |
22976 |
22976 |
0 |
0 |
T3 |
704 |
0 |
0 |
0 |
T4 |
16852 |
0 |
0 |
0 |
T5 |
24966 |
24950 |
0 |
0 |
T7 |
155310 |
154082 |
0 |
0 |
T8 |
87665 |
87170 |
0 |
0 |
T9 |
40127 |
39564 |
0 |
0 |
T10 |
52450 |
52120 |
0 |
0 |
T11 |
344534 |
99646 |
0 |
0 |
T12 |
367045 |
331669 |
0 |
0 |
T13 |
0 |
7842 |
0 |
0 |
T14 |
0 |
96361 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
140 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Total | Covered | Percent |
Conditions | 22 | 17 | 77.27 |
Logical | 22 | 17 | 77.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T11 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T11 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T11 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T4,T11 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T11 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T4,T11 |
1 | 0 | 1 | Covered | T3,T4,T11 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T11 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T11 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T11 |
1 | 0 | Covered | T3,T4,T11 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T11 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T4,T11 |
0 |
0 |
Covered |
T3,T4,T11 |
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T11 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
6338399 |
0 |
0 |
T3 |
704 |
488 |
0 |
0 |
T4 |
16852 |
2536 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
91298 |
0 |
0 |
T12 |
367045 |
8294 |
0 |
0 |
T14 |
0 |
36821 |
0 |
0 |
T23 |
4631 |
1307 |
0 |
0 |
T27 |
0 |
976 |
0 |
0 |
T38 |
0 |
34723 |
0 |
0 |
T39 |
0 |
44925 |
0 |
0 |
T41 |
0 |
37012 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
28401796 |
0 |
0 |
T3 |
704 |
704 |
0 |
0 |
T4 |
16852 |
16632 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
234776 |
0 |
0 |
T12 |
367045 |
33600 |
0 |
0 |
T14 |
0 |
72432 |
0 |
0 |
T23 |
4631 |
4608 |
0 |
0 |
T24 |
0 |
118448 |
0 |
0 |
T25 |
0 |
55816 |
0 |
0 |
T27 |
0 |
1120 |
0 |
0 |
T29 |
0 |
73144 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
28401796 |
0 |
0 |
T3 |
704 |
704 |
0 |
0 |
T4 |
16852 |
16632 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
234776 |
0 |
0 |
T12 |
367045 |
33600 |
0 |
0 |
T14 |
0 |
72432 |
0 |
0 |
T23 |
4631 |
4608 |
0 |
0 |
T24 |
0 |
118448 |
0 |
0 |
T25 |
0 |
55816 |
0 |
0 |
T27 |
0 |
1120 |
0 |
0 |
T29 |
0 |
73144 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
28401796 |
0 |
0 |
T3 |
704 |
704 |
0 |
0 |
T4 |
16852 |
16632 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
234776 |
0 |
0 |
T12 |
367045 |
33600 |
0 |
0 |
T14 |
0 |
72432 |
0 |
0 |
T23 |
4631 |
4608 |
0 |
0 |
T24 |
0 |
118448 |
0 |
0 |
T25 |
0 |
55816 |
0 |
0 |
T27 |
0 |
1120 |
0 |
0 |
T29 |
0 |
73144 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
6338399 |
0 |
0 |
T3 |
704 |
488 |
0 |
0 |
T4 |
16852 |
2536 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
91298 |
0 |
0 |
T12 |
367045 |
8294 |
0 |
0 |
T14 |
0 |
36821 |
0 |
0 |
T23 |
4631 |
1307 |
0 |
0 |
T27 |
0 |
976 |
0 |
0 |
T38 |
0 |
34723 |
0 |
0 |
T39 |
0 |
44925 |
0 |
0 |
T41 |
0 |
37012 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
120 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Total | Covered | Percent |
Conditions | 16 | 9 | 56.25 |
Logical | 16 | 9 | 56.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T3,T4,T11 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T11 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T11 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T4,T11 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T11 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T3,T4,T11 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T3,T4,T11 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T11 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T3,T4,T11 |
0 |
0 |
Covered |
T3,T4,T11 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T11 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
203768 |
0 |
0 |
T3 |
704 |
16 |
0 |
0 |
T4 |
16852 |
81 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
2940 |
0 |
0 |
T12 |
367045 |
267 |
0 |
0 |
T14 |
0 |
1185 |
0 |
0 |
T23 |
4631 |
43 |
0 |
0 |
T27 |
0 |
32 |
0 |
0 |
T38 |
0 |
1122 |
0 |
0 |
T39 |
0 |
1449 |
0 |
0 |
T41 |
0 |
1189 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
28401796 |
0 |
0 |
T3 |
704 |
704 |
0 |
0 |
T4 |
16852 |
16632 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
234776 |
0 |
0 |
T12 |
367045 |
33600 |
0 |
0 |
T14 |
0 |
72432 |
0 |
0 |
T23 |
4631 |
4608 |
0 |
0 |
T24 |
0 |
118448 |
0 |
0 |
T25 |
0 |
55816 |
0 |
0 |
T27 |
0 |
1120 |
0 |
0 |
T29 |
0 |
73144 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
28401796 |
0 |
0 |
T3 |
704 |
704 |
0 |
0 |
T4 |
16852 |
16632 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
234776 |
0 |
0 |
T12 |
367045 |
33600 |
0 |
0 |
T14 |
0 |
72432 |
0 |
0 |
T23 |
4631 |
4608 |
0 |
0 |
T24 |
0 |
118448 |
0 |
0 |
T25 |
0 |
55816 |
0 |
0 |
T27 |
0 |
1120 |
0 |
0 |
T29 |
0 |
73144 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
28401796 |
0 |
0 |
T3 |
704 |
704 |
0 |
0 |
T4 |
16852 |
16632 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
234776 |
0 |
0 |
T12 |
367045 |
33600 |
0 |
0 |
T14 |
0 |
72432 |
0 |
0 |
T23 |
4631 |
4608 |
0 |
0 |
T24 |
0 |
118448 |
0 |
0 |
T25 |
0 |
55816 |
0 |
0 |
T27 |
0 |
1120 |
0 |
0 |
T29 |
0 |
73144 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
131778892 |
203768 |
0 |
0 |
T3 |
704 |
16 |
0 |
0 |
T4 |
16852 |
81 |
0 |
0 |
T5 |
24966 |
0 |
0 |
0 |
T7 |
155310 |
0 |
0 |
0 |
T8 |
87665 |
0 |
0 |
0 |
T9 |
40127 |
0 |
0 |
0 |
T10 |
52450 |
0 |
0 |
0 |
T11 |
344534 |
2940 |
0 |
0 |
T12 |
367045 |
267 |
0 |
0 |
T14 |
0 |
1185 |
0 |
0 |
T23 |
4631 |
43 |
0 |
0 |
T27 |
0 |
32 |
0 |
0 |
T38 |
0 |
1122 |
0 |
0 |
T39 |
0 |
1449 |
0 |
0 |
T41 |
0 |
1189 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
1 |
1 |
111 |
1 |
1 |
112 |
1 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
1 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T8,T9,T10 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T2,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T5 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T5 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
2696474 |
0 |
0 |
T1 |
117885 |
832 |
0 |
0 |
T2 |
2827 |
832 |
0 |
0 |
T3 |
1028 |
0 |
0 |
0 |
T4 |
10790 |
0 |
0 |
0 |
T5 |
10122 |
832 |
0 |
0 |
T6 |
1649 |
0 |
0 |
0 |
T7 |
166880 |
1664 |
0 |
0 |
T8 |
526795 |
833 |
0 |
0 |
T9 |
123473 |
838 |
0 |
0 |
T10 |
56679 |
832 |
0 |
0 |
T11 |
0 |
1664 |
0 |
0 |
T12 |
0 |
2496 |
0 |
0 |
T13 |
0 |
3757 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
417517655 |
0 |
0 |
T1 |
117885 |
117785 |
0 |
0 |
T2 |
2827 |
2739 |
0 |
0 |
T3 |
1028 |
968 |
0 |
0 |
T4 |
10790 |
10740 |
0 |
0 |
T5 |
10122 |
10042 |
0 |
0 |
T6 |
1649 |
1551 |
0 |
0 |
T7 |
166880 |
166830 |
0 |
0 |
T8 |
526795 |
526710 |
0 |
0 |
T9 |
123473 |
123405 |
0 |
0 |
T10 |
56679 |
56595 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
417517655 |
0 |
0 |
T1 |
117885 |
117785 |
0 |
0 |
T2 |
2827 |
2739 |
0 |
0 |
T3 |
1028 |
968 |
0 |
0 |
T4 |
10790 |
10740 |
0 |
0 |
T5 |
10122 |
10042 |
0 |
0 |
T6 |
1649 |
1551 |
0 |
0 |
T7 |
166880 |
166830 |
0 |
0 |
T8 |
526795 |
526710 |
0 |
0 |
T9 |
123473 |
123405 |
0 |
0 |
T10 |
56679 |
56595 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
417517655 |
0 |
0 |
T1 |
117885 |
117785 |
0 |
0 |
T2 |
2827 |
2739 |
0 |
0 |
T3 |
1028 |
968 |
0 |
0 |
T4 |
10790 |
10740 |
0 |
0 |
T5 |
10122 |
10042 |
0 |
0 |
T6 |
1649 |
1551 |
0 |
0 |
T7 |
166880 |
166830 |
0 |
0 |
T8 |
526795 |
526710 |
0 |
0 |
T9 |
123473 |
123405 |
0 |
0 |
T10 |
56679 |
56595 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
2696474 |
0 |
0 |
T1 |
117885 |
832 |
0 |
0 |
T2 |
2827 |
832 |
0 |
0 |
T3 |
1028 |
0 |
0 |
0 |
T4 |
10790 |
0 |
0 |
0 |
T5 |
10122 |
832 |
0 |
0 |
T6 |
1649 |
0 |
0 |
0 |
T7 |
166880 |
1664 |
0 |
0 |
T8 |
526795 |
833 |
0 |
0 |
T9 |
123473 |
838 |
0 |
0 |
T10 |
56679 |
832 |
0 |
0 |
T11 |
0 |
1664 |
0 |
0 |
T12 |
0 |
2496 |
0 |
0 |
T13 |
0 |
3757 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 12 | 80.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
82 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
108 |
0 |
1 |
111 |
1 |
1 |
112 |
0 |
1 |
|
|
|
MISSING_ELSE |
116 |
1 |
1 |
133 |
0 |
1 |
134 |
1 |
1 |
138 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
1 |
50.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
417517655 |
0 |
0 |
T1 |
117885 |
117785 |
0 |
0 |
T2 |
2827 |
2739 |
0 |
0 |
T3 |
1028 |
968 |
0 |
0 |
T4 |
10790 |
10740 |
0 |
0 |
T5 |
10122 |
10042 |
0 |
0 |
T6 |
1649 |
1551 |
0 |
0 |
T7 |
166880 |
166830 |
0 |
0 |
T8 |
526795 |
526710 |
0 |
0 |
T9 |
123473 |
123405 |
0 |
0 |
T10 |
56679 |
56595 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
417517655 |
0 |
0 |
T1 |
117885 |
117785 |
0 |
0 |
T2 |
2827 |
2739 |
0 |
0 |
T3 |
1028 |
968 |
0 |
0 |
T4 |
10790 |
10740 |
0 |
0 |
T5 |
10122 |
10042 |
0 |
0 |
T6 |
1649 |
1551 |
0 |
0 |
T7 |
166880 |
166830 |
0 |
0 |
T8 |
526795 |
526710 |
0 |
0 |
T9 |
123473 |
123405 |
0 |
0 |
T10 |
56679 |
56595 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
417517655 |
0 |
0 |
T1 |
117885 |
117785 |
0 |
0 |
T2 |
2827 |
2739 |
0 |
0 |
T3 |
1028 |
968 |
0 |
0 |
T4 |
10790 |
10740 |
0 |
0 |
T5 |
10122 |
10042 |
0 |
0 |
T6 |
1649 |
1551 |
0 |
0 |
T7 |
166880 |
166830 |
0 |
0 |
T8 |
526795 |
526710 |
0 |
0 |
T9 |
123473 |
123405 |
0 |
0 |
T10 |
56679 |
56595 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
417601744 |
0 |
0 |
0 |