dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.18 100.00 72.73 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.63 95.00 76.19 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.77 98.25 100.00 100.00 90.62 100.00 u_readsram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.45 100.00 81.82 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.62 100.00 90.48 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.77 98.25 100.00 100.00 90.62 100.00 u_readsram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
62.10 85.71 31.25 71.43 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
59.07 84.62 36.11 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
66.67 100.00 33.33 u_arbiter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 56.48 84.00 40.00 45.45


Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.32 100.00 77.27 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.23 95.00 78.57 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.79 99.29 91.20 91.67 96.77 100.00 u_spi_tpm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.06 100.00 56.25 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.36 100.00 75.00 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.67 100.00 83.33 u_arbiter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91


Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.33 95.00 75.00 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.12 94.44 60.33 73.08 84.62 u_tlul2sram_egress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
60.67 80.00 31.25 71.43 60.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
61.32 82.50 47.22 55.56 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
78.12 94.44 60.33 73.08 84.62 u_tlul2sram_egress


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45

Go back
Module Instances:
tb.dut.u_readcmd.u_readsram.u_sram_fifo
tb.dut.u_readcmd.u_readsram.u_fifo
tb.dut.u_upload.u_arbiter.u_req_fifo
tb.dut.u_spi_tpm.u_sram_fifo
tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
tb.dut.u_tlul2sram_egress.u_reqfifo
tb.dut.u_tlul2sram_egress.u_sramreqfifo
Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
TotalCoveredPercent
Conditions221672.73
Logical221672.73
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T5,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T7
10Not Covered
11CoveredT5,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T5,T7
101Not Covered
110Not Covered
111CoveredT5,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T7,T8
110Not Covered
111CoveredT5,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT5,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT5,T7,T8
10CoveredT5,T7,T8
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 130 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T5,T7
0 0 Covered T1,T5,T7


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T7,T8
0 Covered T1,T3,T4


Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 131778892 19384161 0 0
DepthKnown_A 131778892 102074643 0 0
RvalidKnown_A 131778892 102074643 0 0
WreadyKnown_A 131778892 102074643 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 131778892 19384161 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 19384161 0 0
T5 24966 23745 0 0
T7 155310 20738 0 0
T8 87665 128 0 0
T9 40127 0 0 0
T10 52450 42 0 0
T11 344534 11150 0 0
T12 367045 105907 0 0
T13 7842 2340 0 0
T14 0 17513 0 0
T23 4631 0 0 0
T24 124099 0 0 0
T43 0 2004 0 0
T55 0 12688 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 19384161 0 0
T5 24966 23745 0 0
T7 155310 20738 0 0
T8 87665 128 0 0
T9 40127 0 0 0
T10 52450 42 0 0
T11 344534 11150 0 0
T12 367045 105907 0 0
T13 7842 2340 0 0
T14 0 17513 0 0
T23 4631 0 0 0
T24 124099 0 0 0
T43 0 2004 0 0
T55 0 12688 0 0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
TotalCoveredPercent
Conditions221881.82
Logical221881.82
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T7,T8
10CoveredT1,T2,T3
11CoveredT1,T5,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T7
10Not Covered
11CoveredT5,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T5,T7
101CoveredT5,T7,T8
110Not Covered
111CoveredT5,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T7,T8
110Not Covered
111CoveredT5,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT5,T7,T8
10CoveredT1,T2,T3
11CoveredT5,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT5,T7,T8
10CoveredT5,T7,T8
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 130 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T5,T7,T8
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T5,T7
0 0 Covered T1,T5,T7


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T7,T8
0 Covered T1,T3,T4


Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 131778892 20391861 0 0
DepthKnown_A 131778892 102074643 0 0
RvalidKnown_A 131778892 102074643 0 0
WreadyKnown_A 131778892 102074643 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 131778892 20391861 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 20391861 0 0
T5 24966 24694 0 0
T7 155310 21626 0 0
T8 87665 128 0 0
T9 40127 0 0 0
T10 52450 40 0 0
T11 344534 11532 0 0
T12 367045 110782 0 0
T13 7842 2522 0 0
T14 0 18736 0 0
T23 4631 0 0 0
T24 124099 0 0 0
T43 0 2064 0 0
T55 0 13530 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 20391861 0 0
T5 24966 24694 0 0
T7 155310 21626 0 0
T8 87665 128 0 0
T9 40127 0 0 0
T10 52450 40 0 0
T11 344534 11532 0 0
T12 367045 110782 0 0
T13 7842 2522 0 0
T14 0 18736 0 0
T23 4631 0 0 0
T24 124099 0 0 0
T43 0 2064 0 0
T55 0 13530 0 0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
TOTAL141285.71
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS1232150.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 0 1
MISSING_ELSE
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T5,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T7
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T5,T7
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T5,T7
0 0 Covered T1,T5,T7


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T3,T4


Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 131778892 0 0 0
DepthKnown_A 131778892 102074643 0 0
RvalidKnown_A 131778892 102074643 0 0
WreadyKnown_A 131778892 102074643 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 131778892 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 102074643 0 0
T1 22976 22976 0 0
T3 704 0 0 0
T4 16852 0 0 0
T5 24966 24950 0 0
T7 155310 154082 0 0
T8 87665 87170 0 0
T9 40127 39564 0 0
T10 52450 52120 0 0
T11 344534 99646 0 0
T12 367045 331669 0 0
T13 0 7842 0 0
T14 0 96361 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 0 0 0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
140 1 1


Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
TotalCoveredPercent
Conditions221777.27
Logical221777.27
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T4,T11
10CoveredT1,T2,T3
11CoveredT3,T4,T11

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T4,T11
10Not Covered
11CoveredT3,T4,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT3,T4,T11
101Not Covered
110Not Covered
111CoveredT3,T4,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT3,T4,T11
101CoveredT3,T4,T11
110Not Covered
111CoveredT3,T4,T11

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T11

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T11

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT3,T4,T11
10CoveredT3,T4,T11
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 130 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T11
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T11
0 0 Covered T3,T4,T11


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T11
0 Covered T1,T3,T4


Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 131778892 6338399 0 0
DepthKnown_A 131778892 28401796 0 0
RvalidKnown_A 131778892 28401796 0 0
WreadyKnown_A 131778892 28401796 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 131778892 6338399 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 6338399 0 0
T3 704 488 0 0
T4 16852 2536 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 91298 0 0
T12 367045 8294 0 0
T14 0 36821 0 0
T23 4631 1307 0 0
T27 0 976 0 0
T38 0 34723 0 0
T39 0 44925 0 0
T41 0 37012 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 28401796 0 0
T3 704 704 0 0
T4 16852 16632 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 234776 0 0
T12 367045 33600 0 0
T14 0 72432 0 0
T23 4631 4608 0 0
T24 0 118448 0 0
T25 0 55816 0 0
T27 0 1120 0 0
T29 0 73144 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 28401796 0 0
T3 704 704 0 0
T4 16852 16632 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 234776 0 0
T12 367045 33600 0 0
T14 0 72432 0 0
T23 4631 4608 0 0
T24 0 118448 0 0
T25 0 55816 0 0
T27 0 1120 0 0
T29 0 73144 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 28401796 0 0
T3 704 704 0 0
T4 16852 16632 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 234776 0 0
T12 367045 33600 0 0
T14 0 72432 0 0
T23 4631 4608 0 0
T24 0 118448 0 0
T25 0 55816 0 0
T27 0 1120 0 0
T29 0 73144 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 6338399 0 0
T3 704 488 0 0
T4 16852 2536 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 91298 0 0
T12 367045 8294 0 0
T14 0 36821 0 0
T23 4631 1307 0 0
T27 0 976 0 0
T38 0 34723 0 0
T39 0 44925 0 0
T41 0 37012 0 0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
TotalCoveredPercent
Conditions16956.25
Logical16956.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T11

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T4,T11
10Not Covered
11CoveredT3,T4,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT3,T4,T11
101Not Covered
110Not Covered
111CoveredT3,T4,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT3,T4,T11

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T4,T11
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T11


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T11
0 0 Covered T3,T4,T11


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T4,T11
0 Covered T1,T3,T4


Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 131778892 203768 0 0
DepthKnown_A 131778892 28401796 0 0
RvalidKnown_A 131778892 28401796 0 0
WreadyKnown_A 131778892 28401796 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 131778892 203768 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 203768 0 0
T3 704 16 0 0
T4 16852 81 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 2940 0 0
T12 367045 267 0 0
T14 0 1185 0 0
T23 4631 43 0 0
T27 0 32 0 0
T38 0 1122 0 0
T39 0 1449 0 0
T41 0 1189 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 28401796 0 0
T3 704 704 0 0
T4 16852 16632 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 234776 0 0
T12 367045 33600 0 0
T14 0 72432 0 0
T23 4631 4608 0 0
T24 0 118448 0 0
T25 0 55816 0 0
T27 0 1120 0 0
T29 0 73144 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 28401796 0 0
T3 704 704 0 0
T4 16852 16632 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 234776 0 0
T12 367045 33600 0 0
T14 0 72432 0 0
T23 4631 4608 0 0
T24 0 118448 0 0
T25 0 55816 0 0
T27 0 1120 0 0
T29 0 73144 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 28401796 0 0
T3 704 704 0 0
T4 16852 16632 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 234776 0 0
T12 367045 33600 0 0
T14 0 72432 0 0
T23 4631 4608 0 0
T24 0 118448 0 0
T25 0 55816 0 0
T27 0 1120 0 0
T29 0 73144 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 131778892 203768 0 0
T3 704 16 0 0
T4 16852 81 0 0
T5 24966 0 0 0
T7 155310 0 0 0
T8 87665 0 0 0
T9 40127 0 0 0
T10 52450 0 0 0
T11 344534 2940 0 0
T12 367045 267 0 0
T14 0 1185 0 0
T23 4631 43 0 0
T27 0 32 0 0
T38 0 1122 0 0
T39 0 1449 0 0
T41 0 1189 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT8,T9,T10
110Not Covered
111CoveredT1,T2,T5

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 417601744 2696474 0 0
DepthKnown_A 417601744 417517655 0 0
RvalidKnown_A 417601744 417517655 0 0
WreadyKnown_A 417601744 417517655 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 417601744 2696474 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 2696474 0 0
T1 117885 832 0 0
T2 2827 832 0 0
T3 1028 0 0 0
T4 10790 0 0 0
T5 10122 832 0 0
T6 1649 0 0 0
T7 166880 1664 0 0
T8 526795 833 0 0
T9 123473 838 0 0
T10 56679 832 0 0
T11 0 1664 0 0
T12 0 2496 0 0
T13 0 3757 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 417517655 0 0
T1 117885 117785 0 0
T2 2827 2739 0 0
T3 1028 968 0 0
T4 10790 10740 0 0
T5 10122 10042 0 0
T6 1649 1551 0 0
T7 166880 166830 0 0
T8 526795 526710 0 0
T9 123473 123405 0 0
T10 56679 56595 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 417517655 0 0
T1 117885 117785 0 0
T2 2827 2739 0 0
T3 1028 968 0 0
T4 10790 10740 0 0
T5 10122 10042 0 0
T6 1649 1551 0 0
T7 166880 166830 0 0
T8 526795 526710 0 0
T9 123473 123405 0 0
T10 56679 56595 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 417517655 0 0
T1 117885 117785 0 0
T2 2827 2739 0 0
T3 1028 968 0 0
T4 10790 10740 0 0
T5 10122 10042 0 0
T6 1649 1551 0 0
T7 166880 166830 0 0
T8 526795 526710 0 0
T9 123473 123405 0 0
T10 56679 56595 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 2696474 0 0
T1 117885 832 0 0
T2 2827 832 0 0
T3 1028 0 0 0
T4 10790 0 0 0
T5 10122 832 0 0
T6 1649 0 0 0
T7 166880 1664 0 0
T8 526795 833 0 0
T9 123473 838 0 0
T10 56679 832 0 0
T11 0 1664 0 0
T12 0 2496 0 0
T13 0 3757 0 0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL151280.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 5 71.43
TERNARY 138 2 1 50.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 3 60.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 3 60.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 417601744 0 0 0
DepthKnown_A 417601744 417517655 0 0
RvalidKnown_A 417601744 417517655 0 0
WreadyKnown_A 417601744 417517655 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 417601744 0 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 417517655 0 0
T1 117885 117785 0 0
T2 2827 2739 0 0
T3 1028 968 0 0
T4 10790 10740 0 0
T5 10122 10042 0 0
T6 1649 1551 0 0
T7 166880 166830 0 0
T8 526795 526710 0 0
T9 123473 123405 0 0
T10 56679 56595 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 417517655 0 0
T1 117885 117785 0 0
T2 2827 2739 0 0
T3 1028 968 0 0
T4 10790 10740 0 0
T5 10122 10042 0 0
T6 1649 1551 0 0
T7 166880 166830 0 0
T8 526795 526710 0 0
T9 123473 123405 0 0
T10 56679 56595 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 417517655 0 0
T1 117885 117785 0 0
T2 2827 2739 0 0
T3 1028 968 0 0
T4 10790 10740 0 0
T5 10122 10042 0 0
T6 1649 1551 0 0
T7 166880 166830 0 0
T8 526795 526710 0 0
T9 123473 123405 0 0
T10 56679 56595 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 417601744 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%