Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419747884	2504412	0	0
DepthKnown_A	419747884	419619776	0	0
RvalidKnown_A	419747884	419619776	0	0
WreadyKnown_A	419747884	419619776	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2504412	0	0
T1	117885	832	0	0
T2	2827	1663	0	0
T3	1028	0	0	0
T4	10790	0	0	0
T5	10122	1663	0	0
T6	1649	0	0	0
T7	166880	1664	0	0
T8	526795	1664	0	0
T9	123473	1669	0	0
T10	56679	1663	0	0
T11	0	2495	0	0
T12	0	3327	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419747884	2720310	0	0
DepthKnown_A	419747884	419619776	0	0
RvalidKnown_A	419747884	419619776	0	0
WreadyKnown_A	419747884	419619776	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2720310	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	0	0	0
T4	10790	0	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1664	0	0
T8	526795	833	0	0
T9	123473	838	0	0
T10	56679	832	0	0
T11	0	1664	0	0
T12	0	2496	0	0
T13	0	3757	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419747884	165600	0	0
DepthKnown_A	419747884	419619776	0	0
RvalidKnown_A	419747884	419619776	0	0
WreadyKnown_A	419747884	419619776	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	165600	0	0
T4	10790	75	0	0
T5	10122	0	0	0
T6	1649	0	0	0
T7	166880	65	0	0
T8	526795	0	0	0
T9	123473	0	0	0
T10	56679	0	0	0
T11	140603	1596	0	0
T12	377183	240	0	0
T14	0	605	0	0
T23	21647	81	0	0
T38	0	969	0	0
T39	0	978	0	0
T40	0	64	0	0
T41	0	873	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419747884	380131	0	0
DepthKnown_A	419747884	419619776	0	0
RvalidKnown_A	419747884	419619776	0	0
WreadyKnown_A	419747884	419619776	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	380131	0	0
T4	10790	75	0	0
T5	10122	0	0	0
T6	1649	0	0	0
T7	166880	65	0	0
T8	526795	0	0	0
T9	123473	0	0	0
T10	56679	0	0	0
T11	140603	1596	0	0
T12	377183	240	0	0
T14	0	605	0	0
T23	21647	395	0	0
T38	0	4386	0	0
T39	0	4429	0	0
T40	0	64	0	0
T41	0	873	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419747884	6668656	0	0
DepthKnown_A	419747884	419619776	0	0
RvalidKnown_A	419747884	419619776	0	0
WreadyKnown_A	419747884	419619776	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	6668656	0	0
T1	117885	4798	0	0
T2	2827	46	0	0
T3	1028	28	0	0
T4	10790	413	0	0
T5	10122	299	0	0
T6	1649	69	0	0
T7	166880	389	0	0
T8	526795	78	0	0
T9	123473	61	0	0
T10	56679	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419747884	13558534	0	0
DepthKnown_A	419747884	419619776	0	0
RvalidKnown_A	419747884	419619776	0	0
WreadyKnown_A	419747884	419619776	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	13558534	0	0
T1	117885	4798	0	0
T2	2827	46	0	0
T3	1028	28	0	0
T4	10790	409	0	0
T5	10122	1190	0	0
T6	1649	69	0	0
T7	166880	389	0	0
T8	526795	351	0	0
T9	123473	252	0	0
T10	56679	76	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	419619776	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0