Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T4,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Unreachable
1	1	Covered	T3,T4,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T12,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T14
1	0	Covered	T7,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Unreachable
1	1	Covered	T7,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	681159528	547994094	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	681159528	3116829	0	0
GntImpliesValid_A	681159528	3116829	0	0
GrantKnown_A	681159528	547994094	0	0
IdxKnown_A	681159528	547994094	0	0
IndexIsCorrect_A	681159528	3116829	0	0
LockArbDecision_A	681159528	0	0	0
NoReadyValidNoGrant_A	681159528	0	0	0
ReadyAndValidImplyGrant_A	681159528	3116829	0	0
ReqAndReadyImplyGrant_A	681159528	3116829	0	0
ReqImpliesValid_A	681159528	3116829	0	0
ReqStaysHighUntilGranted0_M	681159528	0	0	0
RoundRobin_A	681159528	5	0	926
ValidKnown_A	681159528	547994094	0	0
gen_data_port_assertion.DataFlow_A	681159528	3116829	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	547994094	0	0
T1	140861	140761	0	0
T2	2827	2739	0	0
T3	2436	1672	0	0
T4	44494	27372	0	0
T5	60054	34992	0	0
T6	1649	1551	0	0
T7	477500	320912	0	0
T8	702125	613880	0	0
T9	203727	162969	0	0
T10	161579	108715	0	0
T11	689068	334422	0	0
T12	734090	365269	0	0
T13	0	7842	0	0
T14	0	168793	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	3116829	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1732	32	0	0
T4	27642	536	0	0
T5	35088	832	0	0
T6	1649	0	0	0
T7	477500	2259	0	0
T8	702125	832	0	0
T9	203727	832	0	0
T10	161579	832	0	0
T11	689068	15583	0	0
T12	734090	2648	0	0
T13	7842	0	0	0
T14	0	3634	0	0
T17	0	2992	0	0
T23	9262	368	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T27	0	32	0	0
T38	0	5004	0	0
T39	0	5376	0	0
T40	0	1495	0	0
T41	0	4705	0	0
T45	0	211	0	0
T54	0	749	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	3116829	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1732	32	0	0
T4	27642	536	0	0
T5	35088	832	0	0
T6	1649	0	0	0
T7	477500	2259	0	0
T8	702125	832	0	0
T9	203727	832	0	0
T10	161579	832	0	0
T11	689068	15583	0	0
T12	734090	2648	0	0
T13	7842	0	0	0
T14	0	3634	0	0
T17	0	2992	0	0
T23	9262	368	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T27	0	32	0	0
T38	0	5004	0	0
T39	0	5376	0	0
T40	0	1495	0	0
T41	0	4705	0	0
T45	0	211	0	0
T54	0	749	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	547994094	0	0
T1	140861	140761	0	0
T2	2827	2739	0	0
T3	2436	1672	0	0
T4	44494	27372	0	0
T5	60054	34992	0	0
T6	1649	1551	0	0
T7	477500	320912	0	0
T8	702125	613880	0	0
T9	203727	162969	0	0
T10	161579	108715	0	0
T11	689068	334422	0	0
T12	734090	365269	0	0
T13	0	7842	0	0
T14	0	168793	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	547994094	0	0
T1	140861	140761	0	0
T2	2827	2739	0	0
T3	2436	1672	0	0
T4	44494	27372	0	0
T5	60054	34992	0	0
T6	1649	1551	0	0
T7	477500	320912	0	0
T8	702125	613880	0	0
T9	203727	162969	0	0
T10	161579	108715	0	0
T11	689068	334422	0	0
T12	734090	365269	0	0
T13	0	7842	0	0
T14	0	168793	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	3116829	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1732	32	0	0
T4	27642	536	0	0
T5	35088	832	0	0
T6	1649	0	0	0
T7	477500	2259	0	0
T8	702125	832	0	0
T9	203727	832	0	0
T10	161579	832	0	0
T11	689068	15583	0	0
T12	734090	2648	0	0
T13	7842	0	0	0
T14	0	3634	0	0
T17	0	2992	0	0
T23	9262	368	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T27	0	32	0	0
T38	0	5004	0	0
T39	0	5376	0	0
T40	0	1495	0	0
T41	0	4705	0	0
T45	0	211	0	0
T54	0	749	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	3116829	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1732	32	0	0
T4	27642	536	0	0
T5	35088	832	0	0
T6	1649	0	0	0
T7	477500	2259	0	0
T8	702125	832	0	0
T9	203727	832	0	0
T10	161579	832	0	0
T11	689068	15583	0	0
T12	734090	2648	0	0
T13	7842	0	0	0
T14	0	3634	0	0
T17	0	2992	0	0
T23	9262	368	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T27	0	32	0	0
T38	0	5004	0	0
T39	0	5376	0	0
T40	0	1495	0	0
T41	0	4705	0	0
T45	0	211	0	0
T54	0	749	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	3116829	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1732	32	0	0
T4	27642	536	0	0
T5	35088	832	0	0
T6	1649	0	0	0
T7	477500	2259	0	0
T8	702125	832	0	0
T9	203727	832	0	0
T10	161579	832	0	0
T11	689068	15583	0	0
T12	734090	2648	0	0
T13	7842	0	0	0
T14	0	3634	0	0
T17	0	2992	0	0
T23	9262	368	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T27	0	32	0	0
T38	0	5004	0	0
T39	0	5376	0	0
T40	0	1495	0	0
T41	0	4705	0	0
T45	0	211	0	0
T54	0	749	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	3116829	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1732	32	0	0
T4	27642	536	0	0
T5	35088	832	0	0
T6	1649	0	0	0
T7	477500	2259	0	0
T8	702125	832	0	0
T9	203727	832	0	0
T10	161579	832	0	0
T11	689068	15583	0	0
T12	734090	2648	0	0
T13	7842	0	0	0
T14	0	3634	0	0
T17	0	2992	0	0
T23	9262	368	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T27	0	32	0	0
T38	0	5004	0	0
T39	0	5376	0	0
T40	0	1495	0	0
T41	0	4705	0	0
T45	0	211	0	0
T54	0	749	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	5	0	926
T36	1139	0	0	1
T56	339677	1	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	1067	0	0	1
T62	23727	0	0	1
T63	222699	0	0	1
T64	2382	0	0	1
T65	1006	0	0	1
T66	1287	0	0	1
T67	972825	0	0	1
T68	65936	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	547994094	0	0
T1	140861	140761	0	0
T2	2827	2739	0	0
T3	2436	1672	0	0
T4	44494	27372	0	0
T5	60054	34992	0	0
T6	1649	1551	0	0
T7	477500	320912	0	0
T8	702125	613880	0	0
T9	203727	162969	0	0
T10	161579	108715	0	0
T11	689068	334422	0	0
T12	734090	365269	0	0
T13	0	7842	0	0
T14	0	168793	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	681159528	3116829	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1732	32	0	0
T4	27642	536	0	0
T5	35088	832	0	0
T6	1649	0	0	0
T7	477500	2259	0	0
T8	702125	832	0	0
T9	203727	832	0	0
T10	161579	832	0	0
T11	689068	15583	0	0
T12	734090	2648	0	0
T13	7842	0	0	0
T14	0	3634	0	0
T17	0	2992	0	0
T23	9262	368	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T27	0	32	0	0
T38	0	5004	0	0
T39	0	5376	0	0
T40	0	1495	0	0
T41	0	4705	0	0
T45	0	211	0	0
T54	0	749	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T11,T12
1	0	Covered	T3,T4,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T11
1	0	Unreachable
1	1	Covered	T3,T4,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T11
0	0	1	Unreachable
0	0	0	Covered	T3,T4,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	131778892	28401796	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	131778892	676326	0	0
GntImpliesValid_A	131778892	676326	0	0
GrantKnown_A	131778892	28401796	0	0
IdxKnown_A	131778892	28401796	0	0
IndexIsCorrect_A	131778892	676326	0	0
LockArbDecision_A	131778892	0	0	0
NoReadyValidNoGrant_A	131778892	0	0	0
ReadyAndValidImplyGrant_A	131778892	676326	0	0
ReqAndReadyImplyGrant_A	131778892	676326	0	0
ReqImpliesValid_A	131778892	676326	0	0
ReqStaysHighUntilGranted0_M	131778892	0	0	0
RoundRobin_A	131778892	0	0	0
ValidKnown_A	131778892	28401796	0	0
gen_data_port_assertion.DataFlow_A	131778892	676326	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	28401796	0	0
T3	704	704	0	0
T4	16852	16632	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	234776	0	0
T12	367045	33600	0	0
T14	0	72432	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	676326	0	0
T3	704	16	0	0
T4	16852	380	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	9383	0	0
T12	367045	833	0	0
T14	0	3372	0	0
T23	4631	368	0	0
T27	0	32	0	0
T38	0	4986	0	0
T39	0	5376	0	0
T41	0	4705	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	676326	0	0
T3	704	16	0	0
T4	16852	380	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	9383	0	0
T12	367045	833	0	0
T14	0	3372	0	0
T23	4631	368	0	0
T27	0	32	0	0
T38	0	4986	0	0
T39	0	5376	0	0
T41	0	4705	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	28401796	0	0
T3	704	704	0	0
T4	16852	16632	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	234776	0	0
T12	367045	33600	0	0
T14	0	72432	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	28401796	0	0
T3	704	704	0	0
T4	16852	16632	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	234776	0	0
T12	367045	33600	0	0
T14	0	72432	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	676326	0	0
T3	704	16	0	0
T4	16852	380	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	9383	0	0
T12	367045	833	0	0
T14	0	3372	0	0
T23	4631	368	0	0
T27	0	32	0	0
T38	0	4986	0	0
T39	0	5376	0	0
T41	0	4705	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	676326	0	0
T3	704	16	0	0
T4	16852	380	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	9383	0	0
T12	367045	833	0	0
T14	0	3372	0	0
T23	4631	368	0	0
T27	0	32	0	0
T38	0	4986	0	0
T39	0	5376	0	0
T41	0	4705	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	676326	0	0
T3	704	16	0	0
T4	16852	380	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	9383	0	0
T12	367045	833	0	0
T14	0	3372	0	0
T23	4631	368	0	0
T27	0	32	0	0
T38	0	4986	0	0
T39	0	5376	0	0
T41	0	4705	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	676326	0	0
T3	704	16	0	0
T4	16852	380	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	9383	0	0
T12	367045	833	0	0
T14	0	3372	0	0
T23	4631	368	0	0
T27	0	32	0	0
T38	0	4986	0	0
T39	0	5376	0	0
T41	0	4705	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	28401796	0	0
T3	704	704	0	0
T4	16852	16632	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	234776	0	0
T12	367045	33600	0	0
T14	0	72432	0	0
T23	4631	4608	0	0
T24	0	118448	0	0
T25	0	55816	0	0
T27	0	1120	0	0
T29	0	73144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	676326	0	0
T3	704	16	0	0
T4	16852	380	0	0
T5	24966	0	0	0
T7	155310	0	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	9383	0	0
T12	367045	833	0	0
T14	0	3372	0	0
T23	4631	368	0	0
T27	0	32	0	0
T38	0	4986	0	0
T39	0	5376	0	0
T41	0	4705	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T12,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T12,T14
1	0	Covered	T7,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Unreachable
1	1	Covered	T7,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T12,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	131778892	102074643	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	131778892	446954	0	0
GntImpliesValid_A	131778892	446954	0	0
GrantKnown_A	131778892	102074643	0	0
IdxKnown_A	131778892	102074643	0	0
IndexIsCorrect_A	131778892	446954	0	0
LockArbDecision_A	131778892	0	0	0
NoReadyValidNoGrant_A	131778892	0	0	0
ReadyAndValidImplyGrant_A	131778892	446954	0	0
ReqAndReadyImplyGrant_A	131778892	446954	0	0
ReqImpliesValid_A	131778892	446954	0	0
ReqStaysHighUntilGranted0_M	131778892	0	0	0
RoundRobin_A	131778892	0	0	0
ValidKnown_A	131778892	102074643	0	0
gen_data_port_assertion.DataFlow_A	131778892	446954	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	102074643	0	0
T1	22976	22976	0	0
T3	704	0	0	0
T4	16852	0	0	0
T5	24966	24950	0	0
T7	155310	154082	0	0
T8	87665	87170	0	0
T9	40127	39564	0	0
T10	52450	52120	0	0
T11	344534	99646	0	0
T12	367045	331669	0	0
T13	0	7842	0	0
T14	0	96361	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	446954	0	0
T7	155310	523	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	1815	0	0
T13	7842	0	0	0
T14	0	262	0	0
T17	0	2992	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	18	0	0
T40	0	1495	0	0
T45	0	211	0	0
T46	0	4313	0	0
T54	0	749	0	0
T69	0	6231	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	446954	0	0
T7	155310	523	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	1815	0	0
T13	7842	0	0	0
T14	0	262	0	0
T17	0	2992	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	18	0	0
T40	0	1495	0	0
T45	0	211	0	0
T46	0	4313	0	0
T54	0	749	0	0
T69	0	6231	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	102074643	0	0
T1	22976	22976	0	0
T3	704	0	0	0
T4	16852	0	0	0
T5	24966	24950	0	0
T7	155310	154082	0	0
T8	87665	87170	0	0
T9	40127	39564	0	0
T10	52450	52120	0	0
T11	344534	99646	0	0
T12	367045	331669	0	0
T13	0	7842	0	0
T14	0	96361	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	102074643	0	0
T1	22976	22976	0	0
T3	704	0	0	0
T4	16852	0	0	0
T5	24966	24950	0	0
T7	155310	154082	0	0
T8	87665	87170	0	0
T9	40127	39564	0	0
T10	52450	52120	0	0
T11	344534	99646	0	0
T12	367045	331669	0	0
T13	0	7842	0	0
T14	0	96361	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	446954	0	0
T7	155310	523	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	1815	0	0
T13	7842	0	0	0
T14	0	262	0	0
T17	0	2992	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	18	0	0
T40	0	1495	0	0
T45	0	211	0	0
T46	0	4313	0	0
T54	0	749	0	0
T69	0	6231	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	446954	0	0
T7	155310	523	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	1815	0	0
T13	7842	0	0	0
T14	0	262	0	0
T17	0	2992	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	18	0	0
T40	0	1495	0	0
T45	0	211	0	0
T46	0	4313	0	0
T54	0	749	0	0
T69	0	6231	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	446954	0	0
T7	155310	523	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	1815	0	0
T13	7842	0	0	0
T14	0	262	0	0
T17	0	2992	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	18	0	0
T40	0	1495	0	0
T45	0	211	0	0
T46	0	4313	0	0
T54	0	749	0	0
T69	0	6231	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	446954	0	0
T7	155310	523	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	1815	0	0
T13	7842	0	0	0
T14	0	262	0	0
T17	0	2992	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	18	0	0
T40	0	1495	0	0
T45	0	211	0	0
T46	0	4313	0	0
T54	0	749	0	0
T69	0	6231	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	102074643	0	0
T1	22976	22976	0	0
T3	704	0	0	0
T4	16852	0	0	0
T5	24966	24950	0	0
T7	155310	154082	0	0
T8	87665	87170	0	0
T9	40127	39564	0	0
T10	52450	52120	0	0
T11	344534	99646	0	0
T12	367045	331669	0	0
T13	0	7842	0	0
T14	0	96361	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131778892	446954	0	0
T7	155310	523	0	0
T8	87665	0	0	0
T9	40127	0	0	0
T10	52450	0	0	0
T11	344534	0	0	0
T12	367045	1815	0	0
T13	7842	0	0	0
T14	0	262	0	0
T17	0	2992	0	0
T23	4631	0	0	0
T24	124099	0	0	0
T25	61069	0	0	0
T38	0	18	0	0
T40	0	1495	0	0
T45	0	211	0	0
T46	0	4313	0	0
T54	0	749	0	0
T69	0	6231	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T7,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	417601744	417517655	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	417601744	1993549	0	0
GntImpliesValid_A	417601744	1993549	0	0
GrantKnown_A	417601744	417517655	0	0
IdxKnown_A	417601744	417517655	0	0
IndexIsCorrect_A	417601744	1993549	0	0
LockArbDecision_A	417601744	0	0	0
NoReadyValidNoGrant_A	417601744	0	0	0
ReadyAndValidImplyGrant_A	417601744	1993549	0	0
ReqAndReadyImplyGrant_A	417601744	1993549	0	0
ReqImpliesValid_A	417601744	1993549	0	0
ReqStaysHighUntilGranted0_M	417601744	0	0	0
RoundRobin_A	417601744	5	0	926
ValidKnown_A	417601744	417517655	0	0
gen_data_port_assertion.DataFlow_A	417601744	1993549	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	417517655	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1993549	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	16	0	0
T4	10790	156	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1736	0	0
T8	526795	832	0	0
T9	123473	832	0	0
T10	56679	832	0	0
T11	0	6200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1993549	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	16	0	0
T4	10790	156	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1736	0	0
T8	526795	832	0	0
T9	123473	832	0	0
T10	56679	832	0	0
T11	0	6200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	417517655	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	417517655	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1993549	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	16	0	0
T4	10790	156	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1736	0	0
T8	526795	832	0	0
T9	123473	832	0	0
T10	56679	832	0	0
T11	0	6200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1993549	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	16	0	0
T4	10790	156	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1736	0	0
T8	526795	832	0	0
T9	123473	832	0	0
T10	56679	832	0	0
T11	0	6200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1993549	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	16	0	0
T4	10790	156	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1736	0	0
T8	526795	832	0	0
T9	123473	832	0	0
T10	56679	832	0	0
T11	0	6200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1993549	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	16	0	0
T4	10790	156	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1736	0	0
T8	526795	832	0	0
T9	123473	832	0	0
T10	56679	832	0	0
T11	0	6200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	5	0	926
T36	1139	0	0	1
T56	339677	1	0	1
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	1067	0	0	1
T62	23727	0	0	1
T63	222699	0	0	1
T64	2382	0	0	1
T65	1006	0	0	1
T66	1287	0	0	1
T67	972825	0	0	1
T68	65936	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	417517655	0	0
T1	117885	117785	0	0
T2	2827	2739	0	0
T3	1028	968	0	0
T4	10790	10740	0	0
T5	10122	10042	0	0
T6	1649	1551	0	0
T7	166880	166830	0	0
T8	526795	526710	0	0
T9	123473	123405	0	0
T10	56679	56595	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	417601744	1993549	0	0
T1	117885	832	0	0
T2	2827	832	0	0
T3	1028	16	0	0
T4	10790	156	0	0
T5	10122	832	0	0
T6	1649	0	0	0
T7	166880	1736	0	0
T8	526795	832	0	0
T9	123473	832	0	0
T10	56679	832	0	0
T11	0	6200	0	0