Unified Coverage Report :: Module :: spi_device_csr_assert_fpv

Module : spi_device_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_spi_device_csr_assert_0/spi_device_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.spi_device_csr_assert	100.00						100.00

---

Module Instance : tb.dut.spi_device_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.63	93.89	84.31	97.00		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : spi_device_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	58	58	100.00	58	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	58	58	100.00	58	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	419747884	3260	0	0
addr_swap_data_rd_A	419747884	998	0	0
addr_swap_mask_rd_A	419747884	972	0	0
cfg_rd_A	419747884	1218	0	0
cmd_filter_0_rd_A	419747884	3793	0	0
cmd_filter_1_rd_A	419747884	3735	0	0
cmd_filter_2_rd_A	419747884	4592	0	0
cmd_filter_3_rd_A	419747884	5210	0	0
cmd_filter_4_rd_A	419747884	5011	0	0
cmd_filter_5_rd_A	419747884	4498	0	0
cmd_filter_6_rd_A	419747884	5189	0	0
cmd_filter_7_rd_A	419747884	4677	0	0
cmd_info_0_rd_A	419747884	2562	0	0
cmd_info_10_rd_A	419747884	2256	0	0
cmd_info_11_rd_A	419747884	2734	0	0
cmd_info_12_rd_A	419747884	2472	0	0
cmd_info_13_rd_A	419747884	2754	0	0
cmd_info_14_rd_A	419747884	2507	0	0
cmd_info_15_rd_A	419747884	2512	0	0
cmd_info_16_rd_A	419747884	2163	0	0
cmd_info_17_rd_A	419747884	2571	0	0
cmd_info_18_rd_A	419747884	2472	0	0
cmd_info_19_rd_A	419747884	2449	0	0
cmd_info_1_rd_A	419747884	2431	0	0
cmd_info_20_rd_A	419747884	2414	0	0
cmd_info_21_rd_A	419747884	2587	0	0
cmd_info_22_rd_A	419747884	2614	0	0
cmd_info_23_rd_A	419747884	2491	0	0
cmd_info_2_rd_A	419747884	2646	0	0
cmd_info_3_rd_A	419747884	2626	0	0
cmd_info_4_rd_A	419747884	2626	0	0
cmd_info_5_rd_A	419747884	2331	0	0
cmd_info_6_rd_A	419747884	2583	0	0
cmd_info_7_rd_A	419747884	2452	0	0
cmd_info_8_rd_A	419747884	2482	0	0
cmd_info_9_rd_A	419747884	2283	0	0
cmd_info_en4b_rd_A	419747884	1016	0	0
cmd_info_ex4b_rd_A	419747884	1049	0	0
cmd_info_wrdi_rd_A	419747884	1116	0	0
cmd_info_wren_rd_A	419747884	1050	0	0
intercept_en_rd_A	419747884	1138	0	0
intr_enable_rd_A	419747884	2614	0	0
jedec_cc_rd_A	419747884	1140	0	0
jedec_id_rd_A	419747884	1037	0	0
mailbox_addr_rd_A	419747884	879	0	0
payload_swap_data_rd_A	419747884	963	0	0
payload_swap_mask_rd_A	419747884	906	0	0
read_threshold_rd_A	419747884	915	0	0
tpm_access_0_rd_A	419747884	1277	0	0
tpm_access_1_rd_A	419747884	869	0	0
tpm_cfg_rd_A	419747884	1402	0	0
tpm_did_vid_rd_A	419747884	1031	0	0
tpm_int_enable_rd_A	419747884	1002	0	0
tpm_int_status_rd_A	419747884	882	0	0
tpm_int_vector_rd_A	419747884	1005	0	0
tpm_intf_capability_rd_A	419747884	960	0	0
tpm_rid_rd_A	419747884	886	0	0
tpm_sts_rd_A	419747884	907	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	3260	0	0
T96	4058	128	0	0
T97	8668	4	0	0
T98	99810	4	0	0
T99	1993	1	0	0
T102	4654	5	0	0
T103	13175	156	0	0
T104	10126	143	0	0
T105	10404	215	0	0
T116	2414	4	0	0
T117	5390	13	0	0

addr_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	998	0	0
T82	3849	11	0	0
T84	4670	14	0	0
T98	99810	128	0	0
T111	5591	5	0	0
T121	12058	5	0	0
T126	7117	11	0	0
T127	180189	459	0	0
T154	32000	19	0	0
T155	7848	34	0	0
T156	7217	1	0	0

addr_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	972	0	0
T82	3849	6	0	0
T84	4670	5	0	0
T98	99810	120	0	0
T111	5591	10	0	0
T121	12058	8	0	0
T126	7117	7	0	0
T127	180189	435	0	0
T154	32000	29	0	0
T155	7848	43	0	0
T156	7217	18	0	0

cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1218	0	0
T82	3849	12	0	0
T84	4670	18	0	0
T98	99810	215	0	0
T111	5591	9	0	0
T121	12058	10	0	0
T126	7117	18	0	0
T127	180189	488	0	0
T154	32000	35	0	0
T155	7848	13	0	0
T156	7217	13	0	0

cmd_filter_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	3793	0	0
T82	3849	11	0	0
T84	4670	5	0	0
T98	99810	1614	0	0
T111	5591	15	0	0
T121	12058	157	0	0
T126	7117	4	0	0
T127	180189	426	0	0
T154	32000	429	0	0
T155	7848	29	0	0
T157	7422	26	0	0

cmd_filter_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	3735	0	0
T82	3849	8	0	0
T84	4670	12	0	0
T98	99810	1044	0	0
T111	5591	11	0	0
T121	12058	116	0	0
T126	7117	111	0	0
T127	180189	440	0	0
T154	32000	330	0	0
T155	7848	5	0	0
T156	7217	7	0	0

cmd_filter_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	4592	0	0
T82	3849	9	0	0
T84	4670	10	0	0
T98	99810	2107	0	0
T111	5591	10	0	0
T121	12058	141	0	0
T126	7117	137	0	0
T127	180189	449	0	0
T154	32000	242	0	0
T155	7848	6	0	0
T156	7217	34	0	0

cmd_filter_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	5210	0	0
T82	3849	10	0	0
T84	4670	7	0	0
T98	99810	2414	0	0
T111	5591	138	0	0
T121	12058	348	0	0
T127	180189	431	0	0
T154	32000	395	0	0
T156	7217	5	0	0
T157	7422	29	0	0
T158	5480	114	0	0

cmd_filter_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	5011	0	0
T82	3849	8	0	0
T84	4670	15	0	0
T98	99810	1912	0	0
T111	5591	128	0	0
T121	12058	121	0	0
T126	7117	133	0	0
T127	180189	432	0	0
T154	32000	245	0	0
T155	7848	15	0	0
T156	7217	7	0	0

cmd_filter_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	4498	0	0
T82	3849	9	0	0
T84	4670	9	0	0
T98	99810	1636	0	0
T111	5591	2	0	0
T121	12058	142	0	0
T126	7117	237	0	0
T127	180189	433	0	0
T154	32000	376	0	0
T155	7848	30	0	0
T156	7217	21	0	0

cmd_filter_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	5189	0	0
T84	4670	14	0	0
T98	99810	2359	0	0
T111	5591	149	0	0
T121	12058	238	0	0
T126	7117	8	0	0
T127	180189	526	0	0
T154	32000	704	0	0
T155	7848	3	0	0
T156	7217	25	0	0
T157	7422	13	0	0

cmd_filter_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	4677	0	0
T82	3849	7	0	0
T84	4670	7	0	0
T98	99810	1885	0	0
T111	5591	141	0	0
T121	12058	394	0	0
T126	7117	109	0	0
T127	180189	463	0	0
T154	32000	364	0	0
T155	7848	35	0	0
T156	7217	31	0	0

cmd_info_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2562	0	0
T82	3849	15	0	0
T84	4670	2	0	0
T98	99810	840	0	0
T111	5591	10	0	0
T121	12058	68	0	0
T126	7117	44	0	0
T127	180189	460	0	0
T154	32000	175	0	0
T155	7848	29	0	0
T156	7217	27	0	0

cmd_info_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2256	0	0
T82	3849	8	0	0
T84	4670	8	0	0
T98	99810	613	0	0
T111	5591	4	0	0
T121	12058	108	0	0
T126	7117	10	0	0
T127	180189	474	0	0
T154	32000	54	0	0
T155	7848	32	0	0
T156	7217	22	0	0

cmd_info_11_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2734	0	0
T82	3849	6	0	0
T84	4670	3	0	0
T98	99810	937	0	0
T111	5591	5	0	0
T121	12058	105	0	0
T126	7117	83	0	0
T127	180189	454	0	0
T154	32000	131	0	0
T155	7848	41	0	0
T156	7217	17	0	0

cmd_info_12_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2472	0	0
T82	3849	6	0	0
T84	4670	11	0	0
T98	99810	929	0	0
T111	5591	49	0	0
T121	12058	105	0	0
T126	7117	45	0	0
T127	180189	455	0	0
T154	32000	110	0	0
T155	7848	12	0	0
T156	7217	6	0	0

cmd_info_13_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2754	0	0
T82	3849	8	0	0
T84	4670	9	0	0
T98	99810	917	0	0
T111	5591	78	0	0
T121	12058	85	0	0
T126	7117	106	0	0
T127	180189	491	0	0
T154	32000	220	0	0
T155	7848	20	0	0
T157	7422	6	0	0

cmd_info_14_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2507	0	0
T82	3849	11	0	0
T84	4670	5	0	0
T98	99810	817	0	0
T111	5591	67	0	0
T121	12058	82	0	0
T126	7117	2	0	0
T127	180189	473	0	0
T154	32000	163	0	0
T155	7848	16	0	0
T156	7217	6	0	0

cmd_info_15_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2512	0	0
T82	3849	13	0	0
T84	4670	18	0	0
T98	99810	735	0	0
T111	5591	11	0	0
T121	12058	45	0	0
T126	7117	36	0	0
T127	180189	472	0	0
T154	32000	252	0	0
T155	7848	21	0	0
T156	7217	16	0	0

cmd_info_16_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2163	0	0
T82	3849	9	0	0
T84	4670	8	0	0
T98	99810	885	0	0
T111	5591	3	0	0
T121	12058	68	0	0
T126	7117	65	0	0
T127	180189	457	0	0
T154	32000	101	0	0
T156	7217	8	0	0
T157	7422	23	0	0

cmd_info_17_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2571	0	0
T82	3849	3	0	0
T84	4670	14	0	0
T98	99810	858	0	0
T111	5591	1	0	0
T121	12058	149	0	0
T126	7117	9	0	0
T127	180189	421	0	0
T154	32000	196	0	0
T155	7848	21	0	0
T156	7217	3	0	0

cmd_info_18_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2472	0	0
T82	3849	9	0	0
T84	4670	6	0	0
T98	99810	703	0	0
T111	5591	66	0	0
T121	12058	133	0	0
T126	7117	50	0	0
T127	180189	514	0	0
T154	32000	240	0	0
T155	7848	59	0	0
T156	7217	21	0	0

cmd_info_19_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2449	0	0
T82	3849	5	0	0
T84	4670	16	0	0
T98	99810	835	0	0
T111	5591	53	0	0
T121	12058	8	0	0
T126	7117	87	0	0
T127	180189	427	0	0
T154	32000	147	0	0
T155	7848	5	0	0
T156	7217	12	0	0

cmd_info_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2431	0	0
T82	3849	4	0	0
T84	4670	5	0	0
T98	99810	845	0	0
T111	5591	51	0	0
T121	12058	84	0	0
T126	7117	8	0	0
T127	180189	480	0	0
T154	32000	165	0	0
T155	7848	34	0	0
T156	7217	36	0	0

cmd_info_20_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2414	0	0
T82	3849	6	0	0
T84	4670	2	0	0
T98	99810	760	0	0
T111	5591	57	0	0
T121	12058	68	0	0
T126	7117	52	0	0
T127	180189	533	0	0
T154	32000	161	0	0
T155	7848	25	0	0
T156	7217	13	0	0

cmd_info_21_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2587	0	0
T82	3849	4	0	0
T84	4670	17	0	0
T98	99810	835	0	0
T111	5591	7	0	0
T121	12058	82	0	0
T126	7117	7	0	0
T127	180189	474	0	0
T154	32000	215	0	0
T155	7848	4	0	0
T156	7217	6	0	0

cmd_info_22_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2614	0	0
T82	3849	9	0	0
T84	4670	7	0	0
T98	99810	761	0	0
T111	5591	45	0	0
T121	12058	77	0	0
T126	7117	83	0	0
T127	180189	421	0	0
T154	32000	133	0	0
T155	7848	24	0	0
T156	7217	2	0	0

cmd_info_23_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2491	0	0
T82	3849	13	0	0
T84	4670	9	0	0
T98	99810	816	0	0
T111	5591	15	0	0
T121	12058	175	0	0
T126	7117	57	0	0
T127	180189	510	0	0
T154	32000	226	0	0
T155	7848	36	0	0
T157	7422	5	0	0

cmd_info_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2646	0	0
T82	3849	12	0	0
T84	4670	14	0	0
T98	99810	918	0	0
T111	5591	4	0	0
T121	12058	95	0	0
T126	7117	86	0	0
T127	180189	469	0	0
T154	32000	167	0	0
T155	7848	3	0	0
T156	7217	16	0	0

cmd_info_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2626	0	0
T82	3849	5	0	0
T84	4670	10	0	0
T98	99810	911	0	0
T111	5591	12	0	0
T121	12058	100	0	0
T126	7117	108	0	0
T127	180189	479	0	0
T154	32000	133	0	0
T155	7848	11	0	0
T156	7217	17	0	0

cmd_info_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2626	0	0
T82	3849	4	0	0
T84	4670	12	0	0
T98	99810	1020	0	0
T111	5591	53	0	0
T121	12058	46	0	0
T126	7117	12	0	0
T127	180189	518	0	0
T154	32000	183	0	0
T155	7848	30	0	0
T157	7422	52	0	0

cmd_info_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2331	0	0
T82	3849	10	0	0
T84	4670	10	0	0
T98	99810	672	0	0
T111	5591	65	0	0
T121	12058	70	0	0
T126	7117	91	0	0
T127	180189	451	0	0
T154	32000	123	0	0
T155	7848	9	0	0
T156	7217	1	0	0

cmd_info_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2583	0	0
T82	3849	4	0	0
T84	4670	14	0	0
T98	99810	830	0	0
T111	5591	2	0	0
T121	12058	110	0	0
T126	7117	45	0	0
T127	180189	454	0	0
T154	32000	122	0	0
T155	7848	7	0	0
T157	7422	1	0	0

cmd_info_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2452	0	0
T82	3849	7	0	0
T84	4670	13	0	0
T98	99810	879	0	0
T111	5591	10	0	0
T121	12058	62	0	0
T126	7117	95	0	0
T127	180189	414	0	0
T154	32000	106	0	0
T155	7848	32	0	0
T156	7217	15	0	0

cmd_info_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2482	0	0
T82	3849	11	0	0
T84	4670	4	0	0
T98	99810	809	0	0
T111	5591	52	0	0
T121	12058	98	0	0
T126	7117	2	0	0
T127	180189	461	0	0
T154	32000	169	0	0
T155	7848	7	0	0
T157	7422	21	0	0

cmd_info_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2283	0	0
T82	3849	10	0	0
T84	4670	14	0	0
T98	99810	702	0	0
T111	5591	63	0	0
T121	12058	59	0	0
T126	7117	34	0	0
T127	180189	443	0	0
T154	32000	178	0	0
T155	7848	37	0	0
T156	7217	16	0	0

cmd_info_en4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1016	0	0
T82	3849	11	0	0
T84	4670	16	0	0
T98	99810	159	0	0
T111	5591	8	0	0
T121	12058	13	0	0
T126	7117	9	0	0
T127	180189	436	0	0
T154	32000	24	0	0
T155	7848	4	0	0
T156	7217	16	0	0

cmd_info_ex4b_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1049	0	0
T82	3849	7	0	0
T84	4670	14	0	0
T98	99810	149	0	0
T111	5591	7	0	0
T121	12058	12	0	0
T126	7117	17	0	0
T127	180189	430	0	0
T154	32000	38	0	0
T155	7848	13	0	0
T156	7217	12	0	0

cmd_info_wrdi_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1116	0	0
T82	3849	14	0	0
T84	4670	14	0	0
T98	99810	130	0	0
T103	13175	9	0	0
T121	12058	26	0	0
T126	7117	20	0	0
T127	180189	397	0	0
T154	32000	39	0	0
T155	7848	37	0	0
T156	7217	14	0	0

cmd_info_wren_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1050	0	0
T82	3849	7	0	0
T84	4670	9	0	0
T98	99810	160	0	0
T111	5591	12	0	0
T121	12058	24	0	0
T126	7117	12	0	0
T127	180189	447	0	0
T154	32000	36	0	0
T155	7848	21	0	0
T156	7217	18	0	0

intercept_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1138	0	0
T82	3849	17	0	0
T84	4670	19	0	0
T98	99810	231	0	0
T111	5591	5	0	0
T121	12058	15	0	0
T126	7117	10	0	0
T127	180189	438	0	0
T154	32000	35	0	0
T155	7848	26	0	0
T156	7217	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	2614	0	0
T18	396944	10	0	0
T22	0	63	0	0
T31	0	6	0	0
T56	0	13	0	0
T89	11372	0	0	0
T139	0	44	0	0
T141	0	45	0	0
T159	0	42	0	0
T160	0	13	0	0
T161	0	16	0	0
T162	0	7	0	0
T163	144492	0	0	0
T164	24118	0	0	0
T165	392058	0	0	0
T166	62145	0	0	0
T167	44727	0	0	0
T168	3201	0	0	0
T169	421476	0	0	0
T170	229901	0	0	0

jedec_cc_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1140	0	0
T82	3849	8	0	0
T84	4670	15	0	0
T98	99810	156	0	0
T111	5591	15	0	0
T121	12058	16	0	0
T126	7117	9	0	0
T127	180189	484	0	0
T154	32000	37	0	0
T155	7848	28	0	0
T156	7217	2	0	0

jedec_id_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1037	0	0
T82	3849	12	0	0
T84	4670	8	0	0
T98	99810	184	0	0
T111	5591	14	0	0
T121	12058	17	0	0
T126	7117	4	0	0
T127	180189	435	0	0
T154	32000	45	0	0
T155	7848	33	0	0
T156	7217	1	0	0

mailbox_addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	879	0	0
T82	3849	11	0	0
T84	4670	14	0	0
T98	99810	98	0	0
T111	5591	12	0	0
T121	12058	6	0	0
T126	7117	9	0	0
T127	180189	466	0	0
T154	32000	11	0	0
T155	7848	41	0	0
T156	7217	15	0	0

payload_swap_data_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	963	0	0
T82	3849	4	0	0
T84	4670	4	0	0
T98	99810	135	0	0
T111	5591	6	0	0
T121	12058	14	0	0
T126	7117	5	0	0
T127	180189	433	0	0
T154	32000	27	0	0
T155	7848	25	0	0
T157	7422	19	0	0

payload_swap_mask_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	906	0	0
T82	3849	8	0	0
T84	4670	11	0	0
T98	99810	107	0	0
T111	5591	6	0	0
T121	12058	11	0	0
T126	7117	5	0	0
T127	180189	447	0	0
T154	32000	21	0	0
T155	7848	1	0	0
T156	7217	27	0	0

read_threshold_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	915	0	0
T82	3849	1	0	0
T84	4670	13	0	0
T98	99810	105	0	0
T111	5591	6	0	0
T121	12058	14	0	0
T126	7117	3	0	0
T127	180189	425	0	0
T154	32000	19	0	0
T155	7848	14	0	0
T156	7217	17	0	0

tpm_access_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1277	0	0
T82	3849	5	0	0
T84	4670	18	0	0
T98	99810	264	0	0
T111	5591	3	0	0
T121	12058	16	0	0
T126	7117	13	0	0
T127	180189	456	0	0
T154	32000	58	0	0
T155	7848	2	0	0
T156	7217	8	0	0

tpm_access_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	869	0	0
T82	3849	8	0	0
T84	4670	9	0	0
T98	99810	103	0	0
T111	5591	13	0	0
T121	12058	12	0	0
T126	7117	3	0	0
T127	180189	434	0	0
T154	32000	32	0	0
T155	7848	9	0	0
T156	7217	5	0	0

tpm_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1402	0	0
T82	3849	3	0	0
T84	4670	18	0	0
T98	99810	275	0	0
T111	5591	8	0	0
T121	12058	47	0	0
T126	7117	18	0	0
T127	180189	402	0	0
T154	32000	54	0	0
T155	7848	43	0	0
T156	7217	37	0	0

tpm_did_vid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1031	0	0
T82	3849	3	0	0
T84	4670	10	0	0
T98	99810	183	0	0
T111	5591	8	0	0
T121	12058	22	0	0
T126	7117	26	0	0
T127	180189	383	0	0
T154	32000	17	0	0
T155	7848	17	0	0
T156	7217	17	0	0

tpm_int_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1002	0	0
T82	3849	7	0	0
T84	4670	4	0	0
T98	99810	105	0	0
T111	5591	10	0	0
T121	12058	14	0	0
T126	7117	6	0	0
T127	180189	408	0	0
T154	32000	21	0	0
T155	7848	36	0	0
T156	7217	13	0	0

tpm_int_status_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	882	0	0
T82	3849	2	0	0
T84	4670	11	0	0
T98	99810	125	0	0
T111	5591	13	0	0
T121	12058	11	0	0
T126	7117	9	0	0
T127	180189	401	0	0
T154	32000	25	0	0
T155	7848	3	0	0
T156	7217	15	0	0

tpm_int_vector_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	1005	0	0
T82	3849	5	0	0
T84	4670	11	0	0
T98	99810	102	0	0
T104	10126	7	0	0
T121	12058	15	0	0
T126	7117	11	0	0
T127	180189	468	0	0
T154	32000	23	0	0
T155	7848	11	0	0
T156	7217	9	0	0

tpm_intf_capability_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	960	0	0
T82	3849	9	0	0
T84	4670	2	0	0
T98	99810	96	0	0
T111	5591	16	0	0
T121	12058	14	0	0
T126	7117	10	0	0
T127	180189	441	0	0
T154	32000	30	0	0
T155	7848	49	0	0
T157	7422	24	0	0

tpm_rid_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	886	0	0
T82	3849	5	0	0
T84	4670	10	0	0
T98	99810	107	0	0
T121	12058	4	0	0
T126	7117	10	0	0
T127	180189	413	0	0
T154	32000	23	0	0
T155	7848	9	0	0
T156	7217	24	0	0
T157	7422	38	0	0

tpm_sts_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419747884	907	0	0
T82	3849	8	0	0
T84	4670	13	0	0
T98	99810	107	0	0
T111	5591	2	0	0
T121	12058	13	0	0
T126	7117	3	0	0
T127	180189	463	0	0
T154	32000	23	0	0
T155	7848	11	0	0
T156	7217	8	0	0