Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2908710	1			T1	1		T2	563		T3	1
all_values[1]	2908710	1			T1	1		T2	563		T3	1
all_values[2]	2908710	1			T1	1		T2	563		T3	1
all_values[3]	2908710	1			T1	1		T2	563		T3	1
all_values[4]	2908710	1			T1	1		T2	563		T3	1
all_values[5]	2908710	1			T1	1		T2	563		T3	1
all_values[6]	2908710	1			T1	1		T2	563		T3	1
all_values[7]	2908710	1			T1	1		T2	563		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22335694

1

T1

8

T2

4504

T3

8

auto[1]

933986

1

T26

20

T18

130

T19

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23246460

1

T1

8

T2

4504

T3

8

auto[1]

23220

1

T14

345

T16

19

T26

139

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2789488	1			T1	1		T2	563		T3	1
all_values[0]	auto[0]	auto[1]	11257	1			T14	293		T16	9		T26	58
all_values[0]	auto[1]	auto[0]	106987	1			T26	2		T18	15		T19	5
all_values[0]	auto[1]	auto[1]	978	1			T26	2		T18	6		T19	1
all_values[1]	auto[0]	auto[0]	2741371	1			T1	1		T2	563		T3	1
all_values[1]	auto[0]	auto[1]	5554	1			T14	50		T16	9		T26	57
all_values[1]	auto[1]	auto[0]	161344	1			T26	5		T18	11		T20	3
all_values[1]	auto[1]	auto[1]	441	1			T26	1		T18	7		T19	1
all_values[2]	auto[0]	auto[0]	2783817	1			T1	1		T2	563		T3	1
all_values[2]	auto[0]	auto[1]	2542	1			T14	2		T16	1		T26	12
all_values[2]	auto[1]	auto[0]	122026	1			T26	2		T18	5		T19	1
all_values[2]	auto[1]	auto[1]	325	1			T18	7		T20	3		T45	6
all_values[3]	auto[0]	auto[0]	2819745	1			T1	1		T2	563		T3	1
all_values[3]	auto[0]	auto[1]	220	1			T18	7		T19	1		T20	4
all_values[3]	auto[1]	auto[0]	88567	1			T26	1		T18	9		T19	3
all_values[3]	auto[1]	auto[1]	178	1			T18	6		T20	7		T45	1
all_values[4]	auto[0]	auto[0]	2739269	1			T1	1		T2	563		T3	1
all_values[4]	auto[0]	auto[1]	212	1			T26	2		T18	10		T20	5
all_values[4]	auto[1]	auto[0]	169043	1			T26	1		T18	2		T19	1
all_values[4]	auto[1]	auto[1]	186	1			T26	1		T18	9		T19	1
all_values[5]	auto[0]	auto[0]	2786711	1			T1	1		T2	563		T3	1
all_values[5]	auto[0]	auto[1]	362	1			T26	1		T18	9		T262	6
all_values[5]	auto[1]	auto[0]	121469	1			T26	1		T18	14		T19	5
all_values[5]	auto[1]	auto[1]	168	1			T26	1		T18	4		T20	1
all_values[6]	auto[0]	auto[0]	2878334	1			T1	1		T2	563		T3	1
all_values[6]	auto[0]	auto[1]	216	1			T18	5		T19	1		T20	6
all_values[6]	auto[1]	auto[0]	29961	1			T26	2		T18	13		T19	1
all_values[6]	auto[1]	auto[1]	199	1			T18	4		T19	1		T20	6
all_values[7]	auto[0]	auto[0]	2776411	1			T1	1		T2	563		T3	1
all_values[7]	auto[0]	auto[1]	185	1			T26	3		T18	8		T19	2
all_values[7]	auto[1]	auto[0]	131917	1			T18	11		T19	1		T20	4
all_values[7]	auto[1]	auto[1]	197	1			T26	1		T18	7		T19	1