Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30530	1			T5	2		T7	2		T14	221
auto[SpiFlashAddrCfg]	6245	1			T4	2		T6	6		T14	64
auto[SpiFlashAddr3b]	7574	1			T3	6		T4	4		T13	4
auto[SpiFlashAddr4b]	6423	1			T4	4		T5	2		T13	3

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29154

1

T3

6

T5

4

T6

6

auto[1]

21618

1

T4

10

T14

169

T16

150

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26950

1

T3

6

T4

8

T7

2

auto[1]

23822

1

T4

2

T5

4

T6

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	34493	1			T3	2		T4	4		T5	2
values[1]	982	1			T4	2		T14	11		T16	4
values[2]	1194	1			T3	4		T14	11		T15	4
values[3]	1149	1			T14	15		T16	2		T26	2
values[4]	1177	1			T5	2		T13	1		T14	15
values[5]	1158	1			T14	7		T16	10		T26	2
values[6]	1247	1			T14	25		T16	11		T24	2
values[7]	1169	1			T14	19		T16	8		T26	2
values[8]	8203	1			T4	4		T6	6		T13	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27273

1

T3

6

T4

10

T5

4

auto[1]

23499

1

T13

7

T14

216

T41

305

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

49034

1

T3

6

T4

10

T5

2

write

1738

1

T5

2

T14

15

T16

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16305

1

T4

4

T5

2

T6

6

valids[0x1]

34467

1

T3

6

T4

6

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1253	1			T14	6		T16	3		T26	2
internal_process_ops[0x5a]	1295	1			T3	4		T4	4		T14	18
internal_process_ops[0x05]	19319	1			T14	69		T16	79		T26	10
internal_process_ops[0x35]	1286	1			T5	2		T14	22		T16	5
internal_process_ops[0x15]	1286	1			T14	8		T15	8		T16	3
internal_process_ops[0x03]	913	1			T14	9		T16	7		T49	2
internal_process_ops[0x0b]	897	1			T3	2		T14	4		T16	9
internal_process_ops[0x3b]	936	1			T13	1		T14	11		T16	7
internal_process_ops[0x6b]	889	1			T6	2		T13	1		T14	9
internal_process_ops[0xbb]	909	1			T13	3		T14	8		T16	2
internal_process_ops[0xeb]	903	1			T5	2		T6	4		T13	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49948

1

T3

6

T4

10

T5

4

auto[1]

824

1

T14

6

T16

4

T26

1

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48917

1

T3

6

T4

10

T5

4

auto[1]

1855

1

T14

26

T16

11

T26

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9219

1

T7

2

T14

69

T15

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5863

1

T14

39

T16

82

T26

12

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1945

1

T6

6

T14

14

T15

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1589

1

T4

2

T14

11

T16

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2258

1

T3

6

T14

26

T16

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1963

1

T4

4

T14

13

T16

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1853

1

T5

2

T14

11

T16

22

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1677

1

T4

4

T14

24

T16

16

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

58

1

T5

2

T14

2

T45

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

42

1

T14

1

T47

2

T163

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

66

1

T14

2

T16

5

T53

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

47

1

T16

2

T34

2

T40

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

68

1

T16

1

T39

2

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

39

1

T39

2

T43

3

T45

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

47

1

T16

2

T26

3

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

62

1

T14

3

T16

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

78

1

T14

1

T26

2

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

44

1

T16

1

T19

3

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

50

1

T34

5

T40

1

T66

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

60

1

T40

1

T43

2

T44

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

79

1

T14

1

T34

1

T53

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

53

1

T26

1

T39

1

T53

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

45

1

T16

1

T26

1

T34

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

68

1

T14

1

T66

1

T19

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9053

1

T14

72

T41

126

T51

68

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6004

1

T14

35

T41

89

T51

38

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1169

1

T14

24

T41

14

T51

16

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1129

1

T14

10

T41

13

T51

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1565

1

T13

4

T14

11

T41

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1348

1

T14

13

T41

9

T51

26

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1224

1

T13

3

T14

31

T41

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1175

1

T14

16

T41

12

T51

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

43

1

T51

3

T164

1

T165

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

47

1

T41

1

T166

2

T167

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

46

1

T14

1

T41

4

T164

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

42

1

T51

2

T165

1

T168

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

42

1

T14

2

T164

2

T167

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

62

1

T51

1

T164

1

T169

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

37

1

T51

2

T20

1

T170

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

56

1

T167

1

T171

1

T35

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

65

1

T41

4

T164

1

T167

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

32

1

T170

2

T171

1

T172

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

61

1

T51

6

T167

2

T170

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

50

1

T168

2

T172

1

T35

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

47

1

T41

1

T168

1

T78

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

69

1

T166

2

T167

2

T169

10

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

82

1

T41

2

T51

1

T164

5

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

51

1

T14

1

T167

2

T168

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3665	1			T7	2		T14	39		T16	41
auto[0]	values[0]	valids[0x1]	13773	1			T3	2		T4	4		T5	2
auto[0]	values[1]	valids[0x1]	523	1			T4	2		T14	7		T16	4
auto[0]	values[2]	valids[0x0]	466	1			T14	6		T15	4		T16	7
auto[0]	values[2]	valids[0x1]	257	1			T3	4		T14	1		T34	1
auto[0]	values[3]	valids[0x0]	458	1			T14	4		T16	2		T39	1
auto[0]	values[3]	valids[0x1]	258	1			T14	3		T26	2		T34	5
auto[0]	values[4]	valids[0x0]	454	1			T5	2		T14	2		T16	2
auto[0]	values[4]	valids[0x1]	261	1			T14	6		T25	2		T26	1
auto[0]	values[5]	valids[0x0]	436	1			T14	2		T16	5		T26	2
auto[0]	values[5]	valids[0x1]	278	1			T14	4		T16	5		T34	4
auto[0]	values[6]	valids[0x0]	493	1			T14	13		T16	2		T24	2
auto[0]	values[6]	valids[0x1]	280	1			T14	3		T16	9		T26	4
auto[0]	values[7]	valids[0x0]	480	1			T14	5		T16	5		T39	2
auto[0]	values[7]	valids[0x1]	236	1			T14	3		T16	3		T26	2
auto[0]	values[8]	valids[0x0]	3126	1			T4	4		T6	6		T14	26
auto[0]	values[8]	valids[0x1]	1829	1			T14	15		T15	2		T16	25
auto[1]	values[0]	valids[0x0]	3174	1			T14	66		T41	27		T51	57
auto[1]	values[0]	valids[0x1]	13881	1			T14	66		T41	210		T51	72
auto[1]	values[1]	valids[0x1]	459	1			T14	4		T41	4		T51	4
auto[1]	values[2]	valids[0x0]	276	1			T14	3		T41	3		T51	4
auto[1]	values[2]	valids[0x1]	195	1			T14	1		T41	2		T51	4
auto[1]	values[3]	valids[0x0]	252	1			T14	7		T41	2		T51	7
auto[1]	values[3]	valids[0x1]	181	1			T14	1		T41	1		T51	1
auto[1]	values[4]	valids[0x0]	269	1			T13	1		T14	4		T51	1
auto[1]	values[4]	valids[0x1]	193	1			T14	3		T41	2		T51	5
auto[1]	values[5]	valids[0x0]	262	1			T14	1		T41	2		T51	6
auto[1]	values[5]	valids[0x1]	182	1			T41	5		T51	4		T166	2
auto[1]	values[6]	valids[0x0]	303	1			T14	5		T41	5		T51	6
auto[1]	values[6]	valids[0x1]	171	1			T14	4		T41	6		T51	1
auto[1]	values[7]	valids[0x0]	272	1			T14	10		T41	6		T51	3
auto[1]	values[7]	valids[0x1]	181	1			T14	1		T51	3		T164	10
auto[1]	values[8]	valids[0x0]	1919	1			T13	6		T14	30		T41	18
auto[1]	values[8]	valids[0x1]	1329	1			T14	10		T41	12		T51	18