Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3073948

1

T3

7843

T4

1

T5

1

auto[1]

18021

1

T14

54

T16

73

T26

8

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054623

1

T3

7843

T4

1

T5

1

auto[1]

2037346

1

T14

27309

T15

11322

T16

8973

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	549984	1			T3	1114		T4	1		T5	1
auto[524288:1048575]	363360	1			T6	1024		T14	2608		T16	265
auto[1048576:1572863]	326146	1			T3	786		T6	1		T13	466
auto[1572864:2097151]	342988	1			T3	2		T6	1		T7	2
auto[2097152:2621439]	375060	1			T3	417		T14	8289		T16	1094
auto[2621440:3145727]	382813	1			T3	4661		T6	623		T7	42
auto[3145728:3670015]	365343	1			T6	2445		T13	2		T14	271
auto[3670016:4194303]	386275	1			T3	863		T6	3074		T13	970

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2056252

1

T3

13

T4

1

T5

1

auto[1]

1035717

1

T3

7830

T6

7708

T7

42

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2771554

1

T3

7843

T4

1

T5

1

auto[1]

320415

1

T7

2

T14

2877

T16

3930

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	200714	1			T3	1114		T4	1		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	311428	1			T14	3060		T15	11322		T16	2
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	101656	1			T6	1024		T14	5		T16	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	209610	1			T14	2460		T16	257		T26	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	132059	1			T3	786		T6	1		T13	466
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	168863	1			T14	2126		T16	5		T39	1028
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	108600	1			T3	2		T6	1		T7	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	196238	1			T14	769		T16	1		T39	256
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	95140	1			T3	417		T14	19		T16	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	243854	1			T14	8254		T16	1089		T26	6286
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	137440	1			T3	4661		T6	623		T7	42
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	203656	1			T14	5831		T16	803		T26	2729
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	142799	1			T6	2445		T13	2		T14	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	171797	1			T14	265		T16	1		T41	5
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	126340	1			T3	863		T6	3074		T13	970
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	206451	1			T14	1668		T16	2884		T41	3264
auto[0]	auto[1]	auto[0:524287]	auto[0]	484	1			T7	2		T16	1		T85	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	34442	1			T16	256		T53	1		T164	515
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	199	1			T14	5		T16	3		T34	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	49576	1			T14	130		T51	263		T18	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	964	1			T16	3		T51	1		T53	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	22510	1			T16	6		T164	37		T43	256
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	247	1			T14	11		T16	9		T34	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	35664	1			T14	1148		T16	3607		T34	2574
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1690	1			T14	2		T16	1		T26	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	32142	1			T41	20		T34	1877		T51	128
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	623	1			T14	3		T16	1		T85	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	39265	1			T14	1		T34	257		T166	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2740	1			T85	2		T34	2		T40	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	45370	1			T34	1829		T40	256		T66	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1071	1			T14	2		T85	2		T34	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	50316	1			T14	1569		T51	917		T40	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	237	1			T14	4		T16	2		T26	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2049	1			T14	7		T16	15		T40	29
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	177	1			T14	3		T16	1		T26	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1912	1			T14	2		T26	1		T39	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	175	1			T14	4		T16	1		T39	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1243	1			T14	2		T16	1		T39	11
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	203	1			T14	1		T16	1		T34	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1720	1			T14	1		T16	3		T34	27
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	167	1			T14	5		T26	3		T41	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1664	1			T14	9		T26	2		T41	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	188	1			T14	2		T16	1		T39	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1285	1			T14	2		T16	3		T39	28
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	210	1			T14	1		T16	1		T41	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1811	1			T14	2		T16	1		T41	42
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	171	1			T14	2		T41	4		T34	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1697	1			T14	1		T41	44		T53	110
auto[1]	auto[1]	auto[0:524287]	auto[0]	51	1			T53	1		T164	3		T20	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	579	1			T53	24		T164	22		T165	22
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	28	1			T14	2		T51	4		T164	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	202	1			T14	1		T51	2		T164	23
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	40	1			T16	2		T165	3		T163	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	292	1			T16	12		T165	27		T163	17
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	40	1			T14	2		T16	2		T51	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	276	1			T14	1		T16	27		T20	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	41	1			T40	1		T166	1		T47	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	362	1			T40	8		T47	12		T165	20
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	40	1			T34	1		T166	1		T43	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	316	1			T34	1		T166	4		T43	14
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	52	1			T164	1		T167	2		T47	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	564	1			T164	60		T167	16		T47	13
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	37	1			T51	1		T40	1		T20	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	192	1			T40	36		T20	7		T168	8

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1727395	1			T3	13		T4	1		T5	1
auto[0]	auto[0]	auto[1]	1029250	1			T3	7830		T6	7708		T7	42
auto[0]	auto[1]	auto[0]	311200	1			T7	2		T14	2871		T16	3887
auto[0]	auto[1]	auto[1]	6103	1			T164	4		T43	1		T47	1
auto[1]	auto[0]	auto[0]	14624	1			T14	47		T16	27		T26	8
auto[1]	auto[0]	auto[1]	285	1			T14	1		T16	3		T39	1
auto[1]	auto[1]	auto[0]	3033	1			T14	5		T16	41		T34	2
auto[1]	auto[1]	auto[1]	79	1			T14	1		T16	2		T51	2