Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15736

1

T3

6

T5

4

T6

6

auto[1]

11537

1

T4

10

T14

93

T16

150

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4230	1			T14	89		T16	20		T24	6
values[1]	2946	1			T14	21		T34	21		T40	40
values[2]	3542	1			T4	10		T14	40		T16	75
values[3]	3396	1			T6	6		T16	41		T48	8
values[4]	3364	1			T3	6		T7	2		T39	20
values[5]	3139	1			T14	20		T16	61		T26	68
values[6]	2934	1			T14	22		T15	16		T16	36
values[7]	3722	1			T5	4		T14	26		T16	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3559	1			T16	51		T25	2		T90	16
values[1]	3574	1			T14	20		T16	20		T26	23
values[2]	3180	1			T3	6		T6	6		T49	8
values[3]	2699	1			T14	49		T16	65		T48	8
values[4]	3280	1			T5	4		T7	2		T14	48
values[5]	3392	1			T14	67		T15	16		T26	20
values[6]	4033	1			T24	6		T26	22		T39	40
values[7]	3556	1			T4	10		T14	34		T16	61

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	360	1			T295	22		T45	7		T47	52
auto[0]	values[0]	values[1]	539	1			T40	56		T66	12		T35	18
auto[0]	values[0]	values[2]	420	1			T40	12		T196	16		T20	9
auto[0]	values[0]	values[3]	218	1			T14	20		T214	12		T47	11
auto[0]	values[0]	values[4]	324	1			T16	13		T40	69		T35	16
auto[0]	values[0]	values[5]	127	1			T14	18		T34	12		T59	8
auto[0]	values[0]	values[6]	371	1			T24	6		T39	8		T192	16
auto[0]	values[0]	values[7]	228	1			T14	16		T34	10		T43	13
auto[0]	values[1]	values[0]	276	1			T34	12		T181	19		T184	16
auto[0]	values[1]	values[1]	133	1			T66	17		T47	10		T296	14
auto[0]	values[1]	values[2]	156	1			T224	31		T297	6		T36	10
auto[0]	values[1]	values[3]	181	1			T298	4		T183	16		T35	13
auto[0]	values[1]	values[4]	314	1			T53	85		T66	29		T203	24
auto[0]	values[1]	values[5]	263	1			T14	8		T66	11		T87	4
auto[0]	values[1]	values[6]	310	1			T19	12		T42	16		T299	14
auto[0]	values[1]	values[7]	99	1			T40	18		T161	2		T45	12
auto[0]	values[2]	values[0]	236	1			T16	8		T39	8		T57	10
auto[0]	values[2]	values[1]	138	1			T194	18		T300	10		T54	10
auto[0]	values[2]	values[2]	390	1			T34	14		T208	10		T202	8
auto[0]	values[2]	values[3]	332	1			T14	7		T16	14		T39	9
auto[0]	values[2]	values[4]	169	1			T54	21		T59	10		T301	4
auto[0]	values[2]	values[5]	192	1			T14	13		T26	9		T59	12
auto[0]	values[2]	values[6]	349	1			T40	7		T76	16		T43	11
auto[0]	values[2]	values[7]	345	1			T302	6		T176	20		T303	45
auto[0]	values[3]	values[0]	284	1			T43	18		T216	4		T188	10
auto[0]	values[3]	values[1]	320	1			T16	12		T34	16		T19	13
auto[0]	values[3]	values[2]	42	1			T6	6		T49	8		T136	9
auto[0]	values[3]	values[3]	242	1			T16	11		T48	8		T39	13
auto[0]	values[3]	values[4]	342	1			T53	71		T99	10		T43	12
auto[0]	values[3]	values[5]	242	1			T53	58		T177	10		T57	18
auto[0]	values[3]	values[6]	201	1			T34	10		T43	11		T59	9
auto[0]	values[3]	values[7]	268	1			T40	84		T177	36		T59	7
auto[0]	values[4]	values[0]	240	1			T210	10		T19	15		T163	12
auto[0]	values[4]	values[1]	265	1			T53	12		T210	15		T47	9
auto[0]	values[4]	values[2]	280	1			T3	6		T43	13		T163	12
auto[0]	values[4]	values[3]	168	1			T200	4		T45	31		T47	12
auto[0]	values[4]	values[4]	120	1			T7	2		T45	12		T54	10
auto[0]	values[4]	values[5]	194	1			T34	18		T59	19		T255	8
auto[0]	values[4]	values[6]	304	1			T39	15		T40	9		T47	27
auto[0]	values[4]	values[7]	129	1			T43	25		T54	6		T304	2
auto[0]	values[5]	values[0]	172	1			T173	19		T305	13		T234	22
auto[0]	values[5]	values[1]	144	1			T14	11		T26	12		T135	2
auto[0]	values[5]	values[2]	199	1			T34	13		T77	2		T177	52
auto[0]	values[5]	values[3]	101	1			T20	12		T197	14		T246	8
auto[0]	values[5]	values[4]	256	1			T26	17		T182	10		T211	8
auto[0]	values[5]	values[5]	212	1			T54	14		T224	10		T306	10
auto[0]	values[5]	values[6]	311	1			T26	12		T307	22		T184	16
auto[0]	values[5]	values[7]	484	1			T16	22		T66	7		T163	57
auto[0]	values[6]	values[0]	242	1			T34	15		T40	9		T43	12
auto[0]	values[6]	values[1]	265	1			T40	6		T53	12		T206	8
auto[0]	values[6]	values[2]	138	1			T30	10		T133	16		T59	36
auto[0]	values[6]	values[3]	120	1			T34	11		T53	10		T181	7
auto[0]	values[6]	values[4]	209	1			T14	13		T16	10		T34	16
auto[0]	values[6]	values[5]	306	1			T15	16		T85	24		T177	74
auto[0]	values[6]	values[6]	176	1			T181	16		T256	13		T230	14
auto[0]	values[6]	values[7]	144	1			T34	14		T59	11		T224	12
auto[0]	values[7]	values[0]	245	1			T25	2		T40	16		T35	11
auto[0]	values[7]	values[1]	357	1			T190	8		T308	22		T195	12
auto[0]	values[7]	values[2]	326	1			T66	17		T43	38		T45	51
auto[0]	values[7]	values[3]	192	1			T16	13		T112	4		T193	14
auto[0]	values[7]	values[4]	178	1			T5	4		T14	19		T207	4
auto[0]	values[7]	values[5]	209	1			T34	13		T40	11		T186	12
auto[0]	values[7]	values[6]	300	1			T187	12		T45	9		T173	20
auto[0]	values[7]	values[7]	339	1			T40	17		T53	14		T174	6
auto[1]	values[0]	values[0]	168	1			T45	13		T47	7		T30	11
auto[1]	values[0]	values[1]	193	1			T40	8		T66	13		T35	5
auto[1]	values[0]	values[2]	335	1			T40	8		T20	12		T45	10
auto[1]	values[0]	values[3]	133	1			T14	9		T47	33		T181	23
auto[1]	values[0]	values[4]	186	1			T16	7		T40	18		T35	10
auto[1]	values[0]	values[5]	153	1			T14	8		T34	11		T59	23
auto[1]	values[0]	values[6]	215	1			T39	12		T47	51		T30	7
auto[1]	values[0]	values[7]	260	1			T14	18		T34	11		T43	7
auto[1]	values[1]	values[0]	192	1			T34	9		T181	4		T184	8
auto[1]	values[1]	values[1]	101	1			T66	3		T47	10		T231	11
auto[1]	values[1]	values[2]	120	1			T224	11		T36	22		T230	6
auto[1]	values[1]	values[3]	70	1			T35	9		T227	9		T235	10
auto[1]	values[1]	values[4]	195	1			T53	14		T66	12		T163	58
auto[1]	values[1]	values[5]	314	1			T14	13		T66	9		T59	16
auto[1]	values[1]	values[6]	68	1			T19	13		T42	7		T136	12
auto[1]	values[1]	values[7]	154	1			T40	22		T45	22		T173	13
auto[1]	values[2]	values[0]	144	1			T16	43		T39	12		T217	12
auto[1]	values[2]	values[1]	142	1			T54	10		T61	6		T36	6
auto[1]	values[2]	values[2]	186	1			T34	6		T43	9		T175	4
auto[1]	values[2]	values[3]	214	1			T14	13		T16	10		T39	14
auto[1]	values[2]	values[4]	250	1			T54	6		T59	10		T36	13
auto[1]	values[2]	values[5]	102	1			T14	7		T26	11		T59	8
auto[1]	values[2]	values[6]	175	1			T40	13		T43	13		T181	15
auto[1]	values[2]	values[7]	178	1			T4	10		T57	87		T260	8
auto[1]	values[3]	values[0]	269	1			T43	2		T224	8		T136	59
auto[1]	values[3]	values[1]	195	1			T16	8		T34	5		T19	21
auto[1]	values[3]	values[2]	18	1			T136	11		T243	7		-	-
auto[1]	values[3]	values[3]	224	1			T16	10		T39	48		T34	8
auto[1]	values[3]	values[4]	203	1			T53	11		T43	11		T177	10
auto[1]	values[3]	values[5]	157	1			T53	6		T46	20		T177	10
auto[1]	values[3]	values[6]	176	1			T34	10		T205	12		T43	10
auto[1]	values[3]	values[7]	213	1			T40	9		T189	16		T177	11
auto[1]	values[4]	values[0]	217	1			T210	122		T19	10		T163	8
auto[1]	values[4]	values[1]	287	1			T53	65		T210	5		T47	11
auto[1]	values[4]	values[2]	145	1			T43	10		T44	4		T163	13
auto[1]	values[4]	values[3]	103	1			T45	13		T47	27		T195	12
auto[1]	values[4]	values[4]	209	1			T45	27		T309	6		T54	14
auto[1]	values[4]	values[5]	249	1			T34	5		T59	21		T255	12
auto[1]	values[4]	values[6]	321	1			T39	5		T40	63		T47	5
auto[1]	values[4]	values[7]	133	1			T43	3		T54	20		T258	11
auto[1]	values[5]	values[0]	102	1			T90	16		T310	2		T173	9
auto[1]	values[5]	values[1]	110	1			T14	9		T26	11		T59	7
auto[1]	values[5]	values[2]	137	1			T34	7		T177	6		T35	18
auto[1]	values[5]	values[3]	82	1			T20	8		T245	22		T246	12
auto[1]	values[5]	values[4]	106	1			T26	6		T224	4		T136	9
auto[1]	values[5]	values[5]	176	1			T54	15		T224	10		T255	8
auto[1]	values[5]	values[6]	302	1			T26	10		T184	4		T54	18
auto[1]	values[5]	values[7]	245	1			T16	39		T66	13		T163	21
auto[1]	values[6]	values[0]	208	1			T34	5		T40	48		T43	8
auto[1]	values[6]	values[1]	219	1			T40	14		T53	16		T19	3
auto[1]	values[6]	values[2]	65	1			T30	11		T59	14		T225	7
auto[1]	values[6]	values[3]	160	1			T34	9		T53	10		T181	17
auto[1]	values[6]	values[4]	135	1			T14	9		T16	26		T34	5
auto[1]	values[6]	values[5]	181	1			T177	4		T30	20		T163	14
auto[1]	values[6]	values[6]	235	1			T181	6		T60	8		T256	7
auto[1]	values[6]	values[7]	131	1			T34	7		T59	9		T178	8
auto[1]	values[7]	values[0]	204	1			T40	6		T35	9		T224	99
auto[1]	values[7]	values[1]	166	1			T195	14		T234	8		T280	47
auto[1]	values[7]	values[2]	223	1			T66	3		T43	19		T180	18
auto[1]	values[7]	values[3]	159	1			T16	7		T43	22		T173	7
auto[1]	values[7]	values[4]	84	1			T14	7		T185	2		T47	3
auto[1]	values[7]	values[5]	315	1			T34	36		T40	9		T58	112
auto[1]	values[7]	values[6]	219	1			T45	17		T173	20		T59	9
auto[1]	values[7]	values[7]	206	1			T40	7		T53	39		T45	16