Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2908710	1			T1	1		T2	563		T3	1
all_pins[1]	2908710	1			T1	1		T2	563		T3	1
all_pins[2]	2908710	1			T1	1		T2	563		T3	1
all_pins[3]	2908710	1			T1	1		T2	563		T3	1
all_pins[4]	2908710	1			T1	1		T2	563		T3	1
all_pins[5]	2908710	1			T1	1		T2	563		T3	1
all_pins[6]	2908710	1			T1	1		T2	563		T3	1
all_pins[7]	2908710	1			T1	1		T2	563		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23234325	1			T1	8		T2	4504		T3	8
values[0x1]	35355	1			T26	6		T18	50		T19	5
transitions[0x0=>0x1]	33580	1			T26	6		T18	40		T19	4
transitions[0x1=>0x0]	33591	1			T26	6		T18	40		T19	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2907641	1			T1	1		T2	563		T3	1
all_pins[0]	values[0x1]	1069	1			T26	2		T18	6		T19	1
all_pins[0]	transitions[0x0=>0x1]	785	1			T26	2		T18	6		T19	1
all_pins[0]	transitions[0x1=>0x0]	187	1			T26	1		T18	7		T19	1
all_pins[1]	values[0x0]	2908239	1			T1	1		T2	563		T3	1
all_pins[1]	values[0x1]	471	1			T26	1		T18	7		T19	1
all_pins[1]	transitions[0x0=>0x1]	301	1			T26	1		T18	3		T19	1
all_pins[1]	transitions[0x1=>0x0]	165	1			T18	3		T45	4		T31	6
all_pins[2]	values[0x0]	2908375	1			T1	1		T2	563		T3	1
all_pins[2]	values[0x1]	335	1			T18	7		T20	3		T45	8
all_pins[2]	transitions[0x0=>0x1]	272	1			T18	6		T45	7		T31	4
all_pins[2]	transitions[0x1=>0x0]	115	1			T18	5		T20	4		T31	1
all_pins[3]	values[0x0]	2908532	1			T1	1		T2	563		T3	1
all_pins[3]	values[0x1]	178	1			T18	6		T20	7		T45	1
all_pins[3]	transitions[0x0=>0x1]	131	1			T18	4		T20	7		T45	1
all_pins[3]	transitions[0x1=>0x0]	139	1			T26	1		T18	7		T19	1
all_pins[4]	values[0x0]	2908524	1			T1	1		T2	563		T3	1
all_pins[4]	values[0x1]	186	1			T26	1		T18	9		T19	1
all_pins[4]	transitions[0x0=>0x1]	152	1			T26	1		T18	8		T19	1
all_pins[4]	transitions[0x1=>0x0]	3663	1			T26	1		T18	3		T20	1
all_pins[5]	values[0x0]	2905013	1			T1	1		T2	563		T3	1
all_pins[5]	values[0x1]	3697	1			T26	1		T18	4		T20	1
all_pins[5]	transitions[0x0=>0x1]	2626	1			T26	1		T18	3		T31	3
all_pins[5]	transitions[0x1=>0x0]	28151	1			T18	3		T19	1		T20	5
all_pins[6]	values[0x0]	2879488	1			T1	1		T2	563		T3	1
all_pins[6]	values[0x1]	29222	1			T18	4		T19	1		T20	6
all_pins[6]	transitions[0x0=>0x1]	29170	1			T18	4		T20	2		T45	3
all_pins[6]	transitions[0x1=>0x0]	145	1			T26	1		T18	7		T20	2
all_pins[7]	values[0x0]	2908513	1			T1	1		T2	563		T3	1
all_pins[7]	values[0x1]	197	1			T26	1		T18	7		T19	1
all_pins[7]	transitions[0x0=>0x1]	143	1			T26	1		T18	6		T19	1
all_pins[7]	transitions[0x1=>0x0]	1026	1			T26	2		T18	5		T19	1