Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	371	1			T14	1		T16	2		T48	2
auto[ReadAddrCrossIntoMailbox]	287	1			T14	1		T16	2		T34	6
auto[ReadAddrCrossOutOfMailbox]	281	1			T14	2		T16	1		T26	3
auto[ReadAddrCrossAllMailbox]	203	1			T14	3		T16	2		T26	2
auto[ReadAddrOutsideMailbox]	3086	1			T3	2		T5	2		T6	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2136

1

T3

1

T5

1

T6

3

auto[1]

2092

1

T3

1

T5

1

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	689	1			T14	8		T16	7		T49	2
read_ops[0x0b]	692	1			T3	2		T14	4		T16	9
read_ops[0x3b]	736	1			T14	7		T16	7		T26	3
read_ops[0x6b]	707	1			T6	2		T14	8		T16	4
read_ops[0xbb]	681	1			T14	6		T16	2		T26	2
read_ops[0xeb]	723	1			T5	2		T6	4		T14	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T34	1		T40	3		T53	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T40	2		T206	1		T19	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T34	1		T53	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T40	4		T35	1		T57	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T14	1		T34	1		T40	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T40	1		T173	1		T62	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T16	1		T34	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T14	1		T19	2		T57	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	254	1			T14	4		T16	5		T49	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T14	2		T16	1		T49	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T43	1		T47	2		T30	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T16	1		T40	1		T57	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T40	1		T47	1		T177	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T34	1		T188	1		T35	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T14	1		T40	1		T181	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T40	1		T53	1		T66	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T34	1		T53	1		T206	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T206	1		T285	1		T47	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T3	1		T14	1		T16	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T3	1		T14	2		T16	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T16	1		T34	1		T53	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T34	1		T53	1		T285	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T34	2		T40	3		T19	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T40	1		T19	1		T163	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T16	1		T26	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T40	3		T43	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T16	1		T40	2		T206	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T34	2		T206	1		T163	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T14	6		T16	1		T90	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T14	1		T16	3		T26	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T53	1		T43	1		T47	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T39	1		T66	1		T47	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T47	1		T307	1		T188	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T34	1		T307	1		T188	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T34	1		T285	1		T307	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T26	2		T34	1		T40	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T40	2		T53	1		T177	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T26	1		T47	1		T136	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T6	1		T14	3		T16	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T6	1		T14	5		T16	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T40	1		T66	1		T19	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T39	1		T40	2		T53	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T34	1		T40	1		T66	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T16	1		T40	2		T66	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T34	2		T40	1		T206	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T40	1		T206	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T19	2		T45	1		T307	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T14	1		T26	1		T30	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	252	1			T14	4		T26	1		T39	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	233	1			T14	1		T16	1		T39	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T48	1		T34	1		T53	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T14	1		T48	1		T53	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T47	1		T307	1		T57	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T14	1		T16	1		T53	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T34	2		T53	1		T66	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T43	1		T285	1		T35	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T40	1		T53	1		T45	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T14	1		T66	1		T19	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	278	1			T5	1		T6	2		T14	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T5	1		T6	2		T14	2