Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3920	1			T26	22		T39	84		T34	40
values[1]	3067	1			T14	56		T39	20		T34	91
values[2]	3503	1			T14	26		T16	20		T26	20
values[3]	3356	1			T5	4		T6	6		T14	20
values[4]	3474	1			T7	2		T34	20		T40	23
values[5]	3583	1			T4	10		T14	61		T15	16
values[6]	3353	1			T14	55		T16	61		T49	8
values[7]	3017	1			T3	6		T16	87		T34	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3601	1			T3	6		T4	10		T14	26
values[1]	2838	1			T16	20		T24	6		T25	2
values[2]	2918	1			T14	21		T16	20		T39	20
values[3]	3615	1			T6	6		T14	48		T16	97
values[4]	3897	1			T14	83		T16	21		T26	23
values[5]	3364	1			T7	2		T14	20		T26	20
values[6]	3402	1			T5	4		T14	20		T15	16
values[7]	3638	1			T16	44		T26	22		T34	21

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26858

1

T3

6

T4

10

T5

4

auto[1]

415

1

T14

5

T16

4

T26

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[1]]	0	1	1
[auto[1]]	[values[6]]	[values[6]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	591	1			T40	20		T173	28		T136	146
auto[0]	values[0]	values[1]	258	1			T174	6		T175	4		T176	20
auto[0]	values[0]	values[2]	408	1			T66	20		T45	34		T47	59
auto[0]	values[0]	values[3]	546	1			T34	20		T177	20		T30	23
auto[0]	values[0]	values[4]	746	1			T39	84		T34	20		T40	192
auto[0]	values[0]	values[5]	260	1			T43	23		T57	64		T59	20
auto[0]	values[0]	values[6]	702	1			T40	40		T173	20		T35	52
auto[0]	values[0]	values[7]	367	1			T26	21		T47	30		T59	20
auto[0]	values[1]	values[0]	115	1			T59	19		T178	8		T179	51
auto[0]	values[1]	values[1]	285	1			T66	20		T87	4		T45	26
auto[0]	values[1]	values[2]	398	1			T180	18		T181	24		T35	25
auto[0]	values[1]	values[3]	458	1			T14	21		T181	26		T59	20
auto[0]	values[1]	values[4]	383	1			T14	34		T34	70		T161	2
auto[0]	values[1]	values[5]	395	1			T39	20		T35	28		T59	40
auto[0]	values[1]	values[6]	605	1			T53	28		T19	52		T182	10
auto[0]	values[1]	values[7]	376	1			T34	19		T183	16		T184	24
auto[0]	values[2]	values[0]	436	1			T14	26		T90	16		T185	2
auto[0]	values[2]	values[1]	420	1			T16	20		T48	8		T34	20
auto[0]	values[2]	values[2]	331	1			T186	12		T187	12		T163	20
auto[0]	values[2]	values[3]	521	1			T43	20		T163	51		T188	10
auto[0]	values[2]	values[4]	452	1			T189	16		T190	8		T47	20
auto[0]	values[2]	values[5]	441	1			T26	20		T47	44		T30	20
auto[0]	values[2]	values[6]	248	1			T99	10		T191	14		T54	20
auto[0]	values[2]	values[7]	599	1			T43	20		T192	16		T177	46
auto[0]	values[3]	values[0]	542	1			T39	18		T34	21		T40	91
auto[0]	values[3]	values[1]	318	1			T25	2		T43	23		T35	28
auto[0]	values[3]	values[2]	324	1			T39	19		T53	135		T66	20
auto[0]	values[3]	values[3]	334	1			T6	6		T193	14		T194	18
auto[0]	values[3]	values[4]	428	1			T35	20		T54	21		T195	49
auto[0]	values[3]	values[5]	567	1			T14	20		T34	20		T20	20
auto[0]	values[3]	values[6]	390	1			T5	4		T42	22		T30	21
auto[0]	values[3]	values[7]	403	1			T53	74		T43	18		T195	25
auto[0]	values[4]	values[0]	315	1			T53	64		T45	28		T30	52
auto[0]	values[4]	values[1]	309	1			T34	20		T53	70		T59	20
auto[0]	values[4]	values[2]	385	1			T40	23		T196	16		T19	25
auto[0]	values[4]	values[3]	475	1			T47	20		T197	14		T54	62
auto[0]	values[4]	values[4]	523	1			T43	20		T45	33		T47	37
auto[0]	values[4]	values[5]	577	1			T7	2		T198	2		T47	42
auto[0]	values[4]	values[6]	336	1			T53	28		T66	18		T199	10
auto[0]	values[4]	values[7]	508	1			T184	20		T59	49		T62	12
auto[0]	values[5]	values[0]	548	1			T4	10		T34	21		T66	24
auto[0]	values[5]	values[1]	413	1			T24	6		T40	22		T66	20
auto[0]	values[5]	values[2]	276	1			T14	20		T112	4		T200	4
auto[0]	values[5]	values[3]	286	1			T16	60		T26	23		T34	23
auto[0]	values[5]	values[4]	632	1			T14	20		T26	23		T201	2
auto[0]	values[5]	values[5]	483	1			T85	24		T66	20		T202	8
auto[0]	values[5]	values[6]	398	1			T14	20		T15	16		T203	24
auto[0]	values[5]	values[7]	492	1			T16	24		T66	19		T204	14
auto[0]	values[6]	values[0]	492	1			T40	24		T205	12		T43	20
auto[0]	values[6]	values[1]	539	1			T34	21		T40	20		T53	20
auto[0]	values[6]	values[2]	428	1			T16	20		T206	8		T19	25
auto[0]	values[6]	values[3]	366	1			T14	26		T49	8		T207	4
auto[0]	values[6]	values[4]	411	1			T14	26		T16	21		T40	40
auto[0]	values[6]	values[5]	355	1			T34	20		T208	10		T44	2
auto[0]	values[6]	values[6]	285	1			T209	8		T54	20		T58	125
auto[0]	values[6]	values[7]	415	1			T16	20		T77	2		T210	20
auto[0]	values[7]	values[0]	505	1			T3	6		T16	51		T211	8
auto[0]	values[7]	values[1]	262	1			T35	65		T59	20		T212	2
auto[0]	values[7]	values[2]	333	1			T66	20		T163	23		T54	20
auto[0]	values[7]	values[3]	570	1			T16	33		T40	64		T53	73
auto[0]	values[7]	values[4]	271	1			T43	23		T57	20		T213	20
auto[0]	values[7]	values[5]	227	1			T34	23		T214	12		T215	10
auto[0]	values[7]	values[6]	395	1			T45	43		T216	4		T184	20
auto[0]	values[7]	values[7]	401	1			T217	12		T43	28		T20	21
auto[1]	values[0]	values[0]	7	1			T136	2		T218	1		T219	1
auto[1]	values[0]	values[2]	1	1			T220	1		-	-		-	-
auto[1]	values[0]	values[3]	7	1			T57	3		T221	1		T222	1
auto[1]	values[0]	values[4]	9	1			T40	1		T46	2		T54	1
auto[1]	values[0]	values[5]	3	1			T223	2		T213	1		-	-
auto[1]	values[0]	values[6]	6	1			T57	1		T224	1		T36	1
auto[1]	values[0]	values[7]	9	1			T26	1		T47	2		T36	3
auto[1]	values[1]	values[0]	4	1			T59	1		T179	1		T225	2
auto[1]	values[1]	values[1]	1	1			T226	1		-	-		-	-
auto[1]	values[1]	values[2]	4	1			T35	1		T227	2		T228	1
auto[1]	values[1]	values[3]	13	1			T14	1		T181	4		T229	4
auto[1]	values[1]	values[4]	5	1			T230	2		T231	1		T232	2
auto[1]	values[1]	values[5]	8	1			T35	3		T227	2		T233	1
auto[1]	values[1]	values[6]	9	1			T19	4		T234	1		T235	1
auto[1]	values[1]	values[7]	8	1			T34	2		T234	1		T235	3
auto[1]	values[2]	values[0]	5	1			T224	1		T236	2		T222	1
auto[1]	values[2]	values[1]	4	1			T59	2		T237	2		-	-
auto[1]	values[2]	values[2]	9	1			T238	2		T55	1		T213	2
auto[1]	values[2]	values[3]	7	1			T43	1		T163	1		T136	1
auto[1]	values[2]	values[4]	5	1			T59	2		T231	1		T239	1
auto[1]	values[2]	values[5]	6	1			T179	3		T222	2		T240	1
auto[1]	values[2]	values[6]	6	1			T241	2		T225	1		T220	2
auto[1]	values[2]	values[7]	13	1			T177	1		T35	4		T36	2
auto[1]	values[3]	values[0]	8	1			T39	2		T40	2		T179	1
auto[1]	values[3]	values[1]	6	1			T35	1		T219	1		T235	2
auto[1]	values[3]	values[2]	1	1			T39	1		-	-		-	-
auto[1]	values[3]	values[3]	4	1			T235	1		T242	3		-	-
auto[1]	values[3]	values[4]	6	1			T36	2		T243	1		T244	2
auto[1]	values[3]	values[5]	9	1			T177	2		T245	4		T236	3
auto[1]	values[3]	values[6]	2	1			T42	1		T179	1		-	-
auto[1]	values[3]	values[7]	14	1			T53	3		T43	3		T246	1
auto[1]	values[4]	values[0]	3	1			T30	1		T213	1		T247	1
auto[1]	values[4]	values[1]	6	1			T53	1		T247	1		T237	4
auto[1]	values[4]	values[2]	1	1			T248	1		-	-		-	-
auto[1]	values[4]	values[3]	5	1			T54	2		T218	2		T249	1
auto[1]	values[4]	values[4]	7	1			T47	2		T250	2		T251	3
auto[1]	values[4]	values[5]	6	1			T58	1		T252	2		T56	2
auto[1]	values[4]	values[6]	11	1			T66	3		T234	1		T179	1
auto[1]	values[4]	values[7]	7	1			T59	1		T234	1		T36	1
auto[1]	values[5]	values[0]	9	1			T66	1		T231	3		T239	2
auto[1]	values[5]	values[1]	2	1			T253	1		T254	1		-	-
auto[1]	values[5]	values[2]	4	1			T14	1		T45	1		T30	2
auto[1]	values[5]	values[3]	5	1			T16	1		T218	3		T226	1
auto[1]	values[5]	values[4]	9	1			T181	2		T35	1		T255	2
auto[1]	values[5]	values[5]	10	1			T43	2		T173	1		T256	3
auto[1]	values[5]	values[6]	5	1			T152	3		T249	2		-	-
auto[1]	values[5]	values[7]	11	1			T66	1		T136	1		T36	4
auto[1]	values[6]	values[0]	5	1			T218	2		T252	1		T257	2
auto[1]	values[6]	values[1]	11	1			T221	2		T236	1		T235	2
auto[1]	values[6]	values[2]	12	1			T45	2		T57	5		T258	1
auto[1]	values[6]	values[3]	9	1			T163	1		T225	4		T259	2
auto[1]	values[6]	values[4]	6	1			T14	3		T36	3		-	-
auto[1]	values[6]	values[5]	14	1			T44	2		T260	2		T221	1
auto[1]	values[6]	values[7]	5	1			T163	1		T227	3		T249	1
auto[1]	values[7]	values[0]	16	1			T59	1		T218	4		T243	1
auto[1]	values[7]	values[1]	4	1			T59	1		T233	2		T240	1
auto[1]	values[7]	values[2]	3	1			T36	1		T221	1		T239	1
auto[1]	values[7]	values[3]	9	1			T16	3		T224	2		T235	1
auto[1]	values[7]	values[4]	4	1			T222	1		T261	2		T259	1
auto[1]	values[7]	values[5]	3	1			T35	3		-	-		-	-
auto[1]	values[7]	values[6]	4	1			T45	1		T247	2		T261	1
auto[1]	values[7]	values[7]	10	1			T30	1		T136	2		T36	1