Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1682

1

T1

9

T8

1

T12

10

auto[1]

1698

1

T1

5

T12

14

T27

12

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1833

1

T8

1

T12

24

T27

17

auto[1]

1547

1

T1

14

T14

13

T23

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2668

1

T1

14

T12

17

T27

13

auto[1]

712

1

T8

1

T12

7

T27

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	679	1			T1	4		T12	6		T27	5
valid[1]	678	1			T1	4		T12	6		T27	2
valid[2]	675	1			T1	3		T27	4		T14	6
valid[3]	668	1			T1	2		T12	2		T27	5
valid[4]	680	1			T1	1		T8	1		T12	10

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	111	1			T12	2		T27	2		T14	2
auto[0]	auto[0]	valid[0]	auto[1]	154	1			T1	3		T14	2		T28	4
auto[0]	auto[0]	valid[1]	auto[0]	108	1			T12	2		T14	1		T26	3
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T1	2		T14	2		T28	3
auto[0]	auto[0]	valid[2]	auto[0]	103	1			T27	1		T14	1		T26	2
auto[0]	auto[0]	valid[2]	auto[1]	159	1			T1	2		T14	2		T28	5
auto[0]	auto[0]	valid[3]	auto[0]	113	1			T14	1		T16	1		T26	1
auto[0]	auto[0]	valid[3]	auto[1]	133	1			T1	1		T14	1		T23	3
auto[0]	auto[0]	valid[4]	auto[0]	99	1			T12	3		T27	1		T66	1
auto[0]	auto[0]	valid[4]	auto[1]	159	1			T1	1		T14	1		T23	1
auto[0]	auto[1]	valid[0]	auto[0]	115	1			T12	3		T27	3		T14	1
auto[0]	auto[1]	valid[0]	auto[1]	159	1			T1	1		T23	1		T28	4
auto[0]	auto[1]	valid[1]	auto[0]	125	1			T12	2		T27	1		T14	3
auto[0]	auto[1]	valid[1]	auto[1]	150	1			T1	2		T14	2		T23	2
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T27	2		T14	1		T34	1
auto[0]	auto[1]	valid[2]	auto[1]	149	1			T1	1		T14	1		T28	2
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T27	3		T14	1		T26	2
auto[0]	auto[1]	valid[3]	auto[1]	163	1			T1	1		T28	3		T34	1
auto[0]	auto[1]	valid[4]	auto[0]	114	1			T12	5		T14	2		T26	5
auto[0]	auto[1]	valid[4]	auto[1]	162	1			T14	2		T28	4		T34	3
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T51	1		T18	1		T19	3
auto[1]	auto[0]	valid[1]	auto[0]	68	1			T12	1		T27	1		T14	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T51	1		T166	1		T19	4
auto[1]	auto[0]	valid[3]	auto[0]	77	1			T12	1		T26	1		T51	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T8	1		T12	1		T14	1
auto[1]	auto[1]	valid[0]	auto[0]	61	1			T12	1		T14	3		T16	1
auto[1]	auto[1]	valid[1]	auto[0]	68	1			T12	1		T14	3		T34	1
auto[1]	auto[1]	valid[2]	auto[0]	79	1			T27	1		T14	1		T26	3
auto[1]	auto[1]	valid[3]	auto[0]	60	1			T12	1		T27	2		T14	1
auto[1]	auto[1]	valid[4]	auto[0]	60	1			T12	1		T14	4		T51	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal