Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	831	1			T26	4		T18	27		T19	7
all_values[1]	831	1			T26	4		T18	27		T19	7
all_values[2]	831	1			T26	4		T18	27		T19	7
all_values[3]	831	1			T26	4		T18	27		T19	7
all_values[4]	831	1			T26	4		T18	27		T19	7
all_values[5]	831	1			T26	4		T18	27		T19	7
all_values[6]	831	1			T26	4		T18	27		T19	7
all_values[7]	831	1			T26	4		T18	27		T19	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3510

1

T26

18

T18

107

T19

40

auto[1]

3138

1

T26

14

T18

109

T19

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2592

1

T26

13

T18

77

T19

27

auto[1]

4056

1

T26

19

T18

139

T19

29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3785

1

T26

19

T18

120

T19

34

auto[1]

2863

1

T26

13

T18

96

T19

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	156	1			T26	1		T18	3		T19	1
all_values[0]	auto[0]	auto[0]	auto[1]	82	1			T26	1		T18	2		T20	2
all_values[0]	auto[0]	auto[1]	auto[0]	134	1			T18	7		T19	2		T20	3
all_values[0]	auto[0]	auto[1]	auto[1]	97	1			T26	1		T18	2		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	192	1			T26	1		T18	7		T19	3
all_values[0]	auto[1]	auto[1]	auto[1]	170	1			T18	6		T20	4		T45	1
all_values[1]	auto[0]	auto[0]	auto[0]	155	1			T18	8		T19	1		T45	2
all_values[1]	auto[0]	auto[0]	auto[1]	85	1			T18	2		T19	3		T20	3
all_values[1]	auto[0]	auto[1]	auto[0]	134	1			T26	2		T18	5		T20	2
all_values[1]	auto[0]	auto[1]	auto[1]	101	1			T26	1		T18	4		T20	6
all_values[1]	auto[1]	auto[0]	auto[1]	194	1			T26	1		T18	2		T19	3
all_values[1]	auto[1]	auto[1]	auto[1]	162	1			T18	6		T20	5		T45	1
all_values[2]	auto[0]	auto[0]	auto[0]	142	1			T26	2		T18	7		T19	2
all_values[2]	auto[0]	auto[0]	auto[1]	89	1			T18	6		T19	1		T20	4
all_values[2]	auto[0]	auto[1]	auto[0]	137	1			T26	1		T18	2		T19	1
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T18	3		T20	1		T45	3
all_values[2]	auto[1]	auto[0]	auto[1]	182	1			T18	5		T19	3		T20	5
all_values[2]	auto[1]	auto[1]	auto[1]	187	1			T26	1		T18	4		T20	3
all_values[3]	auto[0]	auto[0]	auto[0]	186	1			T26	2		T18	5		T19	2
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T18	2		T20	3		T45	2
all_values[3]	auto[0]	auto[1]	auto[0]	135	1			T18	3		T19	2		T20	2
all_values[3]	auto[0]	auto[1]	auto[1]	65	1			T18	3		T20	1		T31	2
all_values[3]	auto[1]	auto[0]	auto[1]	191	1			T26	1		T18	8		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	158	1			T26	1		T18	6		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	165	1			T18	2		T19	2		T20	3
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T26	1		T18	4		T20	2
all_values[4]	auto[0]	auto[1]	auto[0]	148	1			T18	2		T19	3		T20	5
all_values[4]	auto[0]	auto[1]	auto[1]	79	1			T18	2		T20	2		T45	2
all_values[4]	auto[1]	auto[0]	auto[1]	202	1			T26	1		T18	8		T19	2
all_values[4]	auto[1]	auto[1]	auto[1]	155	1			T26	2		T18	9		T20	4
all_values[5]	auto[0]	auto[0]	auto[0]	227	1			T26	2		T18	4		T19	3
all_values[5]	auto[0]	auto[1]	auto[0]	255	1			T18	10		T19	3		T20	3
all_values[5]	auto[1]	auto[0]	auto[1]	191	1			T18	7		T20	8		T45	1
all_values[5]	auto[1]	auto[1]	auto[1]	158	1			T26	2		T18	6		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	165	1			T26	2		T18	5		T19	3
all_values[6]	auto[0]	auto[0]	auto[1]	92	1			T18	4		T19	1		T20	3
all_values[6]	auto[0]	auto[1]	auto[0]	128	1			T26	1		T18	8		T20	1
all_values[6]	auto[0]	auto[1]	auto[1]	78	1			T18	3		T20	2		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	209	1			T18	4		T19	2		T20	5
all_values[6]	auto[1]	auto[1]	auto[1]	159	1			T26	1		T18	3		T19	1
all_values[7]	auto[0]	auto[0]	auto[0]	172	1			T18	2		T19	2		T20	1
all_values[7]	auto[0]	auto[0]	auto[1]	68	1			T26	1		T18	2		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T18	4		T45	4		T31	4
all_values[7]	auto[0]	auto[1]	auto[1]	85	1			T26	1		T18	4		T20	3
all_values[7]	auto[1]	auto[0]	auto[1]	187	1			T26	2		T18	8		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	166	1			T18	7		T19	1		T20	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal