Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46656

1

T2

6

T8

52

T12

406

auto[1]

16539

1

T1

14

T14

142

T23

191

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45871

1

T1

14

T2

3

T8

31

auto[1]

17324

1

T2

3

T8

21

T12

138

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32494	1			T1	14		T2	2		T8	27
others[1]	5366	1			T8	4		T12	39		T27	33
others[2]	5366	1			T2	1		T8	8		T12	38
others[3]	6004	1			T8	6		T12	28		T27	46
interest[1]	3503	1			T2	1		T8	1		T12	28
interest[4]	21143	1			T1	14		T2	2		T8	16
interest[64]	10462	1			T2	2		T8	6		T12	74

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15037	1			T2	1		T8	17		T12	121
auto[0]	auto[0]	others[1]	2502	1			T8	3		T12	27		T27	21
auto[0]	auto[0]	others[2]	2519	1			T2	1		T8	4		T12	30
auto[0]	auto[0]	others[3]	2787	1			T8	3		T12	19		T27	32
auto[0]	auto[0]	interest[1]	1634	1			T8	1		T12	18		T27	16
auto[0]	auto[0]	interest[4]	9702	1			T2	1		T8	9		T12	83
auto[0]	auto[0]	interest[64]	4853	1			T2	1		T8	3		T12	53
auto[0]	auto[1]	others[0]	8592	1			T1	14		T14	73		T23	104
auto[0]	auto[1]	others[1]	1370	1			T14	6		T23	9		T28	35
auto[0]	auto[1]	others[2]	1424	1			T14	14		T23	18		T28	29
auto[0]	auto[1]	others[3]	1525	1			T14	18		T23	20		T28	47
auto[0]	auto[1]	interest[1]	904	1			T14	8		T23	10		T28	25
auto[0]	auto[1]	interest[4]	5650	1			T1	14		T14	53		T23	65
auto[0]	auto[1]	interest[64]	2724	1			T14	23		T23	30		T28	69
auto[1]	auto[0]	others[0]	8865	1			T2	1		T8	10		T12	78
auto[1]	auto[0]	others[1]	1494	1			T8	1		T12	12		T27	12
auto[1]	auto[0]	others[2]	1423	1			T8	4		T12	8		T27	13
auto[1]	auto[0]	others[3]	1692	1			T8	3		T12	9		T27	14
auto[1]	auto[0]	interest[1]	965	1			T2	1		T12	10		T27	4
auto[1]	auto[0]	interest[4]	5791	1			T2	1		T8	7		T12	54
auto[1]	auto[0]	interest[64]	2885	1			T2	1		T8	3		T12	21

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal