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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 98.35 94.02 98.62 89.36 97.23 95.43 99.10


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1013 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.52506102 Jun 13 01:47:10 PM PDT 24 Jun 13 01:47:12 PM PDT 24 14843421 ps
T150 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.473822679 Jun 13 01:47:04 PM PDT 24 Jun 13 01:47:20 PM PDT 24 2629732703 ps
T126 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2103951709 Jun 13 01:46:30 PM PDT 24 Jun 13 01:46:33 PM PDT 24 20689039 ps
T1014 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2271046932 Jun 13 01:46:45 PM PDT 24 Jun 13 01:46:49 PM PDT 24 195857009 ps
T1015 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.857471397 Jun 13 01:46:52 PM PDT 24 Jun 13 01:46:58 PM PDT 24 250677203 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2532740876 Jun 13 01:46:28 PM PDT 24 Jun 13 01:46:30 PM PDT 24 22019172 ps
T1016 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2768809643 Jun 13 01:47:19 PM PDT 24 Jun 13 01:47:21 PM PDT 24 40294667 ps
T1017 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.918938383 Jun 13 01:47:11 PM PDT 24 Jun 13 01:47:13 PM PDT 24 48148323 ps
T1018 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2799458762 Jun 13 01:47:09 PM PDT 24 Jun 13 01:47:11 PM PDT 24 111411561 ps
T82 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3747328490 Jun 13 01:46:20 PM PDT 24 Jun 13 01:46:22 PM PDT 24 72132005 ps
T1019 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.373870805 Jun 13 01:46:38 PM PDT 24 Jun 13 01:46:40 PM PDT 24 11922625 ps
T1020 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.428899060 Jun 13 01:46:31 PM PDT 24 Jun 13 01:46:36 PM PDT 24 62729053 ps
T151 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1187724725 Jun 13 01:46:55 PM PDT 24 Jun 13 01:47:01 PM PDT 24 255884025 ps
T1021 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1826826606 Jun 13 01:47:02 PM PDT 24 Jun 13 01:47:05 PM PDT 24 204878900 ps
T1022 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2735419899 Jun 13 01:47:10 PM PDT 24 Jun 13 01:47:13 PM PDT 24 34292733 ps
T1023 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3927659490 Jun 13 01:46:24 PM PDT 24 Jun 13 01:46:26 PM PDT 24 84664843 ps
T1024 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.269022981 Jun 13 01:46:20 PM PDT 24 Jun 13 01:46:24 PM PDT 24 71884913 ps
T108 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2833498612 Jun 13 01:46:37 PM PDT 24 Jun 13 01:46:43 PM PDT 24 804103989 ps
T109 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.894705787 Jun 13 01:47:02 PM PDT 24 Jun 13 01:47:07 PM PDT 24 146500354 ps
T268 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3837866889 Jun 13 01:46:56 PM PDT 24 Jun 13 01:47:16 PM PDT 24 710618596 ps
T1025 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2626867332 Jun 13 01:46:55 PM PDT 24 Jun 13 01:47:02 PM PDT 24 307268428 ps
T263 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3731708050 Jun 13 01:46:53 PM PDT 24 Jun 13 01:47:12 PM PDT 24 1126792258 ps
T1026 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2113375436 Jun 13 01:47:12 PM PDT 24 Jun 13 01:47:14 PM PDT 24 53505919 ps
T1027 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2676437428 Jun 13 01:47:09 PM PDT 24 Jun 13 01:47:12 PM PDT 24 12255731 ps
T1028 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2107117251 Jun 13 01:46:30 PM PDT 24 Jun 13 01:46:32 PM PDT 24 14162102 ps
T1029 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2789313465 Jun 13 01:46:34 PM PDT 24 Jun 13 01:46:36 PM PDT 24 15166857 ps
T1030 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.577049850 Jun 13 01:46:44 PM PDT 24 Jun 13 01:46:48 PM PDT 24 74448346 ps
T1031 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4234942077 Jun 13 01:47:12 PM PDT 24 Jun 13 01:47:14 PM PDT 24 11194393 ps
T107 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1427059749 Jun 13 01:47:03 PM PDT 24 Jun 13 01:47:08 PM PDT 24 109541804 ps
T1032 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2450672091 Jun 13 01:46:31 PM PDT 24 Jun 13 01:46:34 PM PDT 24 249578230 ps
T1033 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2086311504 Jun 13 01:46:49 PM PDT 24 Jun 13 01:46:50 PM PDT 24 58041234 ps
T1034 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1251755244 Jun 13 01:47:03 PM PDT 24 Jun 13 01:47:08 PM PDT 24 602197011 ps
T83 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3180369171 Jun 13 01:46:33 PM PDT 24 Jun 13 01:46:36 PM PDT 24 38287013 ps
T1035 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3967448977 Jun 13 01:47:01 PM PDT 24 Jun 13 01:47:05 PM PDT 24 765291901 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2224957384 Jun 13 01:46:31 PM PDT 24 Jun 13 01:46:33 PM PDT 24 47749181 ps
T1037 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.331545042 Jun 13 01:46:42 PM PDT 24 Jun 13 01:46:44 PM PDT 24 60040641 ps
T1038 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2234103283 Jun 13 01:47:11 PM PDT 24 Jun 13 01:47:14 PM PDT 24 16312278 ps
T1039 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2740811471 Jun 13 01:46:26 PM PDT 24 Jun 13 01:46:28 PM PDT 24 34084939 ps
T1040 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2923183082 Jun 13 01:46:51 PM PDT 24 Jun 13 01:46:58 PM PDT 24 286357750 ps
T1041 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1717606711 Jun 13 01:46:21 PM PDT 24 Jun 13 01:46:26 PM PDT 24 960671976 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3112294959 Jun 13 01:46:19 PM PDT 24 Jun 13 01:46:21 PM PDT 24 12021998 ps
T1043 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3717359632 Jun 13 01:46:56 PM PDT 24 Jun 13 01:47:03 PM PDT 24 198006927 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3422546820 Jun 13 01:47:04 PM PDT 24 Jun 13 01:47:08 PM PDT 24 46141467 ps
T264 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2970796715 Jun 13 01:46:26 PM PDT 24 Jun 13 01:46:46 PM PDT 24 299898109 ps
T1045 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1488954253 Jun 13 01:46:25 PM PDT 24 Jun 13 01:46:28 PM PDT 24 57991670 ps
T1046 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2870953193 Jun 13 01:46:25 PM PDT 24 Jun 13 01:46:31 PM PDT 24 705142713 ps
T1047 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2694406695 Jun 13 01:46:40 PM PDT 24 Jun 13 01:46:48 PM PDT 24 216645029 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1027583402 Jun 13 01:46:31 PM PDT 24 Jun 13 01:47:09 PM PDT 24 25778492706 ps
T1049 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3195965940 Jun 13 01:46:50 PM PDT 24 Jun 13 01:46:54 PM PDT 24 53247904 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.728919921 Jun 13 01:46:37 PM PDT 24 Jun 13 01:46:40 PM PDT 24 194702602 ps
T1051 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.968937614 Jun 13 01:46:50 PM PDT 24 Jun 13 01:46:53 PM PDT 24 13499110 ps
T1052 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3698099126 Jun 13 01:47:01 PM PDT 24 Jun 13 01:47:04 PM PDT 24 46128488 ps
T1053 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.163088465 Jun 13 01:47:19 PM PDT 24 Jun 13 01:47:21 PM PDT 24 21814406 ps
T1054 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1108839223 Jun 13 01:46:25 PM PDT 24 Jun 13 01:46:29 PM PDT 24 158647247 ps
T1055 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.493023082 Jun 13 01:46:52 PM PDT 24 Jun 13 01:46:57 PM PDT 24 83916749 ps
T1056 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1339354769 Jun 13 01:47:10 PM PDT 24 Jun 13 01:47:13 PM PDT 24 21001779 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2029432931 Jun 13 01:46:24 PM PDT 24 Jun 13 01:46:29 PM PDT 24 213356905 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3651148997 Jun 13 01:46:32 PM PDT 24 Jun 13 01:46:38 PM PDT 24 627819878 ps
T1059 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.329596919 Jun 13 01:46:26 PM PDT 24 Jun 13 01:46:30 PM PDT 24 127394780 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2723451067 Jun 13 01:46:34 PM PDT 24 Jun 13 01:46:42 PM PDT 24 206077489 ps
T1061 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2068947076 Jun 13 01:46:36 PM PDT 24 Jun 13 01:46:52 PM PDT 24 603870167 ps
T1062 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1510296621 Jun 13 01:46:33 PM PDT 24 Jun 13 01:46:51 PM PDT 24 1173763324 ps
T1063 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4196822194 Jun 13 01:46:27 PM PDT 24 Jun 13 01:46:29 PM PDT 24 32197102 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3203508432 Jun 13 01:46:56 PM PDT 24 Jun 13 01:47:00 PM PDT 24 75317652 ps
T1065 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3152694005 Jun 13 01:46:50 PM PDT 24 Jun 13 01:46:54 PM PDT 24 28995007 ps
T1066 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1992557867 Jun 13 01:46:41 PM PDT 24 Jun 13 01:47:03 PM PDT 24 1598558828 ps
T1067 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1850175610 Jun 13 01:46:44 PM PDT 24 Jun 13 01:46:46 PM PDT 24 37856689 ps
T1068 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1478527138 Jun 13 01:46:43 PM PDT 24 Jun 13 01:47:04 PM PDT 24 1158218237 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2994732793 Jun 13 01:46:48 PM PDT 24 Jun 13 01:46:58 PM PDT 24 978555026 ps
T1070 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3033818153 Jun 13 01:46:58 PM PDT 24 Jun 13 01:47:01 PM PDT 24 56995579 ps
T1071 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3975697788 Jun 13 01:47:05 PM PDT 24 Jun 13 01:47:08 PM PDT 24 64425393 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3689531614 Jun 13 01:46:33 PM PDT 24 Jun 13 01:46:36 PM PDT 24 79847239 ps
T1073 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3862184774 Jun 13 01:46:49 PM PDT 24 Jun 13 01:46:53 PM PDT 24 406695798 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3517215020 Jun 13 01:46:40 PM PDT 24 Jun 13 01:46:45 PM PDT 24 153898969 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1101395215 Jun 13 01:46:37 PM PDT 24 Jun 13 01:46:39 PM PDT 24 67451740 ps
T1076 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3258494933 Jun 13 01:46:39 PM PDT 24 Jun 13 01:46:44 PM PDT 24 57545962 ps
T1077 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3950025154 Jun 13 01:46:53 PM PDT 24 Jun 13 01:47:00 PM PDT 24 806702176 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.145600901 Jun 13 01:46:49 PM PDT 24 Jun 13 01:46:55 PM PDT 24 168341105 ps
T1079 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.594578887 Jun 13 01:47:09 PM PDT 24 Jun 13 01:47:11 PM PDT 24 25764299 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.68667063 Jun 13 01:46:18 PM PDT 24 Jun 13 01:46:22 PM PDT 24 198757456 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.400568897 Jun 13 01:46:56 PM PDT 24 Jun 13 01:46:59 PM PDT 24 26808954 ps
T1082 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3014972747 Jun 13 01:46:50 PM PDT 24 Jun 13 01:46:54 PM PDT 24 14083549 ps
T1083 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2573805231 Jun 13 01:47:04 PM PDT 24 Jun 13 01:47:07 PM PDT 24 161787044 ps
T1084 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.920832193 Jun 13 01:46:38 PM PDT 24 Jun 13 01:46:42 PM PDT 24 45861384 ps
T1085 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.231190168 Jun 13 01:46:56 PM PDT 24 Jun 13 01:47:02 PM PDT 24 60619992 ps
T1086 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2852246493 Jun 13 01:46:46 PM PDT 24 Jun 13 01:46:50 PM PDT 24 434838079 ps
T1087 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4203983194 Jun 13 01:47:08 PM PDT 24 Jun 13 01:47:10 PM PDT 24 19528968 ps
T1088 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2140851485 Jun 13 01:47:10 PM PDT 24 Jun 13 01:47:13 PM PDT 24 12395950 ps
T1089 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2319894225 Jun 13 01:46:22 PM PDT 24 Jun 13 01:46:24 PM PDT 24 10501416 ps
T1090 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1534506066 Jun 13 01:46:51 PM PDT 24 Jun 13 01:46:56 PM PDT 24 131147798 ps
T1091 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2115216172 Jun 13 01:46:59 PM PDT 24 Jun 13 01:47:02 PM PDT 24 49186373 ps
T1092 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.529611556 Jun 13 01:46:40 PM PDT 24 Jun 13 01:46:45 PM PDT 24 215814437 ps
T1093 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.937868798 Jun 13 01:46:26 PM PDT 24 Jun 13 01:46:49 PM PDT 24 703426866 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2089370190 Jun 13 01:46:21 PM PDT 24 Jun 13 01:46:24 PM PDT 24 80541116 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2518454780 Jun 13 01:46:37 PM PDT 24 Jun 13 01:46:39 PM PDT 24 29624790 ps
T1096 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2639064999 Jun 13 01:47:11 PM PDT 24 Jun 13 01:47:14 PM PDT 24 22108513 ps
T1097 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1318931412 Jun 13 01:47:01 PM PDT 24 Jun 13 01:47:05 PM PDT 24 135927030 ps
T1098 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1184322102 Jun 13 01:46:20 PM PDT 24 Jun 13 01:46:29 PM PDT 24 474356441 ps
T1099 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.196900168 Jun 13 01:47:09 PM PDT 24 Jun 13 01:47:12 PM PDT 24 16402759 ps
T1100 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3206407105 Jun 13 01:47:10 PM PDT 24 Jun 13 01:47:13 PM PDT 24 14005823 ps
T1101 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2975646655 Jun 13 01:47:02 PM PDT 24 Jun 13 01:47:04 PM PDT 24 31482061 ps

Test location /workspace/coverage/default/11.spi_device_mailbox.3178726034
Short name T6
Test name
Test status
Simulation time 3105883689 ps
CPU time 18.45 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:28 PM PDT 24
Peak memory 224888 kb
Host smart-0b2f9297-4b61-4edc-9835-7d57eacf35a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178726034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3178726034
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.4065118998
Short name T14
Test name
Test status
Simulation time 192512827557 ps
CPU time 516.11 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:58:40 PM PDT 24
Peak memory 253188 kb
Host smart-a0a0691c-4198-460b-afce-68a328ac24f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065118998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.4065118998
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.479228156
Short name T26
Test name
Test status
Simulation time 39592896744 ps
CPU time 169.84 seconds
Started Jun 13 02:49:32 PM PDT 24
Finished Jun 13 02:52:43 PM PDT 24
Peak memory 250216 kb
Host smart-7748555f-43c4-41a1-90ea-540fbd8f5c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479228156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stres
s_all.479228156
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1711250725
Short name T95
Test name
Test status
Simulation time 2824952149 ps
CPU time 15.4 seconds
Started Jun 13 01:47:02 PM PDT 24
Finished Jun 13 01:47:20 PM PDT 24
Peak memory 215740 kb
Host smart-9e9fa74c-674b-4c70-a0cb-a6d8ae73a54d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711250725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1711250725
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2353184291
Short name T35
Test name
Test status
Simulation time 17095510774 ps
CPU time 312.65 seconds
Started Jun 13 02:49:40 PM PDT 24
Finished Jun 13 02:55:11 PM PDT 24
Peak memory 288820 kb
Host smart-a4f9c6a7-3e49-4b11-81c5-31bde6412218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353184291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2353184291
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.4024620190
Short name T59
Test name
Test status
Simulation time 810376493043 ps
CPU time 1299.09 seconds
Started Jun 13 02:50:46 PM PDT 24
Finished Jun 13 03:12:38 PM PDT 24
Peak memory 273028 kb
Host smart-572d2d66-88a5-4cd3-9ed6-9775e13f5b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024620190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.4024620190
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3278555377
Short name T69
Test name
Test status
Simulation time 38574326 ps
CPU time 0.73 seconds
Started Jun 13 02:48:11 PM PDT 24
Finished Jun 13 02:48:27 PM PDT 24
Peak memory 216404 kb
Host smart-7f7b7174-f74a-4e83-a021-e23e07b6ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278555377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3278555377
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.371580038
Short name T43
Test name
Test status
Simulation time 333190240509 ps
CPU time 730.92 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 03:03:07 PM PDT 24
Peak memory 265948 kb
Host smart-801daee6-8d93-4171-893d-c70343b3aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371580038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.371580038
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.699677380
Short name T36
Test name
Test status
Simulation time 272259433435 ps
CPU time 292.9 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:53:59 PM PDT 24
Peak memory 281468 kb
Host smart-c0d037be-3533-463b-8c22-d23064d991f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699677380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.699677380
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1235977840
Short name T13
Test name
Test status
Simulation time 4358176407 ps
CPU time 17.6 seconds
Started Jun 13 02:50:41 PM PDT 24
Finished Jun 13 02:51:11 PM PDT 24
Peak memory 224924 kb
Host smart-34d3e654-19db-4733-8b94-1bb3e3e0dd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235977840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1235977840
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2765372330
Short name T167
Test name
Test status
Simulation time 69586007770 ps
CPU time 294.21 seconds
Started Jun 13 02:49:41 PM PDT 24
Finished Jun 13 02:54:53 PM PDT 24
Peak memory 257704 kb
Host smart-9418a828-a9dd-46da-9d5d-e59c1b2cfb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765372330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2765372330
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1382580150
Short name T17
Test name
Test status
Simulation time 47433507 ps
CPU time 1.03 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:48:21 PM PDT 24
Peak memory 235460 kb
Host smart-e3da5ee4-b54f-4d23-9106-0cbb2a8a35c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382580150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1382580150
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.33021713
Short name T91
Test name
Test status
Simulation time 492287884 ps
CPU time 3.59 seconds
Started Jun 13 01:46:49 PM PDT 24
Finished Jun 13 01:46:56 PM PDT 24
Peak memory 215832 kb
Host smart-148e0d36-88dc-4c2b-85c2-9b6a09741fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33021713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.33021713
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1951608470
Short name T225
Test name
Test status
Simulation time 250164423686 ps
CPU time 1213.34 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 03:10:31 PM PDT 24
Peak memory 287232 kb
Host smart-afc314c1-026f-4e7e-9dbf-f804cd1fc20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951608470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1951608470
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1859630996
Short name T53
Test name
Test status
Simulation time 2895629346 ps
CPU time 60.86 seconds
Started Jun 13 02:48:14 PM PDT 24
Finished Jun 13 02:49:30 PM PDT 24
Peak memory 249680 kb
Host smart-0412fae5-5e93-4d21-bdf8-e7a817c97860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859630996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1859630996
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1573184183
Short name T117
Test name
Test status
Simulation time 2180165671 ps
CPU time 23.03 seconds
Started Jun 13 01:46:18 PM PDT 24
Finished Jun 13 01:46:42 PM PDT 24
Peak memory 215756 kb
Host smart-d7a3bc6a-c712-46fb-bea8-cd401d1778ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573184183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1573184183
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3927931154
Short name T54
Test name
Test status
Simulation time 70684608600 ps
CPU time 119.39 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:51:36 PM PDT 24
Peak memory 252048 kb
Host smart-700a3e52-e1fe-4955-8f2c-de29efc6b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927931154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3927931154
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2219892180
Short name T30
Test name
Test status
Simulation time 41827518127 ps
CPU time 359.8 seconds
Started Jun 13 02:50:27 PM PDT 24
Finished Jun 13 02:56:40 PM PDT 24
Peak memory 257120 kb
Host smart-631ae9a6-4a80-4c01-a569-7863787694e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219892180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2219892180
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.4088453745
Short name T22
Test name
Test status
Simulation time 53773017 ps
CPU time 1.03 seconds
Started Jun 13 02:48:03 PM PDT 24
Finished Jun 13 02:48:16 PM PDT 24
Peak memory 218132 kb
Host smart-744abc54-715e-4af4-941b-d39b86f11414
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088453745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.4088453745
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2253860339
Short name T45
Test name
Test status
Simulation time 5025079672 ps
CPU time 88.39 seconds
Started Jun 13 02:49:32 PM PDT 24
Finished Jun 13 02:51:22 PM PDT 24
Peak memory 257708 kb
Host smart-5df5fced-63c0-4038-a627-ea52cf6964f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253860339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2253860339
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1276592855
Short name T235
Test name
Test status
Simulation time 29559613745 ps
CPU time 313.45 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:54:51 PM PDT 24
Peak memory 271880 kb
Host smart-22d88360-d299-4893-998c-dd804520556e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276592855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1276592855
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.4083438562
Short name T222
Test name
Test status
Simulation time 32310609006 ps
CPU time 269.26 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:53:30 PM PDT 24
Peak memory 264616 kb
Host smart-673c4e96-97dc-4105-b628-ad580fa2bdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083438562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.4083438562
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1141936594
Short name T1
Test name
Test status
Simulation time 173748372 ps
CPU time 0.9 seconds
Started Jun 13 02:48:59 PM PDT 24
Finished Jun 13 02:49:19 PM PDT 24
Peak memory 207196 kb
Host smart-1da5106b-f830-4936-873c-a4a631686225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141936594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1141936594
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1926210846
Short name T16
Test name
Test status
Simulation time 38880162302 ps
CPU time 281.6 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:53:46 PM PDT 24
Peak memory 252708 kb
Host smart-85501d77-a1c6-43bb-a53b-aae03da8b8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926210846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1926210846
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2299146027
Short name T341
Test name
Test status
Simulation time 27274451 ps
CPU time 0.75 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:48:36 PM PDT 24
Peak memory 206028 kb
Host smart-4cfb0fa9-b4f5-4a65-8c20-7c4d91b7b100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299146027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
299146027
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3628504572
Short name T40
Test name
Test status
Simulation time 10478505532 ps
CPU time 141.55 seconds
Started Jun 13 02:48:56 PM PDT 24
Finished Jun 13 02:51:35 PM PDT 24
Peak memory 257320 kb
Host smart-e3e615cf-e5e2-4746-a843-7a5d5ef82893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628504572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3628504572
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1427059749
Short name T107
Test name
Test status
Simulation time 109541804 ps
CPU time 3.9 seconds
Started Jun 13 01:47:03 PM PDT 24
Finished Jun 13 01:47:08 PM PDT 24
Peak memory 215800 kb
Host smart-ec5e638d-e423-49e9-b907-4820f619a156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427059749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1427059749
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2421372389
Short name T66
Test name
Test status
Simulation time 99423409396 ps
CPU time 411 seconds
Started Jun 13 02:48:09 PM PDT 24
Finished Jun 13 02:55:14 PM PDT 24
Peak memory 253516 kb
Host smart-e280427d-3429-4820-aed4-366b99983bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421372389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2421372389
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2201697780
Short name T137
Test name
Test status
Simulation time 2691223659 ps
CPU time 69.67 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:51:14 PM PDT 24
Peak memory 255940 kb
Host smart-4a5dc8b2-0866-4596-9ba4-32d077abee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201697780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2201697780
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1226681450
Short name T92
Test name
Test status
Simulation time 1113214629 ps
CPU time 17.89 seconds
Started Jun 13 01:46:44 PM PDT 24
Finished Jun 13 01:47:03 PM PDT 24
Peak memory 215616 kb
Host smart-30c091a7-233e-45ce-90eb-fb17ae3c977d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226681450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1226681450
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.796835704
Short name T56
Test name
Test status
Simulation time 2286224333 ps
CPU time 49.56 seconds
Started Jun 13 02:48:10 PM PDT 24
Finished Jun 13 02:49:14 PM PDT 24
Peak memory 257060 kb
Host smart-e043eb04-95e2-4403-8fcc-11e956c6b5f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796835704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.796835704
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1242582712
Short name T220
Test name
Test status
Simulation time 22746165471 ps
CPU time 233.91 seconds
Started Jun 13 02:48:21 PM PDT 24
Finished Jun 13 02:52:31 PM PDT 24
Peak memory 268420 kb
Host smart-d761b9f3-5d4a-4629-926e-bf722cb9caed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242582712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1242582712
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1284485049
Short name T514
Test name
Test status
Simulation time 2003089700 ps
CPU time 34.78 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 238780 kb
Host smart-324f8df7-ee52-4733-8542-37570764123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284485049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1284485049
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.60661202
Short name T236
Test name
Test status
Simulation time 16071410341 ps
CPU time 88.5 seconds
Started Jun 13 02:49:01 PM PDT 24
Finished Jun 13 02:50:50 PM PDT 24
Peak memory 256416 kb
Host smart-ba08d284-0df0-4a48-88cf-1e82ae802e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60661202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.60661202
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2149033952
Short name T12
Test name
Test status
Simulation time 18771787507 ps
CPU time 29.22 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:50:01 PM PDT 24
Peak memory 216700 kb
Host smart-70203620-8122-4101-b51f-c778f0266f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149033952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2149033952
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2353112546
Short name T282
Test name
Test status
Simulation time 626795338 ps
CPU time 12.87 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:51 PM PDT 24
Peak memory 233116 kb
Host smart-478d9cc6-3fc5-42b6-8a69-266df9dbe752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353112546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2353112546
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3806373867
Short name T230
Test name
Test status
Simulation time 82050806728 ps
CPU time 275.16 seconds
Started Jun 13 02:50:05 PM PDT 24
Finished Jun 13 02:54:53 PM PDT 24
Peak memory 265952 kb
Host smart-a9cc1781-d409-487c-a706-5494d4ce03e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806373867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3806373867
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1839276824
Short name T249
Test name
Test status
Simulation time 292981808850 ps
CPU time 590.52 seconds
Started Jun 13 02:50:35 PM PDT 24
Finished Jun 13 03:00:39 PM PDT 24
Peak memory 252300 kb
Host smart-4bb81772-341b-4306-85d7-52419304d0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839276824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1839276824
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3891726146
Short name T86
Test name
Test status
Simulation time 572646006 ps
CPU time 6.28 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:49:54 PM PDT 24
Peak memory 222860 kb
Host smart-612d510f-4bdd-4411-af6b-99b5d05c07de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3891726146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3891726146
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_intercept.246732658
Short name T204
Test name
Test status
Simulation time 577290615 ps
CPU time 4.95 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:32 PM PDT 24
Peak memory 224828 kb
Host smart-89a043ac-2501-484c-9d20-1a6acbef6038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246732658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.246732658
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3731708050
Short name T263
Test name
Test status
Simulation time 1126792258 ps
CPU time 17.25 seconds
Started Jun 13 01:46:53 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 216284 kb
Host smart-e8a17334-55e7-402a-9e2f-a719f091a333
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731708050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3731708050
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2192523401
Short name T223
Test name
Test status
Simulation time 5076802932 ps
CPU time 50.94 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:53 PM PDT 24
Peak memory 249468 kb
Host smart-54f1d15f-53fe-4530-b13f-435c48c21a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192523401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2192523401
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1627836239
Short name T251
Test name
Test status
Simulation time 24907261055 ps
CPU time 233.97 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:52:57 PM PDT 24
Peak memory 253692 kb
Host smart-c9dcda7e-ca8f-4a19-86cc-a027b605565e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627836239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1627836239
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3261796400
Short name T275
Test name
Test status
Simulation time 12532514954 ps
CPU time 44.07 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:50:20 PM PDT 24
Peak memory 223660 kb
Host smart-8a46a0ce-6f5c-4a0a-8f1b-c864de4a6def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261796400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3261796400
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1272813862
Short name T593
Test name
Test status
Simulation time 239413480 ps
CPU time 6.62 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:38 PM PDT 24
Peak memory 233072 kb
Host smart-db205673-e57b-4c50-a059-07f05d501ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272813862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1272813862
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2359552726
Short name T252
Test name
Test status
Simulation time 12147265274 ps
CPU time 148.41 seconds
Started Jun 13 02:49:17 PM PDT 24
Finished Jun 13 02:52:08 PM PDT 24
Peak memory 255104 kb
Host smart-1d35ce1c-743f-492e-9c10-8f48e3774c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359552726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2359552726
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.155741447
Short name T254
Test name
Test status
Simulation time 13518125155 ps
CPU time 90.81 seconds
Started Jun 13 02:49:30 PM PDT 24
Finished Jun 13 02:51:23 PM PDT 24
Peak memory 233152 kb
Host smart-f9f4a038-838a-42f5-81b4-288c761a61aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155741447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.155741447
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.4073730934
Short name T42
Test name
Test status
Simulation time 17013352676 ps
CPU time 41.23 seconds
Started Jun 13 02:49:27 PM PDT 24
Finished Jun 13 02:50:31 PM PDT 24
Peak memory 224976 kb
Host smart-b16f6c8e-a294-4886-a5eb-c091efcd417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073730934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.4073730934
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1218770047
Short name T243
Test name
Test status
Simulation time 17653101003 ps
CPU time 71.01 seconds
Started Jun 13 02:50:14 PM PDT 24
Finished Jun 13 02:51:37 PM PDT 24
Peak memory 253840 kb
Host smart-697517f1-66a9-495f-b1ba-e8bfa27eee9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218770047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1218770047
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3574370495
Short name T248
Test name
Test status
Simulation time 150692914010 ps
CPU time 237.15 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:54:35 PM PDT 24
Peak memory 254844 kb
Host smart-334c924c-4340-4036-a7fe-0066986c2535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574370495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3574370495
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3173207050
Short name T39
Test name
Test status
Simulation time 13959216400 ps
CPU time 105.48 seconds
Started Jun 13 02:50:20 PM PDT 24
Finished Jun 13 02:52:17 PM PDT 24
Peak memory 255788 kb
Host smart-bc5a2bc6-8d40-45db-8c69-333a899f97db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173207050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3173207050
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4204915051
Short name T226
Test name
Test status
Simulation time 430427517883 ps
CPU time 176.53 seconds
Started Jun 13 02:50:37 PM PDT 24
Finished Jun 13 02:53:47 PM PDT 24
Peak memory 256936 kb
Host smart-655c09b4-50d5-4bd4-a2dd-e9bab83dd714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204915051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4204915051
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3747328490
Short name T82
Test name
Test status
Simulation time 72132005 ps
CPU time 1.21 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:22 PM PDT 24
Peak memory 216664 kb
Host smart-7493f211-d5cc-463f-b937-0d2fc1dd471e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747328490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3747328490
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1291626445
Short name T105
Test name
Test status
Simulation time 33945546 ps
CPU time 2.1 seconds
Started Jun 13 01:46:22 PM PDT 24
Finished Jun 13 01:46:25 PM PDT 24
Peak memory 215988 kb
Host smart-ca33e9a9-9d35-47db-a926-57c4bfdfac7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291626445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
291626445
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2801147353
Short name T116
Test name
Test status
Simulation time 1796093559 ps
CPU time 29.06 seconds
Started Jun 13 01:46:19 PM PDT 24
Finished Jun 13 01:46:49 PM PDT 24
Peak memory 215588 kb
Host smart-9278afea-fc19-48e7-ba8c-2499b8317d51
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801147353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2801147353
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.68667063
Short name T1080
Test name
Test status
Simulation time 198757456 ps
CPU time 2.8 seconds
Started Jun 13 01:46:18 PM PDT 24
Finished Jun 13 01:46:22 PM PDT 24
Peak memory 217172 kb
Host smart-c213c760-6ac4-419c-9bb8-c55dfb245196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68667063 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.68667063
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.269022981
Short name T1024
Test name
Test status
Simulation time 71884913 ps
CPU time 2.37 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:24 PM PDT 24
Peak memory 215664 kb
Host smart-1d9f77c2-2577-4c0f-ae7d-ae1074eef5b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269022981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.269022981
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.686067231
Short name T1008
Test name
Test status
Simulation time 17788545 ps
CPU time 0.75 seconds
Started Jun 13 01:46:19 PM PDT 24
Finished Jun 13 01:46:20 PM PDT 24
Peak memory 204012 kb
Host smart-88501bc6-5ee2-4399-95aa-580403e62bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686067231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.686067231
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2089370190
Short name T1094
Test name
Test status
Simulation time 80541116 ps
CPU time 1.71 seconds
Started Jun 13 01:46:21 PM PDT 24
Finished Jun 13 01:46:24 PM PDT 24
Peak memory 215872 kb
Host smart-be0d517a-6558-4b33-a48e-4b5d46bc88f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089370190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2089370190
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2319894225
Short name T1089
Test name
Test status
Simulation time 10501416 ps
CPU time 0.68 seconds
Started Jun 13 01:46:22 PM PDT 24
Finished Jun 13 01:46:24 PM PDT 24
Peak memory 204088 kb
Host smart-3ff285eb-1618-4d12-ae45-06bcf007b3ff
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319894225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2319894225
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.40481061
Short name T147
Test name
Test status
Simulation time 150984503 ps
CPU time 2.01 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:24 PM PDT 24
Peak memory 215680 kb
Host smart-f18bdf43-5341-4090-9588-c0f401007af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40481061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_same_csr_outstanding.40481061
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1184322102
Short name T1098
Test name
Test status
Simulation time 474356441 ps
CPU time 7.7 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:29 PM PDT 24
Peak memory 215620 kb
Host smart-5c49f78f-5e01-44bf-9bed-b3f0e775d792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184322102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1184322102
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.937868798
Short name T1093
Test name
Test status
Simulation time 703426866 ps
CPU time 21.56 seconds
Started Jun 13 01:46:26 PM PDT 24
Finished Jun 13 01:46:49 PM PDT 24
Peak memory 207436 kb
Host smart-f822c98b-c84b-4f3c-8364-f5341522b2ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937868798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.937868798
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3485379040
Short name T998
Test name
Test status
Simulation time 182638181 ps
CPU time 12.85 seconds
Started Jun 13 01:46:25 PM PDT 24
Finished Jun 13 01:46:39 PM PDT 24
Peak memory 207424 kb
Host smart-06826145-0cbc-4d5d-99a6-b0b2163a19eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485379040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3485379040
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2532740876
Short name T81
Test name
Test status
Simulation time 22019172 ps
CPU time 1.01 seconds
Started Jun 13 01:46:28 PM PDT 24
Finished Jun 13 01:46:30 PM PDT 24
Peak memory 207080 kb
Host smart-62511906-4f86-48d6-a801-dfe5ddc38a1b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532740876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2532740876
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1108839223
Short name T1054
Test name
Test status
Simulation time 158647247 ps
CPU time 2.79 seconds
Started Jun 13 01:46:25 PM PDT 24
Finished Jun 13 01:46:29 PM PDT 24
Peak memory 216968 kb
Host smart-9846332f-69ec-4bb9-b0fe-07fb6ce86aed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108839223 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1108839223
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.329596919
Short name T1059
Test name
Test status
Simulation time 127394780 ps
CPU time 2.23 seconds
Started Jun 13 01:46:26 PM PDT 24
Finished Jun 13 01:46:30 PM PDT 24
Peak memory 215668 kb
Host smart-d8c5b5b8-e09a-4346-b596-2d174d054715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329596919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.329596919
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4102932150
Short name T985
Test name
Test status
Simulation time 14840905 ps
CPU time 0.87 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:22 PM PDT 24
Peak memory 204040 kb
Host smart-9ec50983-7f40-4c9d-9922-6368cd5740bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102932150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
102932150
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2740811471
Short name T1039
Test name
Test status
Simulation time 34084939 ps
CPU time 1.45 seconds
Started Jun 13 01:46:26 PM PDT 24
Finished Jun 13 01:46:28 PM PDT 24
Peak memory 215744 kb
Host smart-3158038c-27c5-48cf-9a9b-4034bb266937
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740811471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2740811471
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3112294959
Short name T1042
Test name
Test status
Simulation time 12021998 ps
CPU time 0.66 seconds
Started Jun 13 01:46:19 PM PDT 24
Finished Jun 13 01:46:21 PM PDT 24
Peak memory 203956 kb
Host smart-c4a44ca2-8fb7-4715-88e4-9279a21b276b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112294959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3112294959
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2870953193
Short name T1046
Test name
Test status
Simulation time 705142713 ps
CPU time 4.06 seconds
Started Jun 13 01:46:25 PM PDT 24
Finished Jun 13 01:46:31 PM PDT 24
Peak memory 215576 kb
Host smart-199235c7-5b4b-4755-a19d-a949303d6bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870953193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2870953193
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1717606711
Short name T1041
Test name
Test status
Simulation time 960671976 ps
CPU time 3.75 seconds
Started Jun 13 01:46:21 PM PDT 24
Finished Jun 13 01:46:26 PM PDT 24
Peak memory 215724 kb
Host smart-9c083237-185f-4433-9086-f2f8bf72c520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717606711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
717606711
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3566864668
Short name T1009
Test name
Test status
Simulation time 529362344 ps
CPU time 14.72 seconds
Started Jun 13 01:46:20 PM PDT 24
Finished Jun 13 01:46:35 PM PDT 24
Peak memory 216008 kb
Host smart-5160d8d1-5ae2-4064-88b3-9bc6b7db5bdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566864668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3566864668
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2923183082
Short name T1040
Test name
Test status
Simulation time 286357750 ps
CPU time 3.61 seconds
Started Jun 13 01:46:51 PM PDT 24
Finished Jun 13 01:46:58 PM PDT 24
Peak memory 216960 kb
Host smart-3b76efe4-8531-4803-9824-fabe3df31a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923183082 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2923183082
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1762634166
Short name T121
Test name
Test status
Simulation time 27634008 ps
CPU time 1.85 seconds
Started Jun 13 01:46:51 PM PDT 24
Finished Jun 13 01:46:55 PM PDT 24
Peak memory 207476 kb
Host smart-03b67b09-d58d-493a-bbd9-42bd1ac94cb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762634166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1762634166
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3014972747
Short name T1082
Test name
Test status
Simulation time 14083549 ps
CPU time 0.7 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:54 PM PDT 24
Peak memory 204216 kb
Host smart-098d82cc-1136-4d89-aeb3-dc917205c71e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014972747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3014972747
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3384039545
Short name T140
Test name
Test status
Simulation time 27578601 ps
CPU time 1.71 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:54 PM PDT 24
Peak memory 215592 kb
Host smart-99462d66-7357-4026-9212-cf861ab0b52f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384039545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3384039545
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3950025154
Short name T1077
Test name
Test status
Simulation time 806702176 ps
CPU time 4.45 seconds
Started Jun 13 01:46:53 PM PDT 24
Finished Jun 13 01:47:00 PM PDT 24
Peak memory 215776 kb
Host smart-ca8333fc-447b-4124-bf2b-e6b7ff4a5f72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950025154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3950025154
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2306989494
Short name T265
Test name
Test status
Simulation time 296384924 ps
CPU time 8.05 seconds
Started Jun 13 01:46:53 PM PDT 24
Finished Jun 13 01:47:04 PM PDT 24
Peak memory 215664 kb
Host smart-055652f9-46b3-4e8b-bb6b-925984b87c43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306989494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2306989494
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.857471397
Short name T1015
Test name
Test status
Simulation time 250677203 ps
CPU time 3.48 seconds
Started Jun 13 01:46:52 PM PDT 24
Finished Jun 13 01:46:58 PM PDT 24
Peak memory 216740 kb
Host smart-8f906989-0c9b-44b8-8082-d51f4dafdd60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857471397 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.857471397
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1064382712
Short name T1005
Test name
Test status
Simulation time 385577941 ps
CPU time 2.01 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:55 PM PDT 24
Peak memory 207400 kb
Host smart-7ca6b892-44a4-4530-bd94-f670e4108f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064382712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1064382712
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2086311504
Short name T1033
Test name
Test status
Simulation time 58041234 ps
CPU time 0.83 seconds
Started Jun 13 01:46:49 PM PDT 24
Finished Jun 13 01:46:50 PM PDT 24
Peak memory 204016 kb
Host smart-5e52a372-f155-4aaf-a700-2f9961c45a90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086311504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2086311504
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.145600901
Short name T1078
Test name
Test status
Simulation time 168341105 ps
CPU time 3.25 seconds
Started Jun 13 01:46:49 PM PDT 24
Finished Jun 13 01:46:55 PM PDT 24
Peak memory 215672 kb
Host smart-0fea3e7b-b937-4449-9180-f5164794b8d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145600901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.145600901
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.493023082
Short name T1055
Test name
Test status
Simulation time 83916749 ps
CPU time 2.76 seconds
Started Jun 13 01:46:52 PM PDT 24
Finished Jun 13 01:46:57 PM PDT 24
Peak memory 215772 kb
Host smart-00f48fff-caad-4136-8d34-3c601cfe7b49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493023082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.493023082
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2994732793
Short name T1069
Test name
Test status
Simulation time 978555026 ps
CPU time 8.29 seconds
Started Jun 13 01:46:48 PM PDT 24
Finished Jun 13 01:46:58 PM PDT 24
Peak memory 215664 kb
Host smart-67500dfd-392d-433c-bb2f-4d35909f6c70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994732793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2994732793
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1534506066
Short name T1090
Test name
Test status
Simulation time 131147798 ps
CPU time 2.49 seconds
Started Jun 13 01:46:51 PM PDT 24
Finished Jun 13 01:46:56 PM PDT 24
Peak memory 217472 kb
Host smart-cff3815d-b4cf-4758-8e8c-331d7b5b2457
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534506066 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1534506066
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4231652656
Short name T123
Test name
Test status
Simulation time 63199330 ps
CPU time 2.08 seconds
Started Jun 13 01:46:51 PM PDT 24
Finished Jun 13 01:46:55 PM PDT 24
Peak memory 215620 kb
Host smart-5a925950-2877-4bf2-9246-ca2b2f6925a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231652656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4231652656
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.968937614
Short name T1051
Test name
Test status
Simulation time 13499110 ps
CPU time 0.7 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:53 PM PDT 24
Peak memory 203948 kb
Host smart-0a805743-1a54-4825-b6d7-f5a8ca3699da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968937614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.968937614
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3152694005
Short name T1065
Test name
Test status
Simulation time 28995007 ps
CPU time 1.67 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:54 PM PDT 24
Peak memory 216136 kb
Host smart-01fb33c1-2191-4847-8239-3580ffdb4108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152694005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3152694005
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3862184774
Short name T1073
Test name
Test status
Simulation time 406695798 ps
CPU time 1.36 seconds
Started Jun 13 01:46:49 PM PDT 24
Finished Jun 13 01:46:53 PM PDT 24
Peak memory 215852 kb
Host smart-41b5ea56-021a-49e8-9211-b6fa8741ce6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862184774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3862184774
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1879726693
Short name T267
Test name
Test status
Simulation time 115314848 ps
CPU time 6.71 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:59 PM PDT 24
Peak memory 215788 kb
Host smart-73063235-3cd9-4696-9f29-61d19da0cd8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879726693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1879726693
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2115216172
Short name T1091
Test name
Test status
Simulation time 49186373 ps
CPU time 1.94 seconds
Started Jun 13 01:46:59 PM PDT 24
Finished Jun 13 01:47:02 PM PDT 24
Peak memory 216692 kb
Host smart-98393bf5-4126-43dd-824e-4750eace9249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115216172 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2115216172
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1695116597
Short name T125
Test name
Test status
Simulation time 219344400 ps
CPU time 1.87 seconds
Started Jun 13 01:46:54 PM PDT 24
Finished Jun 13 01:46:58 PM PDT 24
Peak memory 215668 kb
Host smart-5cd918ca-dd73-4e14-855b-bd2f2726f8d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695116597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1695116597
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3195965940
Short name T1049
Test name
Test status
Simulation time 53247904 ps
CPU time 0.78 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:54 PM PDT 24
Peak memory 204020 kb
Host smart-186b255e-662f-441d-a769-454d9bfcfd54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195965940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3195965940
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.134590577
Short name T1004
Test name
Test status
Simulation time 105700124 ps
CPU time 1.75 seconds
Started Jun 13 01:46:57 PM PDT 24
Finished Jun 13 01:47:02 PM PDT 24
Peak memory 216844 kb
Host smart-1a38379c-14cc-419c-b9f7-cff1740ee796
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134590577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.134590577
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2626867332
Short name T1025
Test name
Test status
Simulation time 307268428 ps
CPU time 4.21 seconds
Started Jun 13 01:46:55 PM PDT 24
Finished Jun 13 01:47:02 PM PDT 24
Peak memory 217364 kb
Host smart-be3639fb-444f-4a12-a5cb-cb486f43e04d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626867332 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2626867332
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3033818153
Short name T1070
Test name
Test status
Simulation time 56995579 ps
CPU time 1.46 seconds
Started Jun 13 01:46:58 PM PDT 24
Finished Jun 13 01:47:01 PM PDT 24
Peak memory 215676 kb
Host smart-b31e94a3-3eb0-4d24-88ab-7469fbdb7c8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033818153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3033818153
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3203508432
Short name T1064
Test name
Test status
Simulation time 75317652 ps
CPU time 0.74 seconds
Started Jun 13 01:46:56 PM PDT 24
Finished Jun 13 01:47:00 PM PDT 24
Peak memory 204276 kb
Host smart-ed8ac7ae-0f59-42e3-aed3-372817e500ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203508432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3203508432
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.608394021
Short name T139
Test name
Test status
Simulation time 393261851 ps
CPU time 2.85 seconds
Started Jun 13 01:46:55 PM PDT 24
Finished Jun 13 01:47:00 PM PDT 24
Peak memory 215564 kb
Host smart-8ead5e0f-068d-4ba2-a3c1-498da48d5863
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608394021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.608394021
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3042709331
Short name T102
Test name
Test status
Simulation time 75019771 ps
CPU time 1.55 seconds
Started Jun 13 01:47:00 PM PDT 24
Finished Jun 13 01:47:02 PM PDT 24
Peak memory 215824 kb
Host smart-86b4eb4b-c857-4e1b-b8a6-58a5b17b7ae2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042709331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3042709331
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2812168668
Short name T1002
Test name
Test status
Simulation time 809093402 ps
CPU time 21.51 seconds
Started Jun 13 01:46:56 PM PDT 24
Finished Jun 13 01:47:20 PM PDT 24
Peak memory 215896 kb
Host smart-e46f8903-2f50-415c-ab9a-97fd64d59b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812168668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2812168668
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1187724725
Short name T151
Test name
Test status
Simulation time 255884025 ps
CPU time 3.16 seconds
Started Jun 13 01:46:55 PM PDT 24
Finished Jun 13 01:47:01 PM PDT 24
Peak memory 217088 kb
Host smart-b82043e6-b4a0-449d-9ecf-b48fd2f4a0c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187724725 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1187724725
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2500853610
Short name T999
Test name
Test status
Simulation time 35450879 ps
CPU time 1.34 seconds
Started Jun 13 01:46:57 PM PDT 24
Finished Jun 13 01:47:01 PM PDT 24
Peak memory 215728 kb
Host smart-89daac08-94a2-4196-9062-5c6f521ccf0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500853610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2500853610
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.400568897
Short name T1081
Test name
Test status
Simulation time 26808954 ps
CPU time 0.69 seconds
Started Jun 13 01:46:56 PM PDT 24
Finished Jun 13 01:46:59 PM PDT 24
Peak memory 204276 kb
Host smart-90dbdb08-5f11-444b-905d-8d786b6d4baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400568897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.400568897
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.231190168
Short name T1085
Test name
Test status
Simulation time 60619992 ps
CPU time 3.68 seconds
Started Jun 13 01:46:56 PM PDT 24
Finished Jun 13 01:47:02 PM PDT 24
Peak memory 215792 kb
Host smart-a5465d69-bbcc-423b-9f9e-456e99fa4331
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231190168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.231190168
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3717359632
Short name T1043
Test name
Test status
Simulation time 198006927 ps
CPU time 4.81 seconds
Started Jun 13 01:46:56 PM PDT 24
Finished Jun 13 01:47:03 PM PDT 24
Peak memory 215856 kb
Host smart-5c9643a1-6a3e-45b1-98a4-9f3e7ea2d96b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717359632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3717359632
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1808180277
Short name T111
Test name
Test status
Simulation time 1147752991 ps
CPU time 8.07 seconds
Started Jun 13 01:46:56 PM PDT 24
Finished Jun 13 01:47:07 PM PDT 24
Peak memory 215604 kb
Host smart-2e0c93b0-60ba-4390-9817-7d3ab3077437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808180277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1808180277
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1251755244
Short name T1034
Test name
Test status
Simulation time 602197011 ps
CPU time 2.89 seconds
Started Jun 13 01:47:03 PM PDT 24
Finished Jun 13 01:47:08 PM PDT 24
Peak memory 217544 kb
Host smart-154bfe39-5569-42f8-9eeb-1017149cc92f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251755244 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1251755244
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2748391686
Short name T118
Test name
Test status
Simulation time 66649813 ps
CPU time 1.99 seconds
Started Jun 13 01:46:57 PM PDT 24
Finished Jun 13 01:47:02 PM PDT 24
Peak memory 207392 kb
Host smart-d9d22e33-643b-4ba2-a3c8-9557471d7cfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748391686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2748391686
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.957402026
Short name T988
Test name
Test status
Simulation time 42290473 ps
CPU time 0.73 seconds
Started Jun 13 01:46:58 PM PDT 24
Finished Jun 13 01:47:01 PM PDT 24
Peak memory 204024 kb
Host smart-5c24edda-300b-47dd-96af-51a38ae5dd54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957402026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.957402026
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2908918006
Short name T992
Test name
Test status
Simulation time 69911210 ps
CPU time 2.65 seconds
Started Jun 13 01:47:05 PM PDT 24
Finished Jun 13 01:47:10 PM PDT 24
Peak memory 215580 kb
Host smart-1caec044-c1a1-467f-bd9f-3eac35e172e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908918006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2908918006
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.765263059
Short name T103
Test name
Test status
Simulation time 195656981 ps
CPU time 1.76 seconds
Started Jun 13 01:46:57 PM PDT 24
Finished Jun 13 01:47:01 PM PDT 24
Peak memory 215904 kb
Host smart-05ee8d98-d2d4-47aa-b353-280db0717b3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765263059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.765263059
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3837866889
Short name T268
Test name
Test status
Simulation time 710618596 ps
CPU time 17.52 seconds
Started Jun 13 01:46:56 PM PDT 24
Finished Jun 13 01:47:16 PM PDT 24
Peak memory 215656 kb
Host smart-71f340cd-6358-4183-9ff3-77f55b0a2857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837866889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3837866889
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3967448977
Short name T1035
Test name
Test status
Simulation time 765291901 ps
CPU time 2.89 seconds
Started Jun 13 01:47:01 PM PDT 24
Finished Jun 13 01:47:05 PM PDT 24
Peak memory 217444 kb
Host smart-ce1260dc-7bac-4e09-a327-383b3ac2fce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967448977 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3967448977
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3975697788
Short name T1071
Test name
Test status
Simulation time 64425393 ps
CPU time 2.02 seconds
Started Jun 13 01:47:05 PM PDT 24
Finished Jun 13 01:47:08 PM PDT 24
Peak memory 207404 kb
Host smart-0364e030-26ca-4926-9210-c67afa011318
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975697788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3975697788
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2975646655
Short name T1101
Test name
Test status
Simulation time 31482061 ps
CPU time 0.86 seconds
Started Jun 13 01:47:02 PM PDT 24
Finished Jun 13 01:47:04 PM PDT 24
Peak memory 204040 kb
Host smart-26c69c9c-e00c-42d1-ab2e-6d09dcc378fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975646655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2975646655
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1318931412
Short name T1097
Test name
Test status
Simulation time 135927030 ps
CPU time 1.95 seconds
Started Jun 13 01:47:01 PM PDT 24
Finished Jun 13 01:47:05 PM PDT 24
Peak memory 207424 kb
Host smart-6961f423-2ace-4bd7-a130-c1a84c7dd774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318931412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1318931412
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.894705787
Short name T109
Test name
Test status
Simulation time 146500354 ps
CPU time 3.06 seconds
Started Jun 13 01:47:02 PM PDT 24
Finished Jun 13 01:47:07 PM PDT 24
Peak memory 215800 kb
Host smart-eb91739c-0750-4efe-bc0b-f166a8736e08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894705787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.894705787
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.986860338
Short name T266
Test name
Test status
Simulation time 539692468 ps
CPU time 15.49 seconds
Started Jun 13 01:47:03 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 215616 kb
Host smart-ab881770-2cdb-4174-ba34-e151cf758e55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986860338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.986860338
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1826826606
Short name T1021
Test name
Test status
Simulation time 204878900 ps
CPU time 1.71 seconds
Started Jun 13 01:47:02 PM PDT 24
Finished Jun 13 01:47:05 PM PDT 24
Peak memory 215732 kb
Host smart-c2279988-248e-4a5d-8ace-fae6ffb257e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826826606 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1826826606
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3689168558
Short name T114
Test name
Test status
Simulation time 31641063 ps
CPU time 1.85 seconds
Started Jun 13 01:47:06 PM PDT 24
Finished Jun 13 01:47:09 PM PDT 24
Peak memory 207468 kb
Host smart-f1be8872-4064-41f8-a2d7-22af3c9dd243
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689168558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3689168558
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3698099126
Short name T1052
Test name
Test status
Simulation time 46128488 ps
CPU time 0.82 seconds
Started Jun 13 01:47:01 PM PDT 24
Finished Jun 13 01:47:04 PM PDT 24
Peak memory 204272 kb
Host smart-f10be702-2a68-4144-868c-c813fefd9100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698099126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3698099126
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3422546820
Short name T1044
Test name
Test status
Simulation time 46141467 ps
CPU time 1.81 seconds
Started Jun 13 01:47:04 PM PDT 24
Finished Jun 13 01:47:08 PM PDT 24
Peak memory 215656 kb
Host smart-7aa2b38a-7bea-4e8e-83da-930e7bc3b230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422546820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3422546820
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3829626649
Short name T101
Test name
Test status
Simulation time 980081642 ps
CPU time 4.45 seconds
Started Jun 13 01:47:02 PM PDT 24
Finished Jun 13 01:47:09 PM PDT 24
Peak memory 215928 kb
Host smart-d244a177-57a9-469f-8237-5bea77484738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829626649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3829626649
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.473822679
Short name T150
Test name
Test status
Simulation time 2629732703 ps
CPU time 14.43 seconds
Started Jun 13 01:47:04 PM PDT 24
Finished Jun 13 01:47:20 PM PDT 24
Peak memory 216324 kb
Host smart-b813bf37-964e-4ae2-bcba-4ea2685c90d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473822679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.473822679
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2734781124
Short name T149
Test name
Test status
Simulation time 365463279 ps
CPU time 2.73 seconds
Started Jun 13 01:47:03 PM PDT 24
Finished Jun 13 01:47:08 PM PDT 24
Peak memory 216832 kb
Host smart-48313757-ebde-4e0c-a71a-aaaf5869c22b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734781124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2734781124
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.888906972
Short name T993
Test name
Test status
Simulation time 76080516 ps
CPU time 1.36 seconds
Started Jun 13 01:47:03 PM PDT 24
Finished Jun 13 01:47:07 PM PDT 24
Peak memory 207468 kb
Host smart-d2249fae-cdfb-4984-a227-b225540e3669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888906972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.888906972
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2573805231
Short name T1083
Test name
Test status
Simulation time 161787044 ps
CPU time 0.67 seconds
Started Jun 13 01:47:04 PM PDT 24
Finished Jun 13 01:47:07 PM PDT 24
Peak memory 203952 kb
Host smart-0db20a7f-0360-4854-b585-3d9cfc9a2643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573805231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2573805231
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2614184467
Short name T1010
Test name
Test status
Simulation time 111899704 ps
CPU time 3.2 seconds
Started Jun 13 01:47:03 PM PDT 24
Finished Jun 13 01:47:09 PM PDT 24
Peak memory 215656 kb
Host smart-ef7215c7-2018-45e6-9ff5-935da68d9c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614184467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2614184467
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3530325970
Short name T122
Test name
Test status
Simulation time 430802247 ps
CPU time 13.74 seconds
Started Jun 13 01:46:29 PM PDT 24
Finished Jun 13 01:46:43 PM PDT 24
Peak memory 207488 kb
Host smart-c7eef284-c7d9-4517-905f-d762663adde1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530325970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3530325970
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.980453548
Short name T146
Test name
Test status
Simulation time 27047026156 ps
CPU time 38.66 seconds
Started Jun 13 01:46:29 PM PDT 24
Finished Jun 13 01:47:09 PM PDT 24
Peak memory 207548 kb
Host smart-88666e07-3d3d-46e0-a0ed-cbc30e86800b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980453548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.980453548
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.373050065
Short name T79
Test name
Test status
Simulation time 18958827 ps
CPU time 1.15 seconds
Started Jun 13 01:46:26 PM PDT 24
Finished Jun 13 01:46:29 PM PDT 24
Peak memory 207440 kb
Host smart-f6a414bc-b538-42ea-a8b6-18919ff50fd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373050065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.373050065
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2029432931
Short name T1057
Test name
Test status
Simulation time 213356905 ps
CPU time 3.69 seconds
Started Jun 13 01:46:24 PM PDT 24
Finished Jun 13 01:46:29 PM PDT 24
Peak memory 217400 kb
Host smart-ea323315-3f09-4777-884e-94ec336d5656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029432931 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2029432931
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.297388019
Short name T141
Test name
Test status
Simulation time 128757909 ps
CPU time 1.38 seconds
Started Jun 13 01:46:26 PM PDT 24
Finished Jun 13 01:46:28 PM PDT 24
Peak memory 207036 kb
Host smart-ea58ba2e-b7fb-4d8d-a1b2-c616a47f6fce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297388019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.297388019
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.865579831
Short name T980
Test name
Test status
Simulation time 55044248 ps
CPU time 0.76 seconds
Started Jun 13 01:46:25 PM PDT 24
Finished Jun 13 01:46:27 PM PDT 24
Peak memory 203992 kb
Host smart-35577b45-8b67-46c4-ae57-c5c30dc74cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865579831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.865579831
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4196822194
Short name T1063
Test name
Test status
Simulation time 32197102 ps
CPU time 1.19 seconds
Started Jun 13 01:46:27 PM PDT 24
Finished Jun 13 01:46:29 PM PDT 24
Peak memory 215676 kb
Host smart-39e1b0ca-e622-4657-952e-a161526d4448
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196822194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4196822194
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3927659490
Short name T1023
Test name
Test status
Simulation time 84664843 ps
CPU time 0.65 seconds
Started Jun 13 01:46:24 PM PDT 24
Finished Jun 13 01:46:26 PM PDT 24
Peak memory 203868 kb
Host smart-00e5c323-efa6-4dcc-9805-69002e3335a8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927659490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3927659490
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1570718998
Short name T1003
Test name
Test status
Simulation time 661204408 ps
CPU time 4.42 seconds
Started Jun 13 01:46:25 PM PDT 24
Finished Jun 13 01:46:31 PM PDT 24
Peak memory 215660 kb
Host smart-de4dc886-0eaf-40e1-8cb8-9f0eef125b58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570718998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1570718998
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1488954253
Short name T1045
Test name
Test status
Simulation time 57991670 ps
CPU time 1.96 seconds
Started Jun 13 01:46:25 PM PDT 24
Finished Jun 13 01:46:28 PM PDT 24
Peak memory 215788 kb
Host smart-3e536b2d-488d-4d80-99a5-63e27fb8a760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488954253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
488954253
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2970796715
Short name T264
Test name
Test status
Simulation time 299898109 ps
CPU time 18.63 seconds
Started Jun 13 01:46:26 PM PDT 24
Finished Jun 13 01:46:46 PM PDT 24
Peak memory 215788 kb
Host smart-92bc3584-5d47-410d-8f93-d633c0a32ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970796715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2970796715
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.103052935
Short name T984
Test name
Test status
Simulation time 11603287 ps
CPU time 0.74 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 203956 kb
Host smart-e3a5ef80-42db-4799-84d0-1c0257092a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103052935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.103052935
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4234942077
Short name T1031
Test name
Test status
Simulation time 11194393 ps
CPU time 0.73 seconds
Started Jun 13 01:47:12 PM PDT 24
Finished Jun 13 01:47:14 PM PDT 24
Peak memory 204276 kb
Host smart-334b867e-59e6-4f24-8a05-101d5e26be97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234942077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4234942077
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1470027608
Short name T1011
Test name
Test status
Simulation time 60275606 ps
CPU time 0.74 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 203964 kb
Host smart-95c59b51-2562-4fef-bba1-a6dbe3d8d4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470027608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1470027608
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.347403765
Short name T983
Test name
Test status
Simulation time 61417538 ps
CPU time 0.69 seconds
Started Jun 13 01:47:13 PM PDT 24
Finished Jun 13 01:47:14 PM PDT 24
Peak memory 204264 kb
Host smart-49347ac8-2ed0-46be-9a8c-c73d693b185b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347403765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.347403765
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.894382694
Short name T989
Test name
Test status
Simulation time 26564688 ps
CPU time 0.78 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 204264 kb
Host smart-6cd4fbe4-0b12-4693-8e3d-8a500b119937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894382694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.894382694
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.684362495
Short name T979
Test name
Test status
Simulation time 16741248 ps
CPU time 0.77 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 204028 kb
Host smart-1371fbb7-786d-4709-9ef3-fd6884d9af20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684362495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.684362495
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2113375436
Short name T1026
Test name
Test status
Simulation time 53505919 ps
CPU time 0.74 seconds
Started Jun 13 01:47:12 PM PDT 24
Finished Jun 13 01:47:14 PM PDT 24
Peak memory 203980 kb
Host smart-fed1deab-38d4-4588-8a25-eea3c50c32d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113375436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2113375436
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.767146504
Short name T995
Test name
Test status
Simulation time 42356444 ps
CPU time 0.79 seconds
Started Jun 13 01:47:11 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 203952 kb
Host smart-baba765c-8481-4548-b4d9-16162d4ba25b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767146504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.767146504
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1339354769
Short name T1056
Test name
Test status
Simulation time 21001779 ps
CPU time 0.72 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 204296 kb
Host smart-0241e0b7-2c4c-4c68-b79e-515b9e0f54c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339354769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1339354769
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1898572552
Short name T991
Test name
Test status
Simulation time 13679201 ps
CPU time 0.73 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 204300 kb
Host smart-33f926a9-afd3-485a-9374-3d454dfe25d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898572552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1898572552
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2949738201
Short name T1001
Test name
Test status
Simulation time 118404508 ps
CPU time 8.6 seconds
Started Jun 13 01:46:31 PM PDT 24
Finished Jun 13 01:46:41 PM PDT 24
Peak memory 215624 kb
Host smart-9a1fa7f5-1fea-4512-8c9e-e8d30f2597fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949738201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2949738201
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1027583402
Short name T1048
Test name
Test status
Simulation time 25778492706 ps
CPU time 37.12 seconds
Started Jun 13 01:46:31 PM PDT 24
Finished Jun 13 01:47:09 PM PDT 24
Peak memory 207628 kb
Host smart-0fc38ffa-ab5d-4a2f-8d89-fb630de01bc9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027583402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1027583402
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2939848305
Short name T80
Test name
Test status
Simulation time 18277257 ps
CPU time 1.19 seconds
Started Jun 13 01:46:33 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 216628 kb
Host smart-57f1c25a-6c84-47f6-a7b8-57059d506881
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939848305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2939848305
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3689531614
Short name T1072
Test name
Test status
Simulation time 79847239 ps
CPU time 1.8 seconds
Started Jun 13 01:46:33 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 216668 kb
Host smart-41bf00de-1c2e-4f6d-84c7-57ae5e488cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689531614 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3689531614
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4221134572
Short name T124
Test name
Test status
Simulation time 188935555 ps
CPU time 2.42 seconds
Started Jun 13 01:46:33 PM PDT 24
Finished Jun 13 01:46:37 PM PDT 24
Peak memory 215672 kb
Host smart-5a0f8376-b729-499c-a673-516ed3759f2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221134572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
221134572
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2107117251
Short name T1028
Test name
Test status
Simulation time 14162102 ps
CPU time 0.72 seconds
Started Jun 13 01:46:30 PM PDT 24
Finished Jun 13 01:46:32 PM PDT 24
Peak memory 204280 kb
Host smart-051e617b-5404-472e-ac82-172ce6ffbc62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107117251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
107117251
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2103951709
Short name T126
Test name
Test status
Simulation time 20689039 ps
CPU time 1.28 seconds
Started Jun 13 01:46:30 PM PDT 24
Finished Jun 13 01:46:33 PM PDT 24
Peak memory 215784 kb
Host smart-d8859b85-ba44-4530-9906-ae5f7bea1e97
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103951709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2103951709
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2789313465
Short name T1029
Test name
Test status
Simulation time 15166857 ps
CPU time 0.65 seconds
Started Jun 13 01:46:34 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 203948 kb
Host smart-98298b1b-c9b2-4aa2-be7c-f9400c2b4a57
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789313465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2789313465
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.428899060
Short name T1020
Test name
Test status
Simulation time 62729053 ps
CPU time 3.87 seconds
Started Jun 13 01:46:31 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 215552 kb
Host smart-5bcfef4b-0b15-48eb-abcc-ed2b6dfbb41e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428899060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.428899060
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3120470158
Short name T106
Test name
Test status
Simulation time 395874755 ps
CPU time 3.34 seconds
Started Jun 13 01:46:32 PM PDT 24
Finished Jun 13 01:46:38 PM PDT 24
Peak memory 215852 kb
Host smart-9a366ca5-32b5-4f64-bb77-a64d74cce370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120470158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
120470158
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2723451067
Short name T1060
Test name
Test status
Simulation time 206077489 ps
CPU time 6.72 seconds
Started Jun 13 01:46:34 PM PDT 24
Finished Jun 13 01:46:42 PM PDT 24
Peak memory 215668 kb
Host smart-77810be7-e7fb-4a7b-8f65-f5730349a622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723451067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2723451067
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.599461612
Short name T982
Test name
Test status
Simulation time 14195901 ps
CPU time 0.7 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 203988 kb
Host smart-e1c2966f-ec9c-4a7f-b135-9cf0b3a2a3ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599461612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.599461612
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3469499097
Short name T997
Test name
Test status
Simulation time 21680521 ps
CPU time 0.71 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 204008 kb
Host smart-fa96a68b-8d61-4182-a086-31a1006ea577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469499097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3469499097
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.196900168
Short name T1099
Test name
Test status
Simulation time 16402759 ps
CPU time 0.79 seconds
Started Jun 13 01:47:09 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 204036 kb
Host smart-20932427-8d52-41b3-bc91-4a87fff88374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196900168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.196900168
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3206407105
Short name T1100
Test name
Test status
Simulation time 14005823 ps
CPU time 0.72 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 203964 kb
Host smart-0ff9a05f-84b5-48bb-b111-7d2080eb191b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206407105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3206407105
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.594578887
Short name T1079
Test name
Test status
Simulation time 25764299 ps
CPU time 0.73 seconds
Started Jun 13 01:47:09 PM PDT 24
Finished Jun 13 01:47:11 PM PDT 24
Peak memory 203940 kb
Host smart-582d94b2-339c-470d-8412-09c7e80f11b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594578887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.594578887
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2768809643
Short name T1016
Test name
Test status
Simulation time 40294667 ps
CPU time 0.7 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 203980 kb
Host smart-9424be3b-505c-48e4-9166-7a4929bd9e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768809643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2768809643
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3423100380
Short name T1012
Test name
Test status
Simulation time 43919387 ps
CPU time 0.73 seconds
Started Jun 13 01:47:09 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 203904 kb
Host smart-6dcaa2f5-d5fd-400d-97b0-b263a1ba9098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423100380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3423100380
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2799458762
Short name T1018
Test name
Test status
Simulation time 111411561 ps
CPU time 0.77 seconds
Started Jun 13 01:47:09 PM PDT 24
Finished Jun 13 01:47:11 PM PDT 24
Peak memory 204280 kb
Host smart-a38c4aa4-b766-40c6-bcdf-8e9a6d46ca5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799458762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2799458762
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2143094373
Short name T996
Test name
Test status
Simulation time 19770186 ps
CPU time 0.74 seconds
Started Jun 13 01:47:09 PM PDT 24
Finished Jun 13 01:47:11 PM PDT 24
Peak memory 204012 kb
Host smart-68e0bb13-64ba-4a40-95b3-7c5e22caa765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143094373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2143094373
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4203983194
Short name T1087
Test name
Test status
Simulation time 19528968 ps
CPU time 0.75 seconds
Started Jun 13 01:47:08 PM PDT 24
Finished Jun 13 01:47:10 PM PDT 24
Peak memory 204280 kb
Host smart-951593b2-c08b-4de5-affe-c5c9f9a4c887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203983194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4203983194
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3984335229
Short name T120
Test name
Test status
Simulation time 612993471 ps
CPU time 21.25 seconds
Started Jun 13 01:46:39 PM PDT 24
Finished Jun 13 01:47:02 PM PDT 24
Peak memory 215628 kb
Host smart-862b6d92-e358-4d53-a7eb-830180eb34bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984335229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3984335229
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1992557867
Short name T1066
Test name
Test status
Simulation time 1598558828 ps
CPU time 20.79 seconds
Started Jun 13 01:46:41 PM PDT 24
Finished Jun 13 01:47:03 PM PDT 24
Peak memory 207400 kb
Host smart-f1546529-60a8-457a-9f28-aeb6307f94da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992557867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1992557867
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3180369171
Short name T83
Test name
Test status
Simulation time 38287013 ps
CPU time 1.4 seconds
Started Jun 13 01:46:33 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 207464 kb
Host smart-1d015f74-eaf7-4a04-80a1-87c5bc9419a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180369171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3180369171
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.728919921
Short name T1050
Test name
Test status
Simulation time 194702602 ps
CPU time 1.75 seconds
Started Jun 13 01:46:37 PM PDT 24
Finished Jun 13 01:46:40 PM PDT 24
Peak memory 215752 kb
Host smart-2061ee4e-5ce2-4879-b30b-18ef36e7b90b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728919921 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.728919921
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2450672091
Short name T1032
Test name
Test status
Simulation time 249578230 ps
CPU time 1.79 seconds
Started Jun 13 01:46:31 PM PDT 24
Finished Jun 13 01:46:34 PM PDT 24
Peak memory 215668 kb
Host smart-7fe724c7-d9c6-46eb-a403-bd58ab2e3074
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450672091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
450672091
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4148067197
Short name T986
Test name
Test status
Simulation time 12483291 ps
CPU time 0.72 seconds
Started Jun 13 01:46:35 PM PDT 24
Finished Jun 13 01:46:37 PM PDT 24
Peak memory 203948 kb
Host smart-1c3f9836-e0ca-46cb-946b-83ad5a366e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148067197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
148067197
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3206322909
Short name T119
Test name
Test status
Simulation time 36314096 ps
CPU time 1.58 seconds
Started Jun 13 01:46:32 PM PDT 24
Finished Jun 13 01:46:36 PM PDT 24
Peak memory 215668 kb
Host smart-e8d61a35-6384-42a6-91df-ff7a737c0ae4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206322909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3206322909
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2224957384
Short name T1036
Test name
Test status
Simulation time 47749181 ps
CPU time 0.66 seconds
Started Jun 13 01:46:31 PM PDT 24
Finished Jun 13 01:46:33 PM PDT 24
Peak memory 203940 kb
Host smart-72e7bed0-ca16-400b-8949-dd9dbe85a7c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224957384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2224957384
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.529611556
Short name T1092
Test name
Test status
Simulation time 215814437 ps
CPU time 4.32 seconds
Started Jun 13 01:46:40 PM PDT 24
Finished Jun 13 01:46:45 PM PDT 24
Peak memory 215604 kb
Host smart-c771d597-27b4-4b8a-876f-0e9312577d8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529611556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.529611556
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3651148997
Short name T1058
Test name
Test status
Simulation time 627819878 ps
CPU time 4.18 seconds
Started Jun 13 01:46:32 PM PDT 24
Finished Jun 13 01:46:38 PM PDT 24
Peak memory 215748 kb
Host smart-1bcbf04f-63b9-4a76-984d-1b70ea6457a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651148997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
651148997
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1510296621
Short name T1062
Test name
Test status
Simulation time 1173763324 ps
CPU time 16.11 seconds
Started Jun 13 01:46:33 PM PDT 24
Finished Jun 13 01:46:51 PM PDT 24
Peak memory 216420 kb
Host smart-b9770dd6-02d3-4518-a9bd-866e695447fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510296621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1510296621
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2639064999
Short name T1096
Test name
Test status
Simulation time 22108513 ps
CPU time 0.72 seconds
Started Jun 13 01:47:11 PM PDT 24
Finished Jun 13 01:47:14 PM PDT 24
Peak memory 203976 kb
Host smart-47425ede-0a94-4853-8037-70f9ecafdb4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639064999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2639064999
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1259333174
Short name T994
Test name
Test status
Simulation time 60371040 ps
CPU time 0.73 seconds
Started Jun 13 01:47:09 PM PDT 24
Finished Jun 13 01:47:11 PM PDT 24
Peak memory 203992 kb
Host smart-97023a76-05c6-4620-8928-161203b7c069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259333174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1259333174
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2234103283
Short name T1038
Test name
Test status
Simulation time 16312278 ps
CPU time 0.75 seconds
Started Jun 13 01:47:11 PM PDT 24
Finished Jun 13 01:47:14 PM PDT 24
Peak memory 204024 kb
Host smart-880c4f33-baac-4cf8-8126-89da386a2c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234103283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2234103283
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.918938383
Short name T1017
Test name
Test status
Simulation time 48148323 ps
CPU time 0.79 seconds
Started Jun 13 01:47:11 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 204276 kb
Host smart-fad0fab3-7c55-4748-a831-3bde5608a94f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918938383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.918938383
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2735419899
Short name T1022
Test name
Test status
Simulation time 34292733 ps
CPU time 0.76 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 203944 kb
Host smart-36b63323-8efa-4ae1-9f7d-3839f6f70acc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735419899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2735419899
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.163088465
Short name T1053
Test name
Test status
Simulation time 21814406 ps
CPU time 0.74 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 204008 kb
Host smart-c6a4e8f0-792c-4018-bdbf-9572e5afd8e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163088465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.163088465
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2140851485
Short name T1088
Test name
Test status
Simulation time 12395950 ps
CPU time 0.75 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:13 PM PDT 24
Peak memory 203984 kb
Host smart-1cf89e2b-3ba6-42a7-9d6d-e13d8d23f51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140851485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2140851485
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.585767578
Short name T1007
Test name
Test status
Simulation time 15221703 ps
CPU time 0.7 seconds
Started Jun 13 01:47:19 PM PDT 24
Finished Jun 13 01:47:21 PM PDT 24
Peak memory 203936 kb
Host smart-6b5742e3-95b4-469c-80d3-420482d72267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585767578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.585767578
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2676437428
Short name T1027
Test name
Test status
Simulation time 12255731 ps
CPU time 0.74 seconds
Started Jun 13 01:47:09 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 203964 kb
Host smart-3d004bff-64d1-48ec-ae3a-5aadd5c9f1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676437428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2676437428
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.52506102
Short name T1013
Test name
Test status
Simulation time 14843421 ps
CPU time 0.74 seconds
Started Jun 13 01:47:10 PM PDT 24
Finished Jun 13 01:47:12 PM PDT 24
Peak memory 203996 kb
Host smart-d01d46db-6991-4d12-af4e-511417e97119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52506102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.52506102
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3366932226
Short name T110
Test name
Test status
Simulation time 27478067 ps
CPU time 1.78 seconds
Started Jun 13 01:46:41 PM PDT 24
Finished Jun 13 01:46:43 PM PDT 24
Peak memory 215712 kb
Host smart-eb360fb8-dc5e-4432-a075-13b68c04cc84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366932226 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3366932226
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1101395215
Short name T1075
Test name
Test status
Simulation time 67451740 ps
CPU time 1.29 seconds
Started Jun 13 01:46:37 PM PDT 24
Finished Jun 13 01:46:39 PM PDT 24
Peak memory 215600 kb
Host smart-313e1002-8b1f-459f-a6a2-1988f2ae75ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101395215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
101395215
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.373870805
Short name T1019
Test name
Test status
Simulation time 11922625 ps
CPU time 0.74 seconds
Started Jun 13 01:46:38 PM PDT 24
Finished Jun 13 01:46:40 PM PDT 24
Peak memory 204320 kb
Host smart-74c68327-619d-425e-84e1-7533b9e729ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373870805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.373870805
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3517215020
Short name T1074
Test name
Test status
Simulation time 153898969 ps
CPU time 3.46 seconds
Started Jun 13 01:46:40 PM PDT 24
Finished Jun 13 01:46:45 PM PDT 24
Peak memory 215576 kb
Host smart-2dcde7dc-0a4c-4547-aba1-53a117dac7e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517215020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3517215020
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2833498612
Short name T108
Test name
Test status
Simulation time 804103989 ps
CPU time 4.73 seconds
Started Jun 13 01:46:37 PM PDT 24
Finished Jun 13 01:46:43 PM PDT 24
Peak memory 215788 kb
Host smart-9d7ede79-faba-420d-8d6a-33afd50cfcb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833498612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
833498612
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2068947076
Short name T1061
Test name
Test status
Simulation time 603870167 ps
CPU time 14.87 seconds
Started Jun 13 01:46:36 PM PDT 24
Finished Jun 13 01:46:52 PM PDT 24
Peak memory 215712 kb
Host smart-c2159733-b3a7-4513-aa19-cba527ed6a05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068947076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2068947076
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3835136782
Short name T93
Test name
Test status
Simulation time 79843982 ps
CPU time 2.66 seconds
Started Jun 13 01:46:37 PM PDT 24
Finished Jun 13 01:46:41 PM PDT 24
Peak memory 216816 kb
Host smart-ed3d3aa4-d553-47bb-a73f-dd008842e819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835136782 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3835136782
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.213836965
Short name T113
Test name
Test status
Simulation time 88521499 ps
CPU time 2.47 seconds
Started Jun 13 01:46:41 PM PDT 24
Finished Jun 13 01:46:44 PM PDT 24
Peak memory 215596 kb
Host smart-771a5443-e8c5-43df-8f6d-53c52ca3dd21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213836965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.213836965
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.447172751
Short name T990
Test name
Test status
Simulation time 17212757 ps
CPU time 0.74 seconds
Started Jun 13 01:46:38 PM PDT 24
Finished Jun 13 01:46:40 PM PDT 24
Peak memory 204016 kb
Host smart-ea427209-6878-47da-a7d8-aac00d214460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447172751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.447172751
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.920832193
Short name T1084
Test name
Test status
Simulation time 45861384 ps
CPU time 2.97 seconds
Started Jun 13 01:46:38 PM PDT 24
Finished Jun 13 01:46:42 PM PDT 24
Peak memory 215572 kb
Host smart-887a94a8-6757-4bc2-9e7a-9000b9549608
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920832193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.920832193
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2652947478
Short name T97
Test name
Test status
Simulation time 423489398 ps
CPU time 2.46 seconds
Started Jun 13 01:46:37 PM PDT 24
Finished Jun 13 01:46:41 PM PDT 24
Peak memory 215776 kb
Host smart-20cc3eb5-3c61-4b67-bdb5-71eac4d8a695
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652947478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
652947478
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2694406695
Short name T1047
Test name
Test status
Simulation time 216645029 ps
CPU time 6.77 seconds
Started Jun 13 01:46:40 PM PDT 24
Finished Jun 13 01:46:48 PM PDT 24
Peak memory 215828 kb
Host smart-e1637386-c780-4245-ba49-2dfd4165c1fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694406695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2694406695
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.577049850
Short name T1030
Test name
Test status
Simulation time 74448346 ps
CPU time 2.63 seconds
Started Jun 13 01:46:44 PM PDT 24
Finished Jun 13 01:46:48 PM PDT 24
Peak memory 217000 kb
Host smart-d617e18a-70da-4581-97e9-3f16a5d58d51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577049850 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.577049850
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1850175610
Short name T1067
Test name
Test status
Simulation time 37856689 ps
CPU time 1.35 seconds
Started Jun 13 01:46:44 PM PDT 24
Finished Jun 13 01:46:46 PM PDT 24
Peak memory 207412 kb
Host smart-bed9b09a-19bd-4fba-947c-e58c81db20a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850175610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
850175610
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2518454780
Short name T1095
Test name
Test status
Simulation time 29624790 ps
CPU time 0.74 seconds
Started Jun 13 01:46:37 PM PDT 24
Finished Jun 13 01:46:39 PM PDT 24
Peak memory 204024 kb
Host smart-5b47a7f0-6301-4c7f-ab73-ab69ef3b61b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518454780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
518454780
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2852246493
Short name T1086
Test name
Test status
Simulation time 434838079 ps
CPU time 3.03 seconds
Started Jun 13 01:46:46 PM PDT 24
Finished Jun 13 01:46:50 PM PDT 24
Peak memory 215672 kb
Host smart-182a4841-26f7-42cb-b52a-7ecafcd74dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852246493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2852246493
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3258494933
Short name T1076
Test name
Test status
Simulation time 57545962 ps
CPU time 3.63 seconds
Started Jun 13 01:46:39 PM PDT 24
Finished Jun 13 01:46:44 PM PDT 24
Peak memory 216812 kb
Host smart-6c21483a-59da-4967-83f6-560ccb57ea91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258494933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
258494933
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2342317843
Short name T96
Test name
Test status
Simulation time 397421609 ps
CPU time 13.03 seconds
Started Jun 13 01:46:41 PM PDT 24
Finished Jun 13 01:46:55 PM PDT 24
Peak memory 216536 kb
Host smart-c8d7cff7-ae01-42e0-a0aa-cf4183b63042
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342317843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2342317843
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.361554492
Short name T148
Test name
Test status
Simulation time 199420384 ps
CPU time 2.62 seconds
Started Jun 13 01:46:45 PM PDT 24
Finished Jun 13 01:46:49 PM PDT 24
Peak memory 216788 kb
Host smart-1402284c-9233-4b7a-9c91-7e1864445367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361554492 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.361554492
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.331545042
Short name T1037
Test name
Test status
Simulation time 60040641 ps
CPU time 1.23 seconds
Started Jun 13 01:46:42 PM PDT 24
Finished Jun 13 01:46:44 PM PDT 24
Peak memory 207416 kb
Host smart-0bb584a3-4a23-42eb-819a-5643a80008bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331545042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.331545042
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2090858028
Short name T981
Test name
Test status
Simulation time 12035936 ps
CPU time 0.78 seconds
Started Jun 13 01:46:43 PM PDT 24
Finished Jun 13 01:46:46 PM PDT 24
Peak memory 203960 kb
Host smart-1812b244-496d-4487-b53b-b85933f6821a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090858028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
090858028
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2271046932
Short name T1014
Test name
Test status
Simulation time 195857009 ps
CPU time 2.93 seconds
Started Jun 13 01:46:45 PM PDT 24
Finished Jun 13 01:46:49 PM PDT 24
Peak memory 215572 kb
Host smart-eb18d68a-8a18-4d1a-8248-42a0d46b74d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271046932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2271046932
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.543165877
Short name T104
Test name
Test status
Simulation time 605954034 ps
CPU time 4.05 seconds
Started Jun 13 01:46:43 PM PDT 24
Finished Jun 13 01:46:49 PM PDT 24
Peak memory 216840 kb
Host smart-60352cb2-7553-4913-9171-b5c08b854fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543165877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.543165877
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.136279784
Short name T1006
Test name
Test status
Simulation time 173358228 ps
CPU time 1.64 seconds
Started Jun 13 01:46:50 PM PDT 24
Finished Jun 13 01:46:54 PM PDT 24
Peak memory 215804 kb
Host smart-c10270b9-4cad-4bc0-98bd-820635f3be57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136279784 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.136279784
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2505750101
Short name T115
Test name
Test status
Simulation time 40148305 ps
CPU time 2.65 seconds
Started Jun 13 01:46:44 PM PDT 24
Finished Jun 13 01:46:48 PM PDT 24
Peak memory 215604 kb
Host smart-e08fbf70-42cf-4e73-98f8-1e9df949435a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505750101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
505750101
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4165317091
Short name T987
Test name
Test status
Simulation time 18287104 ps
CPU time 0.73 seconds
Started Jun 13 01:46:43 PM PDT 24
Finished Jun 13 01:46:45 PM PDT 24
Peak memory 204464 kb
Host smart-33227648-0600-4912-9c31-dac36551e003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165317091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
165317091
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3161965486
Short name T1000
Test name
Test status
Simulation time 111549736 ps
CPU time 1.91 seconds
Started Jun 13 01:46:45 PM PDT 24
Finished Jun 13 01:46:48 PM PDT 24
Peak memory 215588 kb
Host smart-5a579c87-82c3-409c-9ea8-9d09f2589471
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161965486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3161965486
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1770493458
Short name T94
Test name
Test status
Simulation time 511158518 ps
CPU time 3.23 seconds
Started Jun 13 01:46:42 PM PDT 24
Finished Jun 13 01:46:46 PM PDT 24
Peak memory 215768 kb
Host smart-2f5e3479-f0ab-4702-bc49-3afd030c2e98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770493458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
770493458
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1478527138
Short name T1068
Test name
Test status
Simulation time 1158218237 ps
CPU time 19.36 seconds
Started Jun 13 01:46:43 PM PDT 24
Finished Jun 13 01:47:04 PM PDT 24
Peak memory 223736 kb
Host smart-83dd8538-2cfb-423a-92c2-1224102f436f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478527138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1478527138
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3882208964
Short name T446
Test name
Test status
Simulation time 23938467 ps
CPU time 0.71 seconds
Started Jun 13 02:48:03 PM PDT 24
Finished Jun 13 02:48:16 PM PDT 24
Peak memory 205704 kb
Host smart-ad1459af-17de-4575-b495-b8a8a3bcccfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882208964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
882208964
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2846848505
Short name T487
Test name
Test status
Simulation time 273449628 ps
CPU time 3.84 seconds
Started Jun 13 02:48:02 PM PDT 24
Finished Jun 13 02:48:18 PM PDT 24
Peak memory 224872 kb
Host smart-5a7c307f-6670-4084-a0fe-49dc8a23e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846848505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2846848505
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1404352380
Short name T576
Test name
Test status
Simulation time 14200018 ps
CPU time 0.8 seconds
Started Jun 13 02:48:01 PM PDT 24
Finished Jun 13 02:48:14 PM PDT 24
Peak memory 206796 kb
Host smart-f7b13d14-35ed-4f57-903b-f8471b010dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404352380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1404352380
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2087805879
Short name T165
Test name
Test status
Simulation time 13119829594 ps
CPU time 103.47 seconds
Started Jun 13 02:48:07 PM PDT 24
Finished Jun 13 02:50:03 PM PDT 24
Peak memory 240436 kb
Host smart-fb06e2aa-8a37-45b2-bfba-6186daedab92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087805879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2087805879
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1530711560
Short name T631
Test name
Test status
Simulation time 92873099285 ps
CPU time 77.09 seconds
Started Jun 13 02:48:24 PM PDT 24
Finished Jun 13 02:49:57 PM PDT 24
Peak memory 249560 kb
Host smart-ba071148-23c2-4a4b-90e4-50343f21a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530711560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1530711560
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3787695620
Short name T55
Test name
Test status
Simulation time 3036808963 ps
CPU time 32.28 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:48:54 PM PDT 24
Peak memory 249564 kb
Host smart-b4c27dec-0c50-4d58-9de7-4bf9c628d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787695620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3787695620
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3490066604
Short name T377
Test name
Test status
Simulation time 100089481 ps
CPU time 2.69 seconds
Started Jun 13 02:48:23 PM PDT 24
Finished Jun 13 02:48:42 PM PDT 24
Peak memory 224856 kb
Host smart-58a486a4-bacb-4d39-ac1c-cd7bb806af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490066604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3490066604
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3315503092
Short name T885
Test name
Test status
Simulation time 417460250 ps
CPU time 3.4 seconds
Started Jun 13 02:48:27 PM PDT 24
Finished Jun 13 02:48:46 PM PDT 24
Peak memory 224804 kb
Host smart-16b56638-2e45-49c0-a1f9-2635bc62fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315503092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3315503092
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1276714653
Short name T112
Test name
Test status
Simulation time 4139287984 ps
CPU time 14.46 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:48:35 PM PDT 24
Peak memory 240116 kb
Host smart-e0c73cfe-03ed-46ea-9708-95d479d14931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276714653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1276714653
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1074508939
Short name T90
Test name
Test status
Simulation time 1229777840 ps
CPU time 6.89 seconds
Started Jun 13 02:48:07 PM PDT 24
Finished Jun 13 02:48:26 PM PDT 24
Peak memory 233016 kb
Host smart-a7d11818-733d-4e92-a75b-d6af0e6a6600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074508939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1074508939
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3338984692
Short name T808
Test name
Test status
Simulation time 1134308857 ps
CPU time 7.21 seconds
Started Jun 13 02:48:09 PM PDT 24
Finished Jun 13 02:48:30 PM PDT 24
Peak memory 224860 kb
Host smart-5e5d0231-c8f7-4f1e-917d-d96dd321b4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338984692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3338984692
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2107234839
Short name T658
Test name
Test status
Simulation time 485141465 ps
CPU time 5.64 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:48:42 PM PDT 24
Peak memory 221480 kb
Host smart-04f8f0fb-3556-4a4e-b9fb-60610e6d20b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2107234839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2107234839
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.407128714
Short name T477
Test name
Test status
Simulation time 670249774 ps
CPU time 5.3 seconds
Started Jun 13 02:48:22 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 216680 kb
Host smart-d9c13da8-12fd-4663-b420-7331f8e006d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407128714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.407128714
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1063754939
Short name T832
Test name
Test status
Simulation time 2575770998 ps
CPU time 9.68 seconds
Started Jun 13 02:48:00 PM PDT 24
Finished Jun 13 02:48:22 PM PDT 24
Peak memory 216620 kb
Host smart-f5271895-b632-4080-9627-31b320afd6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063754939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1063754939
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.770934982
Short name T383
Test name
Test status
Simulation time 49528520 ps
CPU time 1.6 seconds
Started Jun 13 02:48:29 PM PDT 24
Finished Jun 13 02:48:46 PM PDT 24
Peak memory 216596 kb
Host smart-ad764c08-8202-48a8-812f-772198543945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770934982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.770934982
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2678354015
Short name T673
Test name
Test status
Simulation time 62569094 ps
CPU time 0.74 seconds
Started Jun 13 02:48:27 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 206160 kb
Host smart-9a6ee2cf-316c-4995-9afe-e9424f329cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678354015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2678354015
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2578897575
Short name T760
Test name
Test status
Simulation time 337528437 ps
CPU time 5.9 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:48:28 PM PDT 24
Peak memory 233008 kb
Host smart-bbc1347c-7791-4a30-bfe8-de0556230918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578897575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2578897575
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4263656864
Short name T978
Test name
Test status
Simulation time 861230039 ps
CPU time 11.19 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:48:45 PM PDT 24
Peak memory 224848 kb
Host smart-9ff7a2a5-5105-4c54-9294-7987a18ca14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263656864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4263656864
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3802171156
Short name T387
Test name
Test status
Simulation time 73525526 ps
CPU time 0.78 seconds
Started Jun 13 02:48:05 PM PDT 24
Finished Jun 13 02:48:19 PM PDT 24
Peak memory 206768 kb
Host smart-71c07b96-83f0-49d6-ba75-bdb53786b6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802171156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3802171156
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2015544635
Short name T280
Test name
Test status
Simulation time 29855109126 ps
CPU time 198.45 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:51:39 PM PDT 24
Peak memory 250500 kb
Host smart-ef4ebcb1-45ef-47df-af49-703b44a37222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015544635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2015544635
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2254172891
Short name T835
Test name
Test status
Simulation time 10390981486 ps
CPU time 38.08 seconds
Started Jun 13 02:48:10 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 236924 kb
Host smart-7626d02a-6586-487a-af24-b8ce4cdf6b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254172891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2254172891
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2378227540
Short name T770
Test name
Test status
Simulation time 3641014555 ps
CPU time 39.48 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:49:13 PM PDT 24
Peak memory 235748 kb
Host smart-0e17656d-cfb0-4417-878b-57b0fc115e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378227540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2378227540
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_intercept.630002747
Short name T3
Test name
Test status
Simulation time 11172257170 ps
CPU time 19.53 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:48:55 PM PDT 24
Peak memory 224968 kb
Host smart-7c926c85-49d6-4ed3-bf01-a40c54fb8b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630002747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.630002747
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2042028116
Short name T458
Test name
Test status
Simulation time 1442717182 ps
CPU time 9.7 seconds
Started Jun 13 02:48:09 PM PDT 24
Finished Jun 13 02:48:33 PM PDT 24
Peak memory 240976 kb
Host smart-7269c386-a27e-4316-a273-ebf179149e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042028116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2042028116
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1708211803
Short name T916
Test name
Test status
Simulation time 17033840 ps
CPU time 1.05 seconds
Started Jun 13 02:48:27 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 216896 kb
Host smart-f4670f38-d27d-4464-b8c3-690f8c8916db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708211803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1708211803
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1706770251
Short name T44
Test name
Test status
Simulation time 2021675172 ps
CPU time 9.01 seconds
Started Jun 13 02:48:15 PM PDT 24
Finished Jun 13 02:48:39 PM PDT 24
Peak memory 233068 kb
Host smart-6dde0912-bdf3-4343-a11e-d2b6da94d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706770251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1706770251
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2106240893
Short name T299
Test name
Test status
Simulation time 3623765676 ps
CPU time 7.85 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:48:29 PM PDT 24
Peak memory 241204 kb
Host smart-518c0de7-57f7-4200-8975-8c19282eead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106240893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2106240893
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.184549203
Short name T950
Test name
Test status
Simulation time 223071767 ps
CPU time 4.96 seconds
Started Jun 13 02:48:10 PM PDT 24
Finished Jun 13 02:48:29 PM PDT 24
Peak memory 223404 kb
Host smart-2e053c59-6d4f-42c2-8802-58744de856f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=184549203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.184549203
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2312440609
Short name T29
Test name
Test status
Simulation time 43678531 ps
CPU time 1.01 seconds
Started Jun 13 02:48:15 PM PDT 24
Finished Jun 13 02:48:31 PM PDT 24
Peak memory 235628 kb
Host smart-f6c1a283-8f6d-4402-b0c6-652fb796ef8c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312440609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2312440609
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.140757829
Short name T259
Test name
Test status
Simulation time 18782840022 ps
CPU time 115.15 seconds
Started Jun 13 02:48:11 PM PDT 24
Finished Jun 13 02:50:21 PM PDT 24
Peak memory 239256 kb
Host smart-91a15862-e0c1-4aee-be8b-e32e75f23d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140757829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.140757829
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1968655383
Short name T899
Test name
Test status
Simulation time 5427248771 ps
CPU time 5.98 seconds
Started Jun 13 02:48:14 PM PDT 24
Finished Jun 13 02:48:35 PM PDT 24
Peak memory 216904 kb
Host smart-6d8393fc-155a-405c-9916-6ecfba3b37c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968655383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1968655383
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1954977574
Short name T958
Test name
Test status
Simulation time 22136349227 ps
CPU time 14.59 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:49:00 PM PDT 24
Peak memory 216596 kb
Host smart-4dc6a853-1388-4b01-b1fb-b8060e7d71cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954977574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1954977574
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3403427223
Short name T427
Test name
Test status
Simulation time 448058432 ps
CPU time 7.31 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 216608 kb
Host smart-83a5914b-3b99-4d5f-bf45-cc8eacd6d4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403427223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3403427223
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2500277485
Short name T679
Test name
Test status
Simulation time 49896845 ps
CPU time 0.69 seconds
Started Jun 13 02:48:14 PM PDT 24
Finished Jun 13 02:48:30 PM PDT 24
Peak memory 205804 kb
Host smart-2e551fdd-c9a5-4153-a18a-6df8ed71f837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500277485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2500277485
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2755863580
Short name T918
Test name
Test status
Simulation time 579672654 ps
CPU time 6.17 seconds
Started Jun 13 02:48:09 PM PDT 24
Finished Jun 13 02:48:29 PM PDT 24
Peak memory 232984 kb
Host smart-72af3d29-19f1-4917-853b-27330aa90f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755863580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2755863580
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2365177175
Short name T509
Test name
Test status
Simulation time 44958239 ps
CPU time 0.72 seconds
Started Jun 13 02:48:58 PM PDT 24
Finished Jun 13 02:49:18 PM PDT 24
Peak memory 205128 kb
Host smart-ef99826b-2f51-40a5-9b6c-49e2980260e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365177175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2365177175
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3069807977
Short name T579
Test name
Test status
Simulation time 167101532 ps
CPU time 2.33 seconds
Started Jun 13 02:48:54 PM PDT 24
Finished Jun 13 02:49:13 PM PDT 24
Peak memory 224876 kb
Host smart-e7de672e-7815-4e8d-ba58-e7f1ac455517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069807977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3069807977
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3574009278
Short name T499
Test name
Test status
Simulation time 64246141 ps
CPU time 0.74 seconds
Started Jun 13 02:48:42 PM PDT 24
Finished Jun 13 02:49:00 PM PDT 24
Peak memory 205764 kb
Host smart-e63716ad-7aa1-4a91-b1d6-db1c5dce571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574009278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3574009278
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3507878620
Short name T504
Test name
Test status
Simulation time 7162758144 ps
CPU time 14.97 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:17 PM PDT 24
Peak memory 217904 kb
Host smart-0f670bb4-d465-4d95-80c4-03cc14ab263a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507878620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3507878620
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2466872058
Short name T790
Test name
Test status
Simulation time 2142080826 ps
CPU time 10.96 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:14 PM PDT 24
Peak memory 224580 kb
Host smart-12842341-de0e-4f46-b359-b4b261e97fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466872058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2466872058
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3484058896
Short name T614
Test name
Test status
Simulation time 6039599698 ps
CPU time 17.88 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:49:18 PM PDT 24
Peak memory 233132 kb
Host smart-6822974a-f5cb-4975-a628-836bd0481366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484058896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3484058896
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2903987170
Short name T201
Test name
Test status
Simulation time 933419826 ps
CPU time 4.09 seconds
Started Jun 13 02:48:53 PM PDT 24
Finished Jun 13 02:49:15 PM PDT 24
Peak memory 233056 kb
Host smart-9329412e-9fea-4767-829d-511cc6c07bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903987170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2903987170
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3498209692
Short name T884
Test name
Test status
Simulation time 16549992 ps
CPU time 1.08 seconds
Started Jun 13 02:49:01 PM PDT 24
Finished Jun 13 02:49:22 PM PDT 24
Peak memory 216912 kb
Host smart-2f7787b3-d07f-428c-9cc8-ce8352936045
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498209692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3498209692
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3148178750
Short name T747
Test name
Test status
Simulation time 1678970009 ps
CPU time 4.18 seconds
Started Jun 13 02:48:50 PM PDT 24
Finished Jun 13 02:49:11 PM PDT 24
Peak memory 224780 kb
Host smart-e019fac4-0a08-4358-a7dd-52ea821255f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148178750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3148178750
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.592707591
Short name T937
Test name
Test status
Simulation time 1274852042 ps
CPU time 8.62 seconds
Started Jun 13 02:48:55 PM PDT 24
Finished Jun 13 02:49:21 PM PDT 24
Peak memory 233080 kb
Host smart-722e8367-ec39-405a-9517-cb1cf614e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592707591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.592707591
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1550096353
Short name T382
Test name
Test status
Simulation time 689061756 ps
CPU time 7.21 seconds
Started Jun 13 02:48:43 PM PDT 24
Finished Jun 13 02:49:06 PM PDT 24
Peak memory 220400 kb
Host smart-da0962cf-4854-4068-83c4-ed94629a4cc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1550096353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1550096353
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3215686815
Short name T841
Test name
Test status
Simulation time 11493797976 ps
CPU time 52.32 seconds
Started Jun 13 02:48:52 PM PDT 24
Finished Jun 13 02:50:02 PM PDT 24
Peak memory 241628 kb
Host smart-f5f42bfe-9454-4378-bada-a2d4dbba9dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215686815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3215686815
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3365949750
Short name T588
Test name
Test status
Simulation time 9424234640 ps
CPU time 50.5 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:57 PM PDT 24
Peak memory 216612 kb
Host smart-f0cbccf3-a705-4f82-a048-d5a4011c8ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365949750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3365949750
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3228762262
Short name T533
Test name
Test status
Simulation time 3143941878 ps
CPU time 8.15 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 216516 kb
Host smart-601a8010-dc08-4f79-b1b5-fb633e318249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228762262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3228762262
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.997176899
Short name T2
Test name
Test status
Simulation time 402049835 ps
CPU time 1.77 seconds
Started Jun 13 02:48:57 PM PDT 24
Finished Jun 13 02:49:17 PM PDT 24
Peak memory 208316 kb
Host smart-ab8e7487-d2c6-4fce-ac46-d83284b170e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997176899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.997176899
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.387413428
Short name T743
Test name
Test status
Simulation time 206399982 ps
CPU time 0.9 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 206152 kb
Host smart-3bdf48c0-e6fa-4546-8cfe-f01dc4942476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387413428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.387413428
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2614388397
Short name T300
Test name
Test status
Simulation time 2091828218 ps
CPU time 2.36 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 224808 kb
Host smart-ad25babe-8e7a-4a39-936d-b53b12d0b312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614388397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2614388397
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3045770033
Short name T539
Test name
Test status
Simulation time 19234872 ps
CPU time 0.77 seconds
Started Jun 13 02:48:50 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 205124 kb
Host smart-ea6dfe6b-96f6-443b-b970-6a13deeb9ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045770033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3045770033
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2661814211
Short name T89
Test name
Test status
Simulation time 395526792 ps
CPU time 2.6 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:10 PM PDT 24
Peak memory 233060 kb
Host smart-4eeba9a5-91bd-4007-a762-dfd251f6b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661814211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2661814211
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2283628039
Short name T624
Test name
Test status
Simulation time 50197192 ps
CPU time 0.78 seconds
Started Jun 13 02:48:52 PM PDT 24
Finished Jun 13 02:49:10 PM PDT 24
Peak memory 206804 kb
Host smart-526e9005-70c1-4960-8bce-0a9986329abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283628039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2283628039
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3121575338
Short name T163
Test name
Test status
Simulation time 50311195849 ps
CPU time 326.33 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:54:30 PM PDT 24
Peak memory 255996 kb
Host smart-28c0a772-8add-463c-ad89-dab87f9a462a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121575338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3121575338
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2732175807
Short name T288
Test name
Test status
Simulation time 5798528499 ps
CPU time 69.14 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 265864 kb
Host smart-2a01f3de-6e86-44bb-b62b-1d24621b350a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732175807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2732175807
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2167459206
Short name T537
Test name
Test status
Simulation time 62458299 ps
CPU time 3.32 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 232996 kb
Host smart-1f9f9477-c97a-4ed1-9164-2fd70b2d628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167459206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2167459206
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3387942418
Short name T577
Test name
Test status
Simulation time 2977499755 ps
CPU time 8.64 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:18 PM PDT 24
Peak memory 228792 kb
Host smart-e3660614-1502-4372-8530-6b02989ff390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387942418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3387942418
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1920107888
Short name T397
Test name
Test status
Simulation time 31598046 ps
CPU time 1.08 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 216896 kb
Host smart-b35575ab-f30f-406d-8633-dabf7f345a79
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920107888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1920107888
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2329041387
Short name T963
Test name
Test status
Simulation time 118924903 ps
CPU time 2.18 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:04 PM PDT 24
Peak memory 223024 kb
Host smart-61678781-3926-4e92-aed3-3e3149ae24a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329041387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2329041387
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.490405536
Short name T827
Test name
Test status
Simulation time 4590503583 ps
CPU time 5.25 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:11 PM PDT 24
Peak memory 233124 kb
Host smart-cab49d28-e140-455a-905d-f07abd97e6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490405536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.490405536
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.197125484
Short name T810
Test name
Test status
Simulation time 1659657290 ps
CPU time 6.4 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 219356 kb
Host smart-d42e79a6-b21a-4000-9055-ac7a3a2b3cab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=197125484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.197125484
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.620765695
Short name T771
Test name
Test status
Simulation time 11633522647 ps
CPU time 23.42 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:28 PM PDT 24
Peak memory 216876 kb
Host smart-aa253711-d176-412d-9b71-b2ac82804f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620765695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.620765695
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4222178858
Short name T510
Test name
Test status
Simulation time 1619385268 ps
CPU time 6.6 seconds
Started Jun 13 02:48:52 PM PDT 24
Finished Jun 13 02:49:16 PM PDT 24
Peak memory 216468 kb
Host smart-4966289d-8b78-4199-942a-dc9e9219fc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222178858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4222178858
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1345798119
Short name T345
Test name
Test status
Simulation time 126850375 ps
CPU time 1.51 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 208568 kb
Host smart-20c7be47-cdaf-45fd-a94e-8ff335e69bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345798119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1345798119
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3481651639
Short name T798
Test name
Test status
Simulation time 24223865 ps
CPU time 0.75 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:49:01 PM PDT 24
Peak memory 205996 kb
Host smart-669c44b1-4a15-4170-be84-04750cc8e15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481651639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3481651639
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3177382318
Short name T668
Test name
Test status
Simulation time 5426226479 ps
CPU time 18.7 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:25 PM PDT 24
Peak memory 224896 kb
Host smart-062c1976-24cc-4c0e-b6c4-0057fe5feb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177382318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3177382318
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2494216895
Short name T612
Test name
Test status
Simulation time 13120793 ps
CPU time 0.7 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:06 PM PDT 24
Peak memory 205912 kb
Host smart-cdb9dd56-678e-490d-ba48-0c6ae2cc58da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494216895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2494216895
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2995313918
Short name T449
Test name
Test status
Simulation time 30591125 ps
CPU time 2.39 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 232660 kb
Host smart-0f4ede2a-5aeb-4634-b4d0-2d0d80a8a7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995313918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2995313918
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4256826682
Short name T867
Test name
Test status
Simulation time 23626555 ps
CPU time 0.82 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:10 PM PDT 24
Peak memory 206788 kb
Host smart-e7ccb20c-1599-4ec6-b02b-2739611d5ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256826682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4256826682
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3826537729
Short name T227
Test name
Test status
Simulation time 15850739323 ps
CPU time 72.24 seconds
Started Jun 13 02:48:59 PM PDT 24
Finished Jun 13 02:50:30 PM PDT 24
Peak memory 253224 kb
Host smart-575d7367-0a60-4849-8986-85c7fe385851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826537729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3826537729
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3237776652
Short name T195
Test name
Test status
Simulation time 24212045651 ps
CPU time 232.77 seconds
Started Jun 13 02:49:02 PM PDT 24
Finished Jun 13 02:53:15 PM PDT 24
Peak memory 250056 kb
Host smart-6fe0fae4-4453-4d1d-893e-e83a4b3f97ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237776652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3237776652
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1558988867
Short name T316
Test name
Test status
Simulation time 3518269233 ps
CPU time 10.58 seconds
Started Jun 13 02:48:58 PM PDT 24
Finished Jun 13 02:49:28 PM PDT 24
Peak memory 224816 kb
Host smart-ff915677-6c8c-450d-9b9d-5dd7fcb0c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558988867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1558988867
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3952787015
Short name T652
Test name
Test status
Simulation time 2307574592 ps
CPU time 13.68 seconds
Started Jun 13 02:48:53 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 224872 kb
Host smart-ee902570-895c-42ef-aaf7-5a7f0c45e816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952787015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3952787015
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3604864466
Short name T776
Test name
Test status
Simulation time 1064944915 ps
CPU time 4.66 seconds
Started Jun 13 02:48:53 PM PDT 24
Finished Jun 13 02:49:15 PM PDT 24
Peak memory 233032 kb
Host smart-71dc6f27-87eb-47fb-9a67-a4c4e39129b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604864466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3604864466
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2839153335
Short name T609
Test name
Test status
Simulation time 17229432 ps
CPU time 1.05 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 216904 kb
Host smart-63a2d40e-bfef-451c-b65c-b6e5649af438
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839153335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2839153335
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1620959220
Short name T786
Test name
Test status
Simulation time 51718729 ps
CPU time 2.03 seconds
Started Jun 13 02:48:50 PM PDT 24
Finished Jun 13 02:49:09 PM PDT 24
Peak memory 222968 kb
Host smart-09a213bf-0ab8-4ef2-903b-392ae710ad52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620959220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1620959220
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3509386068
Short name T567
Test name
Test status
Simulation time 11691075685 ps
CPU time 20.3 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 233092 kb
Host smart-c5f1df8f-c1f4-440f-bd88-892b186745c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509386068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3509386068
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4020628277
Short name T433
Test name
Test status
Simulation time 170944564 ps
CPU time 3.98 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 223104 kb
Host smart-124eba06-7306-40c7-866f-cd0f2393925c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4020628277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4020628277
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3827256176
Short name T662
Test name
Test status
Simulation time 43023669842 ps
CPU time 364.54 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:55:12 PM PDT 24
Peak memory 252984 kb
Host smart-dacc7e92-03bb-4420-85fe-f5c8213692e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827256176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3827256176
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2549137826
Short name T385
Test name
Test status
Simulation time 11037361 ps
CPU time 0.74 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 205880 kb
Host smart-4a1ede4b-6311-4f0c-92d9-9e1af3935daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549137826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2549137826
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2092014246
Short name T131
Test name
Test status
Simulation time 976933609 ps
CPU time 5.53 seconds
Started Jun 13 02:48:59 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 216520 kb
Host smart-140a4e11-4d08-4ea6-986e-2cedb22a36bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092014246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2092014246
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.254418265
Short name T590
Test name
Test status
Simulation time 189573036 ps
CPU time 5.22 seconds
Started Jun 13 02:49:08 PM PDT 24
Finished Jun 13 02:49:34 PM PDT 24
Peak memory 216572 kb
Host smart-cb9350e7-7848-4d02-9ebf-2b26687b6a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254418265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.254418265
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1066574662
Short name T754
Test name
Test status
Simulation time 241758496 ps
CPU time 0.8 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 206172 kb
Host smart-d98ba1df-7eb0-4feb-b8bc-d389a198ad5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066574662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1066574662
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.774256156
Short name T498
Test name
Test status
Simulation time 288968137 ps
CPU time 2.88 seconds
Started Jun 13 02:48:54 PM PDT 24
Finished Jun 13 02:49:14 PM PDT 24
Peak memory 233028 kb
Host smart-c0a86b4c-5195-41bc-ae65-e2bda7c5246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774256156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.774256156
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2338913469
Short name T789
Test name
Test status
Simulation time 12689297 ps
CPU time 0.75 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 205688 kb
Host smart-f0c0b755-fa63-42af-b006-9aeacdc8a153
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338913469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2338913469
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2576569238
Short name T714
Test name
Test status
Simulation time 106357510 ps
CPU time 2.2 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 223240 kb
Host smart-8cc7e719-78d2-4ab1-9fa7-56965227730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576569238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2576569238
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2457845440
Short name T724
Test name
Test status
Simulation time 20466900 ps
CPU time 0.82 seconds
Started Jun 13 02:48:50 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 206956 kb
Host smart-7ab2d8c3-4e1c-40f8-a6e9-aae3102142d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457845440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2457845440
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3045058334
Short name T177
Test name
Test status
Simulation time 70181099233 ps
CPU time 132.76 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:51:18 PM PDT 24
Peak memory 256360 kb
Host smart-f1e7a2ed-cfef-4c2e-b8f8-28ac3c044323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045058334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3045058334
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2315707364
Short name T814
Test name
Test status
Simulation time 45876151870 ps
CPU time 89.22 seconds
Started Jun 13 02:48:58 PM PDT 24
Finished Jun 13 02:50:46 PM PDT 24
Peak memory 253988 kb
Host smart-03dee2af-a094-4706-8d9a-dbd5e264b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315707364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2315707364
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3536039504
Short name T290
Test name
Test status
Simulation time 7961387320 ps
CPU time 123.76 seconds
Started Jun 13 02:48:50 PM PDT 24
Finished Jun 13 02:51:11 PM PDT 24
Peak memory 265956 kb
Host smart-2a15bce4-f7f2-482b-b6ec-2e2d273fa457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536039504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3536039504
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2746627106
Short name T159
Test name
Test status
Simulation time 1293332777 ps
CPU time 14.34 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:41 PM PDT 24
Peak memory 234048 kb
Host smart-a25a1e60-6674-4968-852f-70e8003cb750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746627106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2746627106
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1905789215
Short name T161
Test name
Test status
Simulation time 1261593972 ps
CPU time 11.01 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:19 PM PDT 24
Peak memory 224828 kb
Host smart-529eb34f-cf20-4c17-8cee-421bea215960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905789215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1905789215
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4171006035
Short name T199
Test name
Test status
Simulation time 15436047467 ps
CPU time 46.97 seconds
Started Jun 13 02:48:57 PM PDT 24
Finished Jun 13 02:50:02 PM PDT 24
Peak memory 241188 kb
Host smart-3824e484-654c-4817-8f21-4b573bab2f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171006035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4171006035
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2642341933
Short name T936
Test name
Test status
Simulation time 49466998 ps
CPU time 1.09 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 216896 kb
Host smart-765828ec-8a13-497f-8d3b-0b12feec7063
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642341933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2642341933
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.427138102
Short name T289
Test name
Test status
Simulation time 1995914469 ps
CPU time 3.94 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:06 PM PDT 24
Peak memory 224852 kb
Host smart-94544de6-dd4d-4183-9a69-99099de5185d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427138102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.427138102
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.662581100
Short name T626
Test name
Test status
Simulation time 15626254492 ps
CPU time 21.55 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:27 PM PDT 24
Peak memory 239752 kb
Host smart-e1025a1c-06bd-4295-b7fe-22c19f96a34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662581100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.662581100
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4029540909
Short name T340
Test name
Test status
Simulation time 1007197758 ps
CPU time 6.22 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 219556 kb
Host smart-ece433ff-2f87-4a8b-a1a0-3e5e6c443058
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4029540909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4029540909
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3472585064
Short name T18
Test name
Test status
Simulation time 25253221679 ps
CPU time 191.11 seconds
Started Jun 13 02:48:58 PM PDT 24
Finished Jun 13 02:52:28 PM PDT 24
Peak memory 240668 kb
Host smart-88dfd08e-5738-4e87-8086-5bb1d690d0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472585064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3472585064
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1669677538
Short name T860
Test name
Test status
Simulation time 8731699614 ps
CPU time 16.25 seconds
Started Jun 13 02:49:01 PM PDT 24
Finished Jun 13 02:49:37 PM PDT 24
Peak memory 216720 kb
Host smart-9d9b1119-f01b-4135-afe6-189a5785e948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669677538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1669677538
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.367797049
Short name T922
Test name
Test status
Simulation time 6177031014 ps
CPU time 2.46 seconds
Started Jun 13 02:48:52 PM PDT 24
Finished Jun 13 02:49:12 PM PDT 24
Peak memory 216604 kb
Host smart-46b7b5cf-7970-415a-9862-ebbbb177250f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367797049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.367797049
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.41605961
Short name T650
Test name
Test status
Simulation time 265213753 ps
CPU time 7.73 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:12 PM PDT 24
Peak memory 217892 kb
Host smart-eac34976-16ca-446a-9b83-6a36b0af9f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41605961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.41605961
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2131913970
Short name T890
Test name
Test status
Simulation time 23520742 ps
CPU time 0.75 seconds
Started Jun 13 02:48:50 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 206168 kb
Host smart-08b0c0f7-e99e-4d59-8d19-b6a3b0ccaaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131913970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2131913970
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.510542416
Short name T879
Test name
Test status
Simulation time 2449108542 ps
CPU time 6.4 seconds
Started Jun 13 02:48:53 PM PDT 24
Finished Jun 13 02:49:17 PM PDT 24
Peak memory 224868 kb
Host smart-79e7ec0a-07af-4b12-985b-08a91dcb6ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510542416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.510542416
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3440251342
Short name T511
Test name
Test status
Simulation time 42290907 ps
CPU time 0.8 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 205716 kb
Host smart-95c21208-e1ea-403f-8195-f75a6707c919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440251342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3440251342
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2947520134
Short name T87
Test name
Test status
Simulation time 163684599 ps
CPU time 4.13 seconds
Started Jun 13 02:48:56 PM PDT 24
Finished Jun 13 02:49:18 PM PDT 24
Peak memory 224852 kb
Host smart-6e11cfca-75cc-4836-a06c-6dc70b5e2907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947520134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2947520134
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1247520286
Short name T710
Test name
Test status
Simulation time 38674995 ps
CPU time 0.76 seconds
Started Jun 13 02:48:53 PM PDT 24
Finished Jun 13 02:49:11 PM PDT 24
Peak memory 206100 kb
Host smart-20f87870-b069-4349-bf76-fe3c64649476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247520286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1247520286
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2579500834
Short name T232
Test name
Test status
Simulation time 148977675155 ps
CPU time 247.97 seconds
Started Jun 13 02:49:00 PM PDT 24
Finished Jun 13 02:53:28 PM PDT 24
Peak memory 257456 kb
Host smart-fc6fcc30-d5de-441f-9fed-ce514b745aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579500834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2579500834
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1780163775
Short name T242
Test name
Test status
Simulation time 536310034957 ps
CPU time 582.48 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:59:07 PM PDT 24
Peak memory 272500 kb
Host smart-21a442be-bdc8-45f2-9af4-5bc6538deb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780163775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1780163775
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4049156689
Short name T164
Test name
Test status
Simulation time 11402159259 ps
CPU time 67.86 seconds
Started Jun 13 02:49:00 PM PDT 24
Finished Jun 13 02:50:26 PM PDT 24
Peak memory 250596 kb
Host smart-ab324019-3f20-40be-8695-a85ea1125695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049156689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4049156689
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1527455203
Short name T311
Test name
Test status
Simulation time 13693823914 ps
CPU time 46.97 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 02:50:15 PM PDT 24
Peak memory 246024 kb
Host smart-c2eea1b6-f997-4ba6-8235-c6b5a113ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527455203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1527455203
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.764181796
Short name T667
Test name
Test status
Simulation time 1596080929 ps
CPU time 13.94 seconds
Started Jun 13 02:49:03 PM PDT 24
Finished Jun 13 02:49:37 PM PDT 24
Peak memory 233048 kb
Host smart-c990facf-fc07-4d03-8ff3-adcbbe15ee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764181796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.764181796
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.952684118
Short name T598
Test name
Test status
Simulation time 2923317497 ps
CPU time 29.05 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:59 PM PDT 24
Peak memory 240824 kb
Host smart-1b4c408e-fa31-42fb-ab79-025cb3e20bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952684118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.952684118
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.921607950
Short name T38
Test name
Test status
Simulation time 16634393 ps
CPU time 1.01 seconds
Started Jun 13 02:49:03 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 218168 kb
Host smart-72439e04-1dbb-4387-95b0-778330e1bdf5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921607950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.921607950
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4189803803
Short name T309
Test name
Test status
Simulation time 727265064 ps
CPU time 3.15 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:10 PM PDT 24
Peak memory 224792 kb
Host smart-636d11de-c793-4a95-b780-200409236e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189803803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4189803803
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2950581267
Short name T741
Test name
Test status
Simulation time 28767244274 ps
CPU time 20.62 seconds
Started Jun 13 02:48:56 PM PDT 24
Finished Jun 13 02:49:34 PM PDT 24
Peak memory 233116 kb
Host smart-0c373fd9-a558-4bed-81cc-8e5a0a2de240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950581267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2950581267
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1842667223
Short name T524
Test name
Test status
Simulation time 1715714307 ps
CPU time 10.88 seconds
Started Jun 13 02:48:56 PM PDT 24
Finished Jun 13 02:49:25 PM PDT 24
Peak memory 223256 kb
Host smart-98aab5d7-743a-4488-9fd9-ebd9a51f609f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1842667223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1842667223
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3526584790
Short name T518
Test name
Test status
Simulation time 203492329 ps
CPU time 1.02 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:10 PM PDT 24
Peak memory 206868 kb
Host smart-327588f2-3c95-4dfd-9e48-46457326a616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526584790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3526584790
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.746570603
Short name T73
Test name
Test status
Simulation time 7095028227 ps
CPU time 18 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:23 PM PDT 24
Peak memory 216764 kb
Host smart-73a77261-35e5-4696-9319-61963fc20aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746570603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.746570603
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.32006615
Short name T361
Test name
Test status
Simulation time 594106688 ps
CPU time 2.03 seconds
Started Jun 13 02:48:57 PM PDT 24
Finished Jun 13 02:49:17 PM PDT 24
Peak memory 208036 kb
Host smart-f6b49671-77eb-449e-b53f-5908c84a8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32006615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.32006615
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4270862610
Short name T373
Test name
Test status
Simulation time 560461371 ps
CPU time 2.67 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 216384 kb
Host smart-071283c0-543f-48e0-8b53-e8d8b9c3544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270862610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4270862610
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.175413111
Short name T127
Test name
Test status
Simulation time 17161865 ps
CPU time 0.74 seconds
Started Jun 13 02:48:58 PM PDT 24
Finished Jun 13 02:49:18 PM PDT 24
Peak memory 206164 kb
Host smart-02147fb9-3c9a-4ac1-8a10-bb7d0bfaf359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175413111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.175413111
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3105705578
Short name T829
Test name
Test status
Simulation time 791559079 ps
CPU time 6.73 seconds
Started Jun 13 02:49:07 PM PDT 24
Finished Jun 13 02:49:33 PM PDT 24
Peak memory 224816 kb
Host smart-c70e7e29-39bb-4ac0-990e-5d8d7f676241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105705578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3105705578
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3668573599
Short name T482
Test name
Test status
Simulation time 13352690 ps
CPU time 0.74 seconds
Started Jun 13 02:48:57 PM PDT 24
Finished Jun 13 02:49:16 PM PDT 24
Peak memory 205700 kb
Host smart-5d3a6969-9075-4365-acf9-b216ca08fbe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668573599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3668573599
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1253763454
Short name T856
Test name
Test status
Simulation time 4087288001 ps
CPU time 4.27 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:27 PM PDT 24
Peak memory 224944 kb
Host smart-f5c51f8c-ef46-4ed6-98e6-bdc58eeeeb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253763454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1253763454
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.55689117
Short name T681
Test name
Test status
Simulation time 36876381 ps
CPU time 0.76 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 205764 kb
Host smart-437e4e42-4d0d-4683-bf50-99beaa9882a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55689117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.55689117
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.935695088
Short name T512
Test name
Test status
Simulation time 23838397326 ps
CPU time 161.51 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:52:12 PM PDT 24
Peak memory 250544 kb
Host smart-3bd6355d-af98-4e9b-a1b0-b51724a1ead9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935695088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.935695088
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2765773254
Short name T172
Test name
Test status
Simulation time 35663472657 ps
CPU time 92.95 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:51:09 PM PDT 24
Peak memory 257160 kb
Host smart-47f00141-363f-4d84-a25d-bdfb91a3769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765773254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2765773254
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2943959809
Short name T162
Test name
Test status
Simulation time 283192345 ps
CPU time 4.93 seconds
Started Jun 13 02:48:53 PM PDT 24
Finished Jun 13 02:49:15 PM PDT 24
Peak memory 241180 kb
Host smart-c1821c9a-8c5b-4813-80b7-1040e31421dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943959809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2943959809
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.651005953
Short name T294
Test name
Test status
Simulation time 2555752747 ps
CPU time 13.17 seconds
Started Jun 13 02:48:52 PM PDT 24
Finished Jun 13 02:49:23 PM PDT 24
Peak memory 233108 kb
Host smart-4912db47-c4fe-412f-9fb0-88ea105967e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651005953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.651005953
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3570588255
Short name T307
Test name
Test status
Simulation time 1460202540 ps
CPU time 9.69 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 228636 kb
Host smart-0e502909-d4fc-4483-bc0e-4277ea53f4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570588255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3570588255
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2406349997
Short name T376
Test name
Test status
Simulation time 180590502 ps
CPU time 1.01 seconds
Started Jun 13 02:49:00 PM PDT 24
Finished Jun 13 02:49:20 PM PDT 24
Peak memory 216908 kb
Host smart-682ca1cb-03f4-4904-8486-6a3c18fbf3c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406349997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2406349997
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3218213415
Short name T517
Test name
Test status
Simulation time 8917171202 ps
CPU time 12.76 seconds
Started Jun 13 02:48:59 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 224912 kb
Host smart-5d57212d-10cb-43bd-a269-0c0866843602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218213415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3218213415
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1086728362
Short name T966
Test name
Test status
Simulation time 988794024 ps
CPU time 4.11 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:35 PM PDT 24
Peak memory 224840 kb
Host smart-293f6035-e661-4626-9129-3dda80f2d740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086728362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1086728362
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4169250575
Short name T50
Test name
Test status
Simulation time 950215137 ps
CPU time 4.93 seconds
Started Jun 13 02:49:00 PM PDT 24
Finished Jun 13 02:49:25 PM PDT 24
Peak memory 220436 kb
Host smart-e3c9f08a-f818-43b1-ab4f-358009a6bd3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4169250575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4169250575
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2537516844
Short name T534
Test name
Test status
Simulation time 97129166564 ps
CPU time 176.25 seconds
Started Jun 13 02:49:02 PM PDT 24
Finished Jun 13 02:52:17 PM PDT 24
Peak memory 255380 kb
Host smart-f5107556-c004-47d1-9801-bd4f1d8c742c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537516844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2537516844
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4036735079
Short name T365
Test name
Test status
Simulation time 2611064103 ps
CPU time 12.36 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:22 PM PDT 24
Peak memory 216508 kb
Host smart-1560f4b2-722a-42c1-82bf-27149dce7a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036735079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4036735079
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1920310544
Short name T346
Test name
Test status
Simulation time 472759491 ps
CPU time 1.97 seconds
Started Jun 13 02:48:58 PM PDT 24
Finished Jun 13 02:49:19 PM PDT 24
Peak memory 208180 kb
Host smart-109a85ca-6693-43bc-9119-5cd5082d0322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920310544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1920310544
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2415189367
Short name T368
Test name
Test status
Simulation time 572662690 ps
CPU time 5.65 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:13 PM PDT 24
Peak memory 216712 kb
Host smart-99d25900-62c3-4a32-8556-f7ee2fbf7bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415189367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2415189367
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.861251572
Short name T907
Test name
Test status
Simulation time 326010486 ps
CPU time 0.92 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 206164 kb
Host smart-cf3d31fb-86cc-4667-89f8-91fd9bd88780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861251572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.861251572
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.505792659
Short name T194
Test name
Test status
Simulation time 1359742543 ps
CPU time 6.97 seconds
Started Jun 13 02:48:59 PM PDT 24
Finished Jun 13 02:49:25 PM PDT 24
Peak memory 233044 kb
Host smart-8ea43cfe-5af3-41a3-b13a-c1811a3038a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505792659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.505792659
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1976770827
Short name T913
Test name
Test status
Simulation time 36322024 ps
CPU time 0.69 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:27 PM PDT 24
Peak memory 205640 kb
Host smart-87f5c047-4fde-4ac9-ac20-e3c86c66d675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976770827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1976770827
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.629992864
Short name T296
Test name
Test status
Simulation time 72788480 ps
CPU time 2.34 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:40 PM PDT 24
Peak memory 224864 kb
Host smart-2bcecb16-cd63-4111-b843-c7e971d29de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629992864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.629992864
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.468091984
Short name T11
Test name
Test status
Simulation time 130855959 ps
CPU time 0.75 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 02:49:29 PM PDT 24
Peak memory 205732 kb
Host smart-7e285938-90f8-48a4-aa97-fefd0be2bd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468091984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.468091984
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3902446473
Short name T716
Test name
Test status
Simulation time 22054095683 ps
CPU time 57.95 seconds
Started Jun 13 02:49:05 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 241320 kb
Host smart-96464d79-5ce7-42ad-9d6e-bc0f9ac6eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902446473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3902446473
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.30574633
Short name T508
Test name
Test status
Simulation time 969597507 ps
CPU time 10.39 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 241184 kb
Host smart-bc91b9b9-cfdc-49c7-a14a-681c7fabe169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30574633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.30574633
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2752714297
Short name T466
Test name
Test status
Simulation time 374405479 ps
CPU time 3.67 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:30 PM PDT 24
Peak memory 241204 kb
Host smart-c3c0015c-1f59-4567-934e-03960d7776ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752714297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2752714297
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1456214429
Short name T558
Test name
Test status
Simulation time 560205849 ps
CPU time 2.27 seconds
Started Jun 13 02:49:02 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 223096 kb
Host smart-a2ab989d-da87-4599-b571-48987a749fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456214429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1456214429
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2314344019
Short name T881
Test name
Test status
Simulation time 10904321420 ps
CPU time 59.83 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:50:33 PM PDT 24
Peak memory 238572 kb
Host smart-883f480d-7a57-490a-9288-c01418af3dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314344019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2314344019
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2034869320
Short name T37
Test name
Test status
Simulation time 58225057 ps
CPU time 1.05 seconds
Started Jun 13 02:49:05 PM PDT 24
Finished Jun 13 02:49:26 PM PDT 24
Peak memory 216904 kb
Host smart-01545bd4-ee27-40cb-bf5c-962e7a850851
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034869320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2034869320
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1409456922
Short name T522
Test name
Test status
Simulation time 244361505 ps
CPU time 6.49 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 02:49:35 PM PDT 24
Peak memory 233064 kb
Host smart-11f89cec-78b2-40d4-9d0f-2a5b1c187df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409456922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1409456922
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.594028253
Short name T49
Test name
Test status
Simulation time 7001721179 ps
CPU time 10.6 seconds
Started Jun 13 02:48:58 PM PDT 24
Finished Jun 13 02:49:27 PM PDT 24
Peak memory 241180 kb
Host smart-4ceeef7e-8995-40e1-a336-c4e2ff7891ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594028253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.594028253
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2246005651
Short name T851
Test name
Test status
Simulation time 615704865 ps
CPU time 3.65 seconds
Started Jun 13 02:49:08 PM PDT 24
Finished Jun 13 02:49:32 PM PDT 24
Peak memory 219144 kb
Host smart-96850f0b-7299-4d11-b12f-9cab96de445c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2246005651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2246005651
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1618748873
Short name T399
Test name
Test status
Simulation time 118873617 ps
CPU time 0.86 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 207128 kb
Host smart-116301db-152a-446b-b25d-8e9bef37d675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618748873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1618748873
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.751498247
Short name T386
Test name
Test status
Simulation time 19033945 ps
CPU time 0.73 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:32 PM PDT 24
Peak memory 205876 kb
Host smart-e90cfcab-fbd6-4621-b51b-754b5ef5c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751498247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.751498247
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.992901608
Short name T905
Test name
Test status
Simulation time 8106310413 ps
CPU time 8.53 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:47 PM PDT 24
Peak memory 216668 kb
Host smart-11272d8b-0021-4723-bb36-a2a58b07f523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992901608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.992901608
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3213794890
Short name T746
Test name
Test status
Simulation time 40990661 ps
CPU time 1.32 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:26 PM PDT 24
Peak memory 216640 kb
Host smart-3c9368d5-e499-428a-a433-09329d0ebdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213794890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3213794890
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.282134951
Short name T820
Test name
Test status
Simulation time 203334628 ps
CPU time 0.91 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:33 PM PDT 24
Peak memory 207592 kb
Host smart-4ca9824b-18a3-4b6b-bab4-540e47751e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282134951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.282134951
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1408429683
Short name T24
Test name
Test status
Simulation time 389468859 ps
CPU time 3.3 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:35 PM PDT 24
Peak memory 233104 kb
Host smart-bc37dce8-c0b3-499f-9780-fc2d340e8a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408429683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1408429683
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3999453699
Short name T471
Test name
Test status
Simulation time 41632397 ps
CPU time 0.71 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 205120 kb
Host smart-ed9eb4e2-6104-45f2-a018-c7c00dc1f638
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999453699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3999453699
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3083212518
Short name T685
Test name
Test status
Simulation time 1237196754 ps
CPU time 2.96 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:33 PM PDT 24
Peak memory 224844 kb
Host smart-b533a0db-ccbf-4730-adcd-11723d4e2501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083212518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3083212518
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4076316002
Short name T555
Test name
Test status
Simulation time 96241653 ps
CPU time 0.8 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:24 PM PDT 24
Peak memory 207124 kb
Host smart-db1aa09e-aede-4aad-840e-00510c7030ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076316002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4076316002
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2722859437
Short name T240
Test name
Test status
Simulation time 185157584448 ps
CPU time 301.4 seconds
Started Jun 13 02:49:01 PM PDT 24
Finished Jun 13 02:54:22 PM PDT 24
Peak memory 257176 kb
Host smart-a5cae860-5a20-4d3d-885d-d0fdbec8586b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722859437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2722859437
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3270569875
Short name T618
Test name
Test status
Simulation time 7166265249 ps
CPU time 54.65 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 224980 kb
Host smart-8ade7823-ff1e-4c7e-a1a0-fcdee7d87567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270569875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3270569875
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3894060592
Short name T535
Test name
Test status
Simulation time 12775412939 ps
CPU time 120.59 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:51:24 PM PDT 24
Peak memory 251560 kb
Host smart-ca41d12b-c570-4d43-97ae-cc7d0ee194d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894060592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3894060592
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2442239541
Short name T215
Test name
Test status
Simulation time 5459460623 ps
CPU time 16.48 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 224896 kb
Host smart-3a0b3e8b-6ecd-482e-b1bf-344a86db36aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442239541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2442239541
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3640642881
Short name T99
Test name
Test status
Simulation time 21893750952 ps
CPU time 41.19 seconds
Started Jun 13 02:49:03 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 240156 kb
Host smart-fe1ee306-d2c8-41aa-aa12-16ffaa72cc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640642881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3640642881
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2263531496
Short name T600
Test name
Test status
Simulation time 25490745 ps
CPU time 1.07 seconds
Started Jun 13 02:49:07 PM PDT 24
Finished Jun 13 02:49:28 PM PDT 24
Peak memory 216964 kb
Host smart-814c46a2-75fb-48cc-9635-b7ff61e70794
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263531496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2263531496
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2909800598
Short name T647
Test name
Test status
Simulation time 575267904 ps
CPU time 6.25 seconds
Started Jun 13 02:49:05 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 241136 kb
Host smart-9f15c0a1-c4ea-4822-b1af-b09ac3eaa4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909800598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2909800598
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1009833891
Short name T925
Test name
Test status
Simulation time 516821301 ps
CPU time 2.37 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:40 PM PDT 24
Peak memory 233060 kb
Host smart-bc501ef8-2d5f-4f8c-b5c8-6e56930a5bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009833891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1009833891
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4007486621
Short name T364
Test name
Test status
Simulation time 99853036 ps
CPU time 4.08 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:35 PM PDT 24
Peak memory 223384 kb
Host smart-09005d49-c296-4191-b723-7499ee98f90d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4007486621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4007486621
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3040283132
Short name T231
Test name
Test status
Simulation time 122334668208 ps
CPU time 1227.68 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 03:09:58 PM PDT 24
Peak memory 271548 kb
Host smart-d496b89c-291c-41d0-8ddb-adaccb825d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040283132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3040283132
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.141227242
Short name T815
Test name
Test status
Simulation time 1390325520 ps
CPU time 5.51 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:36 PM PDT 24
Peak memory 216564 kb
Host smart-43814ecb-a3b9-48ee-ae4b-adccc2c45ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141227242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.141227242
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2843761715
Short name T604
Test name
Test status
Simulation time 2022631718 ps
CPU time 5.15 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 216564 kb
Host smart-269bcc84-731c-46e2-847a-2c080c85c852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843761715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2843761715
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3538036709
Short name T623
Test name
Test status
Simulation time 166517673 ps
CPU time 1.13 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:40 PM PDT 24
Peak memory 207992 kb
Host smart-557a7adb-73d5-4cf7-845b-2b0655216335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538036709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3538036709
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.45793416
Short name T775
Test name
Test status
Simulation time 75492698 ps
CPU time 0.86 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 206180 kb
Host smart-1223a92f-f66d-4922-8c2b-c15cda61428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45793416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.45793416
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3066890897
Short name T407
Test name
Test status
Simulation time 4689232433 ps
CPU time 5.34 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:38 PM PDT 24
Peak memory 224948 kb
Host smart-d5566bf0-419e-4313-bc0a-429a3dad1822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066890897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3066890897
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2658610833
Short name T683
Test name
Test status
Simulation time 34146477 ps
CPU time 0.71 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 02:49:29 PM PDT 24
Peak memory 205076 kb
Host smart-164030c9-ae02-4538-884d-a74b4432e3f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658610833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2658610833
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2126966172
Short name T965
Test name
Test status
Simulation time 1270543559 ps
CPU time 5.73 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:36 PM PDT 24
Peak memory 224824 kb
Host smart-122705ed-d3c7-413f-805c-70dd2534af47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126966172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2126966172
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1467393410
Short name T767
Test name
Test status
Simulation time 23237340 ps
CPU time 0.74 seconds
Started Jun 13 02:49:01 PM PDT 24
Finished Jun 13 02:49:20 PM PDT 24
Peak memory 206052 kb
Host smart-c6b6334e-c96c-4d07-9f30-c27497ef6a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467393410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1467393410
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1575263453
Short name T276
Test name
Test status
Simulation time 634280282 ps
CPU time 6.26 seconds
Started Jun 13 02:49:26 PM PDT 24
Finished Jun 13 02:49:54 PM PDT 24
Peak memory 224824 kb
Host smart-f822d86d-48c1-41ae-9233-3ac0ad698aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575263453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1575263453
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1805740555
Short name T58
Test name
Test status
Simulation time 1395227623 ps
CPU time 37.18 seconds
Started Jun 13 02:49:13 PM PDT 24
Finished Jun 13 02:50:10 PM PDT 24
Peak memory 249492 kb
Host smart-bcc2c9e5-ff8d-4e94-8352-4e9f19eff3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805740555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1805740555
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3675493876
Short name T219
Test name
Test status
Simulation time 35073100557 ps
CPU time 132.12 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:51:39 PM PDT 24
Peak memory 257036 kb
Host smart-e3b34bb9-102d-4415-945b-95e956e0d8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675493876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3675493876
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2471137287
Short name T795
Test name
Test status
Simulation time 7567757272 ps
CPU time 51.68 seconds
Started Jun 13 02:49:13 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 233120 kb
Host smart-082bf027-d69c-4288-b05c-18a9229c0fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471137287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2471137287
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1144392250
Short name T25
Test name
Test status
Simulation time 338214376 ps
CPU time 5.55 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:44 PM PDT 24
Peak memory 224804 kb
Host smart-dd64f717-d300-4d19-9f2e-b4ed5ce3202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144392250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1144392250
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2229050307
Short name T731
Test name
Test status
Simulation time 4019983340 ps
CPU time 22.01 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:53 PM PDT 24
Peak memory 233124 kb
Host smart-a41f98e2-c193-4112-bab4-f201b89d1762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229050307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2229050307
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1942265855
Short name T353
Test name
Test status
Simulation time 28342609 ps
CPU time 1.01 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:33 PM PDT 24
Peak memory 216908 kb
Host smart-3ae16d72-d8fb-4df2-b06f-725d63f9f43b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942265855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1942265855
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4169649847
Short name T687
Test name
Test status
Simulation time 3050985416 ps
CPU time 7.21 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:37 PM PDT 24
Peak memory 233132 kb
Host smart-99f5c811-22ff-41e3-9ea8-b406e55010bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169649847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4169649847
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.890247301
Short name T802
Test name
Test status
Simulation time 39570779467 ps
CPU time 24.98 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:50:01 PM PDT 24
Peak memory 241248 kb
Host smart-4d568afa-616d-4944-8742-19b12be6549a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890247301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.890247301
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2527927413
Short name T9
Test name
Test status
Simulation time 512134901 ps
CPU time 3.37 seconds
Started Jun 13 02:49:02 PM PDT 24
Finished Jun 13 02:49:25 PM PDT 24
Peak memory 220640 kb
Host smart-b8360abc-7aae-48bb-a070-f4e378993213
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2527927413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2527927413
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2440570256
Short name T540
Test name
Test status
Simulation time 17424624097 ps
CPU time 9.75 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 217796 kb
Host smart-8b4621ad-61a4-4531-a52a-86c2fac34d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440570256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2440570256
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.880175094
Short name T975
Test name
Test status
Simulation time 1309779348 ps
CPU time 7.73 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 216500 kb
Host smart-a05a8044-b7e8-4bd7-b766-d92b17aaa007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880175094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.880175094
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.407459397
Short name T941
Test name
Test status
Simulation time 20616442 ps
CPU time 0.67 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:32 PM PDT 24
Peak memory 205828 kb
Host smart-9e93827c-73f1-48bc-bc64-bb711412331b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407459397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.407459397
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2085249991
Short name T404
Test name
Test status
Simulation time 564426988 ps
CPU time 0.86 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 206164 kb
Host smart-c83e795a-9883-4a6c-b9d8-14939a0a9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085249991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2085249991
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.314285182
Short name T926
Test name
Test status
Simulation time 5639779878 ps
CPU time 7.93 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:46 PM PDT 24
Peak memory 233108 kb
Host smart-2b5984aa-cdb9-4867-8958-a1a84b562319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314285182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.314285182
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.547835442
Short name T529
Test name
Test status
Simulation time 24542744 ps
CPU time 0.75 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:49:37 PM PDT 24
Peak memory 205676 kb
Host smart-42d80758-045b-4506-92d5-97495474ac46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547835442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.547835442
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2817118820
Short name T158
Test name
Test status
Simulation time 515043762 ps
CPU time 5.42 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:37 PM PDT 24
Peak memory 224852 kb
Host smart-dd63705b-a4a1-4559-bb68-98092fde372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817118820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2817118820
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3689613091
Short name T333
Test name
Test status
Simulation time 25155971 ps
CPU time 0.8 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:32 PM PDT 24
Peak memory 205764 kb
Host smart-7711ec3e-e7e8-4988-9f1b-1e6f98959806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689613091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3689613091
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.612703294
Short name T564
Test name
Test status
Simulation time 747946141 ps
CPU time 13.49 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:40 PM PDT 24
Peak memory 224944 kb
Host smart-be8b6704-e3cb-4f84-94ab-79b6a78fdd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612703294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.612703294
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1742148423
Short name T607
Test name
Test status
Simulation time 3070991579 ps
CPU time 41.52 seconds
Started Jun 13 02:49:13 PM PDT 24
Finished Jun 13 02:50:15 PM PDT 24
Peak memory 249544 kb
Host smart-cf9fb1cc-e4ab-433c-960d-b821188e6c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742148423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1742148423
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1011144890
Short name T894
Test name
Test status
Simulation time 681760828 ps
CPU time 12.13 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 02:49:42 PM PDT 24
Peak memory 224880 kb
Host smart-10483efa-e7fa-45f6-87ff-283ce5286d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011144890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1011144890
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1920914370
Short name T939
Test name
Test status
Simulation time 7845507636 ps
CPU time 31.04 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:56 PM PDT 24
Peak memory 220860 kb
Host smart-74f6b0da-096e-4bc1-b0f8-227fcac9dcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920914370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1920914370
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.435834054
Short name T657
Test name
Test status
Simulation time 241823128 ps
CPU time 6.06 seconds
Started Jun 13 02:49:05 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 233080 kb
Host smart-6710033d-b145-4a96-8e60-c07b3b21f0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435834054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.435834054
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.681328002
Short name T394
Test name
Test status
Simulation time 23795176 ps
CPU time 1.01 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 216948 kb
Host smart-259986f9-f0ce-488d-a13d-13d300c16e6b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681328002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.681328002
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3602367046
Short name T310
Test name
Test status
Simulation time 445965686 ps
CPU time 3.6 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:28 PM PDT 24
Peak memory 241060 kb
Host smart-adad7f07-badb-47d0-95b7-9592f8a7a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602367046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3602367046
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1424879928
Short name T306
Test name
Test status
Simulation time 1057270940 ps
CPU time 4.01 seconds
Started Jun 13 02:49:04 PM PDT 24
Finished Jun 13 02:49:27 PM PDT 24
Peak memory 224888 kb
Host smart-66ca3be8-ddd0-4a4c-892f-6eeeb9c4a9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424879928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1424879928
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1328834487
Short name T100
Test name
Test status
Simulation time 6947959311 ps
CPU time 16.44 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 223360 kb
Host smart-a722dca0-dc54-46c3-8a88-ac2e8d455a2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1328834487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1328834487
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2829747493
Short name T31
Test name
Test status
Simulation time 283539477 ps
CPU time 1.18 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:49:37 PM PDT 24
Peak memory 207416 kb
Host smart-5f4b8399-e620-4c28-8b10-d0f59d313836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829747493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2829747493
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.87503727
Short name T319
Test name
Test status
Simulation time 9251843230 ps
CPU time 24.67 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:56 PM PDT 24
Peak memory 216648 kb
Host smart-ba19be2d-f3e9-410c-b53d-3af5e7ef058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87503727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.87503727
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3227732331
Short name T906
Test name
Test status
Simulation time 7631726044 ps
CPU time 21.88 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:55 PM PDT 24
Peak memory 216684 kb
Host smart-d26db565-c678-4d24-bf81-63b72946ff6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227732331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3227732331
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2239759424
Short name T584
Test name
Test status
Simulation time 46710788 ps
CPU time 1.07 seconds
Started Jun 13 02:49:13 PM PDT 24
Finished Jun 13 02:49:34 PM PDT 24
Peak memory 207872 kb
Host smart-234ebb63-dfea-4bf9-bc81-c0e93f366809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239759424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2239759424
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4235770691
Short name T349
Test name
Test status
Simulation time 191146336 ps
CPU time 0.92 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:32 PM PDT 24
Peak memory 206356 kb
Host smart-594406b5-c838-4f46-8f3e-9276fb9dbf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235770691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4235770691
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.353542107
Short name T198
Test name
Test status
Simulation time 96885244 ps
CPU time 3.12 seconds
Started Jun 13 02:49:08 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 224616 kb
Host smart-029f5a51-a6ab-4683-8457-18887711ac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353542107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.353542107
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3989529275
Short name T821
Test name
Test status
Simulation time 122815542 ps
CPU time 0.68 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:48:36 PM PDT 24
Peak memory 205164 kb
Host smart-7187b4f6-0bed-4f3f-8a46-c7743268ada1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989529275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
989529275
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1737557450
Short name T917
Test name
Test status
Simulation time 1894418015 ps
CPU time 17.84 seconds
Started Jun 13 02:48:28 PM PDT 24
Finished Jun 13 02:49:00 PM PDT 24
Peak memory 224788 kb
Host smart-b13fabe1-c174-4159-a106-a707936aea75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737557450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1737557450
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1080772742
Short name T901
Test name
Test status
Simulation time 28276550 ps
CPU time 0.77 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:48:23 PM PDT 24
Peak memory 205636 kb
Host smart-05d0c2d2-cee8-4cfc-9f5b-5e84bfca8e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080772742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1080772742
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2509191324
Short name T430
Test name
Test status
Simulation time 41617028581 ps
CPU time 78.6 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:49:54 PM PDT 24
Peak memory 249704 kb
Host smart-a34f3db9-c045-48c3-aa1c-caae91a49522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509191324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2509191324
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4072568176
Short name T951
Test name
Test status
Simulation time 4031902003 ps
CPU time 29.27 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:49:03 PM PDT 24
Peak memory 241324 kb
Host smart-c11054dd-e208-4cf7-9b40-bccd23e9db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072568176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4072568176
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3225185423
Short name T863
Test name
Test status
Simulation time 797143321 ps
CPU time 4.97 seconds
Started Jun 13 02:48:09 PM PDT 24
Finished Jun 13 02:48:28 PM PDT 24
Peak memory 218924 kb
Host smart-2114926e-fbd9-4f7a-9ede-b26b8c13cef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225185423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3225185423
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.481166921
Short name T753
Test name
Test status
Simulation time 14035786015 ps
CPU time 42.08 seconds
Started Jun 13 02:48:09 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 240276 kb
Host smart-8b1e458b-2995-46bf-b899-2dce4727bbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481166921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.481166921
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.4279702062
Short name T384
Test name
Test status
Simulation time 16417188 ps
CPU time 1.06 seconds
Started Jun 13 02:48:27 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 216868 kb
Host smart-e227ada0-5eaa-4caf-936d-8c66b3a47ad9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279702062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.4279702062
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1783143232
Short name T63
Test name
Test status
Simulation time 1282192752 ps
CPU time 2.75 seconds
Started Jun 13 02:48:13 PM PDT 24
Finished Jun 13 02:48:32 PM PDT 24
Peak memory 233084 kb
Host smart-b2f5d01a-f3d7-45aa-bf7d-fac2c47607a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783143232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1783143232
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2924360047
Short name T398
Test name
Test status
Simulation time 24342361730 ps
CPU time 20.55 seconds
Started Jun 13 02:48:09 PM PDT 24
Finished Jun 13 02:48:44 PM PDT 24
Peak memory 236500 kb
Host smart-78832ee3-7bcc-4cab-b2a4-ec4d4b72443d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924360047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2924360047
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.470457130
Short name T463
Test name
Test status
Simulation time 5740811379 ps
CPU time 14.28 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:48:48 PM PDT 24
Peak memory 219240 kb
Host smart-b49d0010-21c7-4668-864e-e0665b4c92d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=470457130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.470457130
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1048706585
Short name T70
Test name
Test status
Simulation time 971354933 ps
CPU time 1.24 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:48:37 PM PDT 24
Peak memory 235668 kb
Host smart-1ad612a0-1a28-4d3c-b80c-5e613df1b98d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048706585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1048706585
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3828001320
Short name T153
Test name
Test status
Simulation time 39048228475 ps
CPU time 385.88 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:54:59 PM PDT 24
Peak memory 270612 kb
Host smart-23c06448-1502-4fb3-af57-dc7c10167081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828001320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3828001320
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3693489915
Short name T528
Test name
Test status
Simulation time 4285104254 ps
CPU time 22.81 seconds
Started Jun 13 02:48:11 PM PDT 24
Finished Jun 13 02:48:48 PM PDT 24
Peak memory 216676 kb
Host smart-6acdcc14-0d90-471b-bcc7-d3cb617f4fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693489915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3693489915
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4070076439
Short name T356
Test name
Test status
Simulation time 3408450810 ps
CPU time 3.47 seconds
Started Jun 13 02:48:14 PM PDT 24
Finished Jun 13 02:48:33 PM PDT 24
Peak memory 216624 kb
Host smart-ac542830-00f7-4ddf-979b-4aab9989f216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070076439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4070076439
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3682019150
Short name T723
Test name
Test status
Simulation time 558561360 ps
CPU time 2.03 seconds
Started Jun 13 02:48:08 PM PDT 24
Finished Jun 13 02:48:22 PM PDT 24
Peak memory 216716 kb
Host smart-0911f3a5-8e78-4ed2-9612-586879e2925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682019150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3682019150
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2964829812
Short name T329
Test name
Test status
Simulation time 103611038 ps
CPU time 0.71 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:48:34 PM PDT 24
Peak memory 206168 kb
Host smart-d60c68ea-b730-42ed-8161-2ec6fe29f07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964829812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2964829812
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3702807839
Short name T375
Test name
Test status
Simulation time 3082555505 ps
CPU time 11.3 seconds
Started Jun 13 02:48:24 PM PDT 24
Finished Jun 13 02:48:51 PM PDT 24
Peak memory 235056 kb
Host smart-fccec615-3274-4447-89fe-e6640079caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702807839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3702807839
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.210468964
Short name T33
Test name
Test status
Simulation time 30078494 ps
CPU time 0.68 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 205128 kb
Host smart-516beae9-1844-4932-b086-3fc978b3e20e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210468964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.210468964
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1816013577
Short name T402
Test name
Test status
Simulation time 691586740 ps
CPU time 6.14 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:37 PM PDT 24
Peak memory 233044 kb
Host smart-9b4ec717-4765-4e58-8184-2ae2c5d31aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816013577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1816013577
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3403669558
Short name T416
Test name
Test status
Simulation time 39898159 ps
CPU time 0.79 seconds
Started Jun 13 02:49:05 PM PDT 24
Finished Jun 13 02:49:26 PM PDT 24
Peak memory 206796 kb
Host smart-03861c76-9845-4c03-bb5c-159f55391060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403669558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3403669558
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1625954367
Short name T837
Test name
Test status
Simulation time 8586724249 ps
CPU time 27.3 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:53 PM PDT 24
Peak memory 217844 kb
Host smart-96bd6e89-bdef-4dae-9979-2b57a78077ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625954367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1625954367
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.33695125
Short name T493
Test name
Test status
Simulation time 139385503 ps
CPU time 3.45 seconds
Started Jun 13 02:49:10 PM PDT 24
Finished Jun 13 02:49:34 PM PDT 24
Peak memory 224904 kb
Host smart-ec2d1a6d-1a60-41f7-8156-83d947c41cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33695125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.33695125
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2440923082
Short name T763
Test name
Test status
Simulation time 685298103 ps
CPU time 7.4 seconds
Started Jun 13 02:49:05 PM PDT 24
Finished Jun 13 02:49:32 PM PDT 24
Peak memory 224828 kb
Host smart-8c268935-39e6-42d0-83aa-e8603dd23ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440923082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2440923082
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3169037543
Short name T649
Test name
Test status
Simulation time 9640418828 ps
CPU time 67.14 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:50:34 PM PDT 24
Peak memory 233132 kb
Host smart-0020f32b-50a9-4e2b-a499-d8cb0801db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169037543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3169037543
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1248896363
Short name T191
Test name
Test status
Simulation time 276880423 ps
CPU time 4.5 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:36 PM PDT 24
Peak memory 233076 kb
Host smart-0073742b-87f5-43fd-aefa-ebd69c81a1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248896363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1248896363
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3837087771
Short name T211
Test name
Test status
Simulation time 834563320 ps
CPU time 2.73 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:34 PM PDT 24
Peak memory 224832 kb
Host smart-69f46e1b-ae69-4d92-bab8-df9ff2403ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837087771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3837087771
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3423324770
Short name T65
Test name
Test status
Simulation time 2298183450 ps
CPU time 13.59 seconds
Started Jun 13 02:49:09 PM PDT 24
Finished Jun 13 02:49:43 PM PDT 24
Peak memory 223420 kb
Host smart-be27a91f-1b7b-4889-9c0a-016b9b08548e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3423324770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3423324770
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2568787460
Short name T933
Test name
Test status
Simulation time 60054874 ps
CPU time 1.14 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:40 PM PDT 24
Peak memory 207384 kb
Host smart-e6a726ed-da4d-48d3-9217-94b65592c911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568787460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2568787460
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2340523743
Short name T452
Test name
Test status
Simulation time 3861289336 ps
CPU time 10.29 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 216672 kb
Host smart-17246c3a-8cc1-4dd1-9c14-55913b97a83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340523743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2340523743
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1026697173
Short name T412
Test name
Test status
Simulation time 387339121 ps
CPU time 1.87 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:28 PM PDT 24
Peak memory 208132 kb
Host smart-7d9dac05-a55b-4fe3-be0b-bd6de903faf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026697173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1026697173
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.247337688
Short name T413
Test name
Test status
Simulation time 31822503 ps
CPU time 1.14 seconds
Started Jun 13 02:49:06 PM PDT 24
Finished Jun 13 02:49:27 PM PDT 24
Peak memory 207652 kb
Host smart-ed631ef2-422a-44c1-bc4f-b54fe750bd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247337688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.247337688
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.430074645
Short name T677
Test name
Test status
Simulation time 37485103 ps
CPU time 0.81 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:34 PM PDT 24
Peak memory 206164 kb
Host smart-d549207c-8daa-4325-b150-f23e69e9a47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430074645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.430074645
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.507244417
Short name T523
Test name
Test status
Simulation time 1974150833 ps
CPU time 8 seconds
Started Jun 13 02:49:05 PM PDT 24
Finished Jun 13 02:49:33 PM PDT 24
Peak memory 241068 kb
Host smart-b80cd172-7a47-4e02-b0a4-dbda85bdc078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507244417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.507244417
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.133486950
Short name T484
Test name
Test status
Simulation time 13138343 ps
CPU time 0.69 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 205692 kb
Host smart-75527755-239f-4a84-9a49-87a9b8506ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133486950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.133486950
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1201849416
Short name T549
Test name
Test status
Simulation time 346527677 ps
CPU time 2.99 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:35 PM PDT 24
Peak memory 233024 kb
Host smart-a1e4e807-fdc5-4df0-8c43-286a46264c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201849416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1201849416
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1412562805
Short name T796
Test name
Test status
Simulation time 19312488 ps
CPU time 0.78 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 206760 kb
Host smart-39b6c708-ac83-4852-96af-6ce2ca542a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412562805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1412562805
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3597732461
Short name T210
Test name
Test status
Simulation time 2280893861 ps
CPU time 19.5 seconds
Started Jun 13 02:49:12 PM PDT 24
Finished Jun 13 02:49:51 PM PDT 24
Peak memory 241324 kb
Host smart-8d539999-fe87-495e-9fd4-add9e5f38514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597732461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3597732461
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1500791220
Short name T943
Test name
Test status
Simulation time 37249069571 ps
CPU time 59.45 seconds
Started Jun 13 02:49:13 PM PDT 24
Finished Jun 13 02:50:33 PM PDT 24
Peak memory 249556 kb
Host smart-a2976388-4a72-4a4d-ac36-981d9893730d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500791220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1500791220
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1264967383
Short name T843
Test name
Test status
Simulation time 326567004 ps
CPU time 6.87 seconds
Started Jun 13 02:49:13 PM PDT 24
Finished Jun 13 02:49:40 PM PDT 24
Peak memory 238472 kb
Host smart-69ee790b-9a4d-42fb-9401-e8a266991c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264967383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1264967383
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2757749052
Short name T286
Test name
Test status
Simulation time 485545921 ps
CPU time 6.21 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:49:49 PM PDT 24
Peak memory 233100 kb
Host smart-4a969fd0-65ef-4c08-8374-90196efa13df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757749052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2757749052
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.888850050
Short name T190
Test name
Test status
Simulation time 4691636124 ps
CPU time 34.56 seconds
Started Jun 13 02:49:18 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 233088 kb
Host smart-4a640d2e-990e-4fac-87cc-aede24a3425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888850050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.888850050
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2534726084
Short name T927
Test name
Test status
Simulation time 32119634 ps
CPU time 2.24 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:49:38 PM PDT 24
Peak memory 224828 kb
Host smart-7e9611f1-fb3b-4aae-8a4d-c05eeef51dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534726084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2534726084
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1022028184
Short name T176
Test name
Test status
Simulation time 1403724778 ps
CPU time 4.93 seconds
Started Jun 13 02:49:20 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 224864 kb
Host smart-546895b8-e748-4ef5-9b42-36f745748afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022028184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1022028184
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.420867929
Short name T72
Test name
Test status
Simulation time 292905925 ps
CPU time 4.15 seconds
Started Jun 13 02:49:20 PM PDT 24
Finished Jun 13 02:49:47 PM PDT 24
Peak memory 223344 kb
Host smart-10c02284-f5cb-4182-8ba6-9da96e1b19e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=420867929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.420867929
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2522931493
Short name T20
Test name
Test status
Simulation time 144194045207 ps
CPU time 117.87 seconds
Started Jun 13 02:49:14 PM PDT 24
Finished Jun 13 02:51:34 PM PDT 24
Peak memory 249528 kb
Host smart-c5d8c8e1-61e1-4f14-927c-389a07f4c44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522931493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2522931493
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3192923660
Short name T502
Test name
Test status
Simulation time 93207418 ps
CPU time 0.7 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 205888 kb
Host smart-dee2a295-fa27-43e9-9f2a-741a89ca39d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192923660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3192923660
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1207428579
Short name T904
Test name
Test status
Simulation time 2381677567 ps
CPU time 8.13 seconds
Started Jun 13 02:49:20 PM PDT 24
Finished Jun 13 02:49:51 PM PDT 24
Peak memory 216620 kb
Host smart-7b88cb6d-fb62-4bf5-a0fe-6644c0aa0b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207428579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1207428579
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.230418720
Short name T972
Test name
Test status
Simulation time 594688264 ps
CPU time 6.24 seconds
Started Jun 13 02:49:11 PM PDT 24
Finished Jun 13 02:49:38 PM PDT 24
Peak memory 216752 kb
Host smart-5518d9bd-96a6-46b2-a4c8-247f12bb1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230418720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.230418720
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2156735514
Short name T75
Test name
Test status
Simulation time 20771972 ps
CPU time 0.75 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 206164 kb
Host smart-5456acc4-c7e1-4928-b10f-d22d85d6692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156735514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2156735514
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3806547629
Short name T826
Test name
Test status
Simulation time 3688943862 ps
CPU time 10.18 seconds
Started Jun 13 02:49:15 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 224868 kb
Host smart-5d45836a-8570-4464-a5b1-151a0cecdc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806547629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3806547629
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3911414820
Short name T868
Test name
Test status
Simulation time 14145705 ps
CPU time 0.69 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:39 PM PDT 24
Peak memory 205120 kb
Host smart-7976b1bd-7287-4701-b96e-02896f8c7bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911414820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3911414820
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4137537183
Short name T7
Test name
Test status
Simulation time 54874204 ps
CPU time 2.51 seconds
Started Jun 13 02:49:19 PM PDT 24
Finished Jun 13 02:49:44 PM PDT 24
Peak memory 233084 kb
Host smart-7e922152-ecf4-410b-bc90-c62ce79fb751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137537183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4137537183
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1568757092
Short name T756
Test name
Test status
Simulation time 68412013 ps
CPU time 0.79 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:40 PM PDT 24
Peak memory 206780 kb
Host smart-406e31fa-ba2b-4ca9-bd3f-b1dc806d3f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568757092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1568757092
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3461441941
Short name T224
Test name
Test status
Simulation time 12963310380 ps
CPU time 109.56 seconds
Started Jun 13 02:49:20 PM PDT 24
Finished Jun 13 02:51:33 PM PDT 24
Peak memory 253084 kb
Host smart-b2332ac9-97fd-48ab-befa-6ac6f4782708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461441941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3461441941
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1041565583
Short name T173
Test name
Test status
Simulation time 17391663848 ps
CPU time 74.26 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:51:02 PM PDT 24
Peak memory 249600 kb
Host smart-29ab0eff-0f2f-4771-9089-0158d4a84878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041565583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1041565583
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1779864032
Short name T166
Test name
Test status
Simulation time 4113367157 ps
CPU time 35.08 seconds
Started Jun 13 02:49:23 PM PDT 24
Finished Jun 13 02:50:21 PM PDT 24
Peak memory 249576 kb
Host smart-bd52592c-8470-4bf6-9d92-d8ccbad1a53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779864032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1779864032
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.448389603
Short name T799
Test name
Test status
Simulation time 83531093 ps
CPU time 2.13 seconds
Started Jun 13 02:49:19 PM PDT 24
Finished Jun 13 02:49:43 PM PDT 24
Peak memory 219056 kb
Host smart-12495dcc-467f-4b70-acdb-90e40b44f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448389603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.448389603
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4230076170
Short name T214
Test name
Test status
Simulation time 907489315 ps
CPU time 8.33 seconds
Started Jun 13 02:49:18 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 233092 kb
Host smart-7a5e1318-9ad8-4a28-8f6c-5d56821add0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230076170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4230076170
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.86550983
Short name T920
Test name
Test status
Simulation time 5512578732 ps
CPU time 9.58 seconds
Started Jun 13 02:49:22 PM PDT 24
Finished Jun 13 02:49:55 PM PDT 24
Peak memory 233160 kb
Host smart-aa763e54-4502-4432-b7c0-cd79e3169928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86550983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.86550983
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.809453694
Short name T491
Test name
Test status
Simulation time 369226106 ps
CPU time 3.37 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 224740 kb
Host smart-720c0e46-38dd-44e6-986c-6ec6642d450e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809453694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.809453694
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1749594756
Short name T664
Test name
Test status
Simulation time 3966522553 ps
CPU time 10.33 seconds
Started Jun 13 02:49:25 PM PDT 24
Finished Jun 13 02:49:58 PM PDT 24
Peak memory 239580 kb
Host smart-2302be5b-7a84-4c03-a758-10efba418fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749594756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1749594756
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2566022984
Short name T787
Test name
Test status
Simulation time 267997530 ps
CPU time 5.76 seconds
Started Jun 13 02:49:22 PM PDT 24
Finished Jun 13 02:49:50 PM PDT 24
Peak memory 223404 kb
Host smart-ffb3dc39-e6b4-4fac-a874-1597a3f5e70c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2566022984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2566022984
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.929147644
Short name T171
Test name
Test status
Simulation time 29792618189 ps
CPU time 288.05 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:54:31 PM PDT 24
Peak memory 249584 kb
Host smart-504e6429-bf98-4c49-bfb3-e2b6185fe105
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929147644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.929147644
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2361629365
Short name T806
Test name
Test status
Simulation time 16149599316 ps
CPU time 17.97 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:50:02 PM PDT 24
Peak memory 216980 kb
Host smart-9c77b659-ca73-4822-b1d4-d9d131f0870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361629365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2361629365
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2892897868
Short name T557
Test name
Test status
Simulation time 7541006312 ps
CPU time 5.85 seconds
Started Jun 13 02:49:17 PM PDT 24
Finished Jun 13 02:49:46 PM PDT 24
Peak memory 216484 kb
Host smart-f0967e05-2df7-457c-b6b9-0d579d06ba5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892897868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2892897868
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2080203983
Short name T457
Test name
Test status
Simulation time 32205558 ps
CPU time 0.77 seconds
Started Jun 13 02:49:20 PM PDT 24
Finished Jun 13 02:49:44 PM PDT 24
Peak memory 206144 kb
Host smart-0ed96bdd-9c6a-4ec5-97fa-3d2462f0733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080203983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2080203983
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1231259229
Short name T778
Test name
Test status
Simulation time 61722230 ps
CPU time 0.72 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:49:45 PM PDT 24
Peak memory 206144 kb
Host smart-0068dab9-7ae6-48fc-ac47-9272a0ea3cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231259229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1231259229
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.673739887
Short name T272
Test name
Test status
Simulation time 11983061552 ps
CPU time 34.37 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 233024 kb
Host smart-0373594c-8317-4a78-93e7-4be10d3379f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673739887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.673739887
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1493589660
Short name T854
Test name
Test status
Simulation time 15044022 ps
CPU time 0.7 seconds
Started Jun 13 02:49:27 PM PDT 24
Finished Jun 13 02:49:50 PM PDT 24
Peak memory 205992 kb
Host smart-b6b19a89-e953-4e3b-acc3-9239b30c8d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493589660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1493589660
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1545679482
Short name T591
Test name
Test status
Simulation time 261703172 ps
CPU time 5.23 seconds
Started Jun 13 02:49:25 PM PDT 24
Finished Jun 13 02:49:53 PM PDT 24
Peak memory 233044 kb
Host smart-84bd2b8a-0a54-4a00-854a-332e748c71e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545679482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1545679482
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2409388293
Short name T354
Test name
Test status
Simulation time 12134375 ps
CPU time 0.79 seconds
Started Jun 13 02:49:25 PM PDT 24
Finished Jun 13 02:49:49 PM PDT 24
Peak memory 205736 kb
Host smart-87bb18ad-3a75-49f4-9c43-f0ce28a90f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409388293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2409388293
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.4047453978
Short name T643
Test name
Test status
Simulation time 1566846886 ps
CPU time 14.92 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:50:02 PM PDT 24
Peak memory 241272 kb
Host smart-a5e55f23-7abd-42da-a1eb-b7b010830eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047453978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.4047453978
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.631395903
Short name T453
Test name
Test status
Simulation time 7315380372 ps
CPU time 65.72 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:50:52 PM PDT 24
Peak memory 249588 kb
Host smart-b832e1f2-a5bd-41d3-8cd8-cd6bbad2a5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631395903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.631395903
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.685247014
Short name T244
Test name
Test status
Simulation time 53053729870 ps
CPU time 142.66 seconds
Started Jun 13 02:49:22 PM PDT 24
Finished Jun 13 02:52:07 PM PDT 24
Peak memory 241304 kb
Host smart-5d06a13b-943a-4acb-a657-0ee730a985ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685247014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.685247014
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2552847659
Short name T919
Test name
Test status
Simulation time 578128650 ps
CPU time 4.03 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:49:51 PM PDT 24
Peak memory 224836 kb
Host smart-84c75ea4-0408-4757-b35f-8317bfdb94a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552847659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2552847659
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4245862450
Short name T934
Test name
Test status
Simulation time 5627176402 ps
CPU time 14.9 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:49:59 PM PDT 24
Peak memory 224876 kb
Host smart-ce8b7b93-d6d7-45f9-ae04-6f224d820d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245862450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4245862450
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3799172125
Short name T872
Test name
Test status
Simulation time 6442421699 ps
CPU time 63.94 seconds
Started Jun 13 02:49:19 PM PDT 24
Finished Jun 13 02:50:45 PM PDT 24
Peak memory 241220 kb
Host smart-303ea4ea-af42-40e3-8041-da231f0804b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799172125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3799172125
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1832618826
Short name T613
Test name
Test status
Simulation time 4632612980 ps
CPU time 6.86 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:46 PM PDT 24
Peak memory 233116 kb
Host smart-a371b1e5-50b4-404a-aafb-d479a62bcec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832618826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1832618826
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.11789552
Short name T871
Test name
Test status
Simulation time 124107081 ps
CPU time 2.82 seconds
Started Jun 13 02:49:23 PM PDT 24
Finished Jun 13 02:49:49 PM PDT 24
Peak memory 233060 kb
Host smart-f472784f-d0e9-423c-9a96-f0aba121c446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11789552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.11789552
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3111207623
Short name T953
Test name
Test status
Simulation time 80267543164 ps
CPU time 148.25 seconds
Started Jun 13 02:49:22 PM PDT 24
Finished Jun 13 02:52:13 PM PDT 24
Peak memory 253136 kb
Host smart-53526d63-6b64-42bd-8dd4-a746438c5254
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111207623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3111207623
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3804883039
Short name T610
Test name
Test status
Simulation time 5470873508 ps
CPU time 7.26 seconds
Started Jun 13 02:49:16 PM PDT 24
Finished Jun 13 02:49:47 PM PDT 24
Peak memory 216748 kb
Host smart-ec84790e-b15a-4a2e-9797-bd529c426161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804883039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3804883039
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1023195390
Short name T670
Test name
Test status
Simulation time 1378387953 ps
CPU time 2.35 seconds
Started Jun 13 02:49:26 PM PDT 24
Finished Jun 13 02:49:51 PM PDT 24
Peak memory 216488 kb
Host smart-35932c16-326e-4f4a-97ac-a08d85e9921c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023195390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1023195390
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3307444401
Short name T321
Test name
Test status
Simulation time 656158811 ps
CPU time 7.49 seconds
Started Jun 13 02:49:18 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 216584 kb
Host smart-822a57e5-6909-4971-80e2-f28f9fd023a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307444401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3307444401
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4061862161
Short name T568
Test name
Test status
Simulation time 40398819 ps
CPU time 0.72 seconds
Started Jun 13 02:49:18 PM PDT 24
Finished Jun 13 02:49:42 PM PDT 24
Peak memory 206156 kb
Host smart-2cc67ab3-6cc2-4815-b855-19ae800157ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061862161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4061862161
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.764577205
Short name T581
Test name
Test status
Simulation time 270690444 ps
CPU time 5.73 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:49:50 PM PDT 24
Peak memory 233032 kb
Host smart-0c966c65-6c36-4e40-8012-b37747af0f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764577205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.764577205
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1614702882
Short name T596
Test name
Test status
Simulation time 24136933 ps
CPU time 0.72 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 205760 kb
Host smart-7368e9e5-dad5-4810-887d-c60a591ed2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614702882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1614702882
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3980133670
Short name T467
Test name
Test status
Simulation time 642872865 ps
CPU time 3.4 seconds
Started Jun 13 02:49:23 PM PDT 24
Finished Jun 13 02:49:50 PM PDT 24
Peak memory 224856 kb
Host smart-235f0034-1991-40fb-94ad-d8a82dce122d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980133670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3980133670
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2180128213
Short name T526
Test name
Test status
Simulation time 38242982 ps
CPU time 0.76 seconds
Started Jun 13 02:49:26 PM PDT 24
Finished Jun 13 02:49:51 PM PDT 24
Peak memory 205772 kb
Host smart-164c0f7f-1678-4642-9183-51b0a8ba6d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180128213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2180128213
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2040247540
Short name T876
Test name
Test status
Simulation time 5907086257 ps
CPU time 71.51 seconds
Started Jun 13 02:49:23 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 251064 kb
Host smart-37d3b6b1-72a0-456a-a102-edae713939bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040247540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2040247540
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2274682008
Short name T659
Test name
Test status
Simulation time 1151868229 ps
CPU time 3.65 seconds
Started Jun 13 02:49:23 PM PDT 24
Finished Jun 13 02:49:50 PM PDT 24
Peak memory 217740 kb
Host smart-72350b91-f1bb-4e53-bb50-fe4406493bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274682008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2274682008
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2319676662
Short name T777
Test name
Test status
Simulation time 10694578578 ps
CPU time 26.6 seconds
Started Jun 13 02:49:25 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 248972 kb
Host smart-908a500d-027f-4d88-aa29-01c08423521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319676662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2319676662
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.823331448
Short name T278
Test name
Test status
Simulation time 809602417 ps
CPU time 13.56 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:50:01 PM PDT 24
Peak memory 241292 kb
Host smart-aa0c1f83-3d0e-4275-94c5-e0637eaadcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823331448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.823331448
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2121645181
Short name T507
Test name
Test status
Simulation time 59947920 ps
CPU time 2.21 seconds
Started Jun 13 02:49:22 PM PDT 24
Finished Jun 13 02:49:48 PM PDT 24
Peak memory 232848 kb
Host smart-2138c4e5-9f3d-4af6-a0f3-e825791b1af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121645181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2121645181
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.255849646
Short name T206
Test name
Test status
Simulation time 8945983673 ps
CPU time 52.44 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:50:40 PM PDT 24
Peak memory 233064 kb
Host smart-2f8a3174-44ad-4b4e-8e65-e4589d26dd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255849646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.255849646
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3588596954
Short name T570
Test name
Test status
Simulation time 421369256 ps
CPU time 3.02 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:49:51 PM PDT 24
Peak memory 233056 kb
Host smart-cfb0a726-e365-4b21-a340-54ab2eb38aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588596954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3588596954
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2015316800
Short name T674
Test name
Test status
Simulation time 4542406511 ps
CPU time 15.03 seconds
Started Jun 13 02:49:22 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 224928 kb
Host smart-4a32378e-40a3-4ff3-a17f-c0b2560f08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015316800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2015316800
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3794224749
Short name T442
Test name
Test status
Simulation time 249382417 ps
CPU time 5.51 seconds
Started Jun 13 02:49:23 PM PDT 24
Finished Jun 13 02:49:52 PM PDT 24
Peak memory 223504 kb
Host smart-516fb0fa-5c11-49ea-b846-2c1f29c8ca6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3794224749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3794224749
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.856145226
Short name T32
Test name
Test status
Simulation time 69093661 ps
CPU time 0.99 seconds
Started Jun 13 02:49:29 PM PDT 24
Finished Jun 13 02:49:53 PM PDT 24
Peak memory 207112 kb
Host smart-321f4ebc-dcc8-4e91-b363-0b7532bfc5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856145226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.856145226
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1124051814
Short name T671
Test name
Test status
Simulation time 83401147356 ps
CPU time 24.93 seconds
Started Jun 13 02:49:26 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 216608 kb
Host smart-abafb96a-e254-4d1c-bb0b-1d696c5289cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124051814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1124051814
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.386017014
Short name T347
Test name
Test status
Simulation time 342753090 ps
CPU time 2 seconds
Started Jun 13 02:49:24 PM PDT 24
Finished Jun 13 02:49:49 PM PDT 24
Peak memory 216432 kb
Host smart-f995ac8a-5ff9-4fe3-9007-3b7bc01a2786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386017014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.386017014
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4060983832
Short name T640
Test name
Test status
Simulation time 18191062 ps
CPU time 0.81 seconds
Started Jun 13 02:49:23 PM PDT 24
Finished Jun 13 02:49:47 PM PDT 24
Peak memory 207020 kb
Host smart-7194e646-90e9-433d-88eb-82ca726a4e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060983832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4060983832
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2865688507
Short name T414
Test name
Test status
Simulation time 79331854 ps
CPU time 0.86 seconds
Started Jun 13 02:49:22 PM PDT 24
Finished Jun 13 02:49:46 PM PDT 24
Peak memory 206128 kb
Host smart-90a8350a-39fa-44aa-90d0-e38dec2c2c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865688507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2865688507
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2202087866
Short name T877
Test name
Test status
Simulation time 127603244 ps
CPU time 2.58 seconds
Started Jun 13 02:49:21 PM PDT 24
Finished Jun 13 02:49:47 PM PDT 24
Peak memory 233088 kb
Host smart-d0058473-8b8c-47ee-932f-6da08612c632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202087866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2202087866
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2575830407
Short name T68
Test name
Test status
Simulation time 99469455 ps
CPU time 0.7 seconds
Started Jun 13 02:49:34 PM PDT 24
Finished Jun 13 02:49:56 PM PDT 24
Peak memory 206028 kb
Host smart-ecc27365-0c01-4f55-8762-f47d539ac582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575830407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2575830407
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.943319453
Short name T910
Test name
Test status
Simulation time 231863483 ps
CPU time 3.97 seconds
Started Jun 13 02:49:29 PM PDT 24
Finished Jun 13 02:49:55 PM PDT 24
Peak memory 224804 kb
Host smart-43ec4544-3ec2-4547-8bb0-1f14613ceac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943319453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.943319453
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2926093192
Short name T638
Test name
Test status
Simulation time 12843162 ps
CPU time 0.75 seconds
Started Jun 13 02:49:29 PM PDT 24
Finished Jun 13 02:49:52 PM PDT 24
Peak memory 206068 kb
Host smart-2bd80951-4302-4b64-9808-d40bb1640126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926093192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2926093192
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.802879490
Short name T237
Test name
Test status
Simulation time 75034332799 ps
CPU time 572.18 seconds
Started Jun 13 02:49:27 PM PDT 24
Finished Jun 13 02:59:22 PM PDT 24
Peak memory 269512 kb
Host smart-b9463462-56e5-45b9-9bb3-7a44e81f91ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802879490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.802879490
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.181163867
Short name T129
Test name
Test status
Simulation time 6585407083 ps
CPU time 39.76 seconds
Started Jun 13 02:49:37 PM PDT 24
Finished Jun 13 02:50:36 PM PDT 24
Peak memory 233080 kb
Host smart-85ab70c5-9b06-4ca5-826b-0106ad3b8fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181163867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.181163867
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2631686356
Short name T301
Test name
Test status
Simulation time 51971493 ps
CPU time 2.62 seconds
Started Jun 13 02:49:34 PM PDT 24
Finished Jun 13 02:49:58 PM PDT 24
Peak memory 224864 kb
Host smart-3448a905-c8fd-4a4d-8cc5-0fcc433e9b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631686356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2631686356
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2729783073
Short name T842
Test name
Test status
Simulation time 337085696 ps
CPU time 6.41 seconds
Started Jun 13 02:49:28 PM PDT 24
Finished Jun 13 02:49:57 PM PDT 24
Peak memory 224820 kb
Host smart-d24391bf-be49-45fa-b843-ff48dbc51840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729783073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2729783073
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1922256495
Short name T858
Test name
Test status
Simulation time 730191971 ps
CPU time 4.47 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:50:01 PM PDT 24
Peak memory 218932 kb
Host smart-5ca2527a-f6ba-49e9-b951-4eab0ab5f693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922256495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1922256495
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2129109015
Short name T186
Test name
Test status
Simulation time 7500775637 ps
CPU time 7.74 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 233112 kb
Host smart-236e3447-80a2-4928-bb5b-ee2c9f1eb95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129109015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2129109015
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2432031899
Short name T359
Test name
Test status
Simulation time 266553325 ps
CPU time 3.56 seconds
Started Jun 13 02:49:29 PM PDT 24
Finished Jun 13 02:49:54 PM PDT 24
Peak memory 222248 kb
Host smart-91ac316d-f4d0-45f5-96fb-92de40d37cd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2432031899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2432031899
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.447903923
Short name T531
Test name
Test status
Simulation time 4259781145 ps
CPU time 16.49 seconds
Started Jun 13 02:49:31 PM PDT 24
Finished Jun 13 02:50:09 PM PDT 24
Peak memory 216632 kb
Host smart-5e193187-c9b4-4155-bda8-b0bddbef15e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447903923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.447903923
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1027407628
Short name T401
Test name
Test status
Simulation time 422203496 ps
CPU time 2.9 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:49:59 PM PDT 24
Peak memory 216592 kb
Host smart-a0d63d0a-c4fa-41a8-bd98-c7a6a56c7511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027407628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1027407628
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4090827742
Short name T944
Test name
Test status
Simulation time 55391983 ps
CPU time 1.02 seconds
Started Jun 13 02:49:37 PM PDT 24
Finished Jun 13 02:49:58 PM PDT 24
Peak memory 208212 kb
Host smart-eb01c7b4-18a9-43fa-b6af-0fd3821c4a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090827742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4090827742
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4174520274
Short name T130
Test name
Test status
Simulation time 77010679 ps
CPU time 0.96 seconds
Started Jun 13 02:49:29 PM PDT 24
Finished Jun 13 02:49:52 PM PDT 24
Peak memory 206204 kb
Host smart-be9558c2-457b-4e0e-bb82-86b532b1f449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174520274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4174520274
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4133432549
Short name T302
Test name
Test status
Simulation time 420449085 ps
CPU time 3.09 seconds
Started Jun 13 02:49:30 PM PDT 24
Finished Jun 13 02:49:55 PM PDT 24
Peak memory 233084 kb
Host smart-dc4abe93-f1de-4441-96ef-2f18d87e1843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133432549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4133432549
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4188839040
Short name T700
Test name
Test status
Simulation time 16303585 ps
CPU time 0.8 seconds
Started Jun 13 02:49:39 PM PDT 24
Finished Jun 13 02:49:58 PM PDT 24
Peak memory 206036 kb
Host smart-81170a23-551e-44b0-8dd3-4f1a4aa8e66f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188839040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4188839040
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3212761676
Short name T372
Test name
Test status
Simulation time 2471423677 ps
CPU time 4.42 seconds
Started Jun 13 02:49:35 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 224888 kb
Host smart-ce1a2726-9a40-42e3-a083-c8afa44cd2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212761676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3212761676
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2580197877
Short name T928
Test name
Test status
Simulation time 60359507 ps
CPU time 0.75 seconds
Started Jun 13 02:49:37 PM PDT 24
Finished Jun 13 02:49:57 PM PDT 24
Peak memory 206796 kb
Host smart-27f5eabb-c5f3-4c75-b2f3-5ab6d9ddaf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580197877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2580197877
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1587312464
Short name T805
Test name
Test status
Simulation time 17226990073 ps
CPU time 125.14 seconds
Started Jun 13 02:49:35 PM PDT 24
Finished Jun 13 02:52:01 PM PDT 24
Peak memory 249492 kb
Host smart-508846ee-e580-4ab6-82ae-e841c4b7bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587312464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1587312464
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1414987071
Short name T221
Test name
Test status
Simulation time 9516479483 ps
CPU time 117.68 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:51:54 PM PDT 24
Peak memory 265840 kb
Host smart-3284cb7f-b9ce-47af-9c41-2b91bffc5c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414987071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1414987071
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3117590994
Short name T768
Test name
Test status
Simulation time 8385185188 ps
CPU time 99.29 seconds
Started Jun 13 02:49:39 PM PDT 24
Finished Jun 13 02:51:38 PM PDT 24
Peak memory 249716 kb
Host smart-7d0e0138-2171-48b9-9cb5-a1eeafc65ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117590994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3117590994
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4202490204
Short name T396
Test name
Test status
Simulation time 1160790444 ps
CPU time 7.73 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 233004 kb
Host smart-5b96cc94-122f-42a1-9e04-39e9e0a876a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202490204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4202490204
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1511602696
Short name T897
Test name
Test status
Simulation time 11567036117 ps
CPU time 23.19 seconds
Started Jun 13 02:49:33 PM PDT 24
Finished Jun 13 02:50:18 PM PDT 24
Peak memory 224876 kb
Host smart-8845ee65-4af9-4337-b5d5-1c2491b6a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511602696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1511602696
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.729291429
Short name T708
Test name
Test status
Simulation time 938235727 ps
CPU time 9.98 seconds
Started Jun 13 02:49:33 PM PDT 24
Finished Jun 13 02:50:05 PM PDT 24
Peak memory 228232 kb
Host smart-0b11c053-4a6a-4793-821e-48e1f5052307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729291429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.729291429
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.475807279
Short name T245
Test name
Test status
Simulation time 3844880515 ps
CPU time 8.33 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:50:05 PM PDT 24
Peak memory 229064 kb
Host smart-79bf6fb6-4d34-41e0-9073-564e2d825beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475807279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.475807279
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1694875115
Short name T357
Test name
Test status
Simulation time 212299032 ps
CPU time 2.5 seconds
Started Jun 13 02:49:31 PM PDT 24
Finished Jun 13 02:49:56 PM PDT 24
Peak memory 224876 kb
Host smart-080649bc-c06c-4610-b4f6-db6d83003b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694875115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1694875115
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3881757640
Short name T759
Test name
Test status
Simulation time 1404149963 ps
CPU time 6.07 seconds
Started Jun 13 02:49:40 PM PDT 24
Finished Jun 13 02:50:05 PM PDT 24
Peak memory 219284 kb
Host smart-67723357-823f-4421-aa16-4bedf46b6e3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3881757640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3881757640
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.901824443
Short name T704
Test name
Test status
Simulation time 19463327444 ps
CPU time 28.78 seconds
Started Jun 13 02:49:29 PM PDT 24
Finished Jun 13 02:50:21 PM PDT 24
Peak memory 216660 kb
Host smart-1fb3b9a9-4809-431b-a805-810a2a8a630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901824443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.901824443
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3744703949
Short name T734
Test name
Test status
Simulation time 1266689730 ps
CPU time 3.57 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 216520 kb
Host smart-b6e4eccb-fa02-46aa-80c0-a0fbc914f869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744703949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3744703949
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.664768838
Short name T599
Test name
Test status
Simulation time 114069755 ps
CPU time 3.14 seconds
Started Jun 13 02:49:29 PM PDT 24
Finished Jun 13 02:49:54 PM PDT 24
Peak memory 216632 kb
Host smart-f4d17652-cea8-4c76-b449-85d14e357b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664768838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.664768838
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4122478021
Short name T355
Test name
Test status
Simulation time 18354340 ps
CPU time 0.69 seconds
Started Jun 13 02:49:30 PM PDT 24
Finished Jun 13 02:49:53 PM PDT 24
Peak memory 205828 kb
Host smart-c6062b8a-9cd2-4f14-a383-f326bd5f7efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122478021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4122478021
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2040104127
Short name T381
Test name
Test status
Simulation time 400099853 ps
CPU time 5.28 seconds
Started Jun 13 02:49:33 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 224792 kb
Host smart-f4e3132a-b6a2-4a4c-8d94-ed124531e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040104127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2040104127
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4251114562
Short name T597
Test name
Test status
Simulation time 20562714 ps
CPU time 0.73 seconds
Started Jun 13 02:49:42 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 205120 kb
Host smart-bb17e4e4-df9a-4a95-b6f9-e0d8ea4d4188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251114562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4251114562
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1445457258
Short name T448
Test name
Test status
Simulation time 211301614 ps
CPU time 3.53 seconds
Started Jun 13 02:49:43 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 224828 kb
Host smart-4061ad86-6d13-4a71-9454-f3620f032f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445457258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1445457258
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3740288077
Short name T720
Test name
Test status
Simulation time 18200315 ps
CPU time 0.8 seconds
Started Jun 13 02:49:33 PM PDT 24
Finished Jun 13 02:49:56 PM PDT 24
Peak memory 206804 kb
Host smart-179a1347-3f13-4714-8503-79a4c581cc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740288077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3740288077
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2593610963
Short name T179
Test name
Test status
Simulation time 56476467205 ps
CPU time 376.99 seconds
Started Jun 13 02:49:44 PM PDT 24
Finished Jun 13 02:56:18 PM PDT 24
Peak memory 250720 kb
Host smart-3ff21bc0-3b66-4603-abbe-71572f37dda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593610963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2593610963
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2305075807
Short name T712
Test name
Test status
Simulation time 9158042353 ps
CPU time 93.19 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:51:35 PM PDT 24
Peak memory 251016 kb
Host smart-9f9cc243-bff5-4a70-af9b-75f4861de80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305075807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2305075807
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.176696567
Short name T541
Test name
Test status
Simulation time 1471116848 ps
CPU time 14.46 seconds
Started Jun 13 02:49:40 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 233096 kb
Host smart-392e9575-ed6b-4409-b542-5423be8939ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176696567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.176696567
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1552315179
Short name T646
Test name
Test status
Simulation time 2660969300 ps
CPU time 5.45 seconds
Started Jun 13 02:49:34 PM PDT 24
Finished Jun 13 02:50:01 PM PDT 24
Peak memory 218980 kb
Host smart-56a7840c-d393-447f-a9fa-c375eca67492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552315179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1552315179
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4252887837
Short name T736
Test name
Test status
Simulation time 1604581212 ps
CPU time 23.49 seconds
Started Jun 13 02:49:44 PM PDT 24
Finished Jun 13 02:50:24 PM PDT 24
Peak memory 240868 kb
Host smart-5864bf14-ebe0-4112-87c7-6933e16d65dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252887837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4252887837
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3252295657
Short name T445
Test name
Test status
Simulation time 1599579833 ps
CPU time 4.18 seconds
Started Jun 13 02:49:34 PM PDT 24
Finished Jun 13 02:49:59 PM PDT 24
Peak memory 218848 kb
Host smart-fb7fc621-f5d5-4a3f-b348-a8de0305d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252295657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3252295657
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1748525915
Short name T699
Test name
Test status
Simulation time 2189042863 ps
CPU time 9.74 seconds
Started Jun 13 02:49:40 PM PDT 24
Finished Jun 13 02:50:08 PM PDT 24
Peak memory 240384 kb
Host smart-eb19fbbd-edcc-45b2-8b64-466b0f2bcb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748525915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1748525915
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.220040961
Short name T895
Test name
Test status
Simulation time 11365349858 ps
CPU time 7.33 seconds
Started Jun 13 02:49:40 PM PDT 24
Finished Jun 13 02:50:06 PM PDT 24
Peak memory 223556 kb
Host smart-3d2e6fb5-e45d-496a-b352-309856109ee1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=220040961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.220040961
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1955126413
Short name T949
Test name
Test status
Simulation time 210900892 ps
CPU time 1.06 seconds
Started Jun 13 02:49:45 PM PDT 24
Finished Jun 13 02:50:03 PM PDT 24
Peak memory 207088 kb
Host smart-cd88e86b-596c-4f2b-b156-90f1eda52745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955126413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1955126413
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.313678161
Short name T628
Test name
Test status
Simulation time 9455442096 ps
CPU time 52.82 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:50:49 PM PDT 24
Peak memory 216652 kb
Host smart-40e5b317-afbb-4840-97fb-6912837c5675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313678161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.313678161
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3096789262
Short name T661
Test name
Test status
Simulation time 15456750616 ps
CPU time 11.45 seconds
Started Jun 13 02:49:34 PM PDT 24
Finished Jun 13 02:50:07 PM PDT 24
Peak memory 216552 kb
Host smart-bb21c582-39fa-4007-8358-7f5e99f90486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096789262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3096789262
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.253060831
Short name T728
Test name
Test status
Simulation time 110717535 ps
CPU time 1.53 seconds
Started Jun 13 02:49:33 PM PDT 24
Finished Jun 13 02:49:57 PM PDT 24
Peak memory 216572 kb
Host smart-aca6000e-ac28-4032-ab66-adf7464e9d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253060831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.253060831
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2036619842
Short name T748
Test name
Test status
Simulation time 103838723 ps
CPU time 0.9 seconds
Started Jun 13 02:49:36 PM PDT 24
Finished Jun 13 02:49:57 PM PDT 24
Peak memory 206412 kb
Host smart-05fefd1a-3207-4002-aeae-82f49ea2c265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036619842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2036619842
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1946803121
Short name T846
Test name
Test status
Simulation time 3592324126 ps
CPU time 6.26 seconds
Started Jun 13 02:49:44 PM PDT 24
Finished Jun 13 02:50:08 PM PDT 24
Peak memory 233148 kb
Host smart-f35a0edc-3142-485a-8bbc-c611743ae950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946803121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1946803121
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2579697481
Short name T684
Test name
Test status
Simulation time 22579107 ps
CPU time 0.73 seconds
Started Jun 13 02:49:42 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 205712 kb
Host smart-283ac56a-6f4f-4948-93c0-29fb0c3f673b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579697481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2579697481
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.575466202
Short name T803
Test name
Test status
Simulation time 128480599 ps
CPU time 2.7 seconds
Started Jun 13 02:49:43 PM PDT 24
Finished Jun 13 02:50:03 PM PDT 24
Peak memory 224824 kb
Host smart-c45f27b3-0e1c-47db-b8a8-0a9c8f1e8f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575466202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.575466202
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.730139739
Short name T785
Test name
Test status
Simulation time 15964523 ps
CPU time 0.8 seconds
Started Jun 13 02:49:42 PM PDT 24
Finished Jun 13 02:50:00 PM PDT 24
Peak memory 206796 kb
Host smart-92b9c510-09d3-47e1-bab4-63e86309c090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730139739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.730139739
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.831510884
Short name T891
Test name
Test status
Simulation time 13651191761 ps
CPU time 62.02 seconds
Started Jun 13 02:49:44 PM PDT 24
Finished Jun 13 02:51:03 PM PDT 24
Peak memory 237444 kb
Host smart-fcc75012-cc7b-4ee4-9c99-dd104d9bdb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831510884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.831510884
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.824844729
Short name T138
Test name
Test status
Simulation time 33239129751 ps
CPU time 134.16 seconds
Started Jun 13 02:49:42 PM PDT 24
Finished Jun 13 02:52:14 PM PDT 24
Peak memory 257012 kb
Host smart-58c71bd8-6868-42ee-8527-1e6fa2a79a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824844729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.824844729
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.814299328
Short name T908
Test name
Test status
Simulation time 6847213552 ps
CPU time 10.92 seconds
Started Jun 13 02:49:43 PM PDT 24
Finished Jun 13 02:50:11 PM PDT 24
Peak memory 224956 kb
Host smart-66cf18b9-9b35-47a4-88ad-fa534e60d6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814299328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.814299328
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1765237730
Short name T315
Test name
Test status
Simulation time 184797696 ps
CPU time 10.93 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 234072 kb
Host smart-69b37a4b-9557-4336-95b3-320f86b6852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765237730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1765237730
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.337241462
Short name T792
Test name
Test status
Simulation time 1258534713 ps
CPU time 4.49 seconds
Started Jun 13 02:49:42 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 224836 kb
Host smart-4cfc3d0e-fd06-46ef-a791-c75f0fcb25e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337241462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.337241462
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.656848768
Short name T62
Test name
Test status
Simulation time 764672554 ps
CPU time 4.73 seconds
Started Jun 13 02:49:41 PM PDT 24
Finished Jun 13 02:50:03 PM PDT 24
Peak memory 233060 kb
Host smart-87fabd5f-5f2f-484f-aef2-66b0efac46f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656848768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.656848768
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1338807300
Short name T189
Test name
Test status
Simulation time 60264082105 ps
CPU time 18.08 seconds
Started Jun 13 02:49:41 PM PDT 24
Finished Jun 13 02:50:17 PM PDT 24
Peak memory 240668 kb
Host smart-d80490b6-ab6b-4d37-a730-9fa9a60b4465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338807300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1338807300
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3960519035
Short name T847
Test name
Test status
Simulation time 378612959 ps
CPU time 2.28 seconds
Started Jun 13 02:49:42 PM PDT 24
Finished Jun 13 02:50:02 PM PDT 24
Peak memory 232820 kb
Host smart-57e233fb-937b-497d-ba73-d0bd1f57fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960519035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3960519035
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.48827463
Short name T971
Test name
Test status
Simulation time 431933854 ps
CPU time 5.68 seconds
Started Jun 13 02:49:44 PM PDT 24
Finished Jun 13 02:50:06 PM PDT 24
Peak memory 220620 kb
Host smart-b9175649-c499-4999-aad8-f9b29681f3b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48827463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direc
t.48827463
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3498760493
Short name T563
Test name
Test status
Simulation time 8220524345 ps
CPU time 37.16 seconds
Started Jun 13 02:49:45 PM PDT 24
Finished Jun 13 02:50:39 PM PDT 24
Peak memory 216688 kb
Host smart-ff850ad1-6d2f-4fd3-a782-75d9b0d13a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498760493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3498760493
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2850684347
Short name T656
Test name
Test status
Simulation time 12497946 ps
CPU time 0.69 seconds
Started Jun 13 02:51:48 PM PDT 24
Finished Jun 13 02:51:55 PM PDT 24
Peak memory 205856 kb
Host smart-488b3479-23a5-464f-9d7f-b237f1ef254b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850684347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2850684347
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2530923678
Short name T711
Test name
Test status
Simulation time 257681396 ps
CPU time 1.6 seconds
Started Jun 13 02:49:45 PM PDT 24
Finished Jun 13 02:50:03 PM PDT 24
Peak memory 216548 kb
Host smart-737b36c5-defd-4c4e-a7bd-c70af301a4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530923678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2530923678
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.187340860
Short name T418
Test name
Test status
Simulation time 17729306 ps
CPU time 0.72 seconds
Started Jun 13 02:49:44 PM PDT 24
Finished Jun 13 02:50:02 PM PDT 24
Peak memory 206172 kb
Host smart-42627b97-d7eb-4ede-9d17-e108263da15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187340860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.187340860
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.727750665
Short name T559
Test name
Test status
Simulation time 260245886 ps
CPU time 2.97 seconds
Started Jun 13 02:49:41 PM PDT 24
Finished Jun 13 02:50:02 PM PDT 24
Peak memory 233024 kb
Host smart-302b0f9d-7c3e-45ff-b75d-ff965f9cc172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727750665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.727750665
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2129315141
Short name T738
Test name
Test status
Simulation time 109493727 ps
CPU time 0.72 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 205948 kb
Host smart-0a78eb3d-2884-4d15-b033-35f527a595b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129315141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2129315141
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2837705777
Short name T88
Test name
Test status
Simulation time 1464046823 ps
CPU time 8.31 seconds
Started Jun 13 02:49:45 PM PDT 24
Finished Jun 13 02:50:10 PM PDT 24
Peak memory 233080 kb
Host smart-f6a76154-8931-4e2c-a155-58f4469d8213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837705777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2837705777
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2095409267
Short name T10
Test name
Test status
Simulation time 16422670 ps
CPU time 0.76 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:50:05 PM PDT 24
Peak memory 205772 kb
Host smart-627219c8-6975-4761-ba96-4927aa6cd136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095409267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2095409267
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3821028008
Short name T750
Test name
Test status
Simulation time 5029377676 ps
CPU time 39.99 seconds
Started Jun 13 02:49:51 PM PDT 24
Finished Jun 13 02:50:46 PM PDT 24
Peak memory 249520 kb
Host smart-90edd22d-c3c2-43bb-98b2-839923b55106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821028008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3821028008
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3526017414
Short name T830
Test name
Test status
Simulation time 21019408004 ps
CPU time 120.08 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:52:04 PM PDT 24
Peak memory 249576 kb
Host smart-02814b29-cef8-4a9d-aded-0b90bd8a4337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526017414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3526017414
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3597353941
Short name T954
Test name
Test status
Simulation time 89140308187 ps
CPU time 208.02 seconds
Started Jun 13 02:49:50 PM PDT 24
Finished Jun 13 02:53:34 PM PDT 24
Peak memory 257664 kb
Host smart-4998df19-12f2-4128-bdbd-e0a44922b903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597353941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3597353941
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2999384679
Short name T279
Test name
Test status
Simulation time 384012429 ps
CPU time 5.76 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:50:10 PM PDT 24
Peak memory 233096 kb
Host smart-a06b2b63-bb5c-44e2-88bf-2189839136e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999384679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2999384679
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4076517455
Short name T977
Test name
Test status
Simulation time 1091242694 ps
CPU time 4.72 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:08 PM PDT 24
Peak memory 224832 kb
Host smart-b7a61149-01a7-4870-878b-d0206a8650c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076517455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4076517455
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3835940066
Short name T285
Test name
Test status
Simulation time 382791648 ps
CPU time 10.49 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 233028 kb
Host smart-df376e06-23ba-43a9-9974-3cc008ccc27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835940066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3835940066
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3555756519
Short name T229
Test name
Test status
Simulation time 13824193745 ps
CPU time 10.83 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 224816 kb
Host smart-bded3474-f224-49da-af9e-27315a7af8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555756519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3555756519
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1660760692
Short name T371
Test name
Test status
Simulation time 236650853 ps
CPU time 2.11 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 223276 kb
Host smart-0f2f4a33-5d4f-4b92-a983-97ba3f1ec144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660760692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1660760692
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2856251335
Short name T935
Test name
Test status
Simulation time 3122090659 ps
CPU time 6.43 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:10 PM PDT 24
Peak memory 221320 kb
Host smart-2b8e6a2a-9ab6-4980-ab27-a08a6f3a849c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2856251335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2856251335
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1895656373
Short name T660
Test name
Test status
Simulation time 7994924476 ps
CPU time 9.67 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 217920 kb
Host smart-8f0f38d2-3444-4363-9f1e-66d8dfd25ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895656373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1895656373
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2575859343
Short name T772
Test name
Test status
Simulation time 5911739599 ps
CPU time 1.83 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:50:05 PM PDT 24
Peak memory 208248 kb
Host smart-3d13d9c1-123c-40cc-8ebd-64c5123c9735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575859343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2575859343
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2494573819
Short name T370
Test name
Test status
Simulation time 1014829070 ps
CPU time 4.82 seconds
Started Jun 13 02:49:49 PM PDT 24
Finished Jun 13 02:50:09 PM PDT 24
Peak memory 216592 kb
Host smart-0f4f3fb2-7a9d-4832-9ba8-fd95bd55257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494573819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2494573819
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2183600773
Short name T961
Test name
Test status
Simulation time 84100642 ps
CPU time 0.77 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 206172 kb
Host smart-6135ecfb-942f-4c49-a8d6-5da628dbfc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183600773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2183600773
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.952648378
Short name T632
Test name
Test status
Simulation time 4173272892 ps
CPU time 10.1 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 233072 kb
Host smart-a8d5bd98-1131-4a6a-8eea-6556cb57540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952648378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.952648378
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1839322205
Short name T800
Test name
Test status
Simulation time 21797393 ps
CPU time 0.69 seconds
Started Jun 13 02:48:34 PM PDT 24
Finished Jun 13 02:48:51 PM PDT 24
Peak memory 205100 kb
Host smart-b92a364c-2180-49f6-a61b-04b98b459312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839322205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
839322205
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1816261089
Short name T811
Test name
Test status
Simulation time 744272109 ps
CPU time 10.68 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:48:46 PM PDT 24
Peak memory 233040 kb
Host smart-18789c43-9796-46b7-b950-51f6e386aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816261089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1816261089
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3532684864
Short name T506
Test name
Test status
Simulation time 17079489 ps
CPU time 0.78 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:48:37 PM PDT 24
Peak memory 206784 kb
Host smart-e850a527-5b30-4af4-98ae-97b7f3cc8c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532684864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3532684864
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3912286766
Short name T253
Test name
Test status
Simulation time 19654064804 ps
CPU time 63.67 seconds
Started Jun 13 02:48:33 PM PDT 24
Finished Jun 13 02:49:53 PM PDT 24
Peak memory 249532 kb
Host smart-8dc68255-9b19-4dd5-8c56-7792cf2cc9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912286766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3912286766
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2741412440
Short name T793
Test name
Test status
Simulation time 385286346502 ps
CPU time 356.47 seconds
Started Jun 13 02:48:25 PM PDT 24
Finished Jun 13 02:54:37 PM PDT 24
Peak memory 249584 kb
Host smart-f55c59db-2f68-401e-99c3-867b0e195e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741412440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2741412440
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2124503387
Short name T692
Test name
Test status
Simulation time 59993677478 ps
CPU time 285.8 seconds
Started Jun 13 02:48:32 PM PDT 24
Finished Jun 13 02:53:34 PM PDT 24
Peak memory 250996 kb
Host smart-608dd7b9-33fa-47ac-9f89-b1416e11f440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124503387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2124503387
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1916212375
Short name T314
Test name
Test status
Simulation time 2859235749 ps
CPU time 38.95 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:49:12 PM PDT 24
Peak memory 241316 kb
Host smart-0e28b4e9-1d9a-45f8-aaa2-349e67574955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916212375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1916212375
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2305434668
Short name T192
Test name
Test status
Simulation time 3162445834 ps
CPU time 14.72 seconds
Started Jun 13 02:48:21 PM PDT 24
Finished Jun 13 02:48:51 PM PDT 24
Peak memory 224856 kb
Host smart-b230c316-b611-4d9a-b0d2-2aa3cd28fef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305434668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2305434668
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2096629372
Short name T525
Test name
Test status
Simulation time 10632576915 ps
CPU time 48.01 seconds
Started Jun 13 02:48:16 PM PDT 24
Finished Jun 13 02:49:19 PM PDT 24
Peak memory 241272 kb
Host smart-5b42055a-0222-4943-808b-1a0da71a8cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096629372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2096629372
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3387552815
Short name T726
Test name
Test status
Simulation time 43166758 ps
CPU time 1.01 seconds
Started Jun 13 02:48:16 PM PDT 24
Finished Jun 13 02:48:33 PM PDT 24
Peak memory 216904 kb
Host smart-a39d0e60-e095-4b4f-a4a1-5872eb6f66f8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387552815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3387552815
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3184401028
Short name T451
Test name
Test status
Simulation time 5990927134 ps
CPU time 7.2 seconds
Started Jun 13 02:48:14 PM PDT 24
Finished Jun 13 02:48:37 PM PDT 24
Peak memory 225068 kb
Host smart-1c369f9d-15b3-413c-bb69-e723ba4a8365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184401028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3184401028
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.843646453
Short name T882
Test name
Test status
Simulation time 505636882 ps
CPU time 4.07 seconds
Started Jun 13 02:48:14 PM PDT 24
Finished Jun 13 02:48:33 PM PDT 24
Peak memory 224824 kb
Host smart-15721b26-abe6-4bf8-9efd-5cffc623b520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843646453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.843646453
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3394168082
Short name T542
Test name
Test status
Simulation time 249659395 ps
CPU time 5 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:48:56 PM PDT 24
Peak memory 219048 kb
Host smart-db40a4c8-5781-4ed3-9eee-ae0c501aedb7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394168082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3394168082
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2552230111
Short name T21
Test name
Test status
Simulation time 241763169 ps
CPU time 1.09 seconds
Started Jun 13 02:48:24 PM PDT 24
Finished Jun 13 02:48:41 PM PDT 24
Peak memory 235664 kb
Host smart-5f1ee199-6cad-485f-b749-117d3caa11f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552230111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2552230111
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3579696843
Short name T602
Test name
Test status
Simulation time 80760601767 ps
CPU time 710.37 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 03:00:26 PM PDT 24
Peak memory 249780 kb
Host smart-021ab089-99d2-4aa6-9355-54d26534820b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579696843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3579696843
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2420260454
Short name T625
Test name
Test status
Simulation time 11592408245 ps
CPU time 26.64 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 216680 kb
Host smart-84ed1c7c-83db-45eb-ab47-680040448a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420260454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2420260454
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.934825692
Short name T497
Test name
Test status
Simulation time 93350901973 ps
CPU time 11.95 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:48:47 PM PDT 24
Peak memory 216620 kb
Host smart-91255e51-25bd-4404-a9b6-5e759b1594c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934825692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.934825692
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2060289759
Short name T654
Test name
Test status
Simulation time 25220189 ps
CPU time 0.77 seconds
Started Jun 13 02:48:19 PM PDT 24
Finished Jun 13 02:48:36 PM PDT 24
Peak memory 206176 kb
Host smart-dda79fd7-f6c4-413d-b9af-4877fe386102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060289759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2060289759
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3853592781
Short name T505
Test name
Test status
Simulation time 14225019 ps
CPU time 0.79 seconds
Started Jun 13 02:48:18 PM PDT 24
Finished Jun 13 02:48:34 PM PDT 24
Peak memory 206168 kb
Host smart-738d9ab5-cc37-416a-8ae1-296f0a18c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853592781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3853592781
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.382305706
Short name T783
Test name
Test status
Simulation time 942697064 ps
CPU time 2.53 seconds
Started Jun 13 02:48:26 PM PDT 24
Finished Jun 13 02:48:44 PM PDT 24
Peak memory 224596 kb
Host smart-1db341c4-c5a8-4226-9679-79e5cc585a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382305706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.382305706
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3040015969
Short name T547
Test name
Test status
Simulation time 45728301 ps
CPU time 0.69 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 205664 kb
Host smart-b71368c7-ef06-4dfb-9788-78d12b1100b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040015969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3040015969
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3229036007
Short name T914
Test name
Test status
Simulation time 5520643105 ps
CPU time 9.1 seconds
Started Jun 13 02:49:49 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 224872 kb
Host smart-860c5124-5a0f-4d30-b9d5-88aaf72fa445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229036007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3229036007
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2132919173
Short name T403
Test name
Test status
Simulation time 63951436 ps
CPU time 0.82 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 206792 kb
Host smart-8b745ee7-8aa7-448c-b260-3d0dc5a2ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132919173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2132919173
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1830817824
Short name T619
Test name
Test status
Simulation time 2047611402 ps
CPU time 34.05 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:36 PM PDT 24
Peak memory 257660 kb
Host smart-05bffbd2-3c0d-4991-9858-c9f228cc386a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830817824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1830817824
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1060144033
Short name T571
Test name
Test status
Simulation time 58609559541 ps
CPU time 39.47 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:50:43 PM PDT 24
Peak memory 241372 kb
Host smart-9300b2cd-a78d-4c1f-bd8f-7e7b7ce54a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060144033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1060144033
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3985099454
Short name T644
Test name
Test status
Simulation time 102471526 ps
CPU time 5.09 seconds
Started Jun 13 02:49:50 PM PDT 24
Finished Jun 13 02:50:11 PM PDT 24
Peak memory 233060 kb
Host smart-c96e6ca7-4b90-4dce-9b78-a1e62ecd41d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985099454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3985099454
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3439956501
Short name T292
Test name
Test status
Simulation time 161944804 ps
CPU time 3.76 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:07 PM PDT 24
Peak memory 224872 kb
Host smart-cb6daf52-283b-4157-9e65-2670eef9dff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439956501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3439956501
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1021048608
Short name T580
Test name
Test status
Simulation time 3839520583 ps
CPU time 15.7 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:50:19 PM PDT 24
Peak memory 224748 kb
Host smart-078ec6bc-529c-489e-b3dd-fa4235981959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021048608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1021048608
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1578937103
Short name T455
Test name
Test status
Simulation time 34123238 ps
CPU time 2.17 seconds
Started Jun 13 02:49:45 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 224264 kb
Host smart-bce0e901-8854-4b17-bc52-e855b9b8d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578937103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1578937103
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2238704673
Short name T973
Test name
Test status
Simulation time 9550052412 ps
CPU time 21.25 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 233124 kb
Host smart-53c40bb3-5df2-499c-81f2-17339392f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238704673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2238704673
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4095499948
Short name T585
Test name
Test status
Simulation time 1019132914 ps
CPU time 4.63 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 222788 kb
Host smart-fc061560-19d8-4d38-8896-e96db894911a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4095499948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4095499948
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1299389627
Short name T261
Test name
Test status
Simulation time 14611454588 ps
CPU time 234.07 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:54:01 PM PDT 24
Peak memory 264844 kb
Host smart-8cee5100-a880-4572-a95d-a79b7d133088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299389627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1299389627
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4185353583
Short name T393
Test name
Test status
Simulation time 1562238239 ps
CPU time 8.14 seconds
Started Jun 13 02:49:50 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 216596 kb
Host smart-1bdc436d-e7ee-403f-b156-3a49a5a2572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185353583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4185353583
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4061729173
Short name T740
Test name
Test status
Simulation time 298660726 ps
CPU time 1.37 seconds
Started Jun 13 03:01:30 PM PDT 24
Finished Jun 13 03:01:32 PM PDT 24
Peak memory 208008 kb
Host smart-d1454043-eff2-45fb-9423-d79f0d25a04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061729173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4061729173
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4097501455
Short name T702
Test name
Test status
Simulation time 464877665 ps
CPU time 3.97 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:50:07 PM PDT 24
Peak memory 216592 kb
Host smart-719acc2c-fd7d-4f97-adea-bfe461ab35ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097501455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4097501455
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2769688200
Short name T861
Test name
Test status
Simulation time 225202268 ps
CPU time 1.03 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:50:05 PM PDT 24
Peak memory 206548 kb
Host smart-b436fe57-0c58-4853-be8e-da9595fabda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769688200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2769688200
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.786587855
Short name T947
Test name
Test status
Simulation time 3670126522 ps
CPU time 12.37 seconds
Started Jun 13 02:49:58 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 233052 kb
Host smart-2900ce14-4a73-4da4-817b-d73725b1a5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786587855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.786587855
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.688781391
Short name T336
Test name
Test status
Simulation time 24382485 ps
CPU time 0.73 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:09 PM PDT 24
Peak memory 205664 kb
Host smart-890bbcc9-dba7-4f70-ac7a-07f83d1e14c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688781391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.688781391
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4148396153
Short name T862
Test name
Test status
Simulation time 604468423 ps
CPU time 5.7 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:14 PM PDT 24
Peak memory 233024 kb
Host smart-e6b2d321-1b31-481c-b763-5c3fbcebfb71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148396153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4148396153
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2165970299
Short name T751
Test name
Test status
Simulation time 37018748 ps
CPU time 0.76 seconds
Started Jun 13 02:49:48 PM PDT 24
Finished Jun 13 02:50:05 PM PDT 24
Peak memory 207112 kb
Host smart-81a08e84-9567-4612-aee7-b412eb2174f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165970299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2165970299
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1605169389
Short name T431
Test name
Test status
Simulation time 2422734031 ps
CPU time 11.08 seconds
Started Jun 13 02:49:52 PM PDT 24
Finished Jun 13 02:50:18 PM PDT 24
Peak memory 241320 kb
Host smart-9355d7cc-1b66-4492-90ec-1f8819c31cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605169389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1605169389
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1800447648
Short name T896
Test name
Test status
Simulation time 76729947966 ps
CPU time 230.88 seconds
Started Jun 13 02:54:30 PM PDT 24
Finished Jun 13 02:58:21 PM PDT 24
Peak memory 249584 kb
Host smart-8dc03e9c-0e22-4096-b440-572ec9846cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800447648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1800447648
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1321118445
Short name T942
Test name
Test status
Simulation time 3943132020 ps
CPU time 57.31 seconds
Started Jun 13 02:49:54 PM PDT 24
Finished Jun 13 02:51:05 PM PDT 24
Peak memory 249776 kb
Host smart-12cf81cf-2029-45be-954f-8d19e9b534dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321118445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1321118445
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1323152284
Short name T690
Test name
Test status
Simulation time 394808103 ps
CPU time 9.75 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:17 PM PDT 24
Peak memory 224852 kb
Host smart-1e4b631e-947d-4787-833b-352a647189fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323152284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1323152284
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4244437485
Short name T520
Test name
Test status
Simulation time 707840863 ps
CPU time 7.41 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:10 PM PDT 24
Peak memory 224692 kb
Host smart-d3e37246-b002-4abe-bd51-82fcae7d0832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244437485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4244437485
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2799577732
Short name T207
Test name
Test status
Simulation time 1426996431 ps
CPU time 5.79 seconds
Started Jun 13 02:49:52 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 224816 kb
Host smart-6c934220-c92c-4aa0-b162-8a2a9d23cfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799577732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2799577732
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1398854245
Short name T686
Test name
Test status
Simulation time 2112652424 ps
CPU time 6.17 seconds
Started Jun 13 02:49:50 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 233052 kb
Host smart-cec88d31-a6ec-4363-b3fb-f13eb7bd0d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398854245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1398854245
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3688740426
Short name T791
Test name
Test status
Simulation time 3283232619 ps
CPU time 4.8 seconds
Started Jun 13 02:49:49 PM PDT 24
Finished Jun 13 02:50:09 PM PDT 24
Peak memory 233116 kb
Host smart-4a030b6e-2b99-410e-8dde-61c8f6059be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688740426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3688740426
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4143178473
Short name T645
Test name
Test status
Simulation time 80113860 ps
CPU time 3.79 seconds
Started Jun 13 02:49:59 PM PDT 24
Finished Jun 13 02:50:15 PM PDT 24
Peak memory 223196 kb
Host smart-e49bc654-bf25-47ff-956c-a20ab364afd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4143178473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4143178473
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1056884268
Short name T878
Test name
Test status
Simulation time 7372643924 ps
CPU time 121.42 seconds
Started Jun 13 02:49:54 PM PDT 24
Finished Jun 13 02:52:10 PM PDT 24
Peak memory 256740 kb
Host smart-ccaa6140-ff48-40d0-98e1-89f46eee3410
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056884268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1056884268
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3551067654
Short name T733
Test name
Test status
Simulation time 2318793182 ps
CPU time 21.89 seconds
Started Jun 13 02:49:50 PM PDT 24
Finished Jun 13 02:50:28 PM PDT 24
Peak memory 216676 kb
Host smart-e3e5d077-8de5-4ce2-b74d-a654f6b9f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551067654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3551067654
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3236305092
Short name T745
Test name
Test status
Simulation time 1248257366 ps
CPU time 4.48 seconds
Started Jun 13 02:49:46 PM PDT 24
Finished Jun 13 02:50:06 PM PDT 24
Peak memory 216496 kb
Host smart-a5d2c2b7-50de-458a-9991-73d1362a47fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236305092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3236305092
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3523775339
Short name T352
Test name
Test status
Simulation time 110016688 ps
CPU time 1.72 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:09 PM PDT 24
Peak memory 215976 kb
Host smart-2b9fcd33-fedb-4094-93c5-c015a0c1a6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523775339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3523775339
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3855668308
Short name T84
Test name
Test status
Simulation time 23219371 ps
CPU time 0.76 seconds
Started Jun 13 02:49:47 PM PDT 24
Finished Jun 13 02:50:04 PM PDT 24
Peak memory 206172 kb
Host smart-15315a69-033a-42c6-95ec-3956e8857612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855668308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3855668308
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.287954171
Short name T203
Test name
Test status
Simulation time 877201743 ps
CPU time 7.45 seconds
Started Jun 13 02:49:55 PM PDT 24
Finished Jun 13 02:50:16 PM PDT 24
Peak memory 238392 kb
Host smart-0a2d9e8b-d92d-4a38-b66d-1c5f64d2258d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287954171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.287954171
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2286501369
Short name T351
Test name
Test status
Simulation time 38834590 ps
CPU time 0.72 seconds
Started Jun 13 02:50:00 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 205676 kb
Host smart-59675adb-8f69-44c2-b032-ef6d1899108d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286501369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2286501369
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2243744922
Short name T417
Test name
Test status
Simulation time 1431565862 ps
CPU time 5.72 seconds
Started Jun 13 02:50:04 PM PDT 24
Finished Jun 13 02:50:22 PM PDT 24
Peak memory 224808 kb
Host smart-223f2150-d56d-4df9-8af5-a3080f0cde71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243744922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2243744922
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2466874666
Short name T410
Test name
Test status
Simulation time 41645730 ps
CPU time 0.78 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:09 PM PDT 24
Peak memory 206784 kb
Host smart-6e48bfd9-e967-42e0-800a-10c0eb8f84de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466874666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2466874666
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.706771382
Short name T921
Test name
Test status
Simulation time 12945421 ps
CPU time 0.76 seconds
Started Jun 13 02:49:59 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 216208 kb
Host smart-f76127ff-9626-4978-8640-a2badb2f9184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706771382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.706771382
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.914024808
Short name T955
Test name
Test status
Simulation time 2657494546 ps
CPU time 14.53 seconds
Started Jun 13 02:50:02 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 217716 kb
Host smart-269714a5-e0c1-47b3-8da9-0ea918831ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914024808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.914024808
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.879647812
Short name T239
Test name
Test status
Simulation time 438248186512 ps
CPU time 384.64 seconds
Started Jun 13 02:50:05 PM PDT 24
Finished Jun 13 02:56:41 PM PDT 24
Peak memory 268192 kb
Host smart-fa9d0c0f-ea78-4acd-87e9-a422d9c880a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879647812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.879647812
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3772827749
Short name T719
Test name
Test status
Simulation time 1223644774 ps
CPU time 11.37 seconds
Started Jun 13 02:49:59 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 224808 kb
Host smart-7800abd1-b4cb-49c2-8086-b6b0b4d84788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772827749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3772827749
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2347794278
Short name T208
Test name
Test status
Simulation time 2457254893 ps
CPU time 22.91 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:30 PM PDT 24
Peak memory 224916 kb
Host smart-35665773-6378-4628-bba6-dfd9be0bb054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347794278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2347794278
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1582807910
Short name T911
Test name
Test status
Simulation time 2779434722 ps
CPU time 8.15 seconds
Started Jun 13 02:49:53 PM PDT 24
Finished Jun 13 02:50:16 PM PDT 24
Peak memory 224904 kb
Host smart-441dfb70-322a-49a3-b151-37a546e3264b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582807910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1582807910
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1769558063
Short name T945
Test name
Test status
Simulation time 400782757 ps
CPU time 2.5 seconds
Started Jun 13 02:49:55 PM PDT 24
Finished Jun 13 02:50:11 PM PDT 24
Peak memory 224740 kb
Host smart-4c2a5e4c-2fb1-4bc2-8b65-b0b7b70b39de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769558063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1769558063
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1608004290
Short name T857
Test name
Test status
Simulation time 1439481934 ps
CPU time 3.24 seconds
Started Jun 13 02:49:56 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 224856 kb
Host smart-83313883-8526-4dfc-90a1-72b8239d4006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608004290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1608004290
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1306765108
Short name T132
Test name
Test status
Simulation time 353334603 ps
CPU time 3.79 seconds
Started Jun 13 02:50:04 PM PDT 24
Finished Jun 13 02:50:20 PM PDT 24
Peak memory 222904 kb
Host smart-50433b72-f232-4fc0-923a-3b60d6f4eca0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1306765108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1306765108
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3451986808
Short name T154
Test name
Test status
Simulation time 52746693310 ps
CPU time 59.41 seconds
Started Jun 13 02:49:58 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 248628 kb
Host smart-e41533c0-f763-4ee1-bd79-7eb03129290d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451986808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3451986808
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.714151923
Short name T698
Test name
Test status
Simulation time 636836308 ps
CPU time 3.57 seconds
Started Jun 13 02:49:56 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 216576 kb
Host smart-2eaf31be-d0e8-4794-b6a1-bbf87f677b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714151923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.714151923
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.8567076
Short name T819
Test name
Test status
Simulation time 703576002 ps
CPU time 3.23 seconds
Started Jun 13 02:49:56 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 216576 kb
Host smart-1720a858-e5cf-4d16-8858-cd7f34c696aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8567076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.8567076
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1678994938
Short name T642
Test name
Test status
Simulation time 348802310 ps
CPU time 4.12 seconds
Started Jun 13 02:49:55 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 216604 kb
Host smart-15ae465f-d02b-4ff3-856c-26ecdc823a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678994938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1678994938
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3963266388
Short name T639
Test name
Test status
Simulation time 68661319 ps
CPU time 0.83 seconds
Started Jun 13 02:49:58 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 206180 kb
Host smart-1fb5e28a-1bd2-4ccd-874d-2a111ea76e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963266388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3963266388
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1826588513
Short name T694
Test name
Test status
Simulation time 226212488 ps
CPU time 2.82 seconds
Started Jun 13 02:49:52 PM PDT 24
Finished Jun 13 02:50:10 PM PDT 24
Peak memory 224796 kb
Host smart-9dfc4671-3971-445a-ae1e-e76ab3bdcbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826588513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1826588513
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1833792750
Short name T390
Test name
Test status
Simulation time 37567726 ps
CPU time 0.75 seconds
Started Jun 13 02:50:00 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 206008 kb
Host smart-53148bc9-9100-4208-9786-6a79eb661799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833792750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1833792750
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1193481010
Short name T209
Test name
Test status
Simulation time 5992488686 ps
CPU time 14.32 seconds
Started Jun 13 02:49:58 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 224928 kb
Host smart-3c9c9ed7-56c9-439e-b38a-68e259c21abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193481010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1193481010
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1747176472
Short name T948
Test name
Test status
Simulation time 65350372 ps
CPU time 0.76 seconds
Started Jun 13 02:50:02 PM PDT 24
Finished Jun 13 02:50:15 PM PDT 24
Peak memory 205760 kb
Host smart-b6a6e47b-f7a8-4055-b687-320ca7239b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747176472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1747176472
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.134523090
Short name T250
Test name
Test status
Simulation time 159411831446 ps
CPU time 172.88 seconds
Started Jun 13 02:49:59 PM PDT 24
Finished Jun 13 02:53:05 PM PDT 24
Peak memory 265720 kb
Host smart-b6fc7065-147b-4e7d-8126-8f524ee24af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134523090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.134523090
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.687713092
Short name T824
Test name
Test status
Simulation time 7395627446 ps
CPU time 33.45 seconds
Started Jun 13 02:49:59 PM PDT 24
Finished Jun 13 02:50:45 PM PDT 24
Peak memory 235984 kb
Host smart-9715d4bc-d5f8-4d4c-92c3-0e18b6dbf9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687713092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.687713092
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3335074968
Short name T305
Test name
Test status
Simulation time 36367585402 ps
CPU time 152.95 seconds
Started Jun 13 02:50:00 PM PDT 24
Finished Jun 13 02:52:46 PM PDT 24
Peak memory 225256 kb
Host smart-5aa41a2d-ed49-47cf-a172-24b6fa4acaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335074968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3335074968
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1459425632
Short name T313
Test name
Test status
Simulation time 487054548 ps
CPU time 12.36 seconds
Started Jun 13 02:49:58 PM PDT 24
Finished Jun 13 02:50:24 PM PDT 24
Peak memory 233212 kb
Host smart-3c617f0c-cc26-4c34-acd5-4fcf71eead76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459425632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1459425632
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.955158886
Short name T291
Test name
Test status
Simulation time 345472887 ps
CPU time 5.77 seconds
Started Jun 13 02:50:00 PM PDT 24
Finished Jun 13 02:50:19 PM PDT 24
Peak memory 233092 kb
Host smart-66a95b62-110f-4793-83b7-d1fe7b65935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955158886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.955158886
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3612587277
Short name T212
Test name
Test status
Simulation time 8396473341 ps
CPU time 52.07 seconds
Started Jun 13 02:50:00 PM PDT 24
Finished Jun 13 02:51:05 PM PDT 24
Peak memory 233096 kb
Host smart-8ec32293-fdbf-441f-8838-7eb60008fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612587277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3612587277
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3025668753
Short name T4
Test name
Test status
Simulation time 54869859453 ps
CPU time 16.57 seconds
Started Jun 13 02:50:01 PM PDT 24
Finished Jun 13 02:50:30 PM PDT 24
Peak memory 232764 kb
Host smart-04811568-3762-4953-97cd-891285db27c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025668753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3025668753
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1794016621
Short name T459
Test name
Test status
Simulation time 18948149053 ps
CPU time 7.02 seconds
Started Jun 13 02:50:04 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 224860 kb
Host smart-7f21d911-8aa5-489c-8988-d6eb8efb8cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794016621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1794016621
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2061361539
Short name T761
Test name
Test status
Simulation time 2725917014 ps
CPU time 14.88 seconds
Started Jun 13 02:50:01 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 219068 kb
Host smart-1db5545f-3727-496a-a4fa-f0ee7990ba96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2061361539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2061361539
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2182639494
Short name T152
Test name
Test status
Simulation time 31033523592 ps
CPU time 104.74 seconds
Started Jun 13 02:50:00 PM PDT 24
Finished Jun 13 02:51:57 PM PDT 24
Peak memory 255408 kb
Host smart-8cd7d080-1f1d-4801-9b73-f2a7a710bc97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182639494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2182639494
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.216872986
Short name T572
Test name
Test status
Simulation time 1528890341 ps
CPU time 21.07 seconds
Started Jun 13 02:49:59 PM PDT 24
Finished Jun 13 02:50:33 PM PDT 24
Peak memory 219584 kb
Host smart-ebd1ed11-8027-44f2-b2ad-a7386a8d2482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216872986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.216872986
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3619732221
Short name T932
Test name
Test status
Simulation time 35363558019 ps
CPU time 19.69 seconds
Started Jun 13 02:50:00 PM PDT 24
Finished Jun 13 02:50:32 PM PDT 24
Peak memory 216664 kb
Host smart-996d047c-4019-43e3-bd69-c84de2a19284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619732221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3619732221
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3961619718
Short name T521
Test name
Test status
Simulation time 81836666 ps
CPU time 1.19 seconds
Started Jun 13 02:50:01 PM PDT 24
Finished Jun 13 02:50:15 PM PDT 24
Peak memory 216600 kb
Host smart-5f3aa9f3-77b6-40cc-a9bc-83d0101a7fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961619718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3961619718
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.486764461
Short name T617
Test name
Test status
Simulation time 90750481 ps
CPU time 0.97 seconds
Started Jun 13 02:50:01 PM PDT 24
Finished Jun 13 02:50:15 PM PDT 24
Peak memory 206116 kb
Host smart-45574996-bc29-4449-829f-6022ebd8d841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486764461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.486764461
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1009424276
Short name T15
Test name
Test status
Simulation time 9452052349 ps
CPU time 11.66 seconds
Started Jun 13 02:49:59 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 224944 kb
Host smart-035d8897-9367-4cfa-8f4a-41e35c712f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009424276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1009424276
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.385734756
Short name T338
Test name
Test status
Simulation time 81593505 ps
CPU time 0.73 seconds
Started Jun 13 02:50:08 PM PDT 24
Finished Jun 13 02:50:20 PM PDT 24
Peak memory 205120 kb
Host smart-164d4178-c3b2-468b-a6a6-1a053faf4b0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385734756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.385734756
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1099929941
Short name T270
Test name
Test status
Simulation time 1432428849 ps
CPU time 5.63 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:50:24 PM PDT 24
Peak memory 232984 kb
Host smart-8097f78b-9c4b-4a3d-a2ab-a845fd434b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099929941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1099929941
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3450330819
Short name T411
Test name
Test status
Simulation time 32784571 ps
CPU time 0.81 seconds
Started Jun 13 02:49:58 PM PDT 24
Finished Jun 13 02:50:12 PM PDT 24
Peak memory 207060 kb
Host smart-0414a8ff-4d5c-4111-9246-4f7c291bbf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450330819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3450330819
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2834656187
Short name T228
Test name
Test status
Simulation time 38234883443 ps
CPU time 203.5 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:53:41 PM PDT 24
Peak memory 266924 kb
Host smart-fa8c8374-bdcc-4d1b-bee7-56c104ef6a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834656187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2834656187
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2301964717
Short name T474
Test name
Test status
Simulation time 16764427536 ps
CPU time 82.07 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:51:40 PM PDT 24
Peak memory 251800 kb
Host smart-d36f1407-c43b-4a05-9e8b-4a48ab13ab3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301964717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2301964717
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.649659405
Short name T889
Test name
Test status
Simulation time 47588484126 ps
CPU time 206.25 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:53:46 PM PDT 24
Peak memory 249624 kb
Host smart-aee6e1a6-8b1d-4467-ade4-3878ef119244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649659405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.649659405
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.459994471
Short name T423
Test name
Test status
Simulation time 113939469 ps
CPU time 4.89 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:50:24 PM PDT 24
Peak memory 241148 kb
Host smart-eba3a52b-37e8-4ab6-a2eb-6a4fc20f5942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459994471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.459994471
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3989088192
Short name T304
Test name
Test status
Simulation time 591079545 ps
CPU time 3.68 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:21 PM PDT 24
Peak memory 224852 kb
Host smart-3403d4d2-eeca-4067-aeb7-a2a54510e829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989088192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3989088192
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3929056390
Short name T606
Test name
Test status
Simulation time 16155902158 ps
CPU time 21.26 seconds
Started Jun 13 02:50:05 PM PDT 24
Finished Jun 13 02:50:38 PM PDT 24
Peak memory 223900 kb
Host smart-fa1cb269-eca0-4b8b-b44b-70bd36f67341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929056390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3929056390
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3854747862
Short name T566
Test name
Test status
Simulation time 37358900 ps
CPU time 2.33 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:20 PM PDT 24
Peak memory 233060 kb
Host smart-929732ec-d5a7-412d-b1fa-c2739fface42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854747862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3854747862
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1043237096
Short name T691
Test name
Test status
Simulation time 263252519 ps
CPU time 3.74 seconds
Started Jun 13 02:50:05 PM PDT 24
Finished Jun 13 02:50:20 PM PDT 24
Peak memory 224816 kb
Host smart-9ad91bd8-371e-4e3e-9a61-8106ed9c6667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043237096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1043237096
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1854122736
Short name T389
Test name
Test status
Simulation time 155589554 ps
CPU time 3.54 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:21 PM PDT 24
Peak memory 220604 kb
Host smart-9e393a1b-fbb0-49e8-a3f0-67daa1d1a977
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1854122736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1854122736
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2672153868
Short name T318
Test name
Test status
Simulation time 13083729118 ps
CPU time 35.6 seconds
Started Jun 13 02:50:08 PM PDT 24
Finished Jun 13 02:50:56 PM PDT 24
Peak memory 216636 kb
Host smart-12c1087d-14c1-4bc5-a852-3232c69cba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672153868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2672153868
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4154991952
Short name T496
Test name
Test status
Simulation time 12391929831 ps
CPU time 16 seconds
Started Jun 13 02:49:58 PM PDT 24
Finished Jun 13 02:50:27 PM PDT 24
Peak memory 216604 kb
Host smart-0caa811d-cc92-4fed-bd90-a19499c1700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154991952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4154991952
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2089228353
Short name T974
Test name
Test status
Simulation time 281475289 ps
CPU time 3.41 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:21 PM PDT 24
Peak memory 216640 kb
Host smart-600c6553-f398-4caa-990c-18f185cc8a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089228353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2089228353
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3048558959
Short name T391
Test name
Test status
Simulation time 13047519 ps
CPU time 0.7 seconds
Started Jun 13 02:50:11 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 205804 kb
Host smart-a40097cd-f590-4bf8-9dc9-bf6ef42327b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048558959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3048558959
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1609374951
Short name T197
Test name
Test status
Simulation time 1517203305 ps
CPU time 8.74 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:26 PM PDT 24
Peak memory 232928 kb
Host smart-457f15e4-ee87-42c5-83f4-e56957aa294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609374951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1609374951
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.774337312
Short name T405
Test name
Test status
Simulation time 30779018 ps
CPU time 0.73 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:18 PM PDT 24
Peak memory 206004 kb
Host smart-025bc966-c0c1-4862-95fa-c8b9e557f4d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774337312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.774337312
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3213906743
Short name T297
Test name
Test status
Simulation time 5334030198 ps
CPU time 12.31 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:50:31 PM PDT 24
Peak memory 233108 kb
Host smart-c07d6792-87b2-4f90-9b33-45f9bfdc346f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213906743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3213906743
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3930455326
Short name T970
Test name
Test status
Simulation time 15520209 ps
CPU time 0.82 seconds
Started Jun 13 02:50:05 PM PDT 24
Finished Jun 13 02:50:18 PM PDT 24
Peak memory 207108 kb
Host smart-fac5ebf3-9457-405b-bf98-dce1b33fc0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930455326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3930455326
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2562339191
Short name T156
Test name
Test status
Simulation time 33848342 ps
CPU time 0.77 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:50:19 PM PDT 24
Peak memory 216260 kb
Host smart-3381c296-a6a1-4c17-96d5-2ca90dc35072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562339191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2562339191
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1701794807
Short name T51
Test name
Test status
Simulation time 38812400117 ps
CPU time 365.49 seconds
Started Jun 13 02:50:05 PM PDT 24
Finished Jun 13 02:56:22 PM PDT 24
Peak memory 271176 kb
Host smart-d85c76fe-4321-4d86-9373-29e585656927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701794807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1701794807
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3946290013
Short name T637
Test name
Test status
Simulation time 7353977525 ps
CPU time 41.78 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:51:00 PM PDT 24
Peak memory 237216 kb
Host smart-38d62563-cd1e-415e-9ec3-d20f1a53522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946290013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3946290013
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1110855631
Short name T281
Test name
Test status
Simulation time 4166703735 ps
CPU time 57.14 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:51:15 PM PDT 24
Peak memory 251284 kb
Host smart-bf45e261-6dfb-4829-b919-1cc4b459f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110855631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1110855631
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2928304115
Short name T552
Test name
Test status
Simulation time 4970806456 ps
CPU time 14.55 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:50:33 PM PDT 24
Peak memory 233120 kb
Host smart-3dbfa0d2-3126-4620-82dc-b1dea9fde39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928304115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2928304115
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3967785192
Short name T530
Test name
Test status
Simulation time 12681395796 ps
CPU time 99.16 seconds
Started Jun 13 02:50:05 PM PDT 24
Finished Jun 13 02:51:57 PM PDT 24
Peak memory 234388 kb
Host smart-48696f4e-b504-471b-82b5-cb5664b0f070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967785192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3967785192
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.613068385
Short name T870
Test name
Test status
Simulation time 1693953455 ps
CPU time 3.77 seconds
Started Jun 13 02:50:04 PM PDT 24
Finished Jun 13 02:50:20 PM PDT 24
Peak memory 224860 kb
Host smart-ba64c6dc-c24f-4f16-8d51-99199039e50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613068385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.613068385
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2234778329
Short name T678
Test name
Test status
Simulation time 330722472 ps
CPU time 4.27 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 224748 kb
Host smart-7449b0a8-3b9d-45bc-8c61-81412329fdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234778329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2234778329
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1402578124
Short name T621
Test name
Test status
Simulation time 309519946 ps
CPU time 5.45 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 222724 kb
Host smart-523187f8-9e94-47e7-bd55-7836a6ca8e28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1402578124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1402578124
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3586657579
Short name T330
Test name
Test status
Simulation time 44580148 ps
CPU time 0.7 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:19 PM PDT 24
Peak memory 205932 kb
Host smart-3867bb08-29bd-41a1-9f5e-7055888c16a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586657579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3586657579
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1075370079
Short name T388
Test name
Test status
Simulation time 30179915550 ps
CPU time 11.46 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 216620 kb
Host smart-5539ce90-307b-4fb7-954d-d0baad5bf7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075370079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1075370079
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3798293935
Short name T838
Test name
Test status
Simulation time 959764115 ps
CPU time 2.53 seconds
Started Jun 13 02:50:07 PM PDT 24
Finished Jun 13 02:50:22 PM PDT 24
Peak memory 216596 kb
Host smart-3fa93786-b1bd-4ae3-b386-3a4543a55e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798293935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3798293935
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.927730813
Short name T804
Test name
Test status
Simulation time 112982794 ps
CPU time 0.83 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:19 PM PDT 24
Peak memory 206172 kb
Host smart-0ffb66d7-bcb6-442d-8098-38ae5afbfbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927730813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.927730813
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3326868720
Short name T303
Test name
Test status
Simulation time 692062347 ps
CPU time 3.26 seconds
Started Jun 13 02:50:08 PM PDT 24
Finished Jun 13 02:50:24 PM PDT 24
Peak memory 224856 kb
Host smart-d22ccd32-f716-40dc-b38d-1d19a995957d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326868720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3326868720
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2595566227
Short name T722
Test name
Test status
Simulation time 33804760 ps
CPU time 0.72 seconds
Started Jun 13 02:50:12 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 205120 kb
Host smart-2690b5e6-04c4-40ea-bbd3-9d6bbb4b3d8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595566227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2595566227
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.430977548
Short name T737
Test name
Test status
Simulation time 2677339499 ps
CPU time 24.27 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:50:51 PM PDT 24
Peak memory 233100 kb
Host smart-55b95a19-c7b5-44bc-a58c-a8f68a890ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430977548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.430977548
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1385420928
Short name T392
Test name
Test status
Simulation time 28473758 ps
CPU time 0.79 seconds
Started Jun 13 02:50:06 PM PDT 24
Finished Jun 13 02:50:19 PM PDT 24
Peak memory 205780 kb
Host smart-d7bf545e-4343-4f75-9e58-f3083111e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385420928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1385420928
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2520864771
Short name T168
Test name
Test status
Simulation time 98174243857 ps
CPU time 81.95 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:51:49 PM PDT 24
Peak memory 250024 kb
Host smart-780e5ede-478e-4c96-8ec9-8b3ca2893e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520864771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2520864771
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.266828969
Short name T605
Test name
Test status
Simulation time 255387430955 ps
CPU time 314.51 seconds
Started Jun 13 02:50:15 PM PDT 24
Finished Jun 13 02:55:40 PM PDT 24
Peak memory 255888 kb
Host smart-4dc2b692-0fd0-4b84-a3fb-02fd1d0350ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266828969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.266828969
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.339378599
Short name T170
Test name
Test status
Simulation time 2595668001 ps
CPU time 41.61 seconds
Started Jun 13 02:50:12 PM PDT 24
Finished Jun 13 02:51:05 PM PDT 24
Peak memory 250732 kb
Host smart-452492c5-3221-48db-bdb7-78e5cf678218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339378599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.339378599
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4252190180
Short name T839
Test name
Test status
Simulation time 7602182000 ps
CPU time 27.48 seconds
Started Jun 13 02:50:13 PM PDT 24
Finished Jun 13 02:50:51 PM PDT 24
Peak memory 224916 kb
Host smart-f431d103-9a91-458f-86c1-f8f61598dee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252190180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4252190180
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2187770379
Short name T887
Test name
Test status
Simulation time 1540206677 ps
CPU time 7.54 seconds
Started Jun 13 02:50:13 PM PDT 24
Finished Jun 13 02:50:32 PM PDT 24
Peak memory 233016 kb
Host smart-ca5c1fdb-5795-4d9e-bda1-01c68f1aa67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187770379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2187770379
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4095746343
Short name T864
Test name
Test status
Simulation time 13152697876 ps
CPU time 32.69 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:50:59 PM PDT 24
Peak memory 233116 kb
Host smart-108355b6-331a-47ec-8c39-1a5b93da26f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095746343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4095746343
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1849478215
Short name T238
Test name
Test status
Simulation time 5829880250 ps
CPU time 19.39 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:47 PM PDT 24
Peak memory 233124 kb
Host smart-02dbe6d8-dde3-476d-b5c9-84a1902300ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849478215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1849478215
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.909847498
Short name T797
Test name
Test status
Simulation time 333160180 ps
CPU time 6.03 seconds
Started Jun 13 02:50:14 PM PDT 24
Finished Jun 13 02:50:32 PM PDT 24
Peak memory 224880 kb
Host smart-55ae5072-8f23-4fe2-b462-6a4450166119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909847498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.909847498
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.332066343
Short name T464
Test name
Test status
Simulation time 130361386 ps
CPU time 3.38 seconds
Started Jun 13 02:50:13 PM PDT 24
Finished Jun 13 02:50:27 PM PDT 24
Peak memory 219528 kb
Host smart-71e4d67e-7994-49a1-8f39-558ddefbe0c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=332066343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.332066343
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4032030163
Short name T893
Test name
Test status
Simulation time 75810010 ps
CPU time 1.14 seconds
Started Jun 13 02:50:14 PM PDT 24
Finished Jun 13 02:50:26 PM PDT 24
Peak memory 207116 kb
Host smart-ab51cba0-8ea4-42de-925b-ecfe58ec5ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032030163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4032030163
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.818626132
Short name T317
Test name
Test status
Simulation time 1577555914 ps
CPU time 15.37 seconds
Started Jun 13 02:50:15 PM PDT 24
Finished Jun 13 02:50:42 PM PDT 24
Peak memory 216672 kb
Host smart-64a50c18-931e-40ef-ae16-77f26bf44551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818626132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.818626132
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2256404268
Short name T23
Test name
Test status
Simulation time 1280817673 ps
CPU time 3.17 seconds
Started Jun 13 02:50:13 PM PDT 24
Finished Jun 13 02:50:28 PM PDT 24
Peak memory 216496 kb
Host smart-dee825e7-48ed-46f7-8a93-97fddf098933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256404268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2256404268
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.939259431
Short name T931
Test name
Test status
Simulation time 295744717 ps
CPU time 2.69 seconds
Started Jun 13 02:50:15 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 216800 kb
Host smart-a365f5d6-e17a-4b93-8eea-2e8a11a720cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939259431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.939259431
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.99885306
Short name T476
Test name
Test status
Simulation time 122625630 ps
CPU time 0.82 seconds
Started Jun 13 02:50:13 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 206176 kb
Host smart-ccd1e5be-bfc3-4c2c-bb0c-e798db5e98fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99885306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.99885306
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1513837757
Short name T450
Test name
Test status
Simulation time 7094423145 ps
CPU time 22.39 seconds
Started Jun 13 02:50:14 PM PDT 24
Finished Jun 13 02:50:48 PM PDT 24
Peak memory 233148 kb
Host smart-0a66e114-9b4d-4b45-91fd-edbd14fbe0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513837757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1513837757
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3675965692
Short name T825
Test name
Test status
Simulation time 103379899 ps
CPU time 0.69 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:50:28 PM PDT 24
Peak memory 205732 kb
Host smart-b63707fb-d5b2-41ff-bee2-7b67ba9df896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675965692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3675965692
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3857539819
Short name T538
Test name
Test status
Simulation time 159603702 ps
CPU time 2.57 seconds
Started Jun 13 02:50:15 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 218928 kb
Host smart-37e6189f-8ef2-4ee1-b80a-ec8b21557c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857539819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3857539819
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2643008548
Short name T331
Test name
Test status
Simulation time 21032905 ps
CPU time 0.78 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:50:28 PM PDT 24
Peak memory 206796 kb
Host smart-d44b5914-8f04-42f2-8440-d44d48186ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643008548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2643008548
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3211241677
Short name T293
Test name
Test status
Simulation time 10085228956 ps
CPU time 56.97 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:51:25 PM PDT 24
Peak memory 250792 kb
Host smart-16aecf37-9f5a-4a1d-815d-ad5cdfeb70ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211241677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3211241677
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1658285346
Short name T234
Test name
Test status
Simulation time 103847290698 ps
CPU time 448.97 seconds
Started Jun 13 02:50:19 PM PDT 24
Finished Jun 13 02:58:00 PM PDT 24
Peak memory 257696 kb
Host smart-655d7997-c7f9-4a70-b22e-35b4e9d7b21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658285346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1658285346
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.928352361
Short name T713
Test name
Test status
Simulation time 1853105300 ps
CPU time 4.73 seconds
Started Jun 13 02:50:12 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 224872 kb
Host smart-5afc16b4-d355-44e5-b4c8-2431febfe4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928352361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.928352361
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3581518516
Short name T695
Test name
Test status
Simulation time 856992012 ps
CPU time 10.02 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:50:40 PM PDT 24
Peak memory 224812 kb
Host smart-87e66085-1aa0-4668-9bef-242a6266a31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581518516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3581518516
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1500870652
Short name T569
Test name
Test status
Simulation time 2009114851 ps
CPU time 12.03 seconds
Started Jun 13 02:50:19 PM PDT 24
Finished Jun 13 02:50:42 PM PDT 24
Peak memory 233012 kb
Host smart-8c5de366-6d58-4ea1-aa39-7ab4fabd253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500870652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1500870652
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1713752983
Short name T180
Test name
Test status
Simulation time 25958857541 ps
CPU time 17.56 seconds
Started Jun 13 02:50:13 PM PDT 24
Finished Jun 13 02:50:42 PM PDT 24
Peak memory 233120 kb
Host smart-aefb3cbe-a033-4050-b789-f4251fad3c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713752983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1713752983
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.4186024209
Short name T874
Test name
Test status
Simulation time 1900440517 ps
CPU time 6.23 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:50:34 PM PDT 24
Peak memory 233056 kb
Host smart-1ad0f4a7-da81-4124-8a1b-ab6c28a469c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186024209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.4186024209
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1762223997
Short name T715
Test name
Test status
Simulation time 219715823 ps
CPU time 3.45 seconds
Started Jun 13 02:50:20 PM PDT 24
Finished Jun 13 02:50:35 PM PDT 24
Peak memory 220684 kb
Host smart-16472f1d-62ad-40ca-b039-3c7357a76460
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1762223997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1762223997
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2906069164
Short name T739
Test name
Test status
Simulation time 44282896859 ps
CPU time 151.04 seconds
Started Jun 13 02:50:14 PM PDT 24
Finished Jun 13 02:52:57 PM PDT 24
Peak memory 249608 kb
Host smart-e4f9002f-4bb9-4b73-91e1-4a07665ad8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906069164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2906069164
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1426653614
Short name T437
Test name
Test status
Simulation time 3906665366 ps
CPU time 26.27 seconds
Started Jun 13 02:50:15 PM PDT 24
Finished Jun 13 02:50:52 PM PDT 24
Peak memory 216632 kb
Host smart-857c775d-c1e3-4ab1-bc56-b0e13c05d7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426653614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1426653614
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2786714460
Short name T869
Test name
Test status
Simulation time 6372811170 ps
CPU time 14.94 seconds
Started Jun 13 02:50:14 PM PDT 24
Finished Jun 13 02:50:41 PM PDT 24
Peak memory 216684 kb
Host smart-e9b255be-17af-4dae-89c5-b243d4fe9c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786714460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2786714460
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1240361363
Short name T461
Test name
Test status
Simulation time 106070127 ps
CPU time 1.65 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 216556 kb
Host smart-163688b7-a4f7-4910-8d23-5f4cd3e56e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240361363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1240361363
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1364811676
Short name T478
Test name
Test status
Simulation time 20770615 ps
CPU time 0.83 seconds
Started Jun 13 02:50:12 PM PDT 24
Finished Jun 13 02:50:25 PM PDT 24
Peak memory 206160 kb
Host smart-94b57899-6904-4bd3-800b-228ccf154d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364811676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1364811676
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1909090607
Short name T308
Test name
Test status
Simulation time 31045544620 ps
CPU time 23.72 seconds
Started Jun 13 02:50:14 PM PDT 24
Finished Jun 13 02:50:48 PM PDT 24
Peak memory 232988 kb
Host smart-83c9ecd1-7419-4b7c-aa22-ee5213912662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909090607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1909090607
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2465048954
Short name T544
Test name
Test status
Simulation time 98954383 ps
CPU time 0.72 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 205100 kb
Host smart-b3e963a5-befc-4dfd-97c1-98c0f29dc148
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465048954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2465048954
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2942956456
Short name T817
Test name
Test status
Simulation time 1848944485 ps
CPU time 15.44 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:43 PM PDT 24
Peak memory 224828 kb
Host smart-97378950-b1c0-4087-9398-463fe3e1805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942956456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2942956456
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2267679736
Short name T395
Test name
Test status
Simulation time 102283353 ps
CPU time 0.78 seconds
Started Jun 13 02:50:15 PM PDT 24
Finished Jun 13 02:50:27 PM PDT 24
Peak memory 206100 kb
Host smart-841355fb-2824-49fd-948f-8196bab8a4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267679736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2267679736
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1384333822
Short name T494
Test name
Test status
Simulation time 43305619 ps
CPU time 0.77 seconds
Started Jun 13 02:50:19 PM PDT 24
Finished Jun 13 02:50:31 PM PDT 24
Peak memory 216252 kb
Host smart-f7ff04b0-7821-4bf3-9c16-2b46c3d0c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384333822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1384333822
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1130000483
Short name T258
Test name
Test status
Simulation time 34022659175 ps
CPU time 223.89 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:54:14 PM PDT 24
Peak memory 240036 kb
Host smart-0f59dc5b-e962-4b7c-8a6a-0aaa17d463e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130000483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1130000483
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2690621673
Short name T41
Test name
Test status
Simulation time 25834584659 ps
CPU time 97.97 seconds
Started Jun 13 02:50:24 PM PDT 24
Finished Jun 13 02:52:14 PM PDT 24
Peak memory 257200 kb
Host smart-e29c6451-f98b-4186-afbd-db321b5e63b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690621673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2690621673
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2600173548
Short name T367
Test name
Test status
Simulation time 36477701 ps
CPU time 2.67 seconds
Started Jun 13 02:50:20 PM PDT 24
Finished Jun 13 02:50:33 PM PDT 24
Peak memory 233056 kb
Host smart-296dfd0e-5f89-41d9-a6fe-4b5ebc27eb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600173548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2600173548
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.542926492
Short name T909
Test name
Test status
Simulation time 3584662542 ps
CPU time 21.37 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:50:50 PM PDT 24
Peak memory 233136 kb
Host smart-7c5dfcb8-601b-4f74-a747-d2c847fad209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542926492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.542926492
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2355985378
Short name T77
Test name
Test status
Simulation time 1704169770 ps
CPU time 9.39 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:50:39 PM PDT 24
Peak memory 233044 kb
Host smart-0d3571b9-40ed-43ed-92ef-e986e519ffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355985378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2355985378
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2091952711
Short name T957
Test name
Test status
Simulation time 25632843148 ps
CPU time 8.53 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:36 PM PDT 24
Peak memory 227520 kb
Host smart-43ece7cd-1f7d-4486-b6a3-e521807b0676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091952711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2091952711
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1170719357
Short name T946
Test name
Test status
Simulation time 3507977009 ps
CPU time 11.22 seconds
Started Jun 13 02:50:20 PM PDT 24
Finished Jun 13 02:50:43 PM PDT 24
Peak memory 233140 kb
Host smart-571eb0e0-3706-4bcd-a8f6-7a25a74ebd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170719357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1170719357
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.667827720
Short name T465
Test name
Test status
Simulation time 1122485582 ps
CPU time 7.97 seconds
Started Jun 13 02:50:20 PM PDT 24
Finished Jun 13 02:50:40 PM PDT 24
Peak memory 223336 kb
Host smart-8bf6fcbd-bdaf-4f9e-9bc8-348b0727fdad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=667827720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.667827720
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1513642305
Short name T641
Test name
Test status
Simulation time 603981169 ps
CPU time 5.36 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:50:34 PM PDT 24
Peak memory 216620 kb
Host smart-7661ee81-9ec9-4aee-9bf2-a8baed8a3284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513642305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1513642305
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3356477733
Short name T554
Test name
Test status
Simulation time 6112892214 ps
CPU time 4.05 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:50:33 PM PDT 24
Peak memory 216624 kb
Host smart-1e295b32-2501-4772-aea7-adaf31f88644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356477733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3356477733
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2351736197
Short name T425
Test name
Test status
Simulation time 208938445 ps
CPU time 1.71 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:50:29 PM PDT 24
Peak memory 216572 kb
Host smart-0602ffc7-854c-4247-a604-618f62f80885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351736197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2351736197
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4151706281
Short name T952
Test name
Test status
Simulation time 25337712 ps
CPU time 0.68 seconds
Started Jun 13 02:50:24 PM PDT 24
Finished Jun 13 02:50:37 PM PDT 24
Peak memory 205820 kb
Host smart-2e3d466b-5d4e-4f26-9fe4-03cb05eae117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151706281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4151706281
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3826186850
Short name T849
Test name
Test status
Simulation time 504838028 ps
CPU time 7.11 seconds
Started Jun 13 02:50:23 PM PDT 24
Finished Jun 13 02:50:42 PM PDT 24
Peak memory 224820 kb
Host smart-6e7a0332-34ed-45bc-ad87-c07d9549939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826186850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3826186850
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.983279853
Short name T408
Test name
Test status
Simulation time 47795510 ps
CPU time 0.72 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:50:30 PM PDT 24
Peak memory 205640 kb
Host smart-ed06ddd0-f289-4b3d-bd2f-fc7d745f42c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983279853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.983279853
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3264786794
Short name T85
Test name
Test status
Simulation time 351164761 ps
CPU time 2.34 seconds
Started Jun 13 02:50:19 PM PDT 24
Finished Jun 13 02:50:33 PM PDT 24
Peak memory 224788 kb
Host smart-13dda666-8094-450c-9fb6-030b3a2c9d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264786794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3264786794
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2662910461
Short name T374
Test name
Test status
Simulation time 72541356 ps
CPU time 0.83 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:50:31 PM PDT 24
Peak memory 206784 kb
Host smart-1c557eda-8389-41be-8c9b-63d6475853e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662910461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2662910461
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3860095518
Short name T473
Test name
Test status
Simulation time 23934459027 ps
CPU time 26.27 seconds
Started Jun 13 02:50:23 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 224976 kb
Host smart-29a61ac9-7eea-4688-9a3c-f564f5287674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860095518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3860095518
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1890910361
Short name T903
Test name
Test status
Simulation time 82136453245 ps
CPU time 438.25 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:57:46 PM PDT 24
Peak memory 250756 kb
Host smart-1e60523d-d3dd-4485-a0a1-910ec53ad8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890910361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1890910361
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2471809059
Short name T634
Test name
Test status
Simulation time 595423129 ps
CPU time 2.6 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:31 PM PDT 24
Peak memory 224796 kb
Host smart-becf7bf3-c655-4146-982c-7b6362f51675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471809059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2471809059
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1113732754
Short name T898
Test name
Test status
Simulation time 751142323 ps
CPU time 12.91 seconds
Started Jun 13 02:50:16 PM PDT 24
Finished Jun 13 02:50:40 PM PDT 24
Peak memory 219976 kb
Host smart-e5e5e6a1-eb6c-40aa-b7aa-dd6ed227a5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113732754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1113732754
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3057124293
Short name T46
Test name
Test status
Simulation time 825952909 ps
CPU time 8.95 seconds
Started Jun 13 02:50:19 PM PDT 24
Finished Jun 13 02:50:39 PM PDT 24
Peak memory 241180 kb
Host smart-f5225a9a-9bd8-4e69-a3ba-4848573dc41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057124293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3057124293
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3328169830
Short name T527
Test name
Test status
Simulation time 753098071 ps
CPU time 7.07 seconds
Started Jun 13 02:50:24 PM PDT 24
Finished Jun 13 02:50:44 PM PDT 24
Peak memory 241152 kb
Host smart-a7e4c6d0-4b66-4c25-a5f2-1ed82f382cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328169830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3328169830
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4274811919
Short name T669
Test name
Test status
Simulation time 7937306789 ps
CPU time 22.76 seconds
Started Jun 13 02:50:24 PM PDT 24
Finished Jun 13 02:50:59 PM PDT 24
Peak memory 220684 kb
Host smart-5be45ff6-4fc7-4ca0-90e1-a8e9a68b41cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4274811919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4274811919
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3732235234
Short name T749
Test name
Test status
Simulation time 85396542 ps
CPU time 0.91 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:38 PM PDT 24
Peak memory 206092 kb
Host smart-dd4bf007-0268-413f-a328-413e3a043b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732235234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3732235234
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.548011849
Short name T688
Test name
Test status
Simulation time 19601304729 ps
CPU time 32.86 seconds
Started Jun 13 02:50:18 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 216628 kb
Host smart-42c255d8-32fb-45bd-8904-7e4d419045f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548011849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.548011849
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2539530582
Short name T553
Test name
Test status
Simulation time 2857401051 ps
CPU time 3.77 seconds
Started Jun 13 02:50:19 PM PDT 24
Finished Jun 13 02:50:34 PM PDT 24
Peak memory 216600 kb
Host smart-354058b8-758e-4e32-92d0-122d9f140018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539530582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2539530582
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3784071102
Short name T262
Test name
Test status
Simulation time 275419657 ps
CPU time 3.32 seconds
Started Jun 13 02:50:20 PM PDT 24
Finished Jun 13 02:50:35 PM PDT 24
Peak memory 216580 kb
Host smart-110f95d3-438b-4e61-a80e-690358a474a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784071102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3784071102
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4083489259
Short name T378
Test name
Test status
Simulation time 81057582 ps
CPU time 0.78 seconds
Started Jun 13 02:50:24 PM PDT 24
Finished Jun 13 02:50:38 PM PDT 24
Peak memory 206156 kb
Host smart-9398d2cb-5878-4847-a76c-629add973049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083489259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4083489259
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2527204353
Short name T833
Test name
Test status
Simulation time 2909217407 ps
CPU time 8.33 seconds
Started Jun 13 02:50:20 PM PDT 24
Finished Jun 13 02:50:40 PM PDT 24
Peak memory 233152 kb
Host smart-42ede03b-572e-43b3-a5ba-107092166d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527204353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2527204353
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.274178913
Short name T420
Test name
Test status
Simulation time 15447015 ps
CPU time 0.75 seconds
Started Jun 13 02:48:22 PM PDT 24
Finished Jun 13 02:48:39 PM PDT 24
Peak memory 205528 kb
Host smart-515f5672-c19a-4aa9-a838-2e8bed9d579b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274178913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.274178913
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.661810636
Short name T672
Test name
Test status
Simulation time 7313320363 ps
CPU time 5.95 seconds
Started Jun 13 02:48:23 PM PDT 24
Finished Jun 13 02:48:45 PM PDT 24
Peak memory 233120 kb
Host smart-f2a2ec28-3de7-48f1-b5c7-ec60213e97ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661810636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.661810636
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2938679835
Short name T635
Test name
Test status
Simulation time 50005470 ps
CPU time 0.87 seconds
Started Jun 13 02:48:23 PM PDT 24
Finished Jun 13 02:48:40 PM PDT 24
Peak memory 206772 kb
Host smart-3b5b64e0-841f-4470-a259-b17b197edecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938679835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2938679835
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3732732853
Short name T501
Test name
Test status
Simulation time 159311680687 ps
CPU time 214.8 seconds
Started Jun 13 02:48:21 PM PDT 24
Finished Jun 13 02:52:11 PM PDT 24
Peak memory 249524 kb
Host smart-fad535f9-e3f0-4840-ae25-96e326942ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732732853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3732732853
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.166441107
Short name T325
Test name
Test status
Simulation time 173754689158 ps
CPU time 374.53 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:54:51 PM PDT 24
Peak memory 249592 kb
Host smart-d815c831-bdb8-4609-9dd9-cc0ff7c844b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166441107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
166441107
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1724944296
Short name T284
Test name
Test status
Simulation time 9484682242 ps
CPU time 37.17 seconds
Started Jun 13 02:48:33 PM PDT 24
Finished Jun 13 02:49:26 PM PDT 24
Peak memory 224912 kb
Host smart-2ddcc5a4-915c-471f-a2b8-4b710bb7421c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724944296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1724944296
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1847399990
Short name T629
Test name
Test status
Simulation time 4389739864 ps
CPU time 4.38 seconds
Started Jun 13 02:48:32 PM PDT 24
Finished Jun 13 02:48:59 PM PDT 24
Peak memory 224888 kb
Host smart-a7129958-4eb2-4c0a-84f3-65537f368484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847399990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1847399990
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.437253782
Short name T546
Test name
Test status
Simulation time 78439188056 ps
CPU time 45.92 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:49:22 PM PDT 24
Peak memory 241200 kb
Host smart-1eea281f-7893-4939-b327-326b5d55aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437253782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.437253782
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4008065796
Short name T844
Test name
Test status
Simulation time 33171735 ps
CPU time 1.03 seconds
Started Jun 13 02:48:27 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 218156 kb
Host smart-de78358d-7b7f-4a66-bbd4-027afa8a9ede
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008065796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4008065796
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.50632565
Short name T178
Test name
Test status
Simulation time 1334653919 ps
CPU time 2.78 seconds
Started Jun 13 02:48:37 PM PDT 24
Finished Jun 13 02:48:56 PM PDT 24
Peak memory 227612 kb
Host smart-d22580a9-3d08-48d7-96a5-ad5c0fb431f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50632565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.50632565
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.63178588
Short name T495
Test name
Test status
Simulation time 6062012691 ps
CPU time 17.06 seconds
Started Jun 13 02:48:23 PM PDT 24
Finished Jun 13 02:48:56 PM PDT 24
Peak memory 233132 kb
Host smart-fc84f56a-03ab-4ed8-a71f-1e05336b6c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63178588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.63178588
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1506575485
Short name T755
Test name
Test status
Simulation time 156885221 ps
CPU time 3.96 seconds
Started Jun 13 02:48:22 PM PDT 24
Finished Jun 13 02:48:42 PM PDT 24
Peak memory 220776 kb
Host smart-b369054b-5f0c-4cd0-9bd5-778259eda77c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1506575485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1506575485
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.368745725
Short name T71
Test name
Test status
Simulation time 155092467 ps
CPU time 1.2 seconds
Started Jun 13 02:48:23 PM PDT 24
Finished Jun 13 02:48:41 PM PDT 24
Peak memory 235740 kb
Host smart-16b382f7-94a8-4416-9029-191135f99b69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368745725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.368745725
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2296451060
Short name T155
Test name
Test status
Simulation time 52144968759 ps
CPU time 217.5 seconds
Started Jun 13 02:48:36 PM PDT 24
Finished Jun 13 02:52:29 PM PDT 24
Peak memory 249608 kb
Host smart-dc973f44-7e8f-4cc9-b628-01f0bfc6b73b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296451060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2296451060
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2227037419
Short name T326
Test name
Test status
Simulation time 1079816903 ps
CPU time 15.67 seconds
Started Jun 13 02:48:21 PM PDT 24
Finished Jun 13 02:48:52 PM PDT 24
Peak memory 216524 kb
Host smart-3bcdaaaf-3546-4fc2-a609-3f9bc2b95132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227037419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2227037419
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1465978712
Short name T469
Test name
Test status
Simulation time 3813266415 ps
CPU time 13.07 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:49:03 PM PDT 24
Peak memory 216612 kb
Host smart-e9f47f9c-da90-4815-ad31-f7dd772c4c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465978712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1465978712
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2913299227
Short name T548
Test name
Test status
Simulation time 18580091 ps
CPU time 0.84 seconds
Started Jun 13 02:48:25 PM PDT 24
Finished Jun 13 02:48:41 PM PDT 24
Peak memory 206760 kb
Host smart-015b0238-714f-4285-b2a9-3dbc751fa649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913299227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2913299227
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1714217877
Short name T774
Test name
Test status
Simulation time 323529545 ps
CPU time 0.93 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:48:37 PM PDT 24
Peak memory 206184 kb
Host smart-45ec73e7-8364-4304-b8cd-6e030715b80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714217877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1714217877
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1316972698
Short name T574
Test name
Test status
Simulation time 326484476 ps
CPU time 5.87 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:48:57 PM PDT 24
Peak memory 224896 kb
Host smart-efedbace-da82-4d5d-b8bb-ade774f9a7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316972698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1316972698
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1893398263
Short name T875
Test name
Test status
Simulation time 40840329 ps
CPU time 0.74 seconds
Started Jun 13 02:50:27 PM PDT 24
Finished Jun 13 02:50:40 PM PDT 24
Peak memory 205088 kb
Host smart-f67e8005-7da8-43d1-aa95-5b9655dbf91d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893398263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1893398263
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2359702889
Short name T636
Test name
Test status
Simulation time 2846929779 ps
CPU time 4.46 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:42 PM PDT 24
Peak memory 233112 kb
Host smart-3c1bb0e8-995a-4076-9ce8-4d391b2ca5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359702889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2359702889
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3192802285
Short name T788
Test name
Test status
Simulation time 145787909 ps
CPU time 0.81 seconds
Started Jun 13 02:50:19 PM PDT 24
Finished Jun 13 02:50:31 PM PDT 24
Peak memory 207124 kb
Host smart-1fb94c21-e380-42ba-aa46-a505231066cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192802285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3192802285
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1069671518
Short name T823
Test name
Test status
Simulation time 61957265904 ps
CPU time 141.3 seconds
Started Jun 13 02:50:28 PM PDT 24
Finished Jun 13 02:53:02 PM PDT 24
Peak memory 264880 kb
Host smart-8aff03c7-80c3-43fc-8bc7-10b5869e3594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069671518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1069671518
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.379021110
Short name T676
Test name
Test status
Simulation time 341323857989 ps
CPU time 331.56 seconds
Started Jun 13 02:50:30 PM PDT 24
Finished Jun 13 02:56:14 PM PDT 24
Peak memory 257712 kb
Host smart-f37a151f-7c3d-4ea7-b662-ca0005453815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379021110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.379021110
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2360127014
Short name T283
Test name
Test status
Simulation time 36843663710 ps
CPU time 359.15 seconds
Started Jun 13 02:50:27 PM PDT 24
Finished Jun 13 02:56:39 PM PDT 24
Peak memory 249532 kb
Host smart-0851d0d7-0cde-4741-9159-f9cfba72488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360127014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2360127014
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.185157795
Short name T616
Test name
Test status
Simulation time 325307184 ps
CPU time 8.38 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:46 PM PDT 24
Peak memory 241248 kb
Host smart-45c9a727-500b-46cf-bdac-8c366194f3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185157795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.185157795
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3759593298
Short name T545
Test name
Test status
Simulation time 959485484 ps
CPU time 5.18 seconds
Started Jun 13 02:50:27 PM PDT 24
Finished Jun 13 02:50:45 PM PDT 24
Peak memory 224808 kb
Host smart-a222887e-575b-4925-be72-7ad6dd9bb245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759593298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3759593298
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.440493253
Short name T651
Test name
Test status
Simulation time 40026487661 ps
CPU time 28.46 seconds
Started Jun 13 02:50:26 PM PDT 24
Finished Jun 13 02:51:08 PM PDT 24
Peak memory 233096 kb
Host smart-71675ffa-d28b-4557-9d15-f21fdeb405d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440493253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.440493253
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3126799483
Short name T472
Test name
Test status
Simulation time 76852465 ps
CPU time 2.65 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:41 PM PDT 24
Peak memory 233060 kb
Host smart-f96d1d85-36e3-436a-b8aa-9a580abcf338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126799483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3126799483
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4066437774
Short name T766
Test name
Test status
Simulation time 3744062441 ps
CPU time 11.97 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:50 PM PDT 24
Peak memory 233036 kb
Host smart-483d75d2-9565-4c28-a16c-516a67671dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066437774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4066437774
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.282454346
Short name T143
Test name
Test status
Simulation time 9614659875 ps
CPU time 9.75 seconds
Started Jun 13 02:50:26 PM PDT 24
Finished Jun 13 02:50:48 PM PDT 24
Peak memory 223212 kb
Host smart-be213c4f-8648-43a4-bc83-aa9119bcbcc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=282454346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.282454346
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2692881558
Short name T320
Test name
Test status
Simulation time 1413182191 ps
CPU time 8.67 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:36 PM PDT 24
Peak memory 216580 kb
Host smart-f4ecf9f9-bf6f-4770-afe2-26525b2128c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692881558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2692881558
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2707998574
Short name T883
Test name
Test status
Simulation time 6634582499 ps
CPU time 19.06 seconds
Started Jun 13 02:50:17 PM PDT 24
Finished Jun 13 02:50:47 PM PDT 24
Peak memory 216636 kb
Host smart-bac88db0-f924-4169-a10a-6cd6f0a73646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707998574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2707998574
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1790507778
Short name T358
Test name
Test status
Simulation time 74693742 ps
CPU time 0.84 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:39 PM PDT 24
Peak memory 206180 kb
Host smart-e1a1aa86-1233-4f95-bf9c-d636ffee14fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790507778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1790507778
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2697156130
Short name T930
Test name
Test status
Simulation time 126742213 ps
CPU time 0.84 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:39 PM PDT 24
Peak memory 207188 kb
Host smart-917bd52a-29b4-4444-b035-20159fb1f050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697156130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2697156130
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3976870935
Short name T834
Test name
Test status
Simulation time 170048923 ps
CPU time 4 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:42 PM PDT 24
Peak memory 233048 kb
Host smart-747941df-5f1b-490a-b05d-1e4aee1c77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976870935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3976870935
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.548240636
Short name T536
Test name
Test status
Simulation time 18336948 ps
CPU time 0.73 seconds
Started Jun 13 02:50:30 PM PDT 24
Finished Jun 13 02:50:44 PM PDT 24
Peak memory 205636 kb
Host smart-9992a07b-8b2a-4ebc-abf6-d8b1576102bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548240636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.548240636
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2955418398
Short name T696
Test name
Test status
Simulation time 389306588 ps
CPU time 5.16 seconds
Started Jun 13 02:50:26 PM PDT 24
Finished Jun 13 02:50:44 PM PDT 24
Peak memory 224804 kb
Host smart-02ed4f95-58bf-4e97-8d90-07488f36ac1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955418398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2955418398
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1461818797
Short name T960
Test name
Test status
Simulation time 202579065 ps
CPU time 0.75 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:39 PM PDT 24
Peak memory 206788 kb
Host smart-24538150-4cd8-4b56-90ad-fd8ddf112c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461818797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1461818797
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1490396123
Short name T486
Test name
Test status
Simulation time 7145286600 ps
CPU time 36.43 seconds
Started Jun 13 02:50:28 PM PDT 24
Finished Jun 13 02:51:16 PM PDT 24
Peak memory 250880 kb
Host smart-1bca50c0-8804-473d-9ed6-d3110f548606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490396123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1490396123
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1969218296
Short name T560
Test name
Test status
Simulation time 26082762880 ps
CPU time 242.73 seconds
Started Jun 13 02:50:31 PM PDT 24
Finished Jun 13 02:54:46 PM PDT 24
Peak memory 249576 kb
Host smart-4b6fff31-5aee-453e-b456-99f99c23948a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969218296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1969218296
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2016656508
Short name T260
Test name
Test status
Simulation time 16674715429 ps
CPU time 82.21 seconds
Started Jun 13 02:50:31 PM PDT 24
Finished Jun 13 02:52:07 PM PDT 24
Peak memory 233184 kb
Host smart-36593829-93c8-4c79-97ea-452ad726ff9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016656508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2016656508
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1905023306
Short name T348
Test name
Test status
Simulation time 1226364813 ps
CPU time 7.54 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:50:45 PM PDT 24
Peak memory 224688 kb
Host smart-f894fa2c-ec28-47f4-969b-e8058f57ce9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905023306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1905023306
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.897144745
Short name T298
Test name
Test status
Simulation time 754970195 ps
CPU time 7.28 seconds
Started Jun 13 02:50:28 PM PDT 24
Finished Jun 13 02:50:48 PM PDT 24
Peak memory 233036 kb
Host smart-fd956901-cca3-4a82-a625-997627cc50cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897144745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.897144745
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2579124474
Short name T500
Test name
Test status
Simulation time 6442519779 ps
CPU time 22.87 seconds
Started Jun 13 02:50:27 PM PDT 24
Finished Jun 13 02:51:03 PM PDT 24
Peak memory 241164 kb
Host smart-b6605f1a-5357-44e8-841e-3c8240338f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579124474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2579124474
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2658372904
Short name T648
Test name
Test status
Simulation time 17152408353 ps
CPU time 15.44 seconds
Started Jun 13 02:50:26 PM PDT 24
Finished Jun 13 02:50:54 PM PDT 24
Peak memory 233132 kb
Host smart-f1b5e38a-f957-4115-9adc-924afb3ff5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658372904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2658372904
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3353123512
Short name T128
Test name
Test status
Simulation time 201670954 ps
CPU time 5.16 seconds
Started Jun 13 02:50:26 PM PDT 24
Finished Jun 13 02:50:44 PM PDT 24
Peak memory 240584 kb
Host smart-52781d3a-c07c-4ddd-8a65-5724b1d07ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353123512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3353123512
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3054235495
Short name T515
Test name
Test status
Simulation time 376110637 ps
CPU time 6.83 seconds
Started Jun 13 02:50:27 PM PDT 24
Finished Jun 13 02:50:47 PM PDT 24
Peak memory 222824 kb
Host smart-5a18a88a-b7ce-489e-b127-af7a5ba995fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3054235495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3054235495
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2325067749
Short name T680
Test name
Test status
Simulation time 43296774 ps
CPU time 0.95 seconds
Started Jun 13 02:50:33 PM PDT 24
Finished Jun 13 02:50:48 PM PDT 24
Peak memory 206812 kb
Host smart-865dd2e8-3e0d-46f2-a5bb-2d6fc0da30e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325067749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2325067749
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3011941886
Short name T322
Test name
Test status
Simulation time 10941703929 ps
CPU time 32.58 seconds
Started Jun 13 02:50:25 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 216704 kb
Host smart-a5246b35-c652-41bc-9ec6-6a19daf7635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011941886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3011941886
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1241715129
Short name T592
Test name
Test status
Simulation time 33243561 ps
CPU time 0.76 seconds
Started Jun 13 02:50:26 PM PDT 24
Finished Jun 13 02:50:40 PM PDT 24
Peak memory 205880 kb
Host smart-aaed4276-39b6-4b10-83a6-9e0d4d4793c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241715129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1241715129
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1832664050
Short name T324
Test name
Test status
Simulation time 944568809 ps
CPU time 3.47 seconds
Started Jun 13 02:50:26 PM PDT 24
Finished Jun 13 02:50:42 PM PDT 24
Peak memory 216616 kb
Host smart-a3b38aff-bedf-4a27-8867-b3e167fbc645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832664050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1832664050
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.133159803
Short name T779
Test name
Test status
Simulation time 83538869 ps
CPU time 0.84 seconds
Started Jun 13 02:50:24 PM PDT 24
Finished Jun 13 02:50:37 PM PDT 24
Peak memory 206172 kb
Host smart-fa70ef93-43a9-4fb5-93c3-b80c9029ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133159803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.133159803
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.807603950
Short name T682
Test name
Test status
Simulation time 507493523 ps
CPU time 4.72 seconds
Started Jun 13 02:50:27 PM PDT 24
Finished Jun 13 02:50:44 PM PDT 24
Peak memory 224816 kb
Host smart-c6e9f0ef-6aff-4952-a9b7-48a73cf0d096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807603950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.807603950
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3906874598
Short name T586
Test name
Test status
Simulation time 68723628 ps
CPU time 0.73 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:45 PM PDT 24
Peak memory 205120 kb
Host smart-3403248b-3b0f-497a-892a-e48249c0fa4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906874598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3906874598
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4279347940
Short name T780
Test name
Test status
Simulation time 383739432 ps
CPU time 8.45 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:55 PM PDT 24
Peak memory 233060 kb
Host smart-79621598-c80e-4ce8-be73-7c4742959d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279347940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4279347940
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1485239365
Short name T929
Test name
Test status
Simulation time 65437565 ps
CPU time 0.79 seconds
Started Jun 13 02:50:30 PM PDT 24
Finished Jun 13 02:50:43 PM PDT 24
Peak memory 206780 kb
Host smart-24ac84d1-c9fd-402d-931a-1c580c287c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485239365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1485239365
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1481355091
Short name T627
Test name
Test status
Simulation time 656150572795 ps
CPU time 279.37 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:55:24 PM PDT 24
Peak memory 249524 kb
Host smart-f4213a64-591a-42e5-9658-36631f55f87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481355091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1481355091
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1042090715
Short name T587
Test name
Test status
Simulation time 190244372709 ps
CPU time 80.8 seconds
Started Jun 13 02:50:35 PM PDT 24
Finished Jun 13 02:52:09 PM PDT 24
Peak memory 250496 kb
Host smart-3c7785dc-dd0f-45e5-b78b-e17d95810d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042090715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1042090715
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1553320347
Short name T380
Test name
Test status
Simulation time 5407423794 ps
CPU time 22.77 seconds
Started Jun 13 02:50:36 PM PDT 24
Finished Jun 13 02:51:12 PM PDT 24
Peak memory 233072 kb
Host smart-a831145c-a4b4-4316-a93d-7bdacabee9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553320347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1553320347
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3067258488
Short name T435
Test name
Test status
Simulation time 205957719 ps
CPU time 5.23 seconds
Started Jun 13 02:50:33 PM PDT 24
Finished Jun 13 02:50:51 PM PDT 24
Peak memory 233068 kb
Host smart-5b626032-1cb3-46e5-935a-4bf074003107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067258488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3067258488
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2873111746
Short name T900
Test name
Test status
Simulation time 509854243 ps
CPU time 9.12 seconds
Started Jun 13 02:50:35 PM PDT 24
Finished Jun 13 02:50:57 PM PDT 24
Peak memory 233004 kb
Host smart-860ad486-a705-4c16-8c5a-a8c9d0d8cc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873111746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2873111746
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3889962441
Short name T205
Test name
Test status
Simulation time 505750328 ps
CPU time 3.75 seconds
Started Jun 13 02:50:33 PM PDT 24
Finished Jun 13 02:50:50 PM PDT 24
Peak memory 233020 kb
Host smart-e7dc6876-1348-457d-944e-3a5ad9fe939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889962441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3889962441
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1565079810
Short name T902
Test name
Test status
Simulation time 1060673578 ps
CPU time 6.06 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:53 PM PDT 24
Peak memory 224788 kb
Host smart-e51beebd-1b14-4522-9d58-2760f3d6a4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565079810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1565079810
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1337508570
Short name T565
Test name
Test status
Simulation time 1007087670 ps
CPU time 3.1 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:50 PM PDT 24
Peak memory 220860 kb
Host smart-cd59c92e-bc25-4d18-83f3-06116fff26a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1337508570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1337508570
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2100246754
Short name T735
Test name
Test status
Simulation time 156780539202 ps
CPU time 172.95 seconds
Started Jun 13 02:50:33 PM PDT 24
Finished Jun 13 02:53:39 PM PDT 24
Peak memory 249564 kb
Host smart-c6d325d7-76f2-44d5-a0a9-cd908b4e0b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100246754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2100246754
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1527114276
Short name T52
Test name
Test status
Simulation time 296090646 ps
CPU time 2.31 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:49 PM PDT 24
Peak memory 216636 kb
Host smart-fa50af62-aca8-4674-8afe-ef62f366c9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527114276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1527114276
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.502943064
Short name T705
Test name
Test status
Simulation time 1186411501 ps
CPU time 4.41 seconds
Started Jun 13 02:50:31 PM PDT 24
Finished Jun 13 02:50:48 PM PDT 24
Peak memory 216540 kb
Host smart-b212b8f8-b79a-437f-9902-7bba4af5b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502943064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.502943064
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2061201747
Short name T807
Test name
Test status
Simulation time 20887900 ps
CPU time 0.86 seconds
Started Jun 13 02:50:30 PM PDT 24
Finished Jun 13 02:50:43 PM PDT 24
Peak memory 207196 kb
Host smart-fca61c14-11be-4572-baa3-5c6ecbdee89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061201747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2061201747
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2165020553
Short name T850
Test name
Test status
Simulation time 388792062 ps
CPU time 0.81 seconds
Started Jun 13 02:50:33 PM PDT 24
Finished Jun 13 02:50:47 PM PDT 24
Peak memory 206148 kb
Host smart-e94b02a3-9b84-4023-9fa6-2d9fb59c46bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165020553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2165020553
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1565970972
Short name T562
Test name
Test status
Simulation time 1157324889 ps
CPU time 11.72 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:59 PM PDT 24
Peak memory 233024 kb
Host smart-a0483c22-ecb5-4a19-a11c-cb25c2bf815d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565970972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1565970972
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3187468879
Short name T456
Test name
Test status
Simulation time 64507687 ps
CPU time 0.72 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:46 PM PDT 24
Peak memory 205732 kb
Host smart-14d681b2-da44-4c6b-94a6-1880bf9d3979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187468879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3187468879
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2535175280
Short name T938
Test name
Test status
Simulation time 48082987 ps
CPU time 2.77 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:47 PM PDT 24
Peak memory 233048 kb
Host smart-458c937e-4cc6-470c-9c47-c9f01a0f5f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535175280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2535175280
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3759135129
Short name T342
Test name
Test status
Simulation time 14902506 ps
CPU time 0.83 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:45 PM PDT 24
Peak memory 206804 kb
Host smart-436c6f40-ce43-4461-8bc6-932a0c40215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759135129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3759135129
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4014846184
Short name T438
Test name
Test status
Simulation time 881682497 ps
CPU time 5.47 seconds
Started Jun 13 02:50:36 PM PDT 24
Finished Jun 13 02:50:55 PM PDT 24
Peak memory 233112 kb
Host smart-213fc1df-e34a-4523-bca1-3341f504d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014846184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4014846184
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.807235553
Short name T213
Test name
Test status
Simulation time 21989592451 ps
CPU time 117.47 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:52:44 PM PDT 24
Peak memory 255112 kb
Host smart-7d98371f-ef64-44c1-9356-355153ade077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807235553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.807235553
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4053922842
Short name T492
Test name
Test status
Simulation time 9771988974 ps
CPU time 24.31 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:51:09 PM PDT 24
Peak memory 217752 kb
Host smart-3cfda57c-0e6b-483d-9a9b-2a6fd6aeb3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053922842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4053922842
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2740988619
Short name T144
Test name
Test status
Simulation time 1479032196 ps
CPU time 22.8 seconds
Started Jun 13 02:50:37 PM PDT 24
Finished Jun 13 02:51:13 PM PDT 24
Peak memory 234552 kb
Host smart-9b95240d-da6c-4f79-ba1e-519d0e95a95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740988619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2740988619
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.395083531
Short name T183
Test name
Test status
Simulation time 384549125 ps
CPU time 7.77 seconds
Started Jun 13 02:50:35 PM PDT 24
Finished Jun 13 02:50:56 PM PDT 24
Peak memory 233060 kb
Host smart-d0f89a2b-dbc6-4098-8680-8312218329d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395083531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.395083531
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2210800388
Short name T744
Test name
Test status
Simulation time 59310002417 ps
CPU time 119.71 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:52:47 PM PDT 24
Peak memory 249440 kb
Host smart-5d880789-fb4d-4b1f-92ca-e6eedba949bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210800388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2210800388
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2287138303
Short name T185
Test name
Test status
Simulation time 70169025 ps
CPU time 2.55 seconds
Started Jun 13 02:50:31 PM PDT 24
Finished Jun 13 02:50:47 PM PDT 24
Peak memory 227520 kb
Host smart-df6fba69-e4f6-4285-85fa-4a57869256eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287138303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2287138303
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2673976735
Short name T976
Test name
Test status
Simulation time 851747969 ps
CPU time 7.5 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:52 PM PDT 24
Peak memory 241152 kb
Host smart-724f4fb5-aec3-4241-99da-56fa5b2e6148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673976735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2673976735
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.260018975
Short name T764
Test name
Test status
Simulation time 3015551199 ps
CPU time 4.18 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:51 PM PDT 24
Peak memory 219584 kb
Host smart-6e725b50-bda7-4fe8-bf13-259141f0b7be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=260018975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.260018975
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1792241383
Short name T447
Test name
Test status
Simulation time 248067962 ps
CPU time 1.16 seconds
Started Jun 13 02:50:31 PM PDT 24
Finished Jun 13 02:50:46 PM PDT 24
Peak memory 207320 kb
Host smart-350d7bc9-1e2d-4ef8-814d-ee74cfd1e81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792241383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1792241383
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1962405328
Short name T582
Test name
Test status
Simulation time 1852572606 ps
CPU time 12.23 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 216596 kb
Host smart-fc61e082-81a4-4367-98ce-605cc693a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962405328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1962405328
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.28036284
Short name T727
Test name
Test status
Simulation time 9489323309 ps
CPU time 6.67 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:54 PM PDT 24
Peak memory 216604 kb
Host smart-c9cd0a86-4047-43b6-ab39-c62f330ed423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28036284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.28036284
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3461395173
Short name T853
Test name
Test status
Simulation time 294762409 ps
CPU time 1.75 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:46 PM PDT 24
Peak memory 216524 kb
Host smart-3d78dec0-233d-477c-9b3f-72b3e1b34724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461395173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3461395173
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2858730170
Short name T488
Test name
Test status
Simulation time 15156395 ps
CPU time 0.75 seconds
Started Jun 13 02:50:33 PM PDT 24
Finished Jun 13 02:50:48 PM PDT 24
Peak memory 206156 kb
Host smart-8e2b9c1d-c3d1-460d-961a-2cb8ff026d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858730170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2858730170
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.117416775
Short name T193
Test name
Test status
Simulation time 28373400584 ps
CPU time 21.92 seconds
Started Jun 13 02:50:29 PM PDT 24
Finished Jun 13 02:51:04 PM PDT 24
Peak memory 233156 kb
Host smart-f2050914-3000-44d8-949b-c5474dc721a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117416775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.117416775
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3744036270
Short name T578
Test name
Test status
Simulation time 13912744 ps
CPU time 0.72 seconds
Started Jun 13 02:50:35 PM PDT 24
Finished Jun 13 02:50:49 PM PDT 24
Peak memory 205120 kb
Host smart-19924248-ab25-4fe9-81dc-7e30a4c39ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744036270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3744036270
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3897480357
Short name T561
Test name
Test status
Simulation time 1423083649 ps
CPU time 5.92 seconds
Started Jun 13 02:50:37 PM PDT 24
Finished Jun 13 02:50:56 PM PDT 24
Peak memory 224808 kb
Host smart-7cc65db0-32bf-4958-82a9-34536fd990be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897480357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3897480357
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.673245469
Short name T782
Test name
Test status
Simulation time 15899426 ps
CPU time 0.82 seconds
Started Jun 13 02:50:31 PM PDT 24
Finished Jun 13 02:50:44 PM PDT 24
Peak memory 206788 kb
Host smart-abbe1b34-0ea9-4cc1-b916-e66f515a72ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673245469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.673245469
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1034661239
Short name T840
Test name
Test status
Simulation time 52592485219 ps
CPU time 104.14 seconds
Started Jun 13 02:50:38 PM PDT 24
Finished Jun 13 02:52:36 PM PDT 24
Peak memory 241304 kb
Host smart-5b4462b5-b0c8-436f-aa3f-d011c326419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034661239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1034661239
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.626261344
Short name T866
Test name
Test status
Simulation time 2805956642 ps
CPU time 58.46 seconds
Started Jun 13 02:58:30 PM PDT 24
Finished Jun 13 02:59:29 PM PDT 24
Peak memory 257192 kb
Host smart-db9bbd36-69a5-4a08-bb9d-7073ae47384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626261344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.626261344
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.778082073
Short name T34
Test name
Test status
Simulation time 72040420749 ps
CPU time 684.08 seconds
Started Jun 13 02:50:38 PM PDT 24
Finished Jun 13 03:02:16 PM PDT 24
Peak memory 265568 kb
Host smart-1c1022fa-d34c-4b39-b3b9-57f9d547b916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778082073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.778082073
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2461316610
Short name T732
Test name
Test status
Simulation time 7726952653 ps
CPU time 13.09 seconds
Started Jun 13 02:50:41 PM PDT 24
Finished Jun 13 02:51:07 PM PDT 24
Peak memory 233164 kb
Host smart-030be77f-fabd-4e91-ae26-5faf7a6667d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461316610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2461316610
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1251980592
Short name T188
Test name
Test status
Simulation time 5739462515 ps
CPU time 24.7 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:51:18 PM PDT 24
Peak memory 224904 kb
Host smart-fbe23caa-a3aa-453b-a8e7-66fe3f5ac548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251980592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1251980592
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3246362105
Short name T134
Test name
Test status
Simulation time 881686059 ps
CPU time 6.14 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 233100 kb
Host smart-42cb0417-0439-4ab0-a5b5-14e49b4a25b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246362105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3246362105
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.461166534
Short name T440
Test name
Test status
Simulation time 5726038502 ps
CPU time 13.56 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:51:06 PM PDT 24
Peak memory 233084 kb
Host smart-e73f4d33-5f77-4cfd-a7be-1e41ff87daf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461166534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.461166534
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1269057277
Short name T848
Test name
Test status
Simulation time 577407298 ps
CPU time 3.91 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:50:56 PM PDT 24
Peak memory 220368 kb
Host smart-26d7d26c-ef95-43b0-9105-2d24ee1b4563
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1269057277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1269057277
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2877562837
Short name T233
Test name
Test status
Simulation time 44904298383 ps
CPU time 373.86 seconds
Started Jun 13 02:50:38 PM PDT 24
Finished Jun 13 02:57:05 PM PDT 24
Peak memory 269772 kb
Host smart-a4b5716d-92f6-4945-86ed-ff1afbc63caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877562837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2877562837
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3399480417
Short name T8
Test name
Test status
Simulation time 3924482120 ps
CPU time 6.3 seconds
Started Jun 13 02:50:34 PM PDT 24
Finished Jun 13 02:50:53 PM PDT 24
Peak memory 216632 kb
Host smart-2d5cf8d1-b73c-44db-9547-0858cd2bab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399480417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3399480417
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3941585069
Short name T550
Test name
Test status
Simulation time 5030131527 ps
CPU time 4.01 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:49 PM PDT 24
Peak memory 216536 kb
Host smart-80981703-40f3-48a1-b9ad-db9a20bbd4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941585069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3941585069
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3973829467
Short name T706
Test name
Test status
Simulation time 469852358 ps
CPU time 2.1 seconds
Started Jun 13 02:50:30 PM PDT 24
Finished Jun 13 02:50:44 PM PDT 24
Peak memory 216572 kb
Host smart-94561649-f53e-490a-9f04-09e179ad5a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973829467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3973829467
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3731298598
Short name T362
Test name
Test status
Simulation time 68300024 ps
CPU time 0.94 seconds
Started Jun 13 02:50:32 PM PDT 24
Finished Jun 13 02:50:46 PM PDT 24
Peak memory 207192 kb
Host smart-1c2eeaa9-69cc-4702-899b-e143306ae895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731298598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3731298598
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3246156986
Short name T701
Test name
Test status
Simulation time 51154488263 ps
CPU time 8.31 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 224876 kb
Host smart-c65b8dc7-766b-409b-817e-21a43e89b114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246156986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3246156986
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3086087146
Short name T595
Test name
Test status
Simulation time 20290152 ps
CPU time 0.69 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:50:54 PM PDT 24
Peak memory 205676 kb
Host smart-d41e0d1b-c01f-4f72-b326-1a7af4e7acfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086087146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3086087146
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3856032026
Short name T479
Test name
Test status
Simulation time 35335819082 ps
CPU time 25.67 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:51:19 PM PDT 24
Peak memory 224868 kb
Host smart-2356166d-555b-442b-8132-0e66760e6d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856032026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3856032026
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.58758149
Short name T809
Test name
Test status
Simulation time 24206345 ps
CPU time 0.81 seconds
Started Jun 13 02:50:38 PM PDT 24
Finished Jun 13 02:50:52 PM PDT 24
Peak memory 205760 kb
Host smart-4e551c61-8e62-48ca-b548-c7d3782f3d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58758149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.58758149
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2768460425
Short name T769
Test name
Test status
Simulation time 7470576764 ps
CPU time 44.75 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:51:37 PM PDT 24
Peak memory 249300 kb
Host smart-abf35890-5c87-4d39-94d7-09b1a64a6eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768460425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2768460425
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1361961879
Short name T633
Test name
Test status
Simulation time 36135118221 ps
CPU time 196.01 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:54:08 PM PDT 24
Peak memory 249556 kb
Host smart-1cb50208-afcb-48b4-99ac-5b4163d23b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361961879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1361961879
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3288965032
Short name T363
Test name
Test status
Simulation time 2205131217 ps
CPU time 19.09 seconds
Started Jun 13 02:50:38 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 233136 kb
Host smart-6a41c87b-9fe1-483e-a958-3521a52fae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288965032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3288965032
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2593235785
Short name T48
Test name
Test status
Simulation time 103896211 ps
CPU time 3.7 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:50:57 PM PDT 24
Peak memory 224820 kb
Host smart-3e5e8475-c2dc-4a61-9978-3c3acbbfe7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593235785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2593235785
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.362411538
Short name T717
Test name
Test status
Simulation time 100916742 ps
CPU time 4.07 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:50:57 PM PDT 24
Peak memory 241032 kb
Host smart-98717535-9745-4333-adf9-b9a6aed2e0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362411538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.362411538
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1015132762
Short name T241
Test name
Test status
Simulation time 671823111 ps
CPU time 4.1 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:50:56 PM PDT 24
Peak memory 224900 kb
Host smart-2cd129e1-57c4-4725-85fb-7861ab34c0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015132762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1015132762
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3490213681
Short name T196
Test name
Test status
Simulation time 710417122 ps
CPU time 7.01 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:51:00 PM PDT 24
Peak memory 233072 kb
Host smart-67d2f716-b3a8-427f-ae0e-6a9768148b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490213681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3490213681
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2776093712
Short name T859
Test name
Test status
Simulation time 3428116719 ps
CPU time 4.53 seconds
Started Jun 13 02:50:38 PM PDT 24
Finished Jun 13 02:50:56 PM PDT 24
Peak memory 222864 kb
Host smart-db147fe2-dcdf-430e-9130-b22f28baaa32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2776093712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2776093712
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3205234196
Short name T888
Test name
Test status
Simulation time 27907532860 ps
CPU time 104.93 seconds
Started Jun 13 02:50:38 PM PDT 24
Finished Jun 13 02:52:36 PM PDT 24
Peak memory 266224 kb
Host smart-fc4d48bc-1080-4a0b-aa63-d5d3f6545cf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205234196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3205234196
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2872216655
Short name T337
Test name
Test status
Simulation time 321704672 ps
CPU time 4.04 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:50:56 PM PDT 24
Peak memory 216912 kb
Host smart-e93aa92e-0ec5-4ec7-96cf-79ce872aace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872216655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2872216655
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1027179514
Short name T475
Test name
Test status
Simulation time 29270720795 ps
CPU time 9.46 seconds
Started Jun 13 02:50:39 PM PDT 24
Finished Jun 13 02:51:02 PM PDT 24
Peak memory 216660 kb
Host smart-53461b9b-289e-4be6-b89d-4cce321c4e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027179514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1027179514
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4203223953
Short name T923
Test name
Test status
Simulation time 21710778 ps
CPU time 0.9 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:50:57 PM PDT 24
Peak memory 207008 kb
Host smart-773dd4a0-57ea-41ac-93d1-5405454fd039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203223953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4203223953
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2208175564
Short name T816
Test name
Test status
Simulation time 151911495 ps
CPU time 0.89 seconds
Started Jun 13 02:50:41 PM PDT 24
Finished Jun 13 02:50:55 PM PDT 24
Peak memory 206164 kb
Host smart-d71a3529-fcd2-409f-820c-89a72f866995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208175564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2208175564
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3549499620
Short name T583
Test name
Test status
Simulation time 1381572395 ps
CPU time 6.04 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 233032 kb
Host smart-3835ff4a-be2d-4229-bff6-1373a056a922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549499620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3549499620
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3275481777
Short name T794
Test name
Test status
Simulation time 11743608 ps
CPU time 0.73 seconds
Started Jun 13 02:50:48 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 205744 kb
Host smart-08aeb629-85e5-462c-8bd9-9f15b1ac549a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275481777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3275481777
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1524200657
Short name T98
Test name
Test status
Simulation time 29025952 ps
CPU time 1.99 seconds
Started Jun 13 02:50:42 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 224224 kb
Host smart-909976f3-027d-4383-89cd-9abef12b19b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524200657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1524200657
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2321621145
Short name T366
Test name
Test status
Simulation time 106111823 ps
CPU time 0.74 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 206100 kb
Host smart-d7aa396a-13db-4e6a-9f86-37ed66e728fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321621145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2321621145
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1506939074
Short name T47
Test name
Test status
Simulation time 29104195005 ps
CPU time 97.23 seconds
Started Jun 13 02:50:47 PM PDT 24
Finished Jun 13 02:52:37 PM PDT 24
Peak memory 256024 kb
Host smart-9dabc43d-ad65-46e1-9acb-fd475386b9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506939074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1506939074
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.261747982
Short name T721
Test name
Test status
Simulation time 8453401384 ps
CPU time 63.21 seconds
Started Jun 13 02:50:45 PM PDT 24
Finished Jun 13 02:52:01 PM PDT 24
Peak memory 249636 kb
Host smart-32d17c17-d474-4c5b-ab5c-87640456f1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261747982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.261747982
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2137973089
Short name T765
Test name
Test status
Simulation time 2241055578 ps
CPU time 12.4 seconds
Started Jun 13 02:50:46 PM PDT 24
Finished Jun 13 02:51:12 PM PDT 24
Peak memory 233132 kb
Host smart-0698b883-5577-475c-ba70-35f67e73c9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137973089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2137973089
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1032091445
Short name T187
Test name
Test status
Simulation time 4158445111 ps
CPU time 15.56 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:51:12 PM PDT 24
Peak memory 224880 kb
Host smart-7f45f251-c85b-4694-8a57-6dbea992dc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032091445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1032091445
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3691101921
Short name T880
Test name
Test status
Simulation time 975015835 ps
CPU time 14.74 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:51:11 PM PDT 24
Peak memory 233032 kb
Host smart-0a841cfe-24ce-4905-9227-d7510e1d5e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691101921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3691101921
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1662236883
Short name T175
Test name
Test status
Simulation time 489593112 ps
CPU time 3.12 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:50:59 PM PDT 24
Peak memory 224812 kb
Host smart-b526b201-975c-4a93-ad4a-28ff7df2d754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662236883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1662236883
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3077544928
Short name T434
Test name
Test status
Simulation time 701419205 ps
CPU time 2.62 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:51:00 PM PDT 24
Peak memory 224832 kb
Host smart-c1122888-eb9f-4957-9149-678a06dbcbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077544928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3077544928
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2294100969
Short name T142
Test name
Test status
Simulation time 1244513079 ps
CPU time 4.23 seconds
Started Jun 13 02:50:42 PM PDT 24
Finished Jun 13 02:51:00 PM PDT 24
Peak memory 221048 kb
Host smart-0a4180f0-31e3-4a76-9e61-acca66652cb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2294100969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2294100969
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2407975543
Short name T19
Test name
Test status
Simulation time 17983155866 ps
CPU time 105.23 seconds
Started Jun 13 02:50:46 PM PDT 24
Finished Jun 13 02:52:44 PM PDT 24
Peak memory 250176 kb
Host smart-31e41b6a-d781-4f19-aa2a-459470865524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407975543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2407975543
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1394110921
Short name T428
Test name
Test status
Simulation time 657306875 ps
CPU time 11.16 seconds
Started Jun 13 02:50:36 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 216600 kb
Host smart-e234b611-eadd-416b-94fa-f0da16f18572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394110921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1394110921
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3087597321
Short name T422
Test name
Test status
Simulation time 5150552762 ps
CPU time 2.79 seconds
Started Jun 13 02:50:37 PM PDT 24
Finished Jun 13 02:50:53 PM PDT 24
Peak memory 208276 kb
Host smart-3e5fe76b-b8a6-4468-a745-c138556c6085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087597321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3087597321
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2758908013
Short name T653
Test name
Test status
Simulation time 129518831 ps
CPU time 0.81 seconds
Started Jun 13 02:50:41 PM PDT 24
Finished Jun 13 02:50:54 PM PDT 24
Peak memory 206184 kb
Host smart-fb201d5f-8269-4e8b-b3da-8a8c5474078e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758908013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2758908013
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4211183901
Short name T762
Test name
Test status
Simulation time 70104861 ps
CPU time 0.85 seconds
Started Jun 13 02:50:40 PM PDT 24
Finished Jun 13 02:50:54 PM PDT 24
Peak memory 206164 kb
Host smart-4d27cff1-c38b-4284-ad30-c86693553a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211183901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4211183901
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.457903614
Short name T865
Test name
Test status
Simulation time 9249923875 ps
CPU time 12 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:51:09 PM PDT 24
Peak memory 241076 kb
Host smart-5a8a609e-b934-41d8-b3ef-e7c53a314f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457903614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.457903614
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2522257266
Short name T940
Test name
Test status
Simulation time 13900313 ps
CPU time 0.73 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:06 PM PDT 24
Peak memory 205992 kb
Host smart-bda8a0a2-8b88-4207-a852-1a4ae9556dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522257266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2522257266
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3576855417
Short name T485
Test name
Test status
Simulation time 397957956 ps
CPU time 6.38 seconds
Started Jun 13 02:50:47 PM PDT 24
Finished Jun 13 02:51:06 PM PDT 24
Peak memory 233064 kb
Host smart-f64aaa6e-d48a-45bb-a561-fe26426d7bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576855417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3576855417
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.770559242
Short name T969
Test name
Test status
Simulation time 41600050 ps
CPU time 0.76 seconds
Started Jun 13 02:50:47 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 205732 kb
Host smart-19a2c6c9-8719-483a-ac49-0e88ec9e358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770559242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.770559242
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1683403006
Short name T57
Test name
Test status
Simulation time 11450031348 ps
CPU time 60.39 seconds
Started Jun 13 02:50:45 PM PDT 24
Finished Jun 13 02:51:59 PM PDT 24
Peak memory 253480 kb
Host smart-e9271bf5-ff29-4a48-bc91-85e2d96503d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683403006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1683403006
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3638568746
Short name T441
Test name
Test status
Simulation time 24876716184 ps
CPU time 17.53 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:51:14 PM PDT 24
Peak memory 217724 kb
Host smart-6ba76e1c-9c8f-4604-9e77-c7c303adc9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638568746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3638568746
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1098212749
Short name T218
Test name
Test status
Simulation time 6462910473 ps
CPU time 94.71 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:52:32 PM PDT 24
Peak memory 256092 kb
Host smart-5d6b6091-3621-497a-8590-719eb90ed4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098212749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1098212749
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2123986224
Short name T601
Test name
Test status
Simulation time 638361074 ps
CPU time 6.21 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:12 PM PDT 24
Peak memory 233004 kb
Host smart-da850c7c-2fab-498e-968d-1df690a569a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123986224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2123986224
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.877617725
Short name T271
Test name
Test status
Simulation time 291247866 ps
CPU time 5.42 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:11 PM PDT 24
Peak memory 218844 kb
Host smart-96da34d4-0518-4ecd-97d9-d4dc0299b310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877617725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.877617725
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1678646327
Short name T216
Test name
Test status
Simulation time 722128702 ps
CPU time 7.8 seconds
Started Jun 13 02:50:45 PM PDT 24
Finished Jun 13 02:51:06 PM PDT 24
Peak memory 224832 kb
Host smart-05b41e96-1f67-47df-a39e-94887c5f9359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678646327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1678646327
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1002068730
Short name T725
Test name
Test status
Simulation time 4468562064 ps
CPU time 7.59 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:51:04 PM PDT 24
Peak memory 240648 kb
Host smart-07aa64ca-b901-4845-9f28-a16e2658884e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002068730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1002068730
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3095782671
Short name T730
Test name
Test status
Simulation time 3104952760 ps
CPU time 7.68 seconds
Started Jun 13 02:50:42 PM PDT 24
Finished Jun 13 02:51:04 PM PDT 24
Peak memory 224868 kb
Host smart-e2f35ea8-1fe4-4a5f-9063-9676af0d87cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095782671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3095782671
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1692483128
Short name T157
Test name
Test status
Simulation time 5487203546 ps
CPU time 7.31 seconds
Started Jun 13 02:50:47 PM PDT 24
Finished Jun 13 02:51:07 PM PDT 24
Peak memory 223364 kb
Host smart-1c555258-e492-4b5d-b477-b17bdabc0104
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692483128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1692483128
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4168270734
Short name T439
Test name
Test status
Simulation time 6968338865 ps
CPU time 20.85 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:51:18 PM PDT 24
Peak memory 216736 kb
Host smart-0f75660e-3daf-4714-9a27-8dd4b30752ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168270734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4168270734
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.413029156
Short name T836
Test name
Test status
Simulation time 12078236625 ps
CPU time 4.2 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 216636 kb
Host smart-928d2643-1c76-4d1c-aff0-1dc97aeb5cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413029156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.413029156
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1252563956
Short name T444
Test name
Test status
Simulation time 52649500 ps
CPU time 1 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 207288 kb
Host smart-7924aa64-a041-44ef-9a82-04929ddffcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252563956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1252563956
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1482495647
Short name T481
Test name
Test status
Simulation time 190791460 ps
CPU time 0.91 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 206152 kb
Host smart-d8fb1b8a-c09d-4f6a-875e-406c36919d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482495647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1482495647
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1624576611
Short name T454
Test name
Test status
Simulation time 107174093 ps
CPU time 2.51 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:08 PM PDT 24
Peak memory 232652 kb
Host smart-ef59aab8-1b91-40a2-a983-1380bfbf838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624576611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1624576611
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3453342659
Short name T924
Test name
Test status
Simulation time 49413648 ps
CPU time 0.73 seconds
Started Jun 13 02:50:51 PM PDT 24
Finished Jun 13 02:51:05 PM PDT 24
Peak memory 205688 kb
Host smart-3d401eec-4351-4f8f-a798-e8cfb0a0329c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453342659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3453342659
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1057714586
Short name T174
Test name
Test status
Simulation time 1365657936 ps
CPU time 13.09 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:19 PM PDT 24
Peak memory 224684 kb
Host smart-721b6e5e-4741-44f4-8dd3-ce92254662c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057714586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1057714586
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4272151141
Short name T369
Test name
Test status
Simulation time 280814015 ps
CPU time 0.82 seconds
Started Jun 13 02:50:48 PM PDT 24
Finished Jun 13 02:51:01 PM PDT 24
Peak memory 207116 kb
Host smart-c343e950-c82c-42af-aabc-655e260a997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272151141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4272151141
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1470707700
Short name T608
Test name
Test status
Simulation time 13355113 ps
CPU time 0.8 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:50:58 PM PDT 24
Peak memory 216208 kb
Host smart-ef509ab2-e97f-4217-b29b-07722dcce645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470707700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1470707700
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1132349997
Short name T246
Test name
Test status
Simulation time 53281794614 ps
CPU time 244.92 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:55:11 PM PDT 24
Peak memory 257708 kb
Host smart-9bae01e5-4a76-40fb-98d0-86252d13a0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132349997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1132349997
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2095464849
Short name T184
Test name
Test status
Simulation time 8988317901 ps
CPU time 53.76 seconds
Started Jun 13 02:50:58 PM PDT 24
Finished Jun 13 02:52:06 PM PDT 24
Peak memory 240912 kb
Host smart-3c060046-b812-4f3f-a303-bf3a2fbaa026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095464849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2095464849
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3968778923
Short name T855
Test name
Test status
Simulation time 189973173 ps
CPU time 6.65 seconds
Started Jun 13 02:50:42 PM PDT 24
Finished Jun 13 02:51:02 PM PDT 24
Peak memory 241256 kb
Host smart-2de55e1c-f8c0-49c3-a04b-aa280618121c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968778923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3968778923
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1430990991
Short name T964
Test name
Test status
Simulation time 151251868 ps
CPU time 2.38 seconds
Started Jun 13 02:50:47 PM PDT 24
Finished Jun 13 02:51:03 PM PDT 24
Peak memory 224784 kb
Host smart-8aa80912-7115-4995-9bf0-912ad84968d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430990991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1430990991
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.469456539
Short name T675
Test name
Test status
Simulation time 9652210603 ps
CPU time 87.06 seconds
Started Jun 13 02:50:46 PM PDT 24
Finished Jun 13 02:52:26 PM PDT 24
Peak memory 235272 kb
Host smart-4fb4b693-ce60-4860-8752-24bcc8a6530b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469456539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.469456539
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3670948031
Short name T462
Test name
Test status
Simulation time 104885188 ps
CPU time 2.14 seconds
Started Jun 13 02:50:44 PM PDT 24
Finished Jun 13 02:50:59 PM PDT 24
Peak memory 223084 kb
Host smart-5056d398-9e29-4191-9302-fc7f16f7e516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670948031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3670948031
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3264277475
Short name T915
Test name
Test status
Simulation time 2827954277 ps
CPU time 10.89 seconds
Started Jun 13 02:50:45 PM PDT 24
Finished Jun 13 02:51:09 PM PDT 24
Peak memory 233144 kb
Host smart-845650d3-2f0f-4bc2-8bb5-0436bd444f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264277475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3264277475
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1576627547
Short name T436
Test name
Test status
Simulation time 25113757917 ps
CPU time 9.8 seconds
Started Jun 13 02:50:47 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 223536 kb
Host smart-14f52239-0579-486c-bf41-f01098794f22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1576627547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1576627547
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.371313314
Short name T64
Test name
Test status
Simulation time 351298475 ps
CPU time 1.01 seconds
Started Jun 13 02:50:59 PM PDT 24
Finished Jun 13 02:51:14 PM PDT 24
Peak memory 206988 kb
Host smart-6f029d44-431e-46c9-936f-8608895109ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371313314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.371313314
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.82136475
Short name T813
Test name
Test status
Simulation time 2157316482 ps
CPU time 11.99 seconds
Started Jun 13 02:50:45 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 216748 kb
Host smart-1c8b6d25-7d22-4714-92ab-62d4583e1ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82136475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.82136475
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2551860489
Short name T28
Test name
Test status
Simulation time 2485211436 ps
CPU time 7.28 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:51:04 PM PDT 24
Peak memory 216628 kb
Host smart-d8062d01-3e4e-4735-9f29-9e4eb9084041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551860489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2551860489
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3158508455
Short name T489
Test name
Test status
Simulation time 266792392 ps
CPU time 5.38 seconds
Started Jun 13 02:50:46 PM PDT 24
Finished Jun 13 02:51:04 PM PDT 24
Peak memory 216616 kb
Host smart-f1dcf775-0a99-446d-b949-0a0fa2ac72d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158508455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3158508455
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.758485785
Short name T912
Test name
Test status
Simulation time 20240127 ps
CPU time 0.71 seconds
Started Jun 13 02:50:43 PM PDT 24
Finished Jun 13 02:50:57 PM PDT 24
Peak memory 206156 kb
Host smart-fd20c7f2-279b-414c-882f-0ae4cda17d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758485785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.758485785
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.56726365
Short name T615
Test name
Test status
Simulation time 131093379 ps
CPU time 2.52 seconds
Started Jun 13 02:50:47 PM PDT 24
Finished Jun 13 02:51:03 PM PDT 24
Peak memory 232988 kb
Host smart-69b0a652-32c7-45f7-9c92-6a28eddf6230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56726365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.56726365
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2084080361
Short name T543
Test name
Test status
Simulation time 47358660 ps
CPU time 0.71 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:07 PM PDT 24
Peak memory 205112 kb
Host smart-c845b1ed-a321-47f7-9df3-756c63315bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084080361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2084080361
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3661298964
Short name T709
Test name
Test status
Simulation time 104579697 ps
CPU time 2.33 seconds
Started Jun 13 02:50:51 PM PDT 24
Finished Jun 13 02:51:06 PM PDT 24
Peak memory 232748 kb
Host smart-8da06dbf-b5e5-485b-9277-4c0b099b7ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661298964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3661298964
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1164624403
Short name T845
Test name
Test status
Simulation time 38419493 ps
CPU time 0.74 seconds
Started Jun 13 02:50:51 PM PDT 24
Finished Jun 13 02:51:05 PM PDT 24
Peak memory 205772 kb
Host smart-8f1d5356-e5f3-4815-9d55-b18bfff869cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164624403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1164624403
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3494936883
Short name T78
Test name
Test status
Simulation time 17210668634 ps
CPU time 160.87 seconds
Started Jun 13 02:50:53 PM PDT 24
Finished Jun 13 02:53:48 PM PDT 24
Peak memory 249520 kb
Host smart-e5882fa4-5cb6-4e3f-ab03-f15cb0d13646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494936883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3494936883
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1363270452
Short name T443
Test name
Test status
Simulation time 4336492834 ps
CPU time 46.89 seconds
Started Jun 13 02:50:55 PM PDT 24
Finished Jun 13 02:51:56 PM PDT 24
Peak memory 249544 kb
Host smart-7c6a44bb-a0eb-4ccb-a856-a306b3d7bbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363270452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1363270452
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.395185587
Short name T169
Test name
Test status
Simulation time 5945984796 ps
CPU time 39.06 seconds
Started Jun 13 02:50:57 PM PDT 24
Finished Jun 13 02:51:50 PM PDT 24
Peak memory 249564 kb
Host smart-363ad390-6f1d-4829-ba5a-3103823d27c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395185587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.395185587
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2951237748
Short name T603
Test name
Test status
Simulation time 7729431936 ps
CPU time 30.28 seconds
Started Jun 13 02:50:55 PM PDT 24
Finished Jun 13 02:51:39 PM PDT 24
Peak memory 241324 kb
Host smart-028af8de-4e57-4791-a544-fcbf0d49abcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951237748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2951237748
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4055027989
Short name T757
Test name
Test status
Simulation time 158965184 ps
CPU time 5.48 seconds
Started Jun 13 02:50:54 PM PDT 24
Finished Jun 13 02:51:13 PM PDT 24
Peak memory 233036 kb
Host smart-05239a1a-1c15-4e43-8a5e-f916c66feb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055027989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4055027989
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3121668365
Short name T519
Test name
Test status
Simulation time 8349222323 ps
CPU time 21.06 seconds
Started Jun 13 02:51:02 PM PDT 24
Finished Jun 13 02:51:36 PM PDT 24
Peak memory 235896 kb
Host smart-878b1d46-d897-445e-89ef-da7fc8d2d5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121668365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3121668365
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2847443037
Short name T61
Test name
Test status
Simulation time 1547552257 ps
CPU time 5.87 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:11 PM PDT 24
Peak memory 240528 kb
Host smart-6d58f0c9-5c22-4795-950e-baac140bb54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847443037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2847443037
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.137878299
Short name T273
Test name
Test status
Simulation time 1871442129 ps
CPU time 6.87 seconds
Started Jun 13 02:50:50 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 233084 kb
Host smart-f4b95656-e610-4802-824b-8011483a9a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137878299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.137878299
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1709708185
Short name T801
Test name
Test status
Simulation time 1401345340 ps
CPU time 18.42 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:24 PM PDT 24
Peak memory 223096 kb
Host smart-9d9ef8a1-1100-44c7-bf71-816d823eba61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1709708185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1709708185
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1969345125
Short name T828
Test name
Test status
Simulation time 106079707247 ps
CPU time 510.28 seconds
Started Jun 13 02:50:56 PM PDT 24
Finished Jun 13 02:59:40 PM PDT 24
Peak memory 256948 kb
Host smart-1246d066-f331-47de-b306-601362cacec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969345125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1969345125
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1031305078
Short name T573
Test name
Test status
Simulation time 20720880557 ps
CPU time 33.55 seconds
Started Jun 13 02:50:51 PM PDT 24
Finished Jun 13 02:51:39 PM PDT 24
Peak memory 216644 kb
Host smart-b217b9b3-6d6a-4b80-8d75-265006b070c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031305078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1031305078
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1894741511
Short name T160
Test name
Test status
Simulation time 1517258131 ps
CPU time 5.22 seconds
Started Jun 13 02:50:51 PM PDT 24
Finished Jun 13 02:51:09 PM PDT 24
Peak memory 216572 kb
Host smart-95c85439-6234-42ab-b9d0-4eb6ee778d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894741511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1894741511
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.235566559
Short name T470
Test name
Test status
Simulation time 89610978 ps
CPU time 1.56 seconds
Started Jun 13 02:50:52 PM PDT 24
Finished Jun 13 02:51:07 PM PDT 24
Peak memory 216584 kb
Host smart-0232f99a-4a14-4915-a65b-aa4c4d431cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235566559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.235566559
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.173204200
Short name T334
Test name
Test status
Simulation time 35014749 ps
CPU time 0.82 seconds
Started Jun 13 02:50:54 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 206164 kb
Host smart-7f8458f5-3537-49ab-b090-92a7c81784b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173204200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.173204200
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.586102480
Short name T426
Test name
Test status
Simulation time 42080939746 ps
CPU time 13.15 seconds
Started Jun 13 02:50:54 PM PDT 24
Finished Jun 13 02:51:21 PM PDT 24
Peak memory 229736 kb
Host smart-02361e20-0530-4794-b64f-c080b09aeece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586102480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.586102480
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2385836324
Short name T67
Test name
Test status
Simulation time 12061779 ps
CPU time 0.72 seconds
Started Jun 13 02:48:31 PM PDT 24
Finished Jun 13 02:48:48 PM PDT 24
Peak memory 205692 kb
Host smart-caeb2991-c0bc-47b4-bd45-8a8840a95922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385836324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
385836324
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.308657645
Short name T589
Test name
Test status
Simulation time 2083923403 ps
CPU time 17.1 seconds
Started Jun 13 02:48:32 PM PDT 24
Finished Jun 13 02:49:06 PM PDT 24
Peak memory 233024 kb
Host smart-5c7931e0-674a-4d88-af1f-33fc316c2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308657645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.308657645
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1914737644
Short name T327
Test name
Test status
Simulation time 54135201 ps
CPU time 0.81 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:48:52 PM PDT 24
Peak memory 205732 kb
Host smart-e98c1f8e-6448-4031-828b-ac8df0c4c6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914737644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1914737644
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.309294229
Short name T257
Test name
Test status
Simulation time 53750406132 ps
CPU time 365.59 seconds
Started Jun 13 02:48:32 PM PDT 24
Finished Jun 13 02:54:54 PM PDT 24
Peak memory 250420 kb
Host smart-a1b0967c-c14b-4782-95d2-52dc3a0ea604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309294229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.309294229
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.596691354
Short name T421
Test name
Test status
Simulation time 38640906786 ps
CPU time 186.51 seconds
Started Jun 13 02:48:36 PM PDT 24
Finished Jun 13 02:51:58 PM PDT 24
Peak memory 249576 kb
Host smart-ad547fbb-4dbd-4eb1-b7dd-bf25c63a8a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596691354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.596691354
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1093081685
Short name T181
Test name
Test status
Simulation time 32373529603 ps
CPU time 292.81 seconds
Started Jun 13 02:48:29 PM PDT 24
Finished Jun 13 02:53:37 PM PDT 24
Peak memory 255304 kb
Host smart-c5a720cc-e1fc-4047-8d09-90d513341f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093081685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1093081685
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1512199852
Short name T409
Test name
Test status
Simulation time 56716243 ps
CPU time 3.04 seconds
Started Jun 13 02:48:31 PM PDT 24
Finished Jun 13 02:48:50 PM PDT 24
Peak memory 233044 kb
Host smart-d61b0bf6-4221-4fe6-8293-6d3d14166f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512199852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1512199852
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2121229768
Short name T480
Test name
Test status
Simulation time 158447886 ps
CPU time 2.18 seconds
Started Jun 13 02:48:27 PM PDT 24
Finished Jun 13 02:48:44 PM PDT 24
Peak memory 223140 kb
Host smart-5689b659-bf1f-4192-932e-3e3f763d1be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121229768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2121229768
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.115912324
Short name T666
Test name
Test status
Simulation time 4543985372 ps
CPU time 34.74 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:49:21 PM PDT 24
Peak memory 232948 kb
Host smart-6781fbf4-ba7c-47ab-8f12-6da32982f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115912324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.115912324
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1159663675
Short name T419
Test name
Test status
Simulation time 33289411 ps
CPU time 1.11 seconds
Started Jun 13 02:48:21 PM PDT 24
Finished Jun 13 02:48:38 PM PDT 24
Peak memory 216912 kb
Host smart-c36d4a80-d378-4f48-8d87-4f8863a9d0d3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159663675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1159663675
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2433070465
Short name T460
Test name
Test status
Simulation time 1494417768 ps
CPU time 4.91 seconds
Started Jun 13 02:48:24 PM PDT 24
Finished Jun 13 02:48:44 PM PDT 24
Peak memory 224864 kb
Host smart-82826ff0-307a-4beb-a29d-002d8a3759cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433070465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2433070465
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1313961029
Short name T379
Test name
Test status
Simulation time 8351821422 ps
CPU time 6.23 seconds
Started Jun 13 02:48:20 PM PDT 24
Finished Jun 13 02:48:43 PM PDT 24
Peak memory 224916 kb
Host smart-de0a0a50-9ce4-4ce4-b4e2-5daab4f3487e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313961029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1313961029
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2054033952
Short name T145
Test name
Test status
Simulation time 3378335713 ps
CPU time 6.58 seconds
Started Jun 13 02:48:27 PM PDT 24
Finished Jun 13 02:48:49 PM PDT 24
Peak memory 219560 kb
Host smart-aae0b459-844b-4fc4-b4f8-a3bf731f469a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2054033952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2054033952
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3568410603
Short name T968
Test name
Test status
Simulation time 8203732619 ps
CPU time 73.2 seconds
Started Jun 13 02:48:26 PM PDT 24
Finished Jun 13 02:49:54 PM PDT 24
Peak memory 223384 kb
Host smart-65b9557a-c053-4192-ade4-3c85652a80fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568410603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3568410603
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1068586344
Short name T27
Test name
Test status
Simulation time 19129353280 ps
CPU time 27.78 seconds
Started Jun 13 02:48:31 PM PDT 24
Finished Jun 13 02:49:15 PM PDT 24
Peak memory 216624 kb
Host smart-7ad47dc9-f87d-4f76-ac75-79609efbb154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068586344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1068586344
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3523803318
Short name T611
Test name
Test status
Simulation time 8045673698 ps
CPU time 20.41 seconds
Started Jun 13 02:48:21 PM PDT 24
Finished Jun 13 02:48:58 PM PDT 24
Peak memory 216624 kb
Host smart-8eb9feeb-d701-4d7e-908f-c2aa29456811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523803318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3523803318
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.409179849
Short name T343
Test name
Test status
Simulation time 425761306 ps
CPU time 0.87 seconds
Started Jun 13 02:48:22 PM PDT 24
Finished Jun 13 02:48:39 PM PDT 24
Peak memory 206744 kb
Host smart-859ffc43-0510-4861-9b43-821fcbc2db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409179849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.409179849
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.952152262
Short name T873
Test name
Test status
Simulation time 262552662 ps
CPU time 0.89 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:48:47 PM PDT 24
Peak memory 206156 kb
Host smart-1ac77267-eb6f-4da1-9242-45e3c554d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952152262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.952152262
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.191847971
Short name T269
Test name
Test status
Simulation time 107195271 ps
CPU time 2.15 seconds
Started Jun 13 02:48:40 PM PDT 24
Finished Jun 13 02:48:59 PM PDT 24
Peak memory 224804 kb
Host smart-d627eae0-aa61-48b2-9a72-f9758b0b6d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191847971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.191847971
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4105898564
Short name T532
Test name
Test status
Simulation time 39540808 ps
CPU time 0.72 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:48:47 PM PDT 24
Peak memory 206040 kb
Host smart-fa7f496b-1a21-4b53-a8f6-2224b40abab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105898564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
105898564
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2568213290
Short name T742
Test name
Test status
Simulation time 1133090818 ps
CPU time 4.53 seconds
Started Jun 13 02:48:38 PM PDT 24
Finished Jun 13 02:48:59 PM PDT 24
Peak memory 233084 kb
Host smart-ee768935-6008-429a-977a-96b39e791ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568213290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2568213290
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2411238480
Short name T400
Test name
Test status
Simulation time 17505274 ps
CPU time 0.79 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:48:47 PM PDT 24
Peak memory 207280 kb
Host smart-dc6bedd7-30e8-431e-922c-102a7d7db53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411238480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2411238480
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2476209924
Short name T892
Test name
Test status
Simulation time 39185161362 ps
CPU time 90.11 seconds
Started Jun 13 02:48:37 PM PDT 24
Finished Jun 13 02:50:23 PM PDT 24
Peak memory 254436 kb
Host smart-7f1d8b39-97f1-4668-ac0b-b4c09654bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476209924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2476209924
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2258002635
Short name T255
Test name
Test status
Simulation time 481036278787 ps
CPU time 177.36 seconds
Started Jun 13 02:48:36 PM PDT 24
Finished Jun 13 02:51:50 PM PDT 24
Peak memory 250592 kb
Host smart-29a1a7d2-f492-4189-b2c2-72ab213f3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258002635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2258002635
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1363146874
Short name T758
Test name
Test status
Simulation time 230029208402 ps
CPU time 539.88 seconds
Started Jun 13 02:48:34 PM PDT 24
Finished Jun 13 02:57:50 PM PDT 24
Peak memory 256692 kb
Host smart-99398665-5bf8-4c32-a300-3e76accf6506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363146874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1363146874
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3806662112
Short name T630
Test name
Test status
Simulation time 29776445629 ps
CPU time 53.39 seconds
Started Jun 13 02:48:33 PM PDT 24
Finished Jun 13 02:49:42 PM PDT 24
Peak memory 249528 kb
Host smart-d9462cd8-9d72-4d49-bbd6-8ff328880f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806662112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3806662112
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.257721738
Short name T773
Test name
Test status
Simulation time 1187266603 ps
CPU time 7.52 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:48:52 PM PDT 24
Peak memory 233068 kb
Host smart-c3a1dcee-f768-448c-9cf4-2476bf18e1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257721738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.257721738
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3717311295
Short name T513
Test name
Test status
Simulation time 8738473050 ps
CPU time 52.67 seconds
Started Jun 13 02:48:37 PM PDT 24
Finished Jun 13 02:49:46 PM PDT 24
Peak memory 240536 kb
Host smart-cf8fd979-ab7d-4031-b4aa-249e56a3265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717311295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3717311295
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2823134477
Short name T822
Test name
Test status
Simulation time 15344287 ps
CPU time 1.03 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:48:51 PM PDT 24
Peak memory 216920 kb
Host smart-b6818e01-3b73-4bb4-b5f8-1facca53a306
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823134477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2823134477
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2824818920
Short name T620
Test name
Test status
Simulation time 13196235218 ps
CPU time 17.29 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:49:03 PM PDT 24
Peak memory 224896 kb
Host smart-3063a219-e1ac-4a66-bd01-f43e56011d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824818920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2824818920
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3563086184
Short name T133
Test name
Test status
Simulation time 3533315077 ps
CPU time 5.73 seconds
Started Jun 13 02:48:29 PM PDT 24
Finished Jun 13 02:48:50 PM PDT 24
Peak memory 224928 kb
Host smart-673346de-16b8-4a68-8bc9-e2e67bf25418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563086184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3563086184
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1458687203
Short name T360
Test name
Test status
Simulation time 354366218 ps
CPU time 4.21 seconds
Started Jun 13 02:48:32 PM PDT 24
Finished Jun 13 02:48:53 PM PDT 24
Peak memory 219148 kb
Host smart-8a77280a-a63c-43d7-88e4-1320fcd9ed18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1458687203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1458687203
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.498884460
Short name T247
Test name
Test status
Simulation time 190034842802 ps
CPU time 712.22 seconds
Started Jun 13 02:48:31 PM PDT 24
Finished Jun 13 03:00:39 PM PDT 24
Peak memory 265740 kb
Host smart-6547ec15-6849-4323-a853-63e206602756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498884460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.498884460
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2244739427
Short name T831
Test name
Test status
Simulation time 1154796993 ps
CPU time 16.09 seconds
Started Jun 13 02:48:30 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 216780 kb
Host smart-53decd6d-daa8-4260-ba7b-343b88ae8f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244739427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2244739427
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.673242254
Short name T344
Test name
Test status
Simulation time 1413966348 ps
CPU time 2.76 seconds
Started Jun 13 02:48:32 PM PDT 24
Finished Jun 13 02:48:51 PM PDT 24
Peak memory 208168 kb
Host smart-e4a69076-7905-468b-ab8e-9eb8d5ed419f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673242254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.673242254
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3901630228
Short name T429
Test name
Test status
Simulation time 130515853 ps
CPU time 1.83 seconds
Started Jun 13 02:48:37 PM PDT 24
Finished Jun 13 02:48:55 PM PDT 24
Peak memory 216572 kb
Host smart-c7eb51f7-4756-4985-abae-91ec9589532e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901630228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3901630228
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1907005010
Short name T556
Test name
Test status
Simulation time 53886886 ps
CPU time 0.79 seconds
Started Jun 13 02:48:28 PM PDT 24
Finished Jun 13 02:48:44 PM PDT 24
Peak memory 206120 kb
Host smart-ecbd817b-d748-4a30-86af-781ca2d7ce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907005010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1907005010
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3258479833
Short name T295
Test name
Test status
Simulation time 434183475 ps
CPU time 9.64 seconds
Started Jun 13 02:48:33 PM PDT 24
Finished Jun 13 02:48:59 PM PDT 24
Peak memory 241252 kb
Host smart-376813b2-5ed0-412d-aaeb-b40bc74e5f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258479833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3258479833
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3071665434
Short name T697
Test name
Test status
Simulation time 25998537 ps
CPU time 0.73 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 205720 kb
Host smart-717ba841-9e67-4526-8928-417a669a3a14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071665434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
071665434
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.379487790
Short name T818
Test name
Test status
Simulation time 3783795025 ps
CPU time 7.59 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 224920 kb
Host smart-5ca99b2a-6387-419e-8013-4e42ae67f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379487790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.379487790
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2719350245
Short name T332
Test name
Test status
Simulation time 20110158 ps
CPU time 0.75 seconds
Started Jun 13 02:48:33 PM PDT 24
Finished Jun 13 02:48:50 PM PDT 24
Peak memory 205740 kb
Host smart-35385245-4e83-4dde-a711-a8056a036ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719350245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2719350245
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3791137633
Short name T784
Test name
Test status
Simulation time 6819380243 ps
CPU time 40.55 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:45 PM PDT 24
Peak memory 254320 kb
Host smart-9570517e-53c4-448c-b50d-dbc49ebab01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791137633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3791137633
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1636818626
Short name T622
Test name
Test status
Simulation time 2575204512 ps
CPU time 55.23 seconds
Started Jun 13 02:48:39 PM PDT 24
Finished Jun 13 02:49:50 PM PDT 24
Peak memory 254584 kb
Host smart-27f24651-2c7c-4ade-b319-1964d9dddcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636818626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1636818626
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2458539460
Short name T689
Test name
Test status
Simulation time 22635554307 ps
CPU time 74.92 seconds
Started Jun 13 02:48:42 PM PDT 24
Finished Jun 13 02:50:13 PM PDT 24
Peak memory 250680 kb
Host smart-7609a33f-69eb-4e59-8ba8-aa578c1c87d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458539460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2458539460
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2964627421
Short name T312
Test name
Test status
Simulation time 542893619 ps
CPU time 16.83 seconds
Started Jun 13 02:48:51 PM PDT 24
Finished Jun 13 02:49:26 PM PDT 24
Peak memory 241272 kb
Host smart-b5153e31-2c32-4ddc-93cb-588ad94b7464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964627421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2964627421
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.449903381
Short name T886
Test name
Test status
Simulation time 743470760 ps
CPU time 2.11 seconds
Started Jun 13 02:48:37 PM PDT 24
Finished Jun 13 02:48:55 PM PDT 24
Peak memory 223248 kb
Host smart-d9baae8f-a414-4c11-bb62-b5c3706a2e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449903381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.449903381
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.595282872
Short name T287
Test name
Test status
Simulation time 1129995935 ps
CPU time 15 seconds
Started Jun 13 02:48:32 PM PDT 24
Finished Jun 13 02:49:03 PM PDT 24
Peak memory 233184 kb
Host smart-1c51ed46-503d-4648-83f5-0a38df2c2bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595282872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.595282872
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1640962571
Short name T406
Test name
Test status
Simulation time 16257576 ps
CPU time 1.04 seconds
Started Jun 13 02:48:40 PM PDT 24
Finished Jun 13 02:48:57 PM PDT 24
Peak memory 216872 kb
Host smart-7582639e-9e23-4527-879e-31e268607be5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640962571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1640962571
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3747645766
Short name T217
Test name
Test status
Simulation time 15250577026 ps
CPU time 12.8 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:49:04 PM PDT 24
Peak memory 233128 kb
Host smart-d48e7461-33f3-49f1-9c53-f93e49dfeffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747645766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3747645766
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3819765993
Short name T967
Test name
Test status
Simulation time 5035193060 ps
CPU time 5.45 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:10 PM PDT 24
Peak memory 224920 kb
Host smart-5540dd6c-9cc0-4516-81c3-07e2b21e4c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819765993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3819765993
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4069043623
Short name T483
Test name
Test status
Simulation time 2301484626 ps
CPU time 13.88 seconds
Started Jun 13 02:48:34 PM PDT 24
Finished Jun 13 02:49:04 PM PDT 24
Peak memory 219508 kb
Host smart-794064ef-cb75-4b46-899b-c026841e13bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4069043623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4069043623
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3638999530
Short name T729
Test name
Test status
Simulation time 93645599865 ps
CPU time 175.15 seconds
Started Jun 13 02:48:33 PM PDT 24
Finished Jun 13 02:51:45 PM PDT 24
Peak memory 249588 kb
Host smart-5caa2705-64b2-473f-bde7-064edb7d4669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638999530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3638999530
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3585601384
Short name T665
Test name
Test status
Simulation time 10777763996 ps
CPU time 23.1 seconds
Started Jun 13 02:48:43 PM PDT 24
Finished Jun 13 02:49:22 PM PDT 24
Peak memory 216628 kb
Host smart-814af084-3847-490d-b1da-2801d02843bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585601384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3585601384
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2471150977
Short name T516
Test name
Test status
Simulation time 8779876422 ps
CPU time 12.34 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:49:04 PM PDT 24
Peak memory 216632 kb
Host smart-87698c04-06e1-44ab-a634-c59a88c9d9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471150977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2471150977
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3806888896
Short name T339
Test name
Test status
Simulation time 1505097008 ps
CPU time 6.24 seconds
Started Jun 13 02:48:43 PM PDT 24
Finished Jun 13 02:49:06 PM PDT 24
Peak memory 216776 kb
Host smart-440116bf-af0e-4ee2-859c-7c1ae5bdb8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806888896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3806888896
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2986394265
Short name T693
Test name
Test status
Simulation time 31232283 ps
CPU time 0.81 seconds
Started Jun 13 02:48:33 PM PDT 24
Finished Jun 13 02:48:50 PM PDT 24
Peak memory 206160 kb
Host smart-b7ee655c-adbf-411f-a558-4dadca079036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986394265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2986394265
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.4162970542
Short name T200
Test name
Test status
Simulation time 10137595200 ps
CPU time 10.02 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:13 PM PDT 24
Peak memory 224924 kb
Host smart-9a36c120-9e16-4b0e-9519-bcca2e9bd7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162970542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.4162970542
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4162391067
Short name T781
Test name
Test status
Simulation time 17848751 ps
CPU time 0.73 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:49:01 PM PDT 24
Peak memory 205672 kb
Host smart-549ca111-28b2-4de1-a39c-332d8ee22c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162391067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
162391067
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3851437914
Short name T718
Test name
Test status
Simulation time 2424812912 ps
CPU time 9.54 seconds
Started Jun 13 02:48:37 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 224872 kb
Host smart-83913854-8107-45d5-b684-c4a9a98c6361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851437914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3851437914
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.502030076
Short name T503
Test name
Test status
Simulation time 86528384 ps
CPU time 0.84 seconds
Started Jun 13 02:48:39 PM PDT 24
Finished Jun 13 02:48:56 PM PDT 24
Peak memory 206756 kb
Host smart-1652622d-4e44-4208-9994-72216dc55890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502030076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.502030076
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2011614042
Short name T703
Test name
Test status
Simulation time 13787933132 ps
CPU time 18.5 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:23 PM PDT 24
Peak memory 217836 kb
Host smart-def4a4b5-8db8-4a68-b57b-5752f0453e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011614042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2011614042
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3875493203
Short name T594
Test name
Test status
Simulation time 478336854 ps
CPU time 2.96 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:48:53 PM PDT 24
Peak memory 219636 kb
Host smart-24663198-11bb-43d7-98a3-5bacf1e89335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875493203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3875493203
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3593070499
Short name T707
Test name
Test status
Simulation time 236720623 ps
CPU time 6.02 seconds
Started Jun 13 02:48:38 PM PDT 24
Finished Jun 13 02:49:00 PM PDT 24
Peak memory 224840 kb
Host smart-8422f88a-789f-4b40-b47f-ee752a798767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593070499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3593070499
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2068766279
Short name T182
Test name
Test status
Simulation time 1867765937 ps
CPU time 21.15 seconds
Started Jun 13 02:48:45 PM PDT 24
Finished Jun 13 02:49:23 PM PDT 24
Peak memory 224796 kb
Host smart-805a8479-9ad0-4e58-9d6d-6d0ab2a20554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068766279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2068766279
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3508346187
Short name T76
Test name
Test status
Simulation time 49333692232 ps
CPU time 85.45 seconds
Started Jun 13 02:48:34 PM PDT 24
Finished Jun 13 02:50:16 PM PDT 24
Peak memory 233076 kb
Host smart-eceb04ab-0fa0-4521-8022-28dd83c0f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508346187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3508346187
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.175766978
Short name T752
Test name
Test status
Simulation time 49098743 ps
CPU time 1 seconds
Started Jun 13 02:48:42 PM PDT 24
Finished Jun 13 02:49:00 PM PDT 24
Peak memory 218164 kb
Host smart-e299fe9a-ff72-4578-b987-54bb60dc9a09
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175766978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.175766978
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1039541564
Short name T60
Test name
Test status
Simulation time 189700811 ps
CPU time 3.37 seconds
Started Jun 13 02:48:34 PM PDT 24
Finished Jun 13 02:48:54 PM PDT 24
Peak memory 233056 kb
Host smart-db193c62-9d8a-4fea-9b95-f39e703dc962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039541564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1039541564
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4770833
Short name T202
Test name
Test status
Simulation time 5166393649 ps
CPU time 7.54 seconds
Started Jun 13 02:48:38 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 224864 kb
Host smart-4981449a-1ca4-4aa7-986f-59f1e95c6eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4770833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4770833
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3463734161
Short name T551
Test name
Test status
Simulation time 366379658 ps
CPU time 4.82 seconds
Started Jun 13 02:48:39 PM PDT 24
Finished Jun 13 02:48:59 PM PDT 24
Peak memory 220744 kb
Host smart-11b3b5ac-6318-4f96-afc4-448e934c3204
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3463734161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3463734161
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.582141079
Short name T136
Test name
Test status
Simulation time 10471183746 ps
CPU time 128.46 seconds
Started Jun 13 02:48:34 PM PDT 24
Finished Jun 13 02:50:59 PM PDT 24
Peak memory 264432 kb
Host smart-fa2d1ec3-285b-46ca-9f17-99662d2738f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582141079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.582141079
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.289384998
Short name T575
Test name
Test status
Simulation time 16493430031 ps
CPU time 25.36 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:31 PM PDT 24
Peak memory 216664 kb
Host smart-c29d18f7-cd0e-4740-821f-ba73bb052436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289384998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.289384998
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3375883392
Short name T812
Test name
Test status
Simulation time 18763858724 ps
CPU time 11.65 seconds
Started Jun 13 02:48:42 PM PDT 24
Finished Jun 13 02:49:10 PM PDT 24
Peak memory 217732 kb
Host smart-b4171970-37e3-4b66-b86d-854d7b80bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375883392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3375883392
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4104976011
Short name T350
Test name
Test status
Simulation time 31962858 ps
CPU time 1.17 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:49:06 PM PDT 24
Peak memory 216396 kb
Host smart-af4fe275-45b6-4a0b-92e5-f96af564fb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104976011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4104976011
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_upload.2503600129
Short name T277
Test name
Test status
Simulation time 1765470971 ps
CPU time 11.29 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:14 PM PDT 24
Peak memory 234100 kb
Host smart-867478ab-3e13-48df-b247-d4062dc8fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503600129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2503600129
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3708392912
Short name T956
Test name
Test status
Simulation time 15627127 ps
CPU time 0.73 seconds
Started Jun 13 02:48:45 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 205104 kb
Host smart-fbe2d417-3140-4b27-a127-2f3304b457fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708392912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
708392912
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2017330616
Short name T424
Test name
Test status
Simulation time 287184640 ps
CPU time 2.81 seconds
Started Jun 13 02:48:46 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 224812 kb
Host smart-bbe7bcc2-4686-4ae2-b58c-790d136367df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017330616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2017330616
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2810415724
Short name T74
Test name
Test status
Simulation time 31444498 ps
CPU time 0.75 seconds
Started Jun 13 02:48:37 PM PDT 24
Finished Jun 13 02:48:54 PM PDT 24
Peak memory 205764 kb
Host smart-3d945e8d-b5dc-4c46-981b-90679863aa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810415724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2810415724
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.778026055
Short name T655
Test name
Test status
Simulation time 136644168047 ps
CPU time 111.05 seconds
Started Jun 13 02:48:48 PM PDT 24
Finished Jun 13 02:50:57 PM PDT 24
Peak memory 249504 kb
Host smart-20d998bc-4bcb-4ac2-b2de-e079ddce6ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778026055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.778026055
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4114265699
Short name T415
Test name
Test status
Simulation time 2070172743 ps
CPU time 4.04 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:08 PM PDT 24
Peak memory 217592 kb
Host smart-1d28cecf-5346-4074-8f34-effaedcdb597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114265699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4114265699
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.909855837
Short name T468
Test name
Test status
Simulation time 70565237799 ps
CPU time 125.56 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:51:10 PM PDT 24
Peak memory 250804 kb
Host smart-2b358f6a-0945-4d63-b479-ba4837855ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909855837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
909855837
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1228379653
Short name T962
Test name
Test status
Simulation time 129207912 ps
CPU time 2.7 seconds
Started Jun 13 02:48:56 PM PDT 24
Finished Jun 13 02:49:17 PM PDT 24
Peak memory 224864 kb
Host smart-cc80aac0-b7af-44a7-9cb5-eae3c82c74b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228379653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1228379653
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3109840259
Short name T328
Test name
Test status
Simulation time 224558837 ps
CPU time 2.23 seconds
Started Jun 13 02:48:43 PM PDT 24
Finished Jun 13 02:49:02 PM PDT 24
Peak memory 223428 kb
Host smart-63e5ecad-8387-4e17-8e4b-d94bc1c0eab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109840259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3109840259
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3780683767
Short name T274
Test name
Test status
Simulation time 41765880762 ps
CPU time 110.15 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:50:50 PM PDT 24
Peak memory 224848 kb
Host smart-c334d357-a5f1-463e-8072-152d0d7f7cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780683767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3780683767
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3387898504
Short name T663
Test name
Test status
Simulation time 57059974 ps
CPU time 1.02 seconds
Started Jun 13 02:48:47 PM PDT 24
Finished Jun 13 02:49:05 PM PDT 24
Peak memory 216872 kb
Host smart-f78d150b-5b68-4245-8a36-2a135077f9be
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387898504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3387898504
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3764153040
Short name T959
Test name
Test status
Simulation time 2662980613 ps
CPU time 6.2 seconds
Started Jun 13 02:48:54 PM PDT 24
Finished Jun 13 02:49:18 PM PDT 24
Peak memory 233136 kb
Host smart-ae93041c-5acf-4f69-9612-958df0cc0902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764153040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3764153040
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4017770378
Short name T135
Test name
Test status
Simulation time 97225418 ps
CPU time 2.77 seconds
Started Jun 13 02:48:41 PM PDT 24
Finished Jun 13 02:49:00 PM PDT 24
Peak memory 233088 kb
Host smart-923a8677-5806-4d17-829f-137fe5a2c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017770378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4017770378
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3472131141
Short name T432
Test name
Test status
Simulation time 1545595576 ps
CPU time 6.04 seconds
Started Jun 13 02:48:54 PM PDT 24
Finished Jun 13 02:49:17 PM PDT 24
Peak memory 222232 kb
Host smart-0ec2a41e-6148-4ff1-8bf4-2bca54c91984
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3472131141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3472131141
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1191529643
Short name T256
Test name
Test status
Simulation time 89785294413 ps
CPU time 164.92 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:51:51 PM PDT 24
Peak memory 238332 kb
Host smart-9857a4af-7b76-48b6-badc-ed510bdbb42d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191529643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1191529643
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1174625466
Short name T323
Test name
Test status
Simulation time 7894858048 ps
CPU time 20.08 seconds
Started Jun 13 02:48:55 PM PDT 24
Finished Jun 13 02:49:32 PM PDT 24
Peak memory 216700 kb
Host smart-da1dc0d7-45d9-49ec-9b7e-fd3d133179fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174625466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1174625466
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2812229793
Short name T335
Test name
Test status
Simulation time 52882027 ps
CPU time 0.69 seconds
Started Jun 13 02:48:44 PM PDT 24
Finished Jun 13 02:49:01 PM PDT 24
Peak memory 205848 kb
Host smart-1d9f525d-eccc-45ee-a0b0-7910565f943a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812229793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2812229793
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.298239789
Short name T490
Test name
Test status
Simulation time 31439219 ps
CPU time 0.9 seconds
Started Jun 13 02:48:35 PM PDT 24
Finished Jun 13 02:48:51 PM PDT 24
Peak memory 207156 kb
Host smart-e7ec2eae-7b08-4d61-90b7-10a32dc2170c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298239789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.298239789
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3330797300
Short name T852
Test name
Test status
Simulation time 149964101 ps
CPU time 0.84 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:07 PM PDT 24
Peak memory 206172 kb
Host smart-14bf011b-8d9e-4472-abb1-9e2b9a2dbad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330797300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3330797300
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.274321648
Short name T5
Test name
Test status
Simulation time 272158867 ps
CPU time 2.49 seconds
Started Jun 13 02:48:49 PM PDT 24
Finished Jun 13 02:49:09 PM PDT 24
Peak memory 233040 kb
Host smart-8c7dc0da-fcae-424c-a52d-cab5a604db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274321648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.274321648
Directory /workspace/9.spi_device_upload/latest
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