Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3415584	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3887830

1

T1

792

T2

34708

T3

1653

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4041863	1			T1	2278		T2	51906		T3	1506
values[0x0]	1631032	1			T1	394		T2	17888		T3	442
values[0x1]	1630519	1			T1	373		T2	18072		T3	469

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2416286	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4887128

1

T1

1539

T2

51444

T3

1818

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26767	1			T1	8		T2	337		T3	8
valid_sources[0x01]	28648	1			T1	15		T2	376		T3	10
valid_sources[0x02]	29617	1			T1	15		T2	377		T3	3
valid_sources[0x03]	27006	1			T1	14		T2	407		T3	12
valid_sources[0x04]	26655	1			T1	11		T2	366		T3	9
valid_sources[0x05]	29498	1			T1	10		T2	298		T3	11
valid_sources[0x06]	25152	1			T1	9		T2	325		T3	8
valid_sources[0x07]	25930	1			T1	14		T2	352		T3	10
valid_sources[0x08]	27980	1			T1	10		T2	310		T3	7
valid_sources[0x09]	25576	1			T1	12		T2	308		T3	17
valid_sources[0x0a]	34932	1			T1	12		T2	341		T3	10
valid_sources[0x0b]	28681	1			T1	11		T2	366		T3	7
valid_sources[0x0c]	25884	1			T1	6		T2	333		T3	9
valid_sources[0x0d]	25763	1			T1	14		T2	328		T3	8
valid_sources[0x0e]	27595	1			T1	8		T2	319		T3	5
valid_sources[0x0f]	29064	1			T1	10		T2	322		T3	15
valid_sources[0x10]	26391	1			T1	8		T2	343		T3	13
valid_sources[0x11]	31298	1			T1	10		T2	355		T3	13
valid_sources[0x12]	26285	1			T1	8		T2	316		T3	13
valid_sources[0x13]	28911	1			T1	15		T2	318		T3	4
valid_sources[0x14]	29118	1			T1	8		T2	345		T3	11
valid_sources[0x15]	29224	1			T1	4		T2	350		T3	6
valid_sources[0x16]	27944	1			T1	5		T2	325		T3	13
valid_sources[0x17]	30764	1			T1	14		T2	347		T3	11
valid_sources[0x18]	24646	1			T1	8		T2	336		T3	12
valid_sources[0x19]	29642	1			T1	12		T2	356		T3	6
valid_sources[0x1a]	26625	1			T1	17		T2	363		T3	9
valid_sources[0x1b]	24431	1			T1	11		T2	333		T3	8
valid_sources[0x1c]	25883	1			T1	7		T2	328		T3	7
valid_sources[0x1d]	25191	1			T1	14		T2	329		T3	2
valid_sources[0x1e]	27870	1			T1	25		T2	353		T3	14
valid_sources[0x1f]	25972	1			T1	12		T2	349		T3	4
valid_sources[0x20]	30463	1			T1	16		T2	364		T3	10
valid_sources[0x21]	26533	1			T1	13		T2	323		T3	8
valid_sources[0x22]	24778	1			T1	15		T2	332		T3	6
valid_sources[0x23]	29713	1			T1	12		T2	371		T3	9
valid_sources[0x24]	25960	1			T1	15		T2	329		T3	10
valid_sources[0x25]	27199	1			T1	6		T2	368		T3	9
valid_sources[0x26]	24861	1			T1	14		T2	355		T3	6
valid_sources[0x27]	26185	1			T1	12		T2	347		T3	10
valid_sources[0x28]	28639	1			T1	11		T2	385		T3	7
valid_sources[0x29]	42925	1			T1	14		T2	298		T3	15
valid_sources[0x2a]	27895	1			T1	16		T2	306		T3	13
valid_sources[0x2b]	28974	1			T1	17		T2	340		T3	11
valid_sources[0x2c]	26096	1			T1	22		T2	350		T3	10
valid_sources[0x2d]	25799	1			T1	8		T2	336		T3	4
valid_sources[0x2e]	25780	1			T1	6		T2	316		T3	10
valid_sources[0x2f]	26493	1			T1	9		T2	325		T3	17
valid_sources[0x30]	25171	1			T1	12		T2	324		T3	7
valid_sources[0x31]	27591	1			T1	8		T2	348		T3	8
valid_sources[0x32]	26400	1			T1	12		T2	352		T3	5
valid_sources[0x33]	29750	1			T1	6		T2	315		T3	6
valid_sources[0x34]	34637	1			T1	11		T2	339		T3	9
valid_sources[0x35]	28201	1			T1	8		T2	369		T3	2
valid_sources[0x36]	27357	1			T1	17		T2	359		T3	9
valid_sources[0x37]	26424	1			T1	8		T2	364		T3	6
valid_sources[0x38]	26673	1			T1	15		T2	326		T3	6
valid_sources[0x39]	24847	1			T1	16		T2	348		T3	10
valid_sources[0x3a]	27293	1			T1	15		T2	344		T3	12
valid_sources[0x3b]	27883	1			T1	15		T2	358		T3	6
valid_sources[0x3c]	30350	1			T1	9		T2	348		T3	9
valid_sources[0x3d]	26723	1			T1	10		T2	342		T3	8
valid_sources[0x3e]	26557	1			T1	16		T2	353		T3	10
valid_sources[0x3f]	24893	1			T1	13		T2	367		T3	7
valid_sources[0x40]	28176	1			T1	19		T2	356		T3	6
valid_sources[0x41]	36874	1			T1	16		T2	322		T3	7
valid_sources[0x42]	25782	1			T1	7		T2	327		T3	9
valid_sources[0x43]	26432	1			T1	16		T2	339		T3	12
valid_sources[0x44]	26468	1			T1	6		T2	345		T3	8
valid_sources[0x45]	31772	1			T1	14		T2	342		T3	7
valid_sources[0x46]	28081	1			T1	12		T2	316		T3	7
valid_sources[0x47]	26160	1			T1	23		T2	376		T3	8
valid_sources[0x48]	28986	1			T1	13		T2	323		T3	13
valid_sources[0x49]	27857	1			T1	11		T2	345		T3	10
valid_sources[0x4a]	35528	1			T1	14		T2	356		T3	11
valid_sources[0x4b]	26355	1			T1	9		T2	319		T3	9
valid_sources[0x4c]	24741	1			T1	8		T2	343		T3	10
valid_sources[0x4d]	25996	1			T1	10		T2	366		T3	3
valid_sources[0x4e]	25814	1			T1	16		T2	312		T3	18
valid_sources[0x4f]	28833	1			T1	10		T2	365		T3	11
valid_sources[0x50]	26295	1			T1	12		T2	334		T3	7
valid_sources[0x51]	69508	1			T1	15		T2	318		T3	15
valid_sources[0x52]	26784	1			T1	5		T2	326		T3	7
valid_sources[0x53]	24689	1			T1	8		T2	345		T3	10
valid_sources[0x54]	28027	1			T1	13		T2	336		T3	10
valid_sources[0x55]	25796	1			T1	15		T2	356		T3	7
valid_sources[0x56]	30186	1			T1	6		T2	326		T3	8
valid_sources[0x57]	34525	1			T1	16		T2	335		T3	18
valid_sources[0x58]	26187	1			T1	12		T2	323		T3	11
valid_sources[0x59]	24305	1			T1	9		T2	347		T3	10
valid_sources[0x5a]	28273	1			T1	9		T2	338		T3	8
valid_sources[0x5b]	24824	1			T1	3		T2	361		T3	5
valid_sources[0x5c]	27704	1			T1	19		T2	332		T3	8
valid_sources[0x5d]	30672	1			T1	15		T2	376		T3	5
valid_sources[0x5e]	26264	1			T1	14		T2	351		T3	5
valid_sources[0x5f]	28430	1			T1	11		T2	372		T3	4
valid_sources[0x60]	28180	1			T1	12		T2	393		T3	13
valid_sources[0x61]	30386	1			T1	16		T2	344		T3	7
valid_sources[0x62]	28746	1			T1	11		T2	320		T3	17
valid_sources[0x63]	29681	1			T1	11		T2	345		T3	7
valid_sources[0x64]	27500	1			T1	10		T2	356		T3	10
valid_sources[0x65]	30256	1			T1	10		T2	352		T3	8
valid_sources[0x66]	26375	1			T1	11		T2	326		T3	10
valid_sources[0x67]	28655	1			T1	9		T2	339		T3	5
valid_sources[0x68]	25690	1			T1	11		T2	372		T3	13
valid_sources[0x69]	34972	1			T1	11		T2	355		T3	4
valid_sources[0x6a]	26639	1			T1	3		T2	306		T3	12
valid_sources[0x6b]	27913	1			T1	5		T2	368		T3	12
valid_sources[0x6c]	26741	1			T1	11		T2	390		T3	14
valid_sources[0x6d]	26983	1			T1	16		T2	348		T3	5
valid_sources[0x6e]	24524	1			T1	17		T2	343		T3	10
valid_sources[0x6f]	27292	1			T1	10		T2	345		T3	9
valid_sources[0x70]	31064	1			T1	9		T2	370		T3	10
valid_sources[0x71]	31850	1			T1	12		T2	329		T3	6
valid_sources[0x72]	26826	1			T1	13		T2	331		T3	16
valid_sources[0x73]	25875	1			T1	8		T2	343		T3	11
valid_sources[0x74]	27598	1			T1	21		T2	351		T3	8
valid_sources[0x75]	25274	1			T1	9		T2	320		T3	11
valid_sources[0x76]	26186	1			T1	12		T2	323		T3	10
valid_sources[0x77]	29218	1			T1	11		T2	363		T3	10
valid_sources[0x78]	26397	1			T1	12		T2	375		T3	7
valid_sources[0x79]	29566	1			T1	7		T2	344		T3	4
valid_sources[0x7a]	28679	1			T1	19		T2	332		T3	13
valid_sources[0x7b]	26945	1			T1	11		T2	328		T3	11
valid_sources[0x7c]	30838	1			T1	18		T2	333		T3	11
valid_sources[0x7d]	27261	1			T1	6		T2	372		T3	10
valid_sources[0x7e]	27276	1			T1	10		T2	368		T3	13
valid_sources[0x7f]	27312	1			T1	8		T2	337		T3	6
valid_sources[0x80]	28853	1			T1	12		T2	319		T3	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

945902

1

T1

242

T2

4063

T3

746

values[0x0]

all_enables

biggest_size

1482704

1

T1

295

T2

15390

T3

442

values[0x1]

all_enables

biggest_size

1459224

1

T1

255

T2

15255

T3

465