Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3433205

1

T1

2253

T2

53158

T3

764

full_word

3886752

1

T1

792

T2

34708

T3

1653

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7319567	1			T1	3045		T2	87866		T3	2417
auto[TlIntgErrCmd]	122	1			T81	3		T84	8		T85	8
auto[TlIntgErrData]	124	1			T81	4		T84	13		T85	10
auto[TlIntgErrBoth]	144	1			T81	3		T84	9		T85	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4043039

1

T1

2278

T2

51906

T3

1506

auto[1]

3276918

1

T1

767

T2

35960

T3

911

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3096910	1			T1	2036		T2	47843		T3	760
auto[TlIntgErrNone]	partial	auto[1]	335938	1			T1	217		T2	5315		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	945958	1			T1	242		T2	4063		T3	746
auto[TlIntgErrNone]	full_word	auto[1]	2940761	1			T1	550		T2	30645		T3	907
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T81	2		T84	1		T85	4
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T81	1		T84	6		T85	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T96	1		T138	1		T236	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T84	1		T100	2		T237	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T81	2		T84	9		T85	6
auto[TlIntgErrData]	partial	auto[1]	52	1			T81	2		T84	3		T85	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T84	1		T96	1		T238	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T239	2		T240	1		T241	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T81	2		T84	4		T85	5
auto[TlIntgErrBoth]	partial	auto[1]	75	1			T81	1		T84	5		T85	7
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T100	1		T239	1		T235	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T99	1		T98	1		T100	1