Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409598004	2525216	0	0
DepthKnown_A	409598004	409472392	0	0
RvalidKnown_A	409598004	409472392	0	0
WreadyKnown_A	409598004	409472392	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	2525216	0	0
T2	417688	14969	0	0
T3	46004	832	0	0
T4	347744	12476	0	0
T5	270543	12476	0	0
T6	20014	832	0	0
T7	43541	1663	0	0
T8	144661	11644	0	0
T9	145909	14137	0	0
T10	187620	832	0	0
T11	417869	0	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409598004	2882592	0	0
DepthKnown_A	409598004	409472392	0	0
RvalidKnown_A	409598004	409472392	0	0
WreadyKnown_A	409598004	409472392	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	2882592	0	0
T2	417688	9152	0	0
T3	46004	3706	0	0
T4	347744	9152	0	0
T5	270543	9152	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	8320	0	0
T9	145909	13315	0	0
T10	187620	832	0	0
T11	417869	0	0	0
T12	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409598004	178117	0	0
DepthKnown_A	409598004	409472392	0	0
RvalidKnown_A	409598004	409472392	0	0
WreadyKnown_A	409598004	409472392	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	178117	0	0
T1	177087	201	0	0
T2	417688	1057	0	0
T3	46004	0	0	0
T4	347744	550	0	0
T5	270543	2277	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	1408	0	0
T9	145909	979	0	0
T10	187620	0	0	0
T11	0	380	0	0
T24	0	30	0	0
T26	0	1404	0	0
T27	0	884	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409598004	401689	0	0
DepthKnown_A	409598004	409472392	0	0
RvalidKnown_A	409598004	409472392	0	0
WreadyKnown_A	409598004	409472392	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	401689	0	0
T1	177087	920	0	0
T2	417688	1056	0	0
T3	46004	0	0	0
T4	347744	550	0	0
T5	270543	2275	0	0
T6	20014	0	0	0
T7	43541	0	0	0
T8	144661	1408	0	0
T9	145909	3079	0	0
T10	187620	0	0	0
T11	0	380	0	0
T24	0	30	0	0
T26	0	5995	0	0
T27	0	4023	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409598004	5852859	0	0
DepthKnown_A	409598004	409472392	0	0
RvalidKnown_A	409598004	409472392	0	0
WreadyKnown_A	409598004	409472392	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	5852859	0	0
T1	177087	2956	0	0
T2	417688	78087	0	0
T3	46004	1585	0	0
T4	347744	5641	0	0
T5	270543	51535	0	0
T6	20014	52	0	0
T7	43541	293	0	0
T8	144661	29180	0	0
T9	145909	30022	0	0
T10	187620	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	409598004	12419875	0	0
DepthKnown_A	409598004	409472392	0	0
RvalidKnown_A	409598004	409472392	0	0
WreadyKnown_A	409598004	409472392	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	12419875	0	0
T1	177087	12445	0	0
T2	417688	77658	0	0
T3	46004	6961	0	0
T4	347744	5641	0	0
T5	270543	51273	0	0
T6	20014	52	0	0
T7	43541	293	0	0
T8	144661	29018	0	0
T9	145909	87065	0	0
T10	187620	290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409598004	409472392	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0