Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	671365752	537987866	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	671365752	3324431	0	0
GntImpliesValid_A	671365752	3324431	0	0
GrantKnown_A	671365752	537987866	0	0
IdxKnown_A	671365752	537987866	0	0
IndexIsCorrect_A	671365752	3324431	0	0
LockArbDecision_A	671365752	0	0	0
NoReadyValidNoGrant_A	671365752	0	0	0
ReadyAndValidImplyGrant_A	671365752	3324431	0	0
ReqAndReadyImplyGrant_A	671365752	3324431	0	0
ReqImpliesValid_A	671365752	3324431	0	0
ReqStaysHighUntilGranted0_M	671365752	0	0	0
RoundRobin_A	671365752	3	0	926
ValidKnown_A	671365752	537987866	0	0
gen_data_port_assertion.DataFlow_A	671365752	3324431	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	537987866	0	0
T1	199537	197686	0	0
T2	623218	1435222	0	0
T3	69280	57567	0	0
T4	1197426	767850	0	0
T5	471539	1259482	0	0
T6	37266	28563	0	0
T7	63857	53607	0	0
T8	1483825	802205	0	0
T9	1121169	628345	0	0
T10	276516	231992	0	0
T11	52968	49664	0	0
T12	0	22851	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3324431	0	0
T1	199537	1549	0	0
T2	623218	21108	0	0
T3	69280	832	0	0
T4	1197426	15848	0	0
T5	471539	26881	0	0
T6	37266	832	0	0
T7	63857	832	0	0
T8	1483825	18543	0	0
T9	1121169	16427	0	0
T10	276516	832	0	0
T11	52968	2165	0	0
T13	0	7414	0	0
T24	0	143	0	0
T26	0	11192	0	0
T27	0	9383	0	0
T36	0	1234	0	0
T40	0	6644	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3324431	0	0
T1	199537	1549	0	0
T2	623218	21108	0	0
T3	69280	832	0	0
T4	1197426	15848	0	0
T5	471539	26881	0	0
T6	37266	832	0	0
T7	63857	832	0	0
T8	1483825	18543	0	0
T9	1121169	16427	0	0
T10	276516	832	0	0
T11	52968	2165	0	0
T13	0	7414	0	0
T24	0	143	0	0
T26	0	11192	0	0
T27	0	9383	0	0
T36	0	1234	0	0
T40	0	6644	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	537987866	0	0
T1	199537	197686	0	0
T2	623218	1435222	0	0
T3	69280	57567	0	0
T4	1197426	767850	0	0
T5	471539	1259482	0	0
T6	37266	28563	0	0
T7	63857	53607	0	0
T8	1483825	802205	0	0
T9	1121169	628345	0	0
T10	276516	231992	0	0
T11	52968	49664	0	0
T12	0	22851	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	537987866	0	0
T1	199537	197686	0	0
T2	623218	1435222	0	0
T3	69280	57567	0	0
T4	1197426	767850	0	0
T5	471539	1259482	0	0
T6	37266	28563	0	0
T7	63857	53607	0	0
T8	1483825	802205	0	0
T9	1121169	628345	0	0
T10	276516	231992	0	0
T11	52968	49664	0	0
T12	0	22851	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3324431	0	0
T1	199537	1549	0	0
T2	623218	21108	0	0
T3	69280	832	0	0
T4	1197426	15848	0	0
T5	471539	26881	0	0
T6	37266	832	0	0
T7	63857	832	0	0
T8	1483825	18543	0	0
T9	1121169	16427	0	0
T10	276516	832	0	0
T11	52968	2165	0	0
T13	0	7414	0	0
T24	0	143	0	0
T26	0	11192	0	0
T27	0	9383	0	0
T36	0	1234	0	0
T40	0	6644	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3324431	0	0
T1	199537	1549	0	0
T2	623218	21108	0	0
T3	69280	832	0	0
T4	1197426	15848	0	0
T5	471539	26881	0	0
T6	37266	832	0	0
T7	63857	832	0	0
T8	1483825	18543	0	0
T9	1121169	16427	0	0
T10	276516	832	0	0
T11	52968	2165	0	0
T13	0	7414	0	0
T24	0	143	0	0
T26	0	11192	0	0
T27	0	9383	0	0
T36	0	1234	0	0
T40	0	6644	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3324431	0	0
T1	199537	1549	0	0
T2	623218	21108	0	0
T3	69280	832	0	0
T4	1197426	15848	0	0
T5	471539	26881	0	0
T6	37266	832	0	0
T7	63857	832	0	0
T8	1483825	18543	0	0
T9	1121169	16427	0	0
T10	276516	832	0	0
T11	52968	2165	0	0
T13	0	7414	0	0
T24	0	143	0	0
T26	0	11192	0	0
T27	0	9383	0	0
T36	0	1234	0	0
T40	0	6644	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3324431	0	0
T1	199537	1549	0	0
T2	623218	21108	0	0
T3	69280	832	0	0
T4	1197426	15848	0	0
T5	471539	26881	0	0
T6	37266	832	0	0
T7	63857	832	0	0
T8	1483825	18543	0	0
T9	1121169	16427	0	0
T10	276516	832	0	0
T11	52968	2165	0	0
T13	0	7414	0	0
T24	0	143	0	0
T26	0	11192	0	0
T27	0	9383	0	0
T36	0	1234	0	0
T40	0	6644	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3	0	926
T41	559054	2	0	1
T42	0	1	0	0
T43	5959	0	0	1
T44	144022	0	0	1
T45	37154	0	0	1
T46	193862	0	0	1
T47	1338	0	0	1
T48	314192	0	0	1
T49	5538	0	0	1
T50	391263	0	0	1
T51	322672	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	537987866	0	0
T1	199537	197686	0	0
T2	623218	1435222	0	0
T3	69280	57567	0	0
T4	1197426	767850	0	0
T5	471539	1259482	0	0
T6	37266	28563	0	0
T7	63857	53607	0	0
T8	1483825	802205	0	0
T9	1121169	628345	0	0
T10	276516	231992	0	0
T11	52968	49664	0	0
T12	0	22851	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671365752	3324431	0	0
T1	199537	1549	0	0
T2	623218	21108	0	0
T3	69280	832	0	0
T4	1197426	15848	0	0
T5	471539	26881	0	0
T6	37266	832	0	0
T7	63857	832	0	0
T8	1483825	18543	0	0
T9	1121169	16427	0	0
T10	276516	832	0	0
T11	52968	2165	0	0
T13	0	7414	0	0
T24	0	143	0	0
T26	0	11192	0	0
T27	0	9383	0	0
T36	0	1234	0	0
T40	0	6644	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Unreachable
1	1	Covered	T1,T2,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132035216	26980481	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	132035216	595790	0	0
GntImpliesValid_A	132035216	595790	0	0
GrantKnown_A	132035216	26980481	0	0
IdxKnown_A	132035216	26980481	0	0
IndexIsCorrect_A	132035216	595790	0	0
LockArbDecision_A	132035216	0	0	0
NoReadyValidNoGrant_A	132035216	0	0	0
ReadyAndValidImplyGrant_A	132035216	595790	0	0
ReqAndReadyImplyGrant_A	132035216	595790	0	0
ReqImpliesValid_A	132035216	595790	0	0
ReqStaysHighUntilGranted0_M	132035216	0	0	0
RoundRobin_A	132035216	0	0	0
ValidKnown_A	132035216	26980481	0	0
gen_data_port_assertion.DataFlow_A	132035216	595790	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	26980481	0	0
T1	22450	20680	0	0
T2	102765	100952	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	250104	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	159080	0	0
T9	487630	128792	0	0
T10	44448	0	0	0
T11	0	49664	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	595790	0	0
T1	22450	1074	0	0
T2	102765	4115	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	9972	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	5803	0	0
T9	487630	4734	0	0
T10	44448	0	0	0
T11	0	2165	0	0
T24	0	143	0	0
T26	0	3879	0	0
T27	0	2997	0	0
T40	0	3881	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	595790	0	0
T1	22450	1074	0	0
T2	102765	4115	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	9972	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	5803	0	0
T9	487630	4734	0	0
T10	44448	0	0	0
T11	0	2165	0	0
T24	0	143	0	0
T26	0	3879	0	0
T27	0	2997	0	0
T40	0	3881	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	26980481	0	0
T1	22450	20680	0	0
T2	102765	100952	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	250104	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	159080	0	0
T9	487630	128792	0	0
T10	44448	0	0	0
T11	0	49664	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	26980481	0	0
T1	22450	20680	0	0
T2	102765	100952	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	250104	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	159080	0	0
T9	487630	128792	0	0
T10	44448	0	0	0
T11	0	49664	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	595790	0	0
T1	22450	1074	0	0
T2	102765	4115	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	9972	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	5803	0	0
T9	487630	4734	0	0
T10	44448	0	0	0
T11	0	2165	0	0
T24	0	143	0	0
T26	0	3879	0	0
T27	0	2997	0	0
T40	0	3881	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	595790	0	0
T1	22450	1074	0	0
T2	102765	4115	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	9972	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	5803	0	0
T9	487630	4734	0	0
T10	44448	0	0	0
T11	0	2165	0	0
T24	0	143	0	0
T26	0	3879	0	0
T27	0	2997	0	0
T40	0	3881	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	595790	0	0
T1	22450	1074	0	0
T2	102765	4115	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	9972	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	5803	0	0
T9	487630	4734	0	0
T10	44448	0	0	0
T11	0	2165	0	0
T24	0	143	0	0
T26	0	3879	0	0
T27	0	2997	0	0
T40	0	3881	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	595790	0	0
T1	22450	1074	0	0
T2	102765	4115	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	9972	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	5803	0	0
T9	487630	4734	0	0
T10	44448	0	0	0
T11	0	2165	0	0
T24	0	143	0	0
T26	0	3879	0	0
T27	0	2997	0	0
T40	0	3881	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	26980481	0	0
T1	22450	20680	0	0
T2	102765	100952	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	250104	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	159080	0	0
T9	487630	128792	0	0
T10	44448	0	0	0
T11	0	49664	0	0
T24	0	2072	0	0
T25	0	504	0	0
T26	0	334768	0	0
T27	0	67360	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	595790	0	0
T1	22450	1074	0	0
T2	102765	4115	0	0
T3	11638	0	0	0
T4	424841	0	0	0
T5	100498	9972	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	5803	0	0
T9	487630	4734	0	0
T10	44448	0	0	0
T11	0	2165	0	0
T24	0	143	0	0
T26	0	3879	0	0
T27	0	2997	0	0
T40	0	3881	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	132035216	103792977	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	132035216	702720	0	0
GntImpliesValid_A	132035216	702720	0	0
GrantKnown_A	132035216	103792977	0	0
IdxKnown_A	132035216	103792977	0	0
IndexIsCorrect_A	132035216	702720	0	0
LockArbDecision_A	132035216	0	0	0
NoReadyValidNoGrant_A	132035216	0	0	0
ReadyAndValidImplyGrant_A	132035216	702720	0	0
ReqAndReadyImplyGrant_A	132035216	702720	0	0
ReqImpliesValid_A	132035216	702720	0	0
ReqStaysHighUntilGranted0_M	132035216	0	0	0
RoundRobin_A	132035216	0	0	0
ValidKnown_A	132035216	103792977	0	0
gen_data_port_assertion.DataFlow_A	132035216	702720	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	103792977	0	0
T2	102765	916588	0	0
T3	11638	11638	0	0
T4	424841	420111	0	0
T5	100498	738856	0	0
T6	8626	8626	0	0
T7	10158	10158	0	0
T8	669582	498470	0	0
T9	487630	353654	0	0
T10	44448	44448	0	0
T11	52968	0	0	0
T12	0	22851	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	702720	0	0
T2	102765	5697	0	0
T3	11638	0	0	0
T4	424841	6117	0	0
T5	100498	2582	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	1550	0	0
T9	487630	799	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	7414	0	0
T26	0	7313	0	0
T27	0	6386	0	0
T36	0	1234	0	0
T40	0	2763	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	702720	0	0
T2	102765	5697	0	0
T3	11638	0	0	0
T4	424841	6117	0	0
T5	100498	2582	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	1550	0	0
T9	487630	799	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	7414	0	0
T26	0	7313	0	0
T27	0	6386	0	0
T36	0	1234	0	0
T40	0	2763	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	103792977	0	0
T2	102765	916588	0	0
T3	11638	11638	0	0
T4	424841	420111	0	0
T5	100498	738856	0	0
T6	8626	8626	0	0
T7	10158	10158	0	0
T8	669582	498470	0	0
T9	487630	353654	0	0
T10	44448	44448	0	0
T11	52968	0	0	0
T12	0	22851	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	103792977	0	0
T2	102765	916588	0	0
T3	11638	11638	0	0
T4	424841	420111	0	0
T5	100498	738856	0	0
T6	8626	8626	0	0
T7	10158	10158	0	0
T8	669582	498470	0	0
T9	487630	353654	0	0
T10	44448	44448	0	0
T11	52968	0	0	0
T12	0	22851	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	702720	0	0
T2	102765	5697	0	0
T3	11638	0	0	0
T4	424841	6117	0	0
T5	100498	2582	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	1550	0	0
T9	487630	799	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	7414	0	0
T26	0	7313	0	0
T27	0	6386	0	0
T36	0	1234	0	0
T40	0	2763	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	702720	0	0
T2	102765	5697	0	0
T3	11638	0	0	0
T4	424841	6117	0	0
T5	100498	2582	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	1550	0	0
T9	487630	799	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	7414	0	0
T26	0	7313	0	0
T27	0	6386	0	0
T36	0	1234	0	0
T40	0	2763	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	702720	0	0
T2	102765	5697	0	0
T3	11638	0	0	0
T4	424841	6117	0	0
T5	100498	2582	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	1550	0	0
T9	487630	799	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	7414	0	0
T26	0	7313	0	0
T27	0	6386	0	0
T36	0	1234	0	0
T40	0	2763	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	702720	0	0
T2	102765	5697	0	0
T3	11638	0	0	0
T4	424841	6117	0	0
T5	100498	2582	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	1550	0	0
T9	487630	799	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	7414	0	0
T26	0	7313	0	0
T27	0	6386	0	0
T36	0	1234	0	0
T40	0	2763	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	103792977	0	0
T2	102765	916588	0	0
T3	11638	11638	0	0
T4	424841	420111	0	0
T5	100498	738856	0	0
T6	8626	8626	0	0
T7	10158	10158	0	0
T8	669582	498470	0	0
T9	487630	353654	0	0
T10	44448	44448	0	0
T11	52968	0	0	0
T12	0	22851	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132035216	702720	0	0
T2	102765	5697	0	0
T3	11638	0	0	0
T4	424841	6117	0	0
T5	100498	2582	0	0
T6	8626	0	0	0
T7	10158	0	0	0
T8	669582	1550	0	0
T9	487630	799	0	0
T10	44448	0	0	0
T11	52968	0	0	0
T13	0	7414	0	0
T26	0	7313	0	0
T27	0	6386	0	0
T36	0	1234	0	0
T40	0	2763	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	407295320	407214408	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	407295320	2025921	0	0
GntImpliesValid_A	407295320	2025921	0	0
GrantKnown_A	407295320	407214408	0	0
IdxKnown_A	407295320	407214408	0	0
IndexIsCorrect_A	407295320	2025921	0	0
LockArbDecision_A	407295320	0	0	0
NoReadyValidNoGrant_A	407295320	0	0	0
ReadyAndValidImplyGrant_A	407295320	2025921	0	0
ReqAndReadyImplyGrant_A	407295320	2025921	0	0
ReqImpliesValid_A	407295320	2025921	0	0
ReqStaysHighUntilGranted0_M	407295320	0	0	0
RoundRobin_A	407295320	3	0	926
ValidKnown_A	407295320	407214408	0	0
gen_data_port_assertion.DataFlow_A	407295320	2025921	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2025921	0	0
T1	177087	475	0	0
T2	417688	11296	0	0
T3	46004	832	0	0
T4	347744	9731	0	0
T5	270543	14327	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	11190	0	0
T9	145909	10894	0	0
T10	187620	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2025921	0	0
T1	177087	475	0	0
T2	417688	11296	0	0
T3	46004	832	0	0
T4	347744	9731	0	0
T5	270543	14327	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	11190	0	0
T9	145909	10894	0	0
T10	187620	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2025921	0	0
T1	177087	475	0	0
T2	417688	11296	0	0
T3	46004	832	0	0
T4	347744	9731	0	0
T5	270543	14327	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	11190	0	0
T9	145909	10894	0	0
T10	187620	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2025921	0	0
T1	177087	475	0	0
T2	417688	11296	0	0
T3	46004	832	0	0
T4	347744	9731	0	0
T5	270543	14327	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	11190	0	0
T9	145909	10894	0	0
T10	187620	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2025921	0	0
T1	177087	475	0	0
T2	417688	11296	0	0
T3	46004	832	0	0
T4	347744	9731	0	0
T5	270543	14327	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	11190	0	0
T9	145909	10894	0	0
T10	187620	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2025921	0	0
T1	177087	475	0	0
T2	417688	11296	0	0
T3	46004	832	0	0
T4	347744	9731	0	0
T5	270543	14327	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	11190	0	0
T9	145909	10894	0	0
T10	187620	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	3	0	926
T41	559054	2	0	1
T42	0	1	0	0
T43	5959	0	0	1
T44	144022	0	0	1
T45	37154	0	0	1
T46	193862	0	0	1
T47	1338	0	0	1
T48	314192	0	0	1
T49	5538	0	0	1
T50	391263	0	0	1
T51	322672	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	407214408	0	0
T1	177087	177006	0	0
T2	417688	417682	0	0
T3	46004	45929	0	0
T4	347744	347739	0	0
T5	270543	270522	0	0
T6	20014	19937	0	0
T7	43541	43449	0	0
T8	144661	144655	0	0
T9	145909	145899	0	0
T10	187620	187544	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407295320	2025921	0	0
T1	177087	475	0	0
T2	417688	11296	0	0
T3	46004	832	0	0
T4	347744	9731	0	0
T5	270543	14327	0	0
T6	20014	832	0	0
T7	43541	832	0	0
T8	144661	11190	0	0
T9	145909	10894	0	0
T10	187620	832	0	0