Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.20


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1012 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1376521760 Jun 21 06:59:00 PM PDT 24 Jun 21 06:59:04 PM PDT 24 30685164 ps
T1013 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.688090048 Jun 21 06:58:47 PM PDT 24 Jun 21 06:58:53 PM PDT 24 102521848 ps
T1014 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2134997351 Jun 21 06:58:30 PM PDT 24 Jun 21 06:58:44 PM PDT 24 1503737386 ps
T240 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3843669549 Jun 21 06:58:21 PM PDT 24 Jun 21 06:58:47 PM PDT 24 2146683126 ps
T1015 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2217472943 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:07 PM PDT 24 38746464 ps
T111 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2137764623 Jun 21 06:58:31 PM PDT 24 Jun 21 06:59:17 PM PDT 24 14173186028 ps
T1016 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3742344345 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:55 PM PDT 24 159417757 ps
T1017 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.557100640 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:07 PM PDT 24 80336844 ps
T1018 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1065818226 Jun 21 06:58:19 PM PDT 24 Jun 21 06:58:32 PM PDT 24 30309931 ps
T1019 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3219135454 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:09 PM PDT 24 79045628 ps
T1020 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1706260438 Jun 21 06:58:51 PM PDT 24 Jun 21 06:58:57 PM PDT 24 172056545 ps
T1021 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.610508949 Jun 21 06:58:40 PM PDT 24 Jun 21 06:58:47 PM PDT 24 82177837 ps
T1022 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4058181977 Jun 21 06:58:49 PM PDT 24 Jun 21 06:58:55 PM PDT 24 46123666 ps
T1023 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1500287088 Jun 21 06:58:57 PM PDT 24 Jun 21 06:59:00 PM PDT 24 33745369 ps
T236 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2074249442 Jun 21 06:58:48 PM PDT 24 Jun 21 06:59:12 PM PDT 24 2928358853 ps
T1024 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.480172950 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:07 PM PDT 24 111773447 ps
T1025 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3510406496 Jun 21 06:58:59 PM PDT 24 Jun 21 06:59:04 PM PDT 24 290459189 ps
T112 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3347617169 Jun 21 06:58:38 PM PDT 24 Jun 21 06:58:45 PM PDT 24 54092641 ps
T1026 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1153792908 Jun 21 06:58:47 PM PDT 24 Jun 21 06:58:52 PM PDT 24 96105054 ps
T1027 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4044537286 Jun 21 06:58:51 PM PDT 24 Jun 21 06:58:56 PM PDT 24 184088481 ps
T1028 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3248331326 Jun 21 06:58:58 PM PDT 24 Jun 21 06:59:02 PM PDT 24 18684243 ps
T1029 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3440175468 Jun 21 06:58:39 PM PDT 24 Jun 21 06:58:45 PM PDT 24 57131687 ps
T69 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.254342849 Jun 21 06:58:28 PM PDT 24 Jun 21 06:58:36 PM PDT 24 20471574 ps
T1030 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1640423862 Jun 21 06:58:47 PM PDT 24 Jun 21 06:58:53 PM PDT 24 128443544 ps
T1031 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.95757763 Jun 21 06:58:29 PM PDT 24 Jun 21 06:58:42 PM PDT 24 295508453 ps
T1032 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.959908217 Jun 21 06:58:31 PM PDT 24 Jun 21 06:58:39 PM PDT 24 1029441870 ps
T1033 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2047152480 Jun 21 06:58:20 PM PDT 24 Jun 21 06:58:35 PM PDT 24 163772807 ps
T1034 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.165708429 Jun 21 06:58:49 PM PDT 24 Jun 21 06:58:54 PM PDT 24 14878953 ps
T1035 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1408151664 Jun 21 06:58:44 PM PDT 24 Jun 21 06:58:50 PM PDT 24 178098233 ps
T1036 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.9684852 Jun 21 06:58:59 PM PDT 24 Jun 21 06:59:03 PM PDT 24 28259380 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1994273787 Jun 21 06:58:30 PM PDT 24 Jun 21 06:58:37 PM PDT 24 15527271 ps
T1038 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1405715209 Jun 21 06:58:38 PM PDT 24 Jun 21 06:58:44 PM PDT 24 141324931 ps
T1039 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2496595027 Jun 21 06:58:52 PM PDT 24 Jun 21 06:59:00 PM PDT 24 151008563 ps
T93 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3211239963 Jun 21 06:58:30 PM PDT 24 Jun 21 06:58:41 PM PDT 24 291686406 ps
T1040 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1479730013 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:53 PM PDT 24 54249310 ps
T1041 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2465415996 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:05 PM PDT 24 16580403 ps
T1042 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4047987611 Jun 21 06:58:20 PM PDT 24 Jun 21 06:58:35 PM PDT 24 2537343595 ps
T241 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1452670786 Jun 21 06:58:19 PM PDT 24 Jun 21 06:58:39 PM PDT 24 359796793 ps
T1043 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.175776787 Jun 21 06:58:22 PM PDT 24 Jun 21 06:58:35 PM PDT 24 425647609 ps
T94 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.498065081 Jun 21 06:58:47 PM PDT 24 Jun 21 06:58:55 PM PDT 24 54030441 ps
T70 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3812514617 Jun 21 06:58:32 PM PDT 24 Jun 21 06:58:38 PM PDT 24 16914334 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3778027648 Jun 21 06:58:30 PM PDT 24 Jun 21 06:58:37 PM PDT 24 10967856 ps
T1045 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4290591913 Jun 21 06:58:51 PM PDT 24 Jun 21 06:58:57 PM PDT 24 177021380 ps
T1046 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2980471656 Jun 21 06:58:50 PM PDT 24 Jun 21 06:58:59 PM PDT 24 318833780 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3837819629 Jun 21 06:58:28 PM PDT 24 Jun 21 06:58:48 PM PDT 24 2162969395 ps
T1048 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2157526649 Jun 21 06:58:38 PM PDT 24 Jun 21 06:58:44 PM PDT 24 92503024 ps
T1049 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3097927981 Jun 21 06:58:39 PM PDT 24 Jun 21 06:58:57 PM PDT 24 553078123 ps
T1050 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1352357968 Jun 21 06:58:47 PM PDT 24 Jun 21 06:58:53 PM PDT 24 94923136 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3280244226 Jun 21 06:58:22 PM PDT 24 Jun 21 06:58:36 PM PDT 24 59333806 ps
T1052 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2945266117 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:06 PM PDT 24 32469629 ps
T1053 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2682873959 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:07 PM PDT 24 80062601 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.203833566 Jun 21 06:58:32 PM PDT 24 Jun 21 06:58:39 PM PDT 24 52929890 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3356824162 Jun 21 06:58:32 PM PDT 24 Jun 21 06:58:38 PM PDT 24 87027393 ps
T1056 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3455085078 Jun 21 06:58:39 PM PDT 24 Jun 21 06:58:46 PM PDT 24 216092926 ps
T1057 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4200719952 Jun 21 06:58:50 PM PDT 24 Jun 21 06:59:04 PM PDT 24 373495691 ps
T1058 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1514067712 Jun 21 06:58:57 PM PDT 24 Jun 21 06:59:00 PM PDT 24 12934590 ps
T234 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1407025024 Jun 21 06:58:31 PM PDT 24 Jun 21 06:58:41 PM PDT 24 789206257 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.564831683 Jun 21 06:58:38 PM PDT 24 Jun 21 06:58:45 PM PDT 24 83210969 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3683035484 Jun 21 06:58:38 PM PDT 24 Jun 21 06:58:46 PM PDT 24 87129223 ps
T1061 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3990692359 Jun 21 06:58:30 PM PDT 24 Jun 21 06:58:39 PM PDT 24 64289683 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3340764725 Jun 21 06:58:20 PM PDT 24 Jun 21 06:58:33 PM PDT 24 80239821 ps
T1063 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2850411522 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:55 PM PDT 24 258874331 ps
T1064 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3028519308 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:06 PM PDT 24 23768439 ps
T1065 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2195933462 Jun 21 06:58:58 PM PDT 24 Jun 21 06:59:01 PM PDT 24 91122379 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1141600529 Jun 21 06:58:47 PM PDT 24 Jun 21 06:58:53 PM PDT 24 44741268 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.91260342 Jun 21 06:58:19 PM PDT 24 Jun 21 06:58:32 PM PDT 24 210373134 ps
T1068 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2660067661 Jun 21 06:58:30 PM PDT 24 Jun 21 06:58:37 PM PDT 24 17120434 ps
T1069 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.797175869 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:06 PM PDT 24 49097536 ps
T1070 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1247588205 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:06 PM PDT 24 14099920 ps
T71 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.846092222 Jun 21 06:58:28 PM PDT 24 Jun 21 06:58:36 PM PDT 24 73721492 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.263919055 Jun 21 06:58:21 PM PDT 24 Jun 21 06:58:34 PM PDT 24 339425303 ps
T1072 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3685220223 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:55 PM PDT 24 100559564 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1865209549 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:54 PM PDT 24 144283061 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.342479985 Jun 21 06:58:20 PM PDT 24 Jun 21 06:58:32 PM PDT 24 22656526 ps
T1075 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.330105235 Jun 21 06:58:58 PM PDT 24 Jun 21 06:59:01 PM PDT 24 13774874 ps
T1076 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.951806504 Jun 21 06:58:57 PM PDT 24 Jun 21 06:59:01 PM PDT 24 903322811 ps
T1077 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.678554037 Jun 21 06:58:32 PM PDT 24 Jun 21 06:58:51 PM PDT 24 10461104472 ps
T1078 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4018079651 Jun 21 06:58:59 PM PDT 24 Jun 21 06:59:03 PM PDT 24 38212436 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2960748008 Jun 21 06:58:50 PM PDT 24 Jun 21 06:58:56 PM PDT 24 44060881 ps
T1080 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1195834103 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:56 PM PDT 24 60390761 ps
T1081 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3564440066 Jun 21 06:59:00 PM PDT 24 Jun 21 06:59:05 PM PDT 24 37454448 ps
T1082 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.44589247 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:06 PM PDT 24 15488639 ps
T1083 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4276350225 Jun 21 06:58:48 PM PDT 24 Jun 21 06:59:15 PM PDT 24 3277224136 ps
T1084 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2423294284 Jun 21 06:58:59 PM PDT 24 Jun 21 06:59:02 PM PDT 24 113933470 ps
T1085 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1208934113 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:07 PM PDT 24 198432046 ps
T1086 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1084686174 Jun 21 06:58:20 PM PDT 24 Jun 21 06:59:07 PM PDT 24 7543943610 ps
T1087 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2068622197 Jun 21 06:58:29 PM PDT 24 Jun 21 06:58:38 PM PDT 24 96149117 ps
T1088 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.615693036 Jun 21 06:58:50 PM PDT 24 Jun 21 06:58:58 PM PDT 24 371195753 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3980729614 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:55 PM PDT 24 42833541 ps
T1090 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3095571983 Jun 21 06:58:22 PM PDT 24 Jun 21 06:59:06 PM PDT 24 1184553254 ps
T1091 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.180913886 Jun 21 06:59:02 PM PDT 24 Jun 21 06:59:07 PM PDT 24 28590787 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4261050579 Jun 21 06:58:21 PM PDT 24 Jun 21 06:58:33 PM PDT 24 29376102 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.819832770 Jun 21 06:58:37 PM PDT 24 Jun 21 06:58:43 PM PDT 24 280141451 ps
T1094 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1697072974 Jun 21 06:58:51 PM PDT 24 Jun 21 06:59:00 PM PDT 24 57141457 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2954960965 Jun 21 06:58:48 PM PDT 24 Jun 21 06:58:56 PM PDT 24 324641906 ps
T1096 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4211338312 Jun 21 06:58:31 PM PDT 24 Jun 21 06:58:37 PM PDT 24 34349384 ps
T1097 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4057176205 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:06 PM PDT 24 89875534 ps
T1098 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.144731597 Jun 21 06:58:44 PM PDT 24 Jun 21 06:58:52 PM PDT 24 565776958 ps
T1099 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3539915628 Jun 21 06:59:01 PM PDT 24 Jun 21 06:59:06 PM PDT 24 15151511 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1058626360 Jun 21 06:58:27 PM PDT 24 Jun 21 06:58:36 PM PDT 24 84588879 ps
T1101 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1790099815 Jun 21 06:58:50 PM PDT 24 Jun 21 06:58:57 PM PDT 24 122598059 ps

Test location /workspace/coverage/default/19.spi_device_stress_all.1954185344
Short name T5
Test name
Test status
Simulation time 112727300637 ps
CPU time 283.81 seconds
Started Jun 21 07:03:32 PM PDT 24
Finished Jun 21 07:08:23 PM PDT 24
Peak memory 256204 kb
Host smart-b1c4ac10-8c99-4bc7-81cd-6344e7377108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954185344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1954185344
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4034597203
Short name T14
Test name
Test status
Simulation time 62391220694 ps
CPU time 675.15 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:13:47 PM PDT 24
Peak memory 273684 kb
Host smart-21353201-c29b-40e5-b15a-aa4911b0f966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034597203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4034597203
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3592574411
Short name T99
Test name
Test status
Simulation time 1231021022 ps
CPU time 7.53 seconds
Started Jun 21 06:58:58 PM PDT 24
Finished Jun 21 06:59:08 PM PDT 24
Peak memory 215896 kb
Host smart-2997213f-5701-4933-b640-94d3a8c3af32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592574411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3592574411
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.628891897
Short name T13
Test name
Test status
Simulation time 75005322329 ps
CPU time 265.18 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:08:18 PM PDT 24
Peak memory 266324 kb
Host smart-f385c621-cda6-4125-8691-b8bc50d5c6f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628891897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.628891897
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.577855425
Short name T57
Test name
Test status
Simulation time 22873533 ps
CPU time 0.72 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 217128 kb
Host smart-e6ce218d-e428-420e-a7de-7d4a4eda982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577855425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.577855425
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1054593863
Short name T20
Test name
Test status
Simulation time 18456550085 ps
CPU time 182.56 seconds
Started Jun 21 07:03:48 PM PDT 24
Finished Jun 21 07:06:59 PM PDT 24
Peak memory 272336 kb
Host smart-9aec3e8d-d89d-4833-afc2-70ce19d782ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054593863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1054593863
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3328709638
Short name T82
Test name
Test status
Simulation time 240174313 ps
CPU time 3.1 seconds
Started Jun 21 06:58:36 PM PDT 24
Finished Jun 21 06:58:44 PM PDT 24
Peak memory 215452 kb
Host smart-32905dbc-2e13-4ae4-94c4-5e9dd9eaf184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328709638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
328709638
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.119707891
Short name T215
Test name
Test status
Simulation time 162027427122 ps
CPU time 1444.47 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:29:12 PM PDT 24
Peak memory 285800 kb
Host smart-0ffe38e0-c22a-4335-a151-296d2f58fd60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119707891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.119707891
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.250962657
Short name T8
Test name
Test status
Simulation time 14466172771 ps
CPU time 181.77 seconds
Started Jun 21 07:04:54 PM PDT 24
Finished Jun 21 07:08:06 PM PDT 24
Peak memory 249552 kb
Host smart-1ad9e925-5d1a-418e-a161-a54c82d3eb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250962657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.250962657
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.534421232
Short name T18
Test name
Test status
Simulation time 133716437 ps
CPU time 0.97 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 236328 kb
Host smart-1ef41938-b4d6-4d25-8481-05ef2a0ad464
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534421232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.534421232
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3649671186
Short name T130
Test name
Test status
Simulation time 5410410064 ps
CPU time 23.73 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:30 PM PDT 24
Peak memory 236224 kb
Host smart-6947fa21-dc5d-43f7-9aa3-0b4068c8ebc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649671186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3649671186
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.432820560
Short name T211
Test name
Test status
Simulation time 100265022123 ps
CPU time 195.89 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:06:42 PM PDT 24
Peak memory 263676 kb
Host smart-ddce37ee-235b-4210-a8df-e3691ae18b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432820560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.432820560
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2536216759
Short name T66
Test name
Test status
Simulation time 7511687460 ps
CPU time 129.48 seconds
Started Jun 21 07:05:05 PM PDT 24
Finished Jun 21 07:07:24 PM PDT 24
Peak memory 269112 kb
Host smart-ae6b4a21-3e39-40d6-9336-6f8c260d442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536216759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2536216759
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.818072035
Short name T167
Test name
Test status
Simulation time 61738456330 ps
CPU time 442.06 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:10:40 PM PDT 24
Peak memory 266684 kb
Host smart-d3d06242-758f-4db6-9761-e7804a04f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818072035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.818072035
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1962720850
Short name T68
Test name
Test status
Simulation time 32223344 ps
CPU time 1.22 seconds
Started Jun 21 06:58:23 PM PDT 24
Finished Jun 21 06:58:34 PM PDT 24
Peak memory 207072 kb
Host smart-a6b20bf3-1b0b-4db4-b995-5f98af48c063
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962720850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1962720850
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3156839066
Short name T2
Test name
Test status
Simulation time 43510605298 ps
CPU time 426.7 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:11:45 PM PDT 24
Peak memory 264292 kb
Host smart-4893fbe4-43db-4bff-aae6-469e641af1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156839066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3156839066
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2831784858
Short name T189
Test name
Test status
Simulation time 46111567914 ps
CPU time 215.9 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:07:15 PM PDT 24
Peak memory 253404 kb
Host smart-1e771ddd-c75f-4b5b-9a32-2b2a9c93533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831784858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2831784858
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.126048316
Short name T166
Test name
Test status
Simulation time 84045657249 ps
CPU time 447.24 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:12:06 PM PDT 24
Peak memory 266212 kb
Host smart-2795e68c-1363-41d3-b7d2-2c843d6ac82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126048316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.126048316
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3879713778
Short name T31
Test name
Test status
Simulation time 115189826 ps
CPU time 1.09 seconds
Started Jun 21 07:02:23 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 217584 kb
Host smart-dff3b44f-d048-4963-896e-5fdbc3b3ce26
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879713778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3879713778
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3741554197
Short name T15
Test name
Test status
Simulation time 541596735739 ps
CPU time 421.24 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:10:46 PM PDT 24
Peak memory 274800 kb
Host smart-919ac876-0ff9-44d6-88cb-267d1e83eb09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741554197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3741554197
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1277495849
Short name T67
Test name
Test status
Simulation time 969158184809 ps
CPU time 406.18 seconds
Started Jun 21 07:04:14 PM PDT 24
Finished Jun 21 07:11:08 PM PDT 24
Peak memory 264988 kb
Host smart-6b3e108b-70d1-4fe2-8067-e934cce3697b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277495849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1277495849
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.47054235
Short name T249
Test name
Test status
Simulation time 261635080968 ps
CPU time 222.6 seconds
Started Jun 21 07:04:09 PM PDT 24
Finished Jun 21 07:08:01 PM PDT 24
Peak memory 251812 kb
Host smart-ccaa00b1-6685-4eef-831f-37fd5e64ad6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47054235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.47054235
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1949039521
Short name T239
Test name
Test status
Simulation time 720472434 ps
CPU time 19.17 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:59:16 PM PDT 24
Peak memory 215396 kb
Host smart-dcfd89bd-070b-4e9f-b8b4-dfa40ea905d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949039521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1949039521
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2844362471
Short name T216
Test name
Test status
Simulation time 42962661742 ps
CPU time 346.22 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:10:17 PM PDT 24
Peak memory 274252 kb
Host smart-5a528b16-42df-4195-ab5d-bccdfcd6be35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844362471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2844362471
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1141600529
Short name T1066
Test name
Test status
Simulation time 44741268 ps
CPU time 2.57 seconds
Started Jun 21 06:58:47 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 215504 kb
Host smart-edd3c5f8-1a5e-4667-9023-3236ed51fcae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141600529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1141600529
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1303053502
Short name T42
Test name
Test status
Simulation time 157520544021 ps
CPU time 453.71 seconds
Started Jun 21 07:04:24 PM PDT 24
Finished Jun 21 07:12:07 PM PDT 24
Peak memory 266736 kb
Host smart-4aeffbd2-4ad9-478b-bed3-6e591930d90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303053502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1303053502
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2193208251
Short name T377
Test name
Test status
Simulation time 46548361 ps
CPU time 0.76 seconds
Started Jun 21 07:03:05 PM PDT 24
Finished Jun 21 07:03:12 PM PDT 24
Peak memory 205732 kb
Host smart-fe4061fc-1e61-44a9-b162-682aff036b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193208251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2193208251
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3719380110
Short name T201
Test name
Test status
Simulation time 103647068450 ps
CPU time 371.81 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:09:01 PM PDT 24
Peak memory 274032 kb
Host smart-f98b7c89-52e5-416e-97b3-f646b9910155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719380110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3719380110
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1007265131
Short name T27
Test name
Test status
Simulation time 646961665710 ps
CPU time 603.44 seconds
Started Jun 21 07:04:25 PM PDT 24
Finished Jun 21 07:14:37 PM PDT 24
Peak memory 267492 kb
Host smart-517d20a5-8443-4b0b-b19e-32d859e64af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007265131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1007265131
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.455631463
Short name T214
Test name
Test status
Simulation time 175326028277 ps
CPU time 465.54 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:11:03 PM PDT 24
Peak memory 283720 kb
Host smart-570df6b1-cf19-41fa-99f2-6be23e1fcee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455631463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.455631463
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4162480078
Short name T56
Test name
Test status
Simulation time 20230378462 ps
CPU time 191.59 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:06:29 PM PDT 24
Peak memory 254068 kb
Host smart-41203336-c569-4028-bfd6-f5aa6e0e8fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162480078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4162480078
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1060639891
Short name T177
Test name
Test status
Simulation time 10191968512 ps
CPU time 60.24 seconds
Started Jun 21 07:03:16 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 257428 kb
Host smart-150671ec-b41f-491e-9d43-a6311ee4e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060639891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1060639891
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2636135275
Short name T288
Test name
Test status
Simulation time 6746252986 ps
CPU time 45.32 seconds
Started Jun 21 07:03:47 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 225628 kb
Host smart-931c66a6-5330-43d3-aaae-a2537100131d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636135275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2636135275
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3941023655
Short name T199
Test name
Test status
Simulation time 15960907715 ps
CPU time 246.9 seconds
Started Jun 21 07:04:02 PM PDT 24
Finished Jun 21 07:08:18 PM PDT 24
Peak memory 274916 kb
Host smart-024afcf4-8da9-4adc-a498-d0266df3feed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941023655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3941023655
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.538486756
Short name T225
Test name
Test status
Simulation time 56716669070 ps
CPU time 224.09 seconds
Started Jun 21 07:04:37 PM PDT 24
Finished Jun 21 07:08:34 PM PDT 24
Peak memory 250176 kb
Host smart-5e960c3e-5505-40e0-a922-05e4079f903f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538486756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.538486756
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3665351466
Short name T6
Test name
Test status
Simulation time 274200053 ps
CPU time 2.67 seconds
Started Jun 21 07:03:19 PM PDT 24
Finished Jun 21 07:03:26 PM PDT 24
Peak memory 225512 kb
Host smart-b2e14e2c-b295-4dfd-a68d-9f56536b7841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665351466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3665351466
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2074249442
Short name T236
Test name
Test status
Simulation time 2928358853 ps
CPU time 19.38 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:59:12 PM PDT 24
Peak memory 215556 kb
Host smart-89455f17-76d2-4522-8404-c4457f6c8140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074249442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2074249442
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.4145412668
Short name T209
Test name
Test status
Simulation time 71565454881 ps
CPU time 686.57 seconds
Started Jun 21 07:02:59 PM PDT 24
Finished Jun 21 07:14:32 PM PDT 24
Peak memory 271744 kb
Host smart-3e4e0ca4-9d9c-4460-8dae-cb901ce5a7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145412668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.4145412668
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4230376745
Short name T154
Test name
Test status
Simulation time 5148801677 ps
CPU time 95.77 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:05:05 PM PDT 24
Peak memory 250360 kb
Host smart-35dd72ab-b90d-4050-ae2d-4bf7d732b672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230376745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4230376745
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2296722747
Short name T78
Test name
Test status
Simulation time 866169053 ps
CPU time 9.55 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 225516 kb
Host smart-69922f8d-ff8d-42e2-a43d-3f595ee02069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296722747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2296722747
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1349509874
Short name T34
Test name
Test status
Simulation time 4691137618 ps
CPU time 20.04 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 233868 kb
Host smart-db61671f-5b71-4c65-9d74-593c5f05e892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349509874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1349509874
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.202722362
Short name T89
Test name
Test status
Simulation time 51244398 ps
CPU time 1.57 seconds
Started Jun 21 06:58:49 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 207316 kb
Host smart-7004fc81-c0f5-4c8b-9a43-c5bab77132e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202722362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.202722362
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2559849183
Short name T84
Test name
Test status
Simulation time 289606226 ps
CPU time 17.45 seconds
Started Jun 21 06:58:31 PM PDT 24
Finished Jun 21 06:58:54 PM PDT 24
Peak memory 215408 kb
Host smart-5e68f494-9285-4e90-aec9-f2a309122fef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559849183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2559849183
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3318965967
Short name T126
Test name
Test status
Simulation time 332287246887 ps
CPU time 805.51 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:15:58 PM PDT 24
Peak memory 264944 kb
Host smart-dfa8d587-cd2e-4dda-8c8f-9a7767a6b9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318965967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3318965967
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3815375676
Short name T114
Test name
Test status
Simulation time 6663055664 ps
CPU time 55.87 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:04:03 PM PDT 24
Peak memory 242116 kb
Host smart-cc3ddd10-6667-4d49-af5d-61696b37ba84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815375676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3815375676
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2072454378
Short name T292
Test name
Test status
Simulation time 159321084 ps
CPU time 5.6 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:03:35 PM PDT 24
Peak memory 233772 kb
Host smart-8da508c7-bbc3-42a9-b116-faf0bd71e091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072454378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2072454378
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2620684520
Short name T203
Test name
Test status
Simulation time 820853569 ps
CPU time 3.72 seconds
Started Jun 21 07:03:43 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 233752 kb
Host smart-426e555f-9103-478a-be2a-2c28141b8671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620684520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2620684520
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1739984552
Short name T300
Test name
Test status
Simulation time 3740011677 ps
CPU time 22.31 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:05:23 PM PDT 24
Peak memory 224608 kb
Host smart-858e8875-cad9-4fb6-b60d-b8e984360341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739984552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1739984552
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2682876081
Short name T182
Test name
Test status
Simulation time 9504482681 ps
CPU time 90.53 seconds
Started Jun 21 07:04:57 PM PDT 24
Finished Jun 21 07:06:37 PM PDT 24
Peak memory 270184 kb
Host smart-e03c5092-c1e1-4ed5-ab66-a7ed0cc4fd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682876081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2682876081
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1962318295
Short name T219
Test name
Test status
Simulation time 39455543273 ps
CPU time 48.73 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:03:36 PM PDT 24
Peak memory 234812 kb
Host smart-0bffb2c4-7413-4dc5-bac4-a7cdc8bf77c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962318295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1962318295
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3118911904
Short name T29
Test name
Test status
Simulation time 8063399388 ps
CPU time 166.6 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:06:04 PM PDT 24
Peak memory 268488 kb
Host smart-ffa0bb92-582e-4c99-b796-1c79688a5a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118911904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3118911904
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3098678585
Short name T105
Test name
Test status
Simulation time 2256842590 ps
CPU time 8.87 seconds
Started Jun 21 06:58:21 PM PDT 24
Finished Jun 21 06:58:41 PM PDT 24
Peak memory 207108 kb
Host smart-28f501a0-ba43-4052-99d2-5670b8431325
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098678585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3098678585
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3095571983
Short name T1090
Test name
Test status
Simulation time 1184553254 ps
CPU time 32.83 seconds
Started Jun 21 06:58:22 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 207088 kb
Host smart-1be16c3a-da35-4d77-af67-5a5cc8498d37
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095571983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3095571983
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3280244226
Short name T1051
Test name
Test status
Simulation time 59333806 ps
CPU time 4.19 seconds
Started Jun 21 06:58:22 PM PDT 24
Finished Jun 21 06:58:36 PM PDT 24
Peak memory 218392 kb
Host smart-772c89d7-4279-4a1e-8790-68808c053f7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280244226 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3280244226
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.175776787
Short name T1043
Test name
Test status
Simulation time 425647609 ps
CPU time 2.69 seconds
Started Jun 21 06:58:22 PM PDT 24
Finished Jun 21 06:58:35 PM PDT 24
Peak memory 215360 kb
Host smart-c56b874e-8260-450b-a0e1-b7b7b4b00abf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175776787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.175776787
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1065818226
Short name T1018
Test name
Test status
Simulation time 30309931 ps
CPU time 0.68 seconds
Started Jun 21 06:58:19 PM PDT 24
Finished Jun 21 06:58:32 PM PDT 24
Peak memory 203676 kb
Host smart-f9b5e307-a070-4481-91c4-16b7a4e8db5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065818226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
065818226
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1075186908
Short name T104
Test name
Test status
Simulation time 53173151 ps
CPU time 1.63 seconds
Started Jun 21 06:58:19 PM PDT 24
Finished Jun 21 06:58:33 PM PDT 24
Peak memory 215376 kb
Host smart-b8ffb4a0-cd05-4bb0-9df4-a6b044e03d13
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075186908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1075186908
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.342479985
Short name T1074
Test name
Test status
Simulation time 22656526 ps
CPU time 0.66 seconds
Started Jun 21 06:58:20 PM PDT 24
Finished Jun 21 06:58:32 PM PDT 24
Peak memory 203908 kb
Host smart-adb4375c-7107-4512-a28c-29011dfee562
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342479985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.342479985
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2047152480
Short name T1033
Test name
Test status
Simulation time 163772807 ps
CPU time 4.28 seconds
Started Jun 21 06:58:20 PM PDT 24
Finished Jun 21 06:58:35 PM PDT 24
Peak memory 215344 kb
Host smart-6c01b3cd-6716-4653-8095-051159177159
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047152480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2047152480
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.263919055
Short name T1071
Test name
Test status
Simulation time 339425303 ps
CPU time 2.29 seconds
Started Jun 21 06:58:21 PM PDT 24
Finished Jun 21 06:58:34 PM PDT 24
Peak memory 215604 kb
Host smart-2aa24ede-dced-4199-b07e-6001f74c8cfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263919055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.263919055
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3843669549
Short name T240
Test name
Test status
Simulation time 2146683126 ps
CPU time 14.62 seconds
Started Jun 21 06:58:21 PM PDT 24
Finished Jun 21 06:58:47 PM PDT 24
Peak memory 215420 kb
Host smart-d59571fc-46bb-4fc3-bd72-1773b1e0ccce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843669549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3843669549
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3433179308
Short name T103
Test name
Test status
Simulation time 1308965271 ps
CPU time 8.51 seconds
Started Jun 21 06:58:19 PM PDT 24
Finished Jun 21 06:58:40 PM PDT 24
Peak memory 215296 kb
Host smart-c8084a79-19f1-4096-82b7-dd51b0405e13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433179308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3433179308
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1084686174
Short name T1086
Test name
Test status
Simulation time 7543943610 ps
CPU time 35.37 seconds
Started Jun 21 06:58:20 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 207156 kb
Host smart-92339e8e-624d-4386-89f7-c89987dc00fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084686174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1084686174
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3729083496
Short name T102
Test name
Test status
Simulation time 17304255 ps
CPU time 0.93 seconds
Started Jun 21 06:58:20 PM PDT 24
Finished Jun 21 06:58:33 PM PDT 24
Peak memory 206840 kb
Host smart-39913d4e-f782-4134-9e4c-9d22741d2df0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729083496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3729083496
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3340764725
Short name T1062
Test name
Test status
Simulation time 80239821 ps
CPU time 1.55 seconds
Started Jun 21 06:58:20 PM PDT 24
Finished Jun 21 06:58:33 PM PDT 24
Peak memory 215356 kb
Host smart-38f92393-42b1-4e6e-863e-4263e3edc05e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340764725 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3340764725
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3198065826
Short name T108
Test name
Test status
Simulation time 189158256 ps
CPU time 1.5 seconds
Started Jun 21 06:58:21 PM PDT 24
Finished Jun 21 06:58:33 PM PDT 24
Peak memory 207056 kb
Host smart-c2216754-8714-4bc8-8131-45bae2170e7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198065826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
198065826
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4261050579
Short name T1092
Test name
Test status
Simulation time 29376102 ps
CPU time 0.74 seconds
Started Jun 21 06:58:21 PM PDT 24
Finished Jun 21 06:58:33 PM PDT 24
Peak memory 203652 kb
Host smart-83efc4ff-c556-4280-b53e-9de7de7a072f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261050579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
261050579
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2939652618
Short name T109
Test name
Test status
Simulation time 58960957 ps
CPU time 2.23 seconds
Started Jun 21 06:58:20 PM PDT 24
Finished Jun 21 06:58:34 PM PDT 24
Peak memory 215468 kb
Host smart-4617cf9a-26f6-4ae1-97cb-78afda98c0b6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939652618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2939652618
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1324059699
Short name T1005
Test name
Test status
Simulation time 20405698 ps
CPU time 0.65 seconds
Started Jun 21 06:58:21 PM PDT 24
Finished Jun 21 06:58:32 PM PDT 24
Peak memory 203592 kb
Host smart-a9b69ac0-4490-447d-8087-78702e4f7ffb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324059699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1324059699
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.91260342
Short name T1067
Test name
Test status
Simulation time 210373134 ps
CPU time 1.6 seconds
Started Jun 21 06:58:19 PM PDT 24
Finished Jun 21 06:58:32 PM PDT 24
Peak memory 207220 kb
Host smart-8036ba9b-dc29-4b2d-8440-01a9106bc8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91260342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_same_csr_outstanding.91260342
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4047987611
Short name T1042
Test name
Test status
Simulation time 2537343595 ps
CPU time 3.53 seconds
Started Jun 21 06:58:20 PM PDT 24
Finished Jun 21 06:58:35 PM PDT 24
Peak memory 216552 kb
Host smart-51e53211-4d8e-4dd8-8481-5beb12e48b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047987611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
047987611
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.4016414839
Short name T235
Test name
Test status
Simulation time 617927412 ps
CPU time 18.12 seconds
Started Jun 21 06:58:24 PM PDT 24
Finished Jun 21 06:58:52 PM PDT 24
Peak memory 215520 kb
Host smart-ce9f773f-cc21-468f-bb94-abf22536ba57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016414839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.4016414839
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1706260438
Short name T1020
Test name
Test status
Simulation time 172056545 ps
CPU time 1.64 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 215484 kb
Host smart-bec9fce5-871c-463b-a3e1-74125f78c041
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706260438 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1706260438
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2850411522
Short name T1063
Test name
Test status
Simulation time 258874331 ps
CPU time 1.33 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 207004 kb
Host smart-ffa98077-bcb3-48ff-898e-89e8b4786728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850411522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2850411522
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.165708429
Short name T1034
Test name
Test status
Simulation time 14878953 ps
CPU time 0.67 seconds
Started Jun 21 06:58:49 PM PDT 24
Finished Jun 21 06:58:54 PM PDT 24
Peak memory 203764 kb
Host smart-13b03699-9d17-44f5-af89-7c5ce0b449dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165708429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.165708429
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2002680908
Short name T127
Test name
Test status
Simulation time 220804410 ps
CPU time 3.18 seconds
Started Jun 21 06:58:57 PM PDT 24
Finished Jun 21 06:59:02 PM PDT 24
Peak memory 215420 kb
Host smart-8d736a5d-c750-428f-b19a-5f5349578ea5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002680908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2002680908
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.546282427
Short name T92
Test name
Test status
Simulation time 77707276 ps
CPU time 2.45 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:54 PM PDT 24
Peak memory 215504 kb
Host smart-f8e27650-86a1-4010-9c18-737f7a95d1af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546282427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.546282427
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4065799792
Short name T85
Test name
Test status
Simulation time 582897965 ps
CPU time 18.53 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:59:13 PM PDT 24
Peak memory 215376 kb
Host smart-5403ba0b-c709-4bf2-b290-0484e974f0d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065799792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4065799792
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1195834103
Short name T1080
Test name
Test status
Simulation time 60390761 ps
CPU time 3.78 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:56 PM PDT 24
Peak memory 217752 kb
Host smart-5b1df18a-9bae-476a-83f6-21d74dc49906
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195834103 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1195834103
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1865209549
Short name T1073
Test name
Test status
Simulation time 144283061 ps
CPU time 2.29 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:54 PM PDT 24
Peak memory 207228 kb
Host smart-ddb53e5f-0d2e-4b23-a6d0-cd7b61f7b4bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865209549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1865209549
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.424817831
Short name T987
Test name
Test status
Simulation time 89887161 ps
CPU time 0.75 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 203656 kb
Host smart-308b3893-88a0-4d51-87b0-a309e962315f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424817831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.424817831
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.615693036
Short name T1088
Test name
Test status
Simulation time 371195753 ps
CPU time 2.92 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:58 PM PDT 24
Peak memory 215360 kb
Host smart-23588434-c531-4c8c-a739-eede086d6885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615693036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.615693036
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3685220223
Short name T1072
Test name
Test status
Simulation time 100559564 ps
CPU time 1.93 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 216560 kb
Host smart-7759b18d-c422-4205-b6c2-74c7be3d172d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685220223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3685220223
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2419284139
Short name T81
Test name
Test status
Simulation time 519806537 ps
CPU time 6.46 seconds
Started Jun 21 06:58:46 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 215540 kb
Host smart-ea006ee4-c99a-4d3a-bb1a-34071561b2ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419284139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2419284139
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4100379202
Short name T998
Test name
Test status
Simulation time 163692345 ps
CPU time 3.14 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:58 PM PDT 24
Peak memory 217036 kb
Host smart-b4b1528b-57e7-4597-be7e-9cd8fd1ed527
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100379202 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4100379202
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4290591913
Short name T1045
Test name
Test status
Simulation time 177021380 ps
CPU time 1.41 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 207116 kb
Host smart-911b4927-c9a0-4c1b-abf3-8441e17489e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290591913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4290591913
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.172632472
Short name T1009
Test name
Test status
Simulation time 67875504 ps
CPU time 0.74 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 203680 kb
Host smart-4a48e4f4-0192-47c5-9c99-22f89fc63e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172632472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.172632472
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4020663307
Short name T994
Test name
Test status
Simulation time 163473445 ps
CPU time 4.28 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 215344 kb
Host smart-cd758c4a-6a1f-4193-92c6-78487920f144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020663307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4020663307
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2960748008
Short name T1079
Test name
Test status
Simulation time 44060881 ps
CPU time 1.48 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:56 PM PDT 24
Peak memory 215440 kb
Host smart-b839e6ca-6395-485b-820f-45b7d7cbecea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960748008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2960748008
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4200719952
Short name T1057
Test name
Test status
Simulation time 373495691 ps
CPU time 8.68 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:59:04 PM PDT 24
Peak memory 215248 kb
Host smart-f97fffbd-7ce3-4096-ae9a-6df5f67e03b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200719952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4200719952
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2496595027
Short name T1039
Test name
Test status
Simulation time 151008563 ps
CPU time 3.02 seconds
Started Jun 21 06:58:52 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 217220 kb
Host smart-0b1d6c90-faf5-4b14-982f-493a8cd3654d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496595027 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2496595027
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1833394942
Short name T107
Test name
Test status
Simulation time 278754046 ps
CPU time 1.97 seconds
Started Jun 21 06:58:52 PM PDT 24
Finished Jun 21 06:58:59 PM PDT 24
Peak memory 207092 kb
Host smart-c80c1120-7cbb-4946-8af2-65977ba4c01e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833394942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1833394942
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.69913831
Short name T1001
Test name
Test status
Simulation time 48966943 ps
CPU time 0.72 seconds
Started Jun 21 06:58:49 PM PDT 24
Finished Jun 21 06:58:54 PM PDT 24
Peak memory 203748 kb
Host smart-1c5a97d1-c67f-4cbe-8931-a5914e5631f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69913831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.69913831
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3742344345
Short name T1016
Test name
Test status
Simulation time 159417757 ps
CPU time 1.71 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 215400 kb
Host smart-f78abeab-7a54-4499-9b0d-3fe30856c041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742344345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3742344345
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1697072974
Short name T1094
Test name
Test status
Simulation time 57141457 ps
CPU time 3.66 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 215508 kb
Host smart-5d789903-a854-435f-af50-df30e7f7c74d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697072974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1697072974
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2547111016
Short name T80
Test name
Test status
Simulation time 47567276 ps
CPU time 1.59 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 215372 kb
Host smart-81522ca2-ddf2-47a7-90d7-7847c47557e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547111016 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2547111016
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3980729614
Short name T1089
Test name
Test status
Simulation time 42833541 ps
CPU time 2.64 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 207096 kb
Host smart-ec1d0d8a-6477-4dcd-bf66-07ad2521c138
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980729614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3980729614
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.349662514
Short name T990
Test name
Test status
Simulation time 39477421 ps
CPU time 0.73 seconds
Started Jun 21 06:58:49 PM PDT 24
Finished Jun 21 06:58:54 PM PDT 24
Peak memory 203996 kb
Host smart-660a00e3-53ba-4d99-b9a8-8db1627d751f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349662514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.349662514
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2954960965
Short name T1095
Test name
Test status
Simulation time 324641906 ps
CPU time 3.59 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:56 PM PDT 24
Peak memory 215356 kb
Host smart-d8ed7fef-1911-4610-8bf4-84725d3df16d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954960965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2954960965
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4276350225
Short name T1083
Test name
Test status
Simulation time 3277224136 ps
CPU time 22.33 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:59:15 PM PDT 24
Peak memory 215496 kb
Host smart-2ef5bf3b-def1-4bb3-b201-72d31e00c6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276350225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4276350225
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3834662556
Short name T1006
Test name
Test status
Simulation time 244804292 ps
CPU time 3.23 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 217920 kb
Host smart-b3d5e34e-85e9-4e47-b881-ddf48fab8e9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834662556 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3834662556
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1790099815
Short name T1101
Test name
Test status
Simulation time 122598059 ps
CPU time 2.05 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 207024 kb
Host smart-5c523936-282b-4e4f-a9f7-7a25b5aef38e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790099815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1790099815
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4058181977
Short name T1022
Test name
Test status
Simulation time 46123666 ps
CPU time 0.71 seconds
Started Jun 21 06:58:49 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 203704 kb
Host smart-5a125342-e677-47be-aafb-87e216502cbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058181977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4058181977
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.688090048
Short name T1013
Test name
Test status
Simulation time 102521848 ps
CPU time 1.7 seconds
Started Jun 21 06:58:47 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 215216 kb
Host smart-e97e4312-2ab6-42e3-871d-3d1f19210545
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688090048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.688090048
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1352357968
Short name T1050
Test name
Test status
Simulation time 94923136 ps
CPU time 2.78 seconds
Started Jun 21 06:58:47 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 216884 kb
Host smart-9a3045b1-2574-40f7-9fc0-f97dc26096ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352357968 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1352357968
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1679144980
Short name T1004
Test name
Test status
Simulation time 19676922 ps
CPU time 1.35 seconds
Started Jun 21 06:58:57 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 207072 kb
Host smart-0ccf334e-4757-4fb7-9742-36cf08c91414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679144980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1679144980
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4044537286
Short name T1027
Test name
Test status
Simulation time 184088481 ps
CPU time 0.75 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:58:56 PM PDT 24
Peak memory 203992 kb
Host smart-a89320e2-6711-4dc1-9dad-9b706800a9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044537286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4044537286
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1329122160
Short name T142
Test name
Test status
Simulation time 1012421223 ps
CPU time 3.21 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:56 PM PDT 24
Peak memory 215392 kb
Host smart-e53936c4-4be3-4e6f-9c0e-4dfabd84a1e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329122160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1329122160
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.498065081
Short name T94
Test name
Test status
Simulation time 54030441 ps
CPU time 3.18 seconds
Started Jun 21 06:58:47 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 215436 kb
Host smart-b615f4c4-9833-438d-905c-6cc6a8d8e04e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498065081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.498065081
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1669689468
Short name T96
Test name
Test status
Simulation time 1935457639 ps
CPU time 13.26 seconds
Started Jun 21 06:58:49 PM PDT 24
Finished Jun 21 06:59:08 PM PDT 24
Peak memory 215816 kb
Host smart-56523430-2920-4002-8411-7e7bac5435f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669689468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1669689468
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.458769093
Short name T97
Test name
Test status
Simulation time 371927075 ps
CPU time 1.6 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:56 PM PDT 24
Peak memory 215384 kb
Host smart-43ce1d7e-1ae5-4a68-8f5f-bb4bf7e99953
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458769093 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.458769093
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1153792908
Short name T1026
Test name
Test status
Simulation time 96105054 ps
CPU time 1.22 seconds
Started Jun 21 06:58:47 PM PDT 24
Finished Jun 21 06:58:52 PM PDT 24
Peak memory 215292 kb
Host smart-16c1052a-7277-4b5a-94a0-e1dbb66df91f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153792908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1153792908
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2193364867
Short name T986
Test name
Test status
Simulation time 40652911 ps
CPU time 0.7 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:55 PM PDT 24
Peak memory 203688 kb
Host smart-a94332e3-5179-4903-874d-8af4c60323f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193364867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2193364867
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1640423862
Short name T1030
Test name
Test status
Simulation time 128443544 ps
CPU time 1.76 seconds
Started Jun 21 06:58:47 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 215380 kb
Host smart-8edc6815-366f-43e8-9731-14e0eaa6b6e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640423862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1640423862
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1006367963
Short name T87
Test name
Test status
Simulation time 28476629 ps
CPU time 1.91 seconds
Started Jun 21 06:58:51 PM PDT 24
Finished Jun 21 06:58:58 PM PDT 24
Peak memory 215500 kb
Host smart-890e08ba-f05c-43bc-aeeb-58f3eaf95b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006367963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1006367963
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3072222207
Short name T100
Test name
Test status
Simulation time 2030361645 ps
CPU time 21.01 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:59:14 PM PDT 24
Peak memory 221024 kb
Host smart-4f2adf05-9dcb-4196-915a-223dbc774eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072222207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3072222207
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.528255253
Short name T992
Test name
Test status
Simulation time 25437630 ps
CPU time 1.6 seconds
Started Jun 21 06:58:59 PM PDT 24
Finished Jun 21 06:59:04 PM PDT 24
Peak memory 215632 kb
Host smart-a8c80d54-0f14-4be3-91be-cd649401e544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528255253 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.528255253
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1208934113
Short name T1085
Test name
Test status
Simulation time 198432046 ps
CPU time 1.89 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 215380 kb
Host smart-a316a983-87eb-4d9c-945a-03b5a8ec870e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208934113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1208934113
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1479730013
Short name T1040
Test name
Test status
Simulation time 54249310 ps
CPU time 0.7 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:58:53 PM PDT 24
Peak memory 203724 kb
Host smart-a93d99aa-16bd-4d78-abba-f8bc8d83078c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479730013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1479730013
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2152516241
Short name T141
Test name
Test status
Simulation time 139438685 ps
CPU time 3.03 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:08 PM PDT 24
Peak memory 215404 kb
Host smart-2347574b-3b0f-44a1-be6e-6c2e26ffcd6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152516241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2152516241
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1900276403
Short name T91
Test name
Test status
Simulation time 64031705 ps
CPU time 4.17 seconds
Started Jun 21 06:58:52 PM PDT 24
Finished Jun 21 06:59:01 PM PDT 24
Peak memory 215440 kb
Host smart-a4a29b8b-4845-4697-8e5d-747a63337c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900276403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1900276403
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4147320645
Short name T238
Test name
Test status
Simulation time 2066212166 ps
CPU time 13.27 seconds
Started Jun 21 06:58:48 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 215384 kb
Host smart-2768957a-6adf-403e-8de1-b199d54655fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147320645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4147320645
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3219135454
Short name T1019
Test name
Test status
Simulation time 79045628 ps
CPU time 2.83 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:09 PM PDT 24
Peak memory 217260 kb
Host smart-288606df-5d8a-4431-820b-6aaa7814655c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219135454 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3219135454
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4057176205
Short name T1097
Test name
Test status
Simulation time 89875534 ps
CPU time 1.82 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 215336 kb
Host smart-8c926edd-a860-417e-b080-855ced3b9b3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057176205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4057176205
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2217472943
Short name T1015
Test name
Test status
Simulation time 38746464 ps
CPU time 0.75 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 203992 kb
Host smart-b8c41b06-e036-4595-8250-cad09a4168f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217472943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2217472943
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3510406496
Short name T1025
Test name
Test status
Simulation time 290459189 ps
CPU time 1.94 seconds
Started Jun 21 06:58:59 PM PDT 24
Finished Jun 21 06:59:04 PM PDT 24
Peak memory 215400 kb
Host smart-1814b483-6d44-4ace-92fd-c22d8f625090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510406496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3510406496
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.951806504
Short name T1076
Test name
Test status
Simulation time 903322811 ps
CPU time 1.95 seconds
Started Jun 21 06:58:57 PM PDT 24
Finished Jun 21 06:59:01 PM PDT 24
Peak memory 215492 kb
Host smart-756bb1a0-7993-4c1a-a654-dd4614d2bfeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951806504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.951806504
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.663342186
Short name T988
Test name
Test status
Simulation time 118037483 ps
CPU time 8.31 seconds
Started Jun 21 06:58:28 PM PDT 24
Finished Jun 21 06:58:43 PM PDT 24
Peak memory 215264 kb
Host smart-d3fe8db3-50fe-4e08-8cf5-0164a88bd8cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663342186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.663342186
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2137764623
Short name T111
Test name
Test status
Simulation time 14173186028 ps
CPU time 39.99 seconds
Started Jun 21 06:58:31 PM PDT 24
Finished Jun 21 06:59:17 PM PDT 24
Peak memory 215276 kb
Host smart-68df9e22-2966-43bb-a09c-440f0f5203f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137764623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2137764623
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.846092222
Short name T71
Test name
Test status
Simulation time 73721492 ps
CPU time 1.4 seconds
Started Jun 21 06:58:28 PM PDT 24
Finished Jun 21 06:58:36 PM PDT 24
Peak memory 216304 kb
Host smart-625923e8-2a0d-48b7-b69c-647db6bcb8b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846092222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.846092222
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3843948903
Short name T139
Test name
Test status
Simulation time 106852267 ps
CPU time 1.6 seconds
Started Jun 21 06:58:32 PM PDT 24
Finished Jun 21 06:58:39 PM PDT 24
Peak memory 215328 kb
Host smart-9c36f3d7-884e-4a73-b110-362e7b9e7045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843948903 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3843948903
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.203833566
Short name T1054
Test name
Test status
Simulation time 52929890 ps
CPU time 1.9 seconds
Started Jun 21 06:58:32 PM PDT 24
Finished Jun 21 06:58:39 PM PDT 24
Peak memory 215348 kb
Host smart-fbf90500-720b-4d02-862b-10f593c78c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203833566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.203833566
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2793079874
Short name T991
Test name
Test status
Simulation time 13785962 ps
CPU time 0.74 seconds
Started Jun 21 06:58:22 PM PDT 24
Finished Jun 21 06:58:33 PM PDT 24
Peak memory 203992 kb
Host smart-5cce1131-2353-4cbd-bde2-53427002e0f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793079874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
793079874
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.237018321
Short name T106
Test name
Test status
Simulation time 22822338 ps
CPU time 1.78 seconds
Started Jun 21 06:58:27 PM PDT 24
Finished Jun 21 06:58:36 PM PDT 24
Peak memory 215400 kb
Host smart-e2f94f66-d146-4215-84b3-244d730b991e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237018321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.237018321
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4278993679
Short name T982
Test name
Test status
Simulation time 22272257 ps
CPU time 0.68 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:43 PM PDT 24
Peak memory 203900 kb
Host smart-8ce51da6-1220-40d9-b2cf-1e396c76ba5c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278993679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4278993679
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2727768756
Short name T137
Test name
Test status
Simulation time 216742443 ps
CPU time 4.45 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:41 PM PDT 24
Peak memory 215376 kb
Host smart-a70fd8ce-6aaa-4f02-9eab-8b5ddd78a441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727768756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2727768756
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1575244339
Short name T90
Test name
Test status
Simulation time 710391772 ps
CPU time 4.63 seconds
Started Jun 21 06:58:19 PM PDT 24
Finished Jun 21 06:58:36 PM PDT 24
Peak memory 215520 kb
Host smart-9ce9b3f3-8a1b-4a38-b219-ba14bf129e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575244339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
575244339
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1452670786
Short name T241
Test name
Test status
Simulation time 359796793 ps
CPU time 8.02 seconds
Started Jun 21 06:58:19 PM PDT 24
Finished Jun 21 06:58:39 PM PDT 24
Peak memory 216116 kb
Host smart-9b39178f-1549-4de1-8ac7-df6ab6bab2e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452670786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1452670786
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.283046379
Short name T1003
Test name
Test status
Simulation time 40072422 ps
CPU time 0.71 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 203972 kb
Host smart-45aae6c5-cd78-45cb-8be5-ed1583677045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283046379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.283046379
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2443824387
Short name T996
Test name
Test status
Simulation time 117862345 ps
CPU time 0.83 seconds
Started Jun 21 06:58:59 PM PDT 24
Finished Jun 21 06:59:03 PM PDT 24
Peak memory 203736 kb
Host smart-22dc6f5a-934e-4960-a40e-2f0f83f96639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443824387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2443824387
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1500287088
Short name T1023
Test name
Test status
Simulation time 33745369 ps
CPU time 0.73 seconds
Started Jun 21 06:58:57 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 203688 kb
Host smart-7e12775f-8d7e-4c14-9876-c368d042f74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500287088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1500287088
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2465415996
Short name T1041
Test name
Test status
Simulation time 16580403 ps
CPU time 0.75 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:05 PM PDT 24
Peak memory 204048 kb
Host smart-c6abce22-8dc6-48c7-8cee-322931a2a9da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465415996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2465415996
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.797175869
Short name T1069
Test name
Test status
Simulation time 49097536 ps
CPU time 0.78 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 203716 kb
Host smart-1e30fdfa-9c34-4c08-9101-6ac902eb7b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797175869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.797175869
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3539915628
Short name T1099
Test name
Test status
Simulation time 15151511 ps
CPU time 0.7 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 203996 kb
Host smart-8564b19a-826d-4529-bff7-f1d1db508df8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539915628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3539915628
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2195933462
Short name T1065
Test name
Test status
Simulation time 91122379 ps
CPU time 0.7 seconds
Started Jun 21 06:58:58 PM PDT 24
Finished Jun 21 06:59:01 PM PDT 24
Peak memory 203624 kb
Host smart-7a196270-d35e-47f5-8445-4752f2a05a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195933462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2195933462
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1376521760
Short name T1012
Test name
Test status
Simulation time 30685164 ps
CPU time 0.73 seconds
Started Jun 21 06:59:00 PM PDT 24
Finished Jun 21 06:59:04 PM PDT 24
Peak memory 204020 kb
Host smart-a68575fe-d38e-4848-b350-69fd54f960b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376521760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1376521760
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3248331326
Short name T1028
Test name
Test status
Simulation time 18684243 ps
CPU time 0.73 seconds
Started Jun 21 06:58:58 PM PDT 24
Finished Jun 21 06:59:02 PM PDT 24
Peak memory 203724 kb
Host smart-5325e92c-5a4f-4c29-9513-595319439f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248331326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3248331326
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2700963150
Short name T984
Test name
Test status
Simulation time 22070528 ps
CPU time 0.8 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 204032 kb
Host smart-c9d19f20-2ca6-435f-8ab6-00579c0c8ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700963150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2700963150
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2134997351
Short name T1014
Test name
Test status
Simulation time 1503737386 ps
CPU time 8.27 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:44 PM PDT 24
Peak memory 206968 kb
Host smart-f7744d52-ca36-4ea1-89d2-43b687a98535
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134997351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2134997351
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3837819629
Short name T1047
Test name
Test status
Simulation time 2162969395 ps
CPU time 12.8 seconds
Started Jun 21 06:58:28 PM PDT 24
Finished Jun 21 06:58:48 PM PDT 24
Peak memory 207136 kb
Host smart-432c5ae2-ed22-4f0b-aff7-c71110c9c7cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837819629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3837819629
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.254342849
Short name T69
Test name
Test status
Simulation time 20471574 ps
CPU time 1 seconds
Started Jun 21 06:58:28 PM PDT 24
Finished Jun 21 06:58:36 PM PDT 24
Peak memory 206908 kb
Host smart-a16e2865-33be-4cb5-964a-ea37f6dcb9e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254342849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.254342849
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3866587598
Short name T1010
Test name
Test status
Simulation time 119550338 ps
CPU time 2.86 seconds
Started Jun 21 06:58:31 PM PDT 24
Finished Jun 21 06:58:40 PM PDT 24
Peak memory 217008 kb
Host smart-ec675c15-0ebd-4965-9228-49fd66a10165
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866587598 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3866587598
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1058626360
Short name T1100
Test name
Test status
Simulation time 84588879 ps
CPU time 1.41 seconds
Started Jun 21 06:58:27 PM PDT 24
Finished Jun 21 06:58:36 PM PDT 24
Peak memory 215336 kb
Host smart-7cbb9195-8c44-4ad1-9354-90da4ea52656
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058626360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
058626360
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3356824162
Short name T1055
Test name
Test status
Simulation time 87027393 ps
CPU time 0.73 seconds
Started Jun 21 06:58:32 PM PDT 24
Finished Jun 21 06:58:38 PM PDT 24
Peak memory 203656 kb
Host smart-88e1c0fa-0f54-4637-ac26-c32b5f7a4284
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356824162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
356824162
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2068622197
Short name T1087
Test name
Test status
Simulation time 96149117 ps
CPU time 1.92 seconds
Started Jun 21 06:58:29 PM PDT 24
Finished Jun 21 06:58:38 PM PDT 24
Peak memory 215296 kb
Host smart-0465e8fb-e7e1-4f24-8959-7d51946f4fed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068622197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2068622197
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4211338312
Short name T1096
Test name
Test status
Simulation time 34349384 ps
CPU time 0.66 seconds
Started Jun 21 06:58:31 PM PDT 24
Finished Jun 21 06:58:37 PM PDT 24
Peak memory 203588 kb
Host smart-b4f54fbe-a308-47bf-af93-facb9f46b598
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211338312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4211338312
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.959908217
Short name T1032
Test name
Test status
Simulation time 1029441870 ps
CPU time 2.84 seconds
Started Jun 21 06:58:31 PM PDT 24
Finished Jun 21 06:58:39 PM PDT 24
Peak memory 215264 kb
Host smart-3710c300-c662-42cc-818c-d23ea78d0a1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959908217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.959908217
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3211239963
Short name T93
Test name
Test status
Simulation time 291686406 ps
CPU time 4.88 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:41 PM PDT 24
Peak memory 215480 kb
Host smart-b30afb3e-d909-431b-9852-efd53b70f9b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211239963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
211239963
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.95757763
Short name T1031
Test name
Test status
Simulation time 295508453 ps
CPU time 6.72 seconds
Started Jun 21 06:58:29 PM PDT 24
Finished Jun 21 06:58:42 PM PDT 24
Peak memory 216492 kb
Host smart-170d25af-3758-40d8-a875-a34348b68da5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95757763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_t
l_intg_err.95757763
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1514067712
Short name T1058
Test name
Test status
Simulation time 12934590 ps
CPU time 0.7 seconds
Started Jun 21 06:58:57 PM PDT 24
Finished Jun 21 06:59:00 PM PDT 24
Peak memory 204000 kb
Host smart-c44e7dbb-77a8-402e-adf5-7ccfba48a7f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514067712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1514067712
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3199578245
Short name T993
Test name
Test status
Simulation time 37903007 ps
CPU time 0.67 seconds
Started Jun 21 06:58:57 PM PDT 24
Finished Jun 21 06:58:59 PM PDT 24
Peak memory 203908 kb
Host smart-25314eab-14f6-4b37-9f99-5d037db1bee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199578245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3199578245
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3564440066
Short name T1081
Test name
Test status
Simulation time 37454448 ps
CPU time 0.75 seconds
Started Jun 21 06:59:00 PM PDT 24
Finished Jun 21 06:59:05 PM PDT 24
Peak memory 204016 kb
Host smart-cadf50ff-00eb-40c4-8e42-2373ff7f25ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564440066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3564440066
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3028519308
Short name T1064
Test name
Test status
Simulation time 23768439 ps
CPU time 0.7 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 203992 kb
Host smart-32c4acef-2217-4f0c-af02-bcf7c2708ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028519308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3028519308
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1895075225
Short name T989
Test name
Test status
Simulation time 27147960 ps
CPU time 0.69 seconds
Started Jun 21 06:58:58 PM PDT 24
Finished Jun 21 06:59:01 PM PDT 24
Peak memory 203796 kb
Host smart-5a8bf998-dc65-47eb-a650-ec20b9e7ccb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895075225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1895075225
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.42242013
Short name T1011
Test name
Test status
Simulation time 13465071 ps
CPU time 0.7 seconds
Started Jun 21 06:59:00 PM PDT 24
Finished Jun 21 06:59:05 PM PDT 24
Peak memory 204004 kb
Host smart-988d4dd4-b0e7-48cd-acce-b6e7e5e0c3fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42242013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.42242013
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1864036380
Short name T995
Test name
Test status
Simulation time 20724448 ps
CPU time 0.7 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 203660 kb
Host smart-9320fe5c-0ae5-416f-93f1-ca54cb3dc341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864036380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1864036380
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1018884827
Short name T985
Test name
Test status
Simulation time 24146429 ps
CPU time 0.73 seconds
Started Jun 21 06:59:03 PM PDT 24
Finished Jun 21 06:59:08 PM PDT 24
Peak memory 203744 kb
Host smart-e0133fed-7706-497a-b9c9-84c8a91e8486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018884827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1018884827
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.180913886
Short name T1091
Test name
Test status
Simulation time 28590787 ps
CPU time 0.81 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 203704 kb
Host smart-e24dd5d4-1735-46d4-9272-fbdc50a186c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180913886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.180913886
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.330105235
Short name T1075
Test name
Test status
Simulation time 13774874 ps
CPU time 0.75 seconds
Started Jun 21 06:58:58 PM PDT 24
Finished Jun 21 06:59:01 PM PDT 24
Peak memory 203760 kb
Host smart-7c0c919a-cba4-4359-b080-9c9763d09672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330105235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.330105235
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2837959469
Short name T110
Test name
Test status
Simulation time 597930423 ps
CPU time 19.93 seconds
Started Jun 21 06:58:32 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 215200 kb
Host smart-686971bb-9aa4-443b-9e6f-6af94d109e24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837959469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2837959469
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3411143243
Short name T1007
Test name
Test status
Simulation time 1908942791 ps
CPU time 35.2 seconds
Started Jun 21 06:58:28 PM PDT 24
Finished Jun 21 06:59:10 PM PDT 24
Peak memory 207064 kb
Host smart-e77d59e2-6d93-46e4-a614-5beefe8bbb18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411143243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3411143243
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3812514617
Short name T70
Test name
Test status
Simulation time 16914334 ps
CPU time 0.95 seconds
Started Jun 21 06:58:32 PM PDT 24
Finished Jun 21 06:58:38 PM PDT 24
Peak memory 206628 kb
Host smart-fbeb4965-77a0-4c0e-8f99-ea81aad9a3ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812514617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3812514617
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3727930435
Short name T140
Test name
Test status
Simulation time 177788284 ps
CPU time 1.51 seconds
Started Jun 21 06:58:29 PM PDT 24
Finished Jun 21 06:58:37 PM PDT 24
Peak memory 215404 kb
Host smart-8fa9e750-203f-4563-bdb6-08e8a419779b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727930435 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3727930435
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3474590563
Short name T153
Test name
Test status
Simulation time 98594237 ps
CPU time 1.5 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:38 PM PDT 24
Peak memory 207024 kb
Host smart-08dcaec8-6162-4de3-a809-e3bd43660d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474590563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
474590563
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1994273787
Short name T1037
Test name
Test status
Simulation time 15527271 ps
CPU time 0.68 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:37 PM PDT 24
Peak memory 203996 kb
Host smart-5f1d7f07-f234-4ddf-a478-756e5181e2ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994273787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
994273787
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3990692359
Short name T1061
Test name
Test status
Simulation time 64289683 ps
CPU time 2.14 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:39 PM PDT 24
Peak memory 215316 kb
Host smart-dea2eb72-825a-4b87-8e4b-cd0dde98f632
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990692359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3990692359
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3778027648
Short name T1044
Test name
Test status
Simulation time 10967856 ps
CPU time 0.67 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:37 PM PDT 24
Peak memory 203584 kb
Host smart-97db7353-49c5-4680-8b5b-f8b4ce8057c0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778027648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3778027648
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1969608622
Short name T128
Test name
Test status
Simulation time 104067893 ps
CPU time 2.98 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:39 PM PDT 24
Peak memory 215344 kb
Host smart-e6a19ff8-6f9d-4b73-931a-74e0dc3c0c0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969608622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1969608622
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1407025024
Short name T234
Test name
Test status
Simulation time 789206257 ps
CPU time 4.27 seconds
Started Jun 21 06:58:31 PM PDT 24
Finished Jun 21 06:58:41 PM PDT 24
Peak memory 216516 kb
Host smart-af586e51-9a08-44b7-85c7-a63da064b5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407025024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
407025024
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.480172950
Short name T1024
Test name
Test status
Simulation time 111773447 ps
CPU time 0.72 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 203992 kb
Host smart-f524cbfc-26e0-4970-bdd2-8fd4b8edf4ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480172950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.480172950
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.9684852
Short name T1036
Test name
Test status
Simulation time 28259380 ps
CPU time 0.79 seconds
Started Jun 21 06:58:59 PM PDT 24
Finished Jun 21 06:59:03 PM PDT 24
Peak memory 203976 kb
Host smart-4736ae60-79cf-4a9d-946f-48fd59ce8fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9684852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.9684852
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1247588205
Short name T1070
Test name
Test status
Simulation time 14099920 ps
CPU time 0.72 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 203976 kb
Host smart-3b6ac5f2-cd09-4c70-861f-28d068e73f17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247588205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1247588205
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.44589247
Short name T1082
Test name
Test status
Simulation time 15488639 ps
CPU time 0.71 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 204000 kb
Host smart-f6c26847-97b6-4363-a676-7c994af0b3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44589247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.44589247
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1711342180
Short name T999
Test name
Test status
Simulation time 14562645 ps
CPU time 0.74 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 203744 kb
Host smart-b2945037-1f20-49ef-b1d5-fb7377c84274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711342180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1711342180
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4018079651
Short name T1078
Test name
Test status
Simulation time 38212436 ps
CPU time 0.7 seconds
Started Jun 21 06:58:59 PM PDT 24
Finished Jun 21 06:59:03 PM PDT 24
Peak memory 203640 kb
Host smart-c70ce849-c1d5-4b71-87bd-4e14a0f21cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018079651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4018079651
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2682873959
Short name T1053
Test name
Test status
Simulation time 80062601 ps
CPU time 0.7 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 203976 kb
Host smart-afce38cb-c257-4a8b-86ab-ad3cc19a78af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682873959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2682873959
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2423294284
Short name T1084
Test name
Test status
Simulation time 113933470 ps
CPU time 0.73 seconds
Started Jun 21 06:58:59 PM PDT 24
Finished Jun 21 06:59:02 PM PDT 24
Peak memory 203600 kb
Host smart-55d1ae15-27dd-4f3b-8681-f12484eb6f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423294284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2423294284
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2945266117
Short name T1052
Test name
Test status
Simulation time 32469629 ps
CPU time 0.67 seconds
Started Jun 21 06:59:01 PM PDT 24
Finished Jun 21 06:59:06 PM PDT 24
Peak memory 203668 kb
Host smart-41d574db-2f22-4c4b-9a13-184e840ff136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945266117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2945266117
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.557100640
Short name T1017
Test name
Test status
Simulation time 80336844 ps
CPU time 0.71 seconds
Started Jun 21 06:59:02 PM PDT 24
Finished Jun 21 06:59:07 PM PDT 24
Peak memory 203992 kb
Host smart-985247b5-447b-47f7-a24f-1559c1f2870b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557100640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.557100640
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.610508949
Short name T1021
Test name
Test status
Simulation time 82177837 ps
CPU time 1.88 seconds
Started Jun 21 06:58:40 PM PDT 24
Finished Jun 21 06:58:47 PM PDT 24
Peak memory 216444 kb
Host smart-75d237ca-08ab-415f-9158-f03c74a014be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610508949 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.610508949
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1405715209
Short name T1038
Test name
Test status
Simulation time 141324931 ps
CPU time 1.28 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:44 PM PDT 24
Peak memory 207052 kb
Host smart-75db7fe8-47e7-45cd-b7ba-141715045178
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405715209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
405715209
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2660067661
Short name T1068
Test name
Test status
Simulation time 17120434 ps
CPU time 0.75 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:37 PM PDT 24
Peak memory 204036 kb
Host smart-d58dd096-9bcf-4efe-a117-1377a86f9b4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660067661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
660067661
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.564831683
Short name T1059
Test name
Test status
Simulation time 83210969 ps
CPU time 2.75 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:45 PM PDT 24
Peak memory 215320 kb
Host smart-d1739544-de6a-4789-8562-2da3cf308602
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564831683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.564831683
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4247037452
Short name T95
Test name
Test status
Simulation time 223508225 ps
CPU time 3.29 seconds
Started Jun 21 06:58:30 PM PDT 24
Finished Jun 21 06:58:40 PM PDT 24
Peak memory 215516 kb
Host smart-e475c36a-32d6-45d4-ae74-4d2833b162e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247037452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
247037452
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.678554037
Short name T1077
Test name
Test status
Simulation time 10461104472 ps
CPU time 14.33 seconds
Started Jun 21 06:58:32 PM PDT 24
Finished Jun 21 06:58:51 PM PDT 24
Peak memory 215504 kb
Host smart-d6e5b9bc-0c9b-409e-b2d1-0a01717ad478
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678554037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.678554037
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.777038902
Short name T86
Test name
Test status
Simulation time 151550519 ps
CPU time 1.52 seconds
Started Jun 21 06:58:39 PM PDT 24
Finished Jun 21 06:58:46 PM PDT 24
Peak memory 215360 kb
Host smart-cfc529a7-90a2-4e62-be7e-65452338f3e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777038902 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.777038902
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1408151664
Short name T1035
Test name
Test status
Simulation time 178098233 ps
CPU time 1.47 seconds
Started Jun 21 06:58:44 PM PDT 24
Finished Jun 21 06:58:50 PM PDT 24
Peak memory 215360 kb
Host smart-ac6a86b2-0603-4533-9e28-4acc04ec3dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408151664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
408151664
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3757299237
Short name T997
Test name
Test status
Simulation time 60280185 ps
CPU time 0.73 seconds
Started Jun 21 06:58:36 PM PDT 24
Finished Jun 21 06:58:42 PM PDT 24
Peak memory 203676 kb
Host smart-ab7de142-dda2-49ab-9f8e-735690b6dd78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757299237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
757299237
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3683035484
Short name T1060
Test name
Test status
Simulation time 87129223 ps
CPU time 2.83 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:46 PM PDT 24
Peak memory 215284 kb
Host smart-0b55fc1d-1944-48c7-8901-17fd069763bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683035484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3683035484
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3455085078
Short name T1056
Test name
Test status
Simulation time 216092926 ps
CPU time 1.95 seconds
Started Jun 21 06:58:39 PM PDT 24
Finished Jun 21 06:58:46 PM PDT 24
Peak memory 215488 kb
Host smart-a7704077-715a-41b1-955c-37ffbe8740e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455085078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
455085078
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3043206409
Short name T98
Test name
Test status
Simulation time 423613773 ps
CPU time 6.7 seconds
Started Jun 21 06:58:39 PM PDT 24
Finished Jun 21 06:58:51 PM PDT 24
Peak memory 216168 kb
Host smart-fd415b44-8b2f-4d8e-ad7b-e113a393628f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043206409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3043206409
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2601972292
Short name T83
Test name
Test status
Simulation time 160372330 ps
CPU time 2.67 seconds
Started Jun 21 06:58:37 PM PDT 24
Finished Jun 21 06:58:44 PM PDT 24
Peak memory 217032 kb
Host smart-043bcf77-e838-4248-94f7-0c1e5423b5b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601972292 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2601972292
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1443987986
Short name T129
Test name
Test status
Simulation time 37237716 ps
CPU time 1.32 seconds
Started Jun 21 06:58:37 PM PDT 24
Finished Jun 21 06:58:43 PM PDT 24
Peak memory 215360 kb
Host smart-a0b099bf-77f1-4b63-a38d-ca4e2d40df2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443987986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
443987986
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2069603996
Short name T983
Test name
Test status
Simulation time 18391157 ps
CPU time 0.73 seconds
Started Jun 21 06:58:41 PM PDT 24
Finished Jun 21 06:58:47 PM PDT 24
Peak memory 203624 kb
Host smart-363834fe-1627-4dd5-b961-eeb0c6c97525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069603996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
069603996
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3440175468
Short name T1029
Test name
Test status
Simulation time 57131687 ps
CPU time 1.69 seconds
Started Jun 21 06:58:39 PM PDT 24
Finished Jun 21 06:58:45 PM PDT 24
Peak memory 215376 kb
Host smart-3b2038e5-b7d4-4277-bc23-c4f48df91da0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440175468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3440175468
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.124954729
Short name T1008
Test name
Test status
Simulation time 134616440 ps
CPU time 2.42 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:46 PM PDT 24
Peak memory 215512 kb
Host smart-535bb7ed-b672-40ab-a063-824c80cdec77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124954729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.124954729
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3097927981
Short name T1049
Test name
Test status
Simulation time 553078123 ps
CPU time 13.66 seconds
Started Jun 21 06:58:39 PM PDT 24
Finished Jun 21 06:58:57 PM PDT 24
Peak memory 215388 kb
Host smart-0b01a620-839c-4718-9f93-5a98fb775211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097927981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3097927981
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.144731597
Short name T1098
Test name
Test status
Simulation time 565776958 ps
CPU time 2.98 seconds
Started Jun 21 06:58:44 PM PDT 24
Finished Jun 21 06:58:52 PM PDT 24
Peak memory 216716 kb
Host smart-b995ed6f-ebc0-41bc-bf3b-675672d682d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144731597 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.144731597
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.819832770
Short name T1093
Test name
Test status
Simulation time 280141451 ps
CPU time 1.27 seconds
Started Jun 21 06:58:37 PM PDT 24
Finished Jun 21 06:58:43 PM PDT 24
Peak memory 207032 kb
Host smart-dfc1593c-ac98-4a63-ac1e-af244a87e828
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819832770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.819832770
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1061960376
Short name T981
Test name
Test status
Simulation time 107027188 ps
CPU time 0.72 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:44 PM PDT 24
Peak memory 203956 kb
Host smart-45357119-7682-4540-8b10-45c71690c244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061960376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
061960376
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.703899506
Short name T1000
Test name
Test status
Simulation time 30627098 ps
CPU time 1.83 seconds
Started Jun 21 06:58:36 PM PDT 24
Finished Jun 21 06:58:43 PM PDT 24
Peak memory 215252 kb
Host smart-7e737d1b-8829-4ba1-9c48-4752e6098b2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703899506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.703899506
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3056818309
Short name T138
Test name
Test status
Simulation time 1394457932 ps
CPU time 8.14 seconds
Started Jun 21 06:58:37 PM PDT 24
Finished Jun 21 06:58:50 PM PDT 24
Peak memory 215392 kb
Host smart-099d1b2d-11bb-4168-88b9-bf9aadd2d208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056818309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3056818309
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2698788210
Short name T1002
Test name
Test status
Simulation time 40598992 ps
CPU time 2.5 seconds
Started Jun 21 06:58:49 PM PDT 24
Finished Jun 21 06:58:56 PM PDT 24
Peak memory 216748 kb
Host smart-e5570017-2499-44a8-ad29-0260569e6be1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698788210 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2698788210
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3347617169
Short name T112
Test name
Test status
Simulation time 54092641 ps
CPU time 1.37 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:45 PM PDT 24
Peak memory 215224 kb
Host smart-f234ed58-a3df-4a1d-82e8-8e035f3384ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347617169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
347617169
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2157526649
Short name T1048
Test name
Test status
Simulation time 92503024 ps
CPU time 0.72 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:44 PM PDT 24
Peak memory 203616 kb
Host smart-e260991a-d113-4b11-8fb7-251b0be777c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157526649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
157526649
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2980471656
Short name T1046
Test name
Test status
Simulation time 318833780 ps
CPU time 4.32 seconds
Started Jun 21 06:58:50 PM PDT 24
Finished Jun 21 06:58:59 PM PDT 24
Peak memory 215356 kb
Host smart-0c1eb663-0289-4e2d-b121-26112a465313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980471656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2980471656
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3211337821
Short name T88
Test name
Test status
Simulation time 150358011 ps
CPU time 4.3 seconds
Started Jun 21 06:58:43 PM PDT 24
Finished Jun 21 06:58:52 PM PDT 24
Peak memory 215592 kb
Host smart-da4e39f2-0634-437a-8138-6381fa6893f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211337821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
211337821
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2456550857
Short name T237
Test name
Test status
Simulation time 2606284831 ps
CPU time 6.3 seconds
Started Jun 21 06:58:38 PM PDT 24
Finished Jun 21 06:58:49 PM PDT 24
Peak memory 215652 kb
Host smart-f7b799c8-2ad2-41b3-9203-f2998f3ddc4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456550857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2456550857
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3600332373
Short name T912
Test name
Test status
Simulation time 67043626 ps
CPU time 0.76 seconds
Started Jun 21 07:02:30 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 206264 kb
Host smart-f1738647-b952-4d85-8115-7a3b696aad70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600332373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
600332373
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3989449238
Short name T271
Test name
Test status
Simulation time 39842274 ps
CPU time 2.64 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:02:37 PM PDT 24
Peak memory 233768 kb
Host smart-351fff63-2461-49f4-ac38-70a197d461e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989449238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3989449238
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3608807850
Short name T407
Test name
Test status
Simulation time 67575629 ps
CPU time 0.73 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:31 PM PDT 24
Peak memory 206260 kb
Host smart-5e64ebac-9f5a-4d10-995a-f33e934fafff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608807850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3608807850
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2457180209
Short name T798
Test name
Test status
Simulation time 1979839166 ps
CPU time 33.64 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:03:05 PM PDT 24
Peak memory 256188 kb
Host smart-f9752aea-2330-420c-a457-9b91d636ab12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457180209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2457180209
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.526731858
Short name T36
Test name
Test status
Simulation time 13381871158 ps
CPU time 103.06 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 249376 kb
Host smart-7db301e4-1132-4cae-8051-000c46090f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526731858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.526731858
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2931027231
Short name T157
Test name
Test status
Simulation time 72759487780 ps
CPU time 97.88 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 255292 kb
Host smart-74a17162-ae5b-4f66-8842-d8d1a3b1edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931027231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2931027231
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.4009741654
Short name T285
Test name
Test status
Simulation time 11395689603 ps
CPU time 60.15 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:03:32 PM PDT 24
Peak memory 242260 kb
Host smart-c60bd487-8efc-4309-969a-1f6fb2bde921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009741654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4009741654
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.511161493
Short name T50
Test name
Test status
Simulation time 24454089993 ps
CPU time 39.34 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 225668 kb
Host smart-eeddee99-e256-4be4-8dd6-ea84cce1ccb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511161493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.511161493
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1623982622
Short name T170
Test name
Test status
Simulation time 20431874465 ps
CPU time 48.86 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:03:21 PM PDT 24
Peak memory 233832 kb
Host smart-e2e44f60-1d1f-4aa8-9ec3-63f69fca10ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623982622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1623982622
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3019898133
Short name T162
Test name
Test status
Simulation time 297364759 ps
CPU time 3.07 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:34 PM PDT 24
Peak memory 233472 kb
Host smart-95c12956-0635-4b93-afa2-1536701a2fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019898133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3019898133
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1684631123
Short name T619
Test name
Test status
Simulation time 3445163209 ps
CPU time 6.3 seconds
Started Jun 21 07:02:21 PM PDT 24
Finished Jun 21 07:02:31 PM PDT 24
Peak memory 233860 kb
Host smart-0b8bc5ba-b362-49bd-86e6-7e084dfa7227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684631123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1684631123
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.733207607
Short name T404
Test name
Test status
Simulation time 1564537292 ps
CPU time 4.62 seconds
Started Jun 21 07:02:32 PM PDT 24
Finished Jun 21 07:02:42 PM PDT 24
Peak memory 224136 kb
Host smart-42ae2bee-5ecd-42f6-b793-7cd3d8de867a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=733207607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.733207607
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3166403175
Short name T490
Test name
Test status
Simulation time 47043230 ps
CPU time 0.71 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:32 PM PDT 24
Peak memory 206596 kb
Host smart-bd10db3b-2250-46f3-b192-80bab3c03b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166403175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3166403175
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3713495167
Short name T332
Test name
Test status
Simulation time 1040902441 ps
CPU time 1.35 seconds
Started Jun 21 07:02:23 PM PDT 24
Finished Jun 21 07:02:28 PM PDT 24
Peak memory 208756 kb
Host smart-ad9dd28e-c675-43bd-9640-fc4d93cbe65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713495167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3713495167
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2656913644
Short name T896
Test name
Test status
Simulation time 24787239 ps
CPU time 0.69 seconds
Started Jun 21 07:02:22 PM PDT 24
Finished Jun 21 07:02:27 PM PDT 24
Peak memory 206564 kb
Host smart-171457e2-dca3-4c4a-8f5f-eb51cc2876c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656913644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2656913644
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3088260328
Short name T363
Test name
Test status
Simulation time 93506021 ps
CPU time 0.79 seconds
Started Jun 21 07:02:20 PM PDT 24
Finished Jun 21 07:02:24 PM PDT 24
Peak memory 206888 kb
Host smart-cfb2ec58-8dcd-4eed-9000-ae2c1a90fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088260328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3088260328
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2907085775
Short name T445
Test name
Test status
Simulation time 6306473820 ps
CPU time 6.17 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:37 PM PDT 24
Peak memory 225692 kb
Host smart-caf8608c-85fb-4953-a370-74b7391c43cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907085775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2907085775
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3134997711
Short name T726
Test name
Test status
Simulation time 11341930 ps
CPU time 0.72 seconds
Started Jun 21 07:02:30 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 206268 kb
Host smart-d54d86c3-6678-4c04-90d9-e56e1fdd597f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134997711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
134997711
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.788187890
Short name T150
Test name
Test status
Simulation time 878894804 ps
CPU time 3.5 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:02:36 PM PDT 24
Peak memory 233768 kb
Host smart-59c11b38-d0b2-41f6-9ba4-b916a460f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788187890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.788187890
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.901164013
Short name T366
Test name
Test status
Simulation time 65532181 ps
CPU time 0.82 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:02:33 PM PDT 24
Peak memory 207428 kb
Host smart-bfb537f4-028d-4ce1-97ed-d2db972351c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901164013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.901164013
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1902268951
Short name T602
Test name
Test status
Simulation time 11066863767 ps
CPU time 111.84 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:04:25 PM PDT 24
Peak memory 250136 kb
Host smart-f0715d8c-8a60-481e-baa3-208f2688c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902268951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1902268951
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.576554170
Short name T938
Test name
Test status
Simulation time 130251388673 ps
CPU time 264.56 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:06:56 PM PDT 24
Peak memory 250696 kb
Host smart-4829acf3-4a7d-48ab-a5c5-cd7a3362ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576554170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.576554170
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3221297757
Short name T230
Test name
Test status
Simulation time 5794636229 ps
CPU time 92.54 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:04:03 PM PDT 24
Peak memory 250644 kb
Host smart-d7ce59e4-fa5b-47b3-a9d8-d51031d6c474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221297757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3221297757
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3981566333
Short name T331
Test name
Test status
Simulation time 6559961496 ps
CPU time 10.35 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:02:45 PM PDT 24
Peak memory 238100 kb
Host smart-fa9c7150-55de-41c9-9d97-d8599f3e1739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981566333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3981566333
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4266381310
Short name T881
Test name
Test status
Simulation time 1089934406 ps
CPU time 3.96 seconds
Started Jun 21 07:02:25 PM PDT 24
Finished Jun 21 07:02:35 PM PDT 24
Peak memory 225484 kb
Host smart-a99df14f-09f4-4a00-8567-5a70ff5f2d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266381310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4266381310
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1930335119
Short name T589
Test name
Test status
Simulation time 7988981410 ps
CPU time 66.03 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:03:39 PM PDT 24
Peak memory 241680 kb
Host smart-1de442ac-f2b8-4381-91cb-00591bf90d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930335119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1930335119
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3079557244
Short name T856
Test name
Test status
Simulation time 15460020 ps
CPU time 1.08 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:02:34 PM PDT 24
Peak memory 217656 kb
Host smart-8eb24f27-a1c0-4ab2-8801-af28e29138eb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079557244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3079557244
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2370252639
Short name T662
Test name
Test status
Simulation time 30371826 ps
CPU time 2.38 seconds
Started Jun 21 07:02:30 PM PDT 24
Finished Jun 21 07:02:38 PM PDT 24
Peak memory 233484 kb
Host smart-882497c6-764d-44d5-b5ed-f90a86667205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370252639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2370252639
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2471262988
Short name T599
Test name
Test status
Simulation time 670634400 ps
CPU time 4.49 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:02:39 PM PDT 24
Peak memory 233796 kb
Host smart-1e568c9a-560d-4a22-b806-ab0b9f389f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471262988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2471262988
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1381006334
Short name T403
Test name
Test status
Simulation time 1217425491 ps
CPU time 5.25 seconds
Started Jun 21 07:02:30 PM PDT 24
Finished Jun 21 07:02:41 PM PDT 24
Peak memory 221880 kb
Host smart-319a802f-2bc7-423d-ae2a-1f57fbfba316
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1381006334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1381006334
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1902524809
Short name T58
Test name
Test status
Simulation time 66271789 ps
CPU time 1 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:32 PM PDT 24
Peak memory 236684 kb
Host smart-2d6ded1a-3a1e-49ee-8d28-b99d068e37e3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902524809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1902524809
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2177096460
Short name T867
Test name
Test status
Simulation time 16983942278 ps
CPU time 23.47 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:02:56 PM PDT 24
Peak memory 250480 kb
Host smart-4c49337e-f4e5-4c70-bff9-e5923ddc87d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177096460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2177096460
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.264735172
Short name T671
Test name
Test status
Simulation time 58880221 ps
CPU time 0.7 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:02:35 PM PDT 24
Peak memory 206676 kb
Host smart-26ef640b-3031-494c-8db7-159ea70c8c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264735172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.264735172
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1666648377
Short name T737
Test name
Test status
Simulation time 5287300944 ps
CPU time 9.73 seconds
Started Jun 21 07:02:30 PM PDT 24
Finished Jun 21 07:02:45 PM PDT 24
Peak memory 217504 kb
Host smart-a2c57680-7343-467d-80ef-ba0916197603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666648377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1666648377
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3047958791
Short name T900
Test name
Test status
Simulation time 501039089 ps
CPU time 10.29 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:02:44 PM PDT 24
Peak memory 217408 kb
Host smart-b0d98f35-cc23-4b45-b492-d3ebe2eed37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047958791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3047958791
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1746123916
Short name T345
Test name
Test status
Simulation time 36248301 ps
CPU time 0.78 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:31 PM PDT 24
Peak memory 206884 kb
Host smart-ccd3ee26-6559-4daf-9f21-fa6307ceba3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746123916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1746123916
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4141990704
Short name T559
Test name
Test status
Simulation time 79882613 ps
CPU time 2.4 seconds
Started Jun 21 07:02:30 PM PDT 24
Finished Jun 21 07:02:38 PM PDT 24
Peak memory 225508 kb
Host smart-df11b5cb-52e5-431c-bb91-f6e5c71bc74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141990704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4141990704
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3438920116
Short name T796
Test name
Test status
Simulation time 46144034 ps
CPU time 0.74 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 206408 kb
Host smart-a423fb86-d3d6-47ca-88af-1491a79d7bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438920116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3438920116
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.129956004
Short name T789
Test name
Test status
Simulation time 16755960 ps
CPU time 0.76 seconds
Started Jun 21 07:03:04 PM PDT 24
Finished Jun 21 07:03:11 PM PDT 24
Peak memory 216856 kb
Host smart-f0bff4ed-8fc4-40b5-89d8-0ac27d5908a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129956004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.129956004
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2910235381
Short name T603
Test name
Test status
Simulation time 30786153564 ps
CPU time 93.46 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:04:42 PM PDT 24
Peak memory 250384 kb
Host smart-de676a23-0bc9-403b-ae8c-bb076ee3e7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910235381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2910235381
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3493261500
Short name T198
Test name
Test status
Simulation time 18278934878 ps
CPU time 229.62 seconds
Started Jun 21 07:03:04 PM PDT 24
Finished Jun 21 07:07:01 PM PDT 24
Peak memory 265280 kb
Host smart-48e8271c-daf7-46a3-9370-d80d79c480a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493261500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3493261500
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4086810725
Short name T394
Test name
Test status
Simulation time 264656074 ps
CPU time 7.11 seconds
Started Jun 21 07:03:00 PM PDT 24
Finished Jun 21 07:03:14 PM PDT 24
Peak memory 233688 kb
Host smart-1bd05694-bb19-48a5-baa9-2ed2f50de915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086810725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4086810725
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3693583275
Short name T79
Test name
Test status
Simulation time 4540072973 ps
CPU time 15.16 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:14 PM PDT 24
Peak memory 233908 kb
Host smart-1c455e65-7e25-4c3b-b3c4-a0b0364cd6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693583275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3693583275
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2996891326
Short name T642
Test name
Test status
Simulation time 3292088108 ps
CPU time 13.49 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:03:11 PM PDT 24
Peak memory 233892 kb
Host smart-fe498e59-99e3-4d57-b401-d8daa48393d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996891326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2996891326
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.392171391
Short name T465
Test name
Test status
Simulation time 50354529 ps
CPU time 1.05 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 217600 kb
Host smart-4a4ebb51-e1dd-4530-a0ff-1cda613bef64
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392171391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.392171391
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1903682052
Short name T174
Test name
Test status
Simulation time 408718251 ps
CPU time 4.56 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:03 PM PDT 24
Peak memory 233760 kb
Host smart-6f028f95-1e44-4842-bdc7-3b131cf2b3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903682052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1903682052
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1100667429
Short name T775
Test name
Test status
Simulation time 12344504982 ps
CPU time 27.27 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:28 PM PDT 24
Peak memory 233844 kb
Host smart-b378ed47-bcfa-45f1-a5d5-09391a7803c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100667429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1100667429
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3247032262
Short name T132
Test name
Test status
Simulation time 1319829163 ps
CPU time 11.87 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 219608 kb
Host smart-f493bfd8-e80c-4325-93dc-84d9f3783df2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3247032262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3247032262
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1512497455
Short name T902
Test name
Test status
Simulation time 210127626 ps
CPU time 1.12 seconds
Started Jun 21 07:02:59 PM PDT 24
Finished Jun 21 07:03:06 PM PDT 24
Peak memory 207840 kb
Host smart-98cbaba9-c22a-454c-84f7-b2f882458f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512497455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1512497455
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1553068641
Short name T784
Test name
Test status
Simulation time 9519988980 ps
CPU time 25.31 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:24 PM PDT 24
Peak memory 217580 kb
Host smart-699cc8bd-6d0d-4830-a0bc-eead585996e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553068641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1553068641
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.641093763
Short name T433
Test name
Test status
Simulation time 4833454042 ps
CPU time 7.55 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:06 PM PDT 24
Peak memory 217512 kb
Host smart-a6f23fd6-2ce6-4558-8c07-3182bb490aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641093763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.641093763
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1768864082
Short name T658
Test name
Test status
Simulation time 69089948 ps
CPU time 0.83 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 207000 kb
Host smart-f1929732-7581-4e20-b110-6eb5340a1249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768864082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1768864082
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1349672909
Short name T967
Test name
Test status
Simulation time 52179764 ps
CPU time 0.87 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:02:59 PM PDT 24
Peak memory 206892 kb
Host smart-b5157f70-119c-4dcd-9d22-ec191bb2f6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349672909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1349672909
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2766757375
Short name T243
Test name
Test status
Simulation time 103965602 ps
CPU time 3.71 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:04 PM PDT 24
Peak memory 237284 kb
Host smart-f71c31d4-8ea9-4e57-95f0-57aa59ce5a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766757375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2766757375
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3729162343
Short name T624
Test name
Test status
Simulation time 31819575 ps
CPU time 0.71 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 206300 kb
Host smart-cf97dca3-8595-44a2-a5f7-10ad368cb612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729162343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3729162343
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2228628705
Short name T448
Test name
Test status
Simulation time 941978491 ps
CPU time 5.55 seconds
Started Jun 21 07:03:00 PM PDT 24
Finished Jun 21 07:03:11 PM PDT 24
Peak memory 233776 kb
Host smart-79048526-0a7e-4b5f-a2fb-c24364cb3dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228628705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2228628705
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.154718713
Short name T802
Test name
Test status
Simulation time 14831958 ps
CPU time 0.87 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 207788 kb
Host smart-66c5ba9e-601b-47ac-b950-1786213d98a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154718713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.154718713
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2703743574
Short name T701
Test name
Test status
Simulation time 20258788610 ps
CPU time 45.77 seconds
Started Jun 21 07:03:03 PM PDT 24
Finished Jun 21 07:03:55 PM PDT 24
Peak memory 233884 kb
Host smart-e18a81e8-e644-4457-b363-4a3ddc20834b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703743574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2703743574
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2217878747
Short name T151
Test name
Test status
Simulation time 13128981947 ps
CPU time 106.47 seconds
Started Jun 21 07:03:04 PM PDT 24
Finished Jun 21 07:04:56 PM PDT 24
Peak memory 250460 kb
Host smart-d5c15c88-3d04-4e83-a35f-80eb0b324df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217878747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2217878747
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3461516276
Short name T553
Test name
Test status
Simulation time 5724661887 ps
CPU time 69.07 seconds
Started Jun 21 07:03:03 PM PDT 24
Finished Jun 21 07:04:19 PM PDT 24
Peak memory 250292 kb
Host smart-a83731a2-40c9-4889-8723-c3b4b394694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461516276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3461516276
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2330093937
Short name T173
Test name
Test status
Simulation time 153322602 ps
CPU time 2.26 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 225524 kb
Host smart-b486b649-6b23-4c73-81e6-00d5e577d858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330093937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2330093937
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3195396526
Short name T753
Test name
Test status
Simulation time 4168347795 ps
CPU time 22.36 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:30 PM PDT 24
Peak memory 241468 kb
Host smart-567dd575-0a44-432a-9299-f103bb140fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195396526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3195396526
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3314134619
Short name T818
Test name
Test status
Simulation time 17566622 ps
CPU time 1.04 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 217632 kb
Host smart-85d5193a-7cb8-4aab-9f2b-57d5ebc11795
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314134619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3314134619
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3708623198
Short name T543
Test name
Test status
Simulation time 1815783339 ps
CPU time 5.69 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:14 PM PDT 24
Peak memory 225500 kb
Host smart-0300b4e6-e69b-4cdf-916e-f3e8eca7594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708623198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3708623198
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3770592983
Short name T330
Test name
Test status
Simulation time 31906735 ps
CPU time 2.46 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 233516 kb
Host smart-ca6f3dec-0278-4c55-b355-3bb406cefae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770592983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3770592983
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.56728379
Short name T513
Test name
Test status
Simulation time 4734374094 ps
CPU time 5.57 seconds
Started Jun 21 07:03:04 PM PDT 24
Finished Jun 21 07:03:17 PM PDT 24
Peak memory 222180 kb
Host smart-3ccce4fc-7c17-4d38-8459-860dc7bc42ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=56728379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direc
t.56728379
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1467651526
Short name T676
Test name
Test status
Simulation time 5347665634 ps
CPU time 83.2 seconds
Started Jun 21 07:02:59 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 258544 kb
Host smart-704d0b5c-4522-4134-936d-bc59798c1f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467651526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1467651526
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2310562049
Short name T491
Test name
Test status
Simulation time 2653016599 ps
CPU time 26.06 seconds
Started Jun 21 07:03:04 PM PDT 24
Finished Jun 21 07:03:36 PM PDT 24
Peak memory 217560 kb
Host smart-d71ec7cb-1716-4502-a3f2-1eb7572f52f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310562049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2310562049
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.655112448
Short name T318
Test name
Test status
Simulation time 26342677749 ps
CPU time 16 seconds
Started Jun 21 07:03:05 PM PDT 24
Finished Jun 21 07:03:27 PM PDT 24
Peak memory 217528 kb
Host smart-aeed92ef-dc18-4e76-b601-e12302ece7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655112448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.655112448
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1738948635
Short name T427
Test name
Test status
Simulation time 15637309 ps
CPU time 0.9 seconds
Started Jun 21 07:03:00 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 208024 kb
Host smart-41b62eb4-ab36-44d4-bf67-a8b3e19e3d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738948635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1738948635
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2422766694
Short name T782
Test name
Test status
Simulation time 71490310 ps
CPU time 0.84 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 206892 kb
Host smart-1fad8f95-724b-4336-b05b-103e4f404d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422766694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2422766694
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3819896853
Short name T462
Test name
Test status
Simulation time 1106057864 ps
CPU time 5.19 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:12 PM PDT 24
Peak memory 225544 kb
Host smart-73bfd090-e458-419a-bbc5-5192aeedf867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819896853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3819896853
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.253237987
Short name T353
Test name
Test status
Simulation time 30444905 ps
CPU time 0.72 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 206240 kb
Host smart-ce7aa48a-353a-46fe-9b5f-f12664ae4caa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253237987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.253237987
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.823814689
Short name T632
Test name
Test status
Simulation time 275080540 ps
CPU time 3.33 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:11 PM PDT 24
Peak memory 225500 kb
Host smart-69659d06-eda2-44ac-984e-381a116ee0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823814689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.823814689
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1542705553
Short name T657
Test name
Test status
Simulation time 49370262 ps
CPU time 0.78 seconds
Started Jun 21 07:03:03 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 206488 kb
Host smart-01f71a90-17a6-4de6-957e-cef7a422fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542705553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1542705553
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.271047196
Short name T437
Test name
Test status
Simulation time 88636489734 ps
CPU time 144.96 seconds
Started Jun 21 07:03:03 PM PDT 24
Finished Jun 21 07:05:35 PM PDT 24
Peak memory 239284 kb
Host smart-1a8ac7c5-270b-41ba-9d98-e7ae8fbe24a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271047196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.271047196
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1265061283
Short name T423
Test name
Test status
Simulation time 37603507849 ps
CPU time 56.75 seconds
Started Jun 21 07:03:05 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 233876 kb
Host smart-54ec7ba5-8ac7-4c74-bf54-988dd77f82ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265061283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1265061283
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1702554032
Short name T740
Test name
Test status
Simulation time 527926849 ps
CPU time 6.92 seconds
Started Jun 21 07:03:03 PM PDT 24
Finished Jun 21 07:03:17 PM PDT 24
Peak memory 234808 kb
Host smart-911480d4-50ba-4da4-9c3b-4cd934a22269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702554032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1702554032
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1951370373
Short name T518
Test name
Test status
Simulation time 3709130117 ps
CPU time 8.15 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:16 PM PDT 24
Peak memory 233908 kb
Host smart-9535512f-82cc-4219-8649-a3b231b735e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951370373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1951370373
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1742387211
Short name T768
Test name
Test status
Simulation time 2849614936 ps
CPU time 10.62 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 233900 kb
Host smart-e11eac3d-44a1-46d7-92c5-765f70c75f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742387211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1742387211
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.470436155
Short name T509
Test name
Test status
Simulation time 31339010 ps
CPU time 1.11 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 217628 kb
Host smart-77cab8e6-689b-4c0b-ad5a-f0c2639dbfb1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470436155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.470436155
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3729067422
Short name T280
Test name
Test status
Simulation time 871063351 ps
CPU time 4.35 seconds
Started Jun 21 07:03:03 PM PDT 24
Finished Jun 21 07:03:14 PM PDT 24
Peak memory 225472 kb
Host smart-da632fe3-2230-4b06-ab7a-622afc11e30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729067422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3729067422
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1866235167
Short name T417
Test name
Test status
Simulation time 10549197259 ps
CPU time 30 seconds
Started Jun 21 07:03:03 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 233912 kb
Host smart-d0422af9-0909-4c36-b2ff-7caa15e4d754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866235167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1866235167
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3489396868
Short name T820
Test name
Test status
Simulation time 1089133567 ps
CPU time 11.6 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:20 PM PDT 24
Peak memory 222640 kb
Host smart-06c54049-ad30-447f-aecd-8d1598570d8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3489396868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3489396868
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.987251626
Short name T946
Test name
Test status
Simulation time 210074174 ps
CPU time 1.09 seconds
Started Jun 21 07:03:05 PM PDT 24
Finished Jun 21 07:03:12 PM PDT 24
Peak memory 208036 kb
Host smart-ef5c79b0-974e-492d-9675-8ec6f38080f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987251626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.987251626
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1827924853
Short name T755
Test name
Test status
Simulation time 2108559644 ps
CPU time 9.48 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:18 PM PDT 24
Peak memory 217476 kb
Host smart-3048364a-ae9f-4285-a046-87757762e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827924853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1827924853
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2568821721
Short name T61
Test name
Test status
Simulation time 1325324366 ps
CPU time 5.9 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:13 PM PDT 24
Peak memory 217336 kb
Host smart-a16e9ecf-2def-49bb-b7f1-9082fc294543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568821721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2568821721
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3054861923
Short name T307
Test name
Test status
Simulation time 108606668 ps
CPU time 1.13 seconds
Started Jun 21 07:03:05 PM PDT 24
Finished Jun 21 07:03:12 PM PDT 24
Peak memory 208520 kb
Host smart-cb8af77b-f718-465a-96e8-64645bb3e5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054861923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3054861923
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.553186573
Short name T709
Test name
Test status
Simulation time 14350437 ps
CPU time 0.74 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 206908 kb
Host smart-aabbd7a8-c8d4-4a64-afa3-35fd9b284cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553186573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.553186573
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4275383797
Short name T876
Test name
Test status
Simulation time 10071965511 ps
CPU time 18.6 seconds
Started Jun 21 07:03:05 PM PDT 24
Finished Jun 21 07:03:30 PM PDT 24
Peak memory 233904 kb
Host smart-98485a0b-66d0-459e-9344-960e685fb91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275383797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4275383797
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.685935671
Short name T452
Test name
Test status
Simulation time 14489713 ps
CPU time 0.75 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:03:18 PM PDT 24
Peak memory 205732 kb
Host smart-5685ab3f-487c-4c79-bdc8-0e89e721b36c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685935671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.685935671
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3191306352
Short name T193
Test name
Test status
Simulation time 598697775 ps
CPU time 4.24 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:03:22 PM PDT 24
Peak memory 233696 kb
Host smart-826c8fd1-ea86-486e-bfc0-b5fdb20fccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191306352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3191306352
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2146449931
Short name T118
Test name
Test status
Simulation time 20901947 ps
CPU time 0.79 seconds
Started Jun 21 07:03:05 PM PDT 24
Finished Jun 21 07:03:12 PM PDT 24
Peak memory 205876 kb
Host smart-03b060fd-1285-419e-b87b-6a42942290d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146449931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2146449931
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.567705310
Short name T479
Test name
Test status
Simulation time 15245709410 ps
CPU time 65.86 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 250276 kb
Host smart-4f03500c-0070-4ca8-8c6e-64a262a35eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567705310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.567705310
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2546264395
Short name T764
Test name
Test status
Simulation time 31674627985 ps
CPU time 290.41 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:08:09 PM PDT 24
Peak memory 258496 kb
Host smart-29e05abd-b5b6-4e57-8d8d-f1f40f42319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546264395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2546264395
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.400932457
Short name T287
Test name
Test status
Simulation time 682078239 ps
CPU time 18.22 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:34 PM PDT 24
Peak memory 239320 kb
Host smart-0357a5d5-6eaa-4994-86ca-720f126e92f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400932457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.400932457
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.687561591
Short name T164
Test name
Test status
Simulation time 391941226 ps
CPU time 7.33 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:25 PM PDT 24
Peak memory 225532 kb
Host smart-ee3a503a-b594-4453-a0d6-d4a4fa68c3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687561591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.687561591
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3297752491
Short name T245
Test name
Test status
Simulation time 45702882489 ps
CPU time 94.21 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 241904 kb
Host smart-28c5cae5-1281-401b-9e93-30acc22a406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297752491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3297752491
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.604494299
Short name T899
Test name
Test status
Simulation time 135978307 ps
CPU time 1.19 seconds
Started Jun 21 07:02:59 PM PDT 24
Finished Jun 21 07:03:07 PM PDT 24
Peak memory 217628 kb
Host smart-967c53ee-e376-446e-a29b-7786f02d6acd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604494299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.604494299
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3068002280
Short name T282
Test name
Test status
Simulation time 31700086624 ps
CPU time 21.37 seconds
Started Jun 21 07:03:10 PM PDT 24
Finished Jun 21 07:03:37 PM PDT 24
Peak memory 225660 kb
Host smart-58123450-ffed-4b69-a801-34a1a38785e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068002280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3068002280
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2038266479
Short name T647
Test name
Test status
Simulation time 1137319091 ps
CPU time 5.68 seconds
Started Jun 21 07:03:14 PM PDT 24
Finished Jun 21 07:03:24 PM PDT 24
Peak memory 241892 kb
Host smart-f2684834-dd10-4790-bbca-a32f055bcce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038266479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2038266479
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1571416830
Short name T504
Test name
Test status
Simulation time 202198963 ps
CPU time 3.99 seconds
Started Jun 21 07:03:14 PM PDT 24
Finished Jun 21 07:03:23 PM PDT 24
Peak memory 221476 kb
Host smart-1a09874e-2bf6-421d-9f4c-1efe452f74c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1571416830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1571416830
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3944980587
Short name T570
Test name
Test status
Simulation time 23825321743 ps
CPU time 51.64 seconds
Started Jun 21 07:02:59 PM PDT 24
Finished Jun 21 07:03:57 PM PDT 24
Peak memory 217448 kb
Host smart-74d39e68-97ad-4daa-af9f-1131c160ea19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944980587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3944980587
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3240251342
Short name T668
Test name
Test status
Simulation time 270263293 ps
CPU time 2.39 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 217332 kb
Host smart-ec636ecd-c17e-42d9-b339-6430e7d20a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240251342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3240251342
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.930588988
Short name T315
Test name
Test status
Simulation time 781194953 ps
CPU time 2.76 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:21 PM PDT 24
Peak memory 217312 kb
Host smart-0f059fdb-4afb-4ce8-8555-7065cb2fcb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930588988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.930588988
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1778091564
Short name T968
Test name
Test status
Simulation time 103595928 ps
CPU time 0.85 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:17 PM PDT 24
Peak memory 206892 kb
Host smart-8fe6c92a-2ed7-43dc-a5f6-3dbd32d6e2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778091564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1778091564
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.914345204
Short name T925
Test name
Test status
Simulation time 3559317327 ps
CPU time 9.28 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:03:26 PM PDT 24
Peak memory 241940 kb
Host smart-9ea42cd8-6903-4499-9f6d-0c2fa026d955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914345204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.914345204
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3064885525
Short name T664
Test name
Test status
Simulation time 152474446 ps
CPU time 0.75 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:03:18 PM PDT 24
Peak memory 206276 kb
Host smart-c5861625-9c58-4416-92a2-38cd0bd9e21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064885525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3064885525
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3120084640
Short name T687
Test name
Test status
Simulation time 13123012844 ps
CPU time 18.2 seconds
Started Jun 21 07:03:14 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 225760 kb
Host smart-685ff1c7-c5da-413f-84f7-cca7ccb34dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120084640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3120084640
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3594570919
Short name T860
Test name
Test status
Simulation time 14337561 ps
CPU time 0.81 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 206836 kb
Host smart-bd3585bd-463b-4fcf-a3fd-9d1d5efbaab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594570919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3594570919
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1124985156
Short name T168
Test name
Test status
Simulation time 16463860534 ps
CPU time 59.46 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:04:17 PM PDT 24
Peak memory 257348 kb
Host smart-988be1e7-b401-48b9-998f-fd074788fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124985156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1124985156
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2033968058
Short name T529
Test name
Test status
Simulation time 990583892 ps
CPU time 4.63 seconds
Started Jun 21 07:03:14 PM PDT 24
Finished Jun 21 07:03:24 PM PDT 24
Peak memory 233788 kb
Host smart-bb7d1096-4c02-45c6-be63-15333ebe53fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033968058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2033968058
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2146659678
Short name T101
Test name
Test status
Simulation time 113908257 ps
CPU time 2.79 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:03:21 PM PDT 24
Peak memory 233724 kb
Host smart-4e9098ef-e5d5-4e89-b549-14c1a67f3845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146659678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2146659678
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3396752315
Short name T371
Test name
Test status
Simulation time 2811827866 ps
CPU time 25.37 seconds
Started Jun 21 07:03:14 PM PDT 24
Finished Jun 21 07:03:45 PM PDT 24
Peak memory 233864 kb
Host smart-88126d60-e805-49e6-bd47-6eb58bdddae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396752315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3396752315
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1556059488
Short name T453
Test name
Test status
Simulation time 196077277 ps
CPU time 1.04 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:17 PM PDT 24
Peak memory 218876 kb
Host smart-5c67440c-4948-4711-8828-c5b06b4074fc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556059488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1556059488
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.776060528
Short name T221
Test name
Test status
Simulation time 9656995245 ps
CPU time 31.09 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 241788 kb
Host smart-1370685a-22d5-4294-9e71-fe599ac09c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776060528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.776060528
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.259719171
Short name T661
Test name
Test status
Simulation time 294802549 ps
CPU time 4.4 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:22 PM PDT 24
Peak memory 225528 kb
Host smart-f32cb46a-fd88-465b-a71d-97e40d4f26e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259719171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.259719171
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1766688000
Short name T46
Test name
Test status
Simulation time 8077748154 ps
CPU time 16.98 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:34 PM PDT 24
Peak memory 220216 kb
Host smart-7ed8e9eb-7c25-4ae1-b3df-fadcc3ccb3ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1766688000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1766688000
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1954287038
Short name T652
Test name
Test status
Simulation time 1431025663 ps
CPU time 9.22 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:03:27 PM PDT 24
Peak memory 218644 kb
Host smart-f8fade2d-4b8f-4099-91d8-eb585b3b6a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954287038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1954287038
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1778028326
Short name T607
Test name
Test status
Simulation time 7788972186 ps
CPU time 5.71 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:24 PM PDT 24
Peak memory 217492 kb
Host smart-e158e22a-1e66-4b15-8f84-4da24d70b336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778028326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1778028326
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4251305528
Short name T787
Test name
Test status
Simulation time 26799835 ps
CPU time 1.11 seconds
Started Jun 21 07:03:12 PM PDT 24
Finished Jun 21 07:03:18 PM PDT 24
Peak memory 208904 kb
Host smart-cb7fcc07-7bc2-48eb-b756-4eec9e0c7897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251305528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4251305528
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2677561586
Short name T389
Test name
Test status
Simulation time 189073489 ps
CPU time 0.82 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 206892 kb
Host smart-dd8cdb04-48f3-4ce3-89d9-19b53e727871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677561586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2677561586
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.499462550
Short name T43
Test name
Test status
Simulation time 248388781 ps
CPU time 2.89 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 233808 kb
Host smart-76a8caaa-9094-4a42-8874-7b7303563d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499462550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.499462550
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1730764553
Short name T466
Test name
Test status
Simulation time 89397994 ps
CPU time 0.71 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:03:33 PM PDT 24
Peak memory 205724 kb
Host smart-414587ad-893e-4e3d-ba7c-77242ec3bf1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730764553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1730764553
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2280169883
Short name T362
Test name
Test status
Simulation time 522820665 ps
CPU time 7.45 seconds
Started Jun 21 07:03:23 PM PDT 24
Finished Jun 21 07:03:39 PM PDT 24
Peak memory 233764 kb
Host smart-2c314b64-085c-48d5-abe4-de2431a3d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280169883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2280169883
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4234366166
Short name T834
Test name
Test status
Simulation time 43010270 ps
CPU time 0.75 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 206772 kb
Host smart-9ab705bf-7c49-4841-9ccc-aee747de843a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234366166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4234366166
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3858705721
Short name T401
Test name
Test status
Simulation time 19723170525 ps
CPU time 34.83 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:03:59 PM PDT 24
Peak memory 240620 kb
Host smart-5a2ca799-3a14-4b0c-9838-fcb60b3b1523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858705721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3858705721
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2528512456
Short name T562
Test name
Test status
Simulation time 321322766 ps
CPU time 4.77 seconds
Started Jun 21 07:03:23 PM PDT 24
Finished Jun 21 07:03:36 PM PDT 24
Peak memory 220532 kb
Host smart-8b4dc4e6-a714-4a85-b60e-c49af54a8982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528512456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2528512456
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2197190904
Short name T382
Test name
Test status
Simulation time 2456030589 ps
CPU time 8.91 seconds
Started Jun 21 07:03:23 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 242072 kb
Host smart-248a3373-2782-4d92-a514-6e218e4c8449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197190904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2197190904
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2880953266
Short name T116
Test name
Test status
Simulation time 1278992474 ps
CPU time 5.31 seconds
Started Jun 21 07:03:23 PM PDT 24
Finished Jun 21 07:03:35 PM PDT 24
Peak memory 233800 kb
Host smart-bf084774-01f6-41bf-8603-df97c576f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880953266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2880953266
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2996017262
Short name T719
Test name
Test status
Simulation time 842024827 ps
CPU time 5.96 seconds
Started Jun 21 07:03:19 PM PDT 24
Finished Jun 21 07:03:29 PM PDT 24
Peak memory 233772 kb
Host smart-2e74fd47-dc75-4288-af0e-8f68f07c6bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996017262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2996017262
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.975054317
Short name T601
Test name
Test status
Simulation time 27844634 ps
CPU time 1.07 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:17 PM PDT 24
Peak memory 217608 kb
Host smart-4a87fbb1-2394-4624-90d8-aeb5ae7d05c0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975054317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.975054317
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2883829446
Short name T520
Test name
Test status
Simulation time 1050678679 ps
CPU time 3.54 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:22 PM PDT 24
Peak memory 225576 kb
Host smart-68b48fa7-8d99-42bf-8793-95773ba3d730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883829446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2883829446
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.807926580
Short name T468
Test name
Test status
Simulation time 6340213618 ps
CPU time 10.68 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:27 PM PDT 24
Peak memory 233832 kb
Host smart-1611ab65-9871-4a16-a874-f9351094baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807926580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.807926580
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1974479649
Short name T739
Test name
Test status
Simulation time 983931848 ps
CPU time 7.89 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:03:32 PM PDT 24
Peak memory 224196 kb
Host smart-6218072f-2df5-4e90-b07e-af4694b62526
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1974479649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1974479649
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.832273948
Short name T155
Test name
Test status
Simulation time 1947203904 ps
CPU time 35.4 seconds
Started Jun 21 07:03:21 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 250236 kb
Host smart-54e5d287-1cf5-4356-8fa6-f7133b9cae57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832273948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.832273948
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2959648127
Short name T488
Test name
Test status
Simulation time 6641661092 ps
CPU time 32.9 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:50 PM PDT 24
Peak memory 217512 kb
Host smart-36971267-f6be-437f-af47-df596fb482eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959648127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2959648127
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1060090400
Short name T923
Test name
Test status
Simulation time 59117757044 ps
CPU time 18.39 seconds
Started Jun 21 07:03:11 PM PDT 24
Finished Jun 21 07:03:35 PM PDT 24
Peak memory 217496 kb
Host smart-45bc42d9-6a43-46d9-93a8-62d0c60ad104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060090400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1060090400
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2634361333
Short name T691
Test name
Test status
Simulation time 650466763 ps
CPU time 2.5 seconds
Started Jun 21 07:03:10 PM PDT 24
Finished Jun 21 07:03:18 PM PDT 24
Peak memory 217380 kb
Host smart-13ccec63-8c79-4b3e-8f39-9da7c3f867b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634361333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2634361333
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3505941951
Short name T745
Test name
Test status
Simulation time 64692223 ps
CPU time 0.82 seconds
Started Jun 21 07:03:13 PM PDT 24
Finished Jun 21 07:03:19 PM PDT 24
Peak memory 206888 kb
Host smart-e710563c-77ed-4fd0-8cfd-b5a15bf44f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505941951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3505941951
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3775892105
Short name T852
Test name
Test status
Simulation time 183015983 ps
CPU time 2.47 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:03:26 PM PDT 24
Peak memory 225596 kb
Host smart-7769d5c2-be79-4f62-89e3-33484211e89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775892105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3775892105
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2639902645
Short name T428
Test name
Test status
Simulation time 41703538 ps
CPU time 0.76 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:03:27 PM PDT 24
Peak memory 206304 kb
Host smart-6e1a8cd5-1aed-433f-a008-15d26acba6d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639902645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2639902645
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2291008035
Short name T792
Test name
Test status
Simulation time 15729124612 ps
CPU time 11.97 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:03:45 PM PDT 24
Peak memory 225604 kb
Host smart-fb6f254a-2405-489e-af9e-450d62a946b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291008035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2291008035
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2233711572
Short name T909
Test name
Test status
Simulation time 35289964 ps
CPU time 0.81 seconds
Started Jun 21 07:03:25 PM PDT 24
Finished Jun 21 07:03:34 PM PDT 24
Peak memory 207816 kb
Host smart-23ea821d-29ac-4073-bb4b-75fdb39aaa47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233711572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2233711572
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2841764109
Short name T190
Test name
Test status
Simulation time 27292567320 ps
CPU time 216.81 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:07:06 PM PDT 24
Peak memory 250316 kb
Host smart-37910e7a-7cba-4e6d-be0f-e28cfe7ee032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841764109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2841764109
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2293837866
Short name T124
Test name
Test status
Simulation time 2355542635 ps
CPU time 52.08 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:04:25 PM PDT 24
Peak memory 251204 kb
Host smart-dd3ccf3f-6df7-4fea-a031-23241bbc5a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293837866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2293837866
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2021197475
Short name T48
Test name
Test status
Simulation time 44884728391 ps
CPU time 72.66 seconds
Started Jun 21 07:03:21 PM PDT 24
Finished Jun 21 07:04:39 PM PDT 24
Peak memory 248988 kb
Host smart-b2db8b71-110c-4405-a88e-e3d77bcced3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021197475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2021197475
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1727195019
Short name T609
Test name
Test status
Simulation time 10663844000 ps
CPU time 17.44 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:03:47 PM PDT 24
Peak memory 225648 kb
Host smart-5b19f2d4-aa6c-4133-8ed3-86317d17b52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727195019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1727195019
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3358833102
Short name T966
Test name
Test status
Simulation time 1074048612 ps
CPU time 8.42 seconds
Started Jun 21 07:03:25 PM PDT 24
Finished Jun 21 07:03:42 PM PDT 24
Peak memory 236188 kb
Host smart-9abf285f-9574-4fd8-a1e3-5422f7ea3834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358833102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3358833102
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3959305061
Short name T735
Test name
Test status
Simulation time 59043549 ps
CPU time 1.12 seconds
Started Jun 21 07:03:26 PM PDT 24
Finished Jun 21 07:03:36 PM PDT 24
Peak memory 217628 kb
Host smart-1fb08d9f-f99c-4671-aea8-8bd3d2a0c3d9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959305061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3959305061
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4173688211
Short name T669
Test name
Test status
Simulation time 1346996309 ps
CPU time 9.6 seconds
Started Jun 21 07:03:25 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 241936 kb
Host smart-a8e575f4-1866-4616-9e46-758700731b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173688211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4173688211
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.348785002
Short name T630
Test name
Test status
Simulation time 635995998 ps
CPU time 8.32 seconds
Started Jun 21 07:03:26 PM PDT 24
Finished Jun 21 07:03:42 PM PDT 24
Peak memory 223040 kb
Host smart-732f9813-d37b-4889-8103-8fd62bb03d06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=348785002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.348785002
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3470307667
Short name T716
Test name
Test status
Simulation time 8647387496 ps
CPU time 44.07 seconds
Started Jun 21 07:03:21 PM PDT 24
Finished Jun 21 07:04:11 PM PDT 24
Peak memory 217424 kb
Host smart-5afd55a9-9f1a-4a93-81a3-ee6053677b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470307667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3470307667
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2007970020
Short name T346
Test name
Test status
Simulation time 595675341 ps
CPU time 1.47 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:03:31 PM PDT 24
Peak memory 207976 kb
Host smart-59603de3-0e75-4024-85f7-44c815d22d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007970020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2007970020
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1984550879
Short name T327
Test name
Test status
Simulation time 343442660 ps
CPU time 4.56 seconds
Started Jun 21 07:03:25 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 217276 kb
Host smart-97edf487-b2cd-4f05-bafe-6be40c4000e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984550879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1984550879
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2664454316
Short name T310
Test name
Test status
Simulation time 875100115 ps
CPU time 0.9 seconds
Started Jun 21 07:03:26 PM PDT 24
Finished Jun 21 07:03:35 PM PDT 24
Peak memory 206900 kb
Host smart-8e76b44a-7fd1-480a-8f74-773d185ec583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664454316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2664454316
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2031302276
Short name T708
Test name
Test status
Simulation time 1673349214 ps
CPU time 12.03 seconds
Started Jun 21 07:03:21 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 233748 kb
Host smart-b090b621-91fd-4c9b-b8d8-5de6fcd9863b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031302276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2031302276
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3165607291
Short name T54
Test name
Test status
Simulation time 30047553 ps
CPU time 0.74 seconds
Started Jun 21 07:03:21 PM PDT 24
Finished Jun 21 07:03:28 PM PDT 24
Peak memory 205720 kb
Host smart-9389f0ae-cd11-42b4-b1aa-49f55c1e8e52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165607291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3165607291
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2575502365
Short name T826
Test name
Test status
Simulation time 2875980493 ps
CPU time 22.72 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:03:53 PM PDT 24
Peak memory 233832 kb
Host smart-57b40a2c-5d4c-4d32-9954-b6ee6749390e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575502365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2575502365
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3544211058
Short name T524
Test name
Test status
Simulation time 13110210 ps
CPU time 0.74 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:03:33 PM PDT 24
Peak memory 206824 kb
Host smart-5155192a-2bbb-4465-ab65-d80868515fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544211058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3544211058
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.651861834
Short name T4
Test name
Test status
Simulation time 35125666097 ps
CPU time 254.15 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:07:46 PM PDT 24
Peak memory 250312 kb
Host smart-75cab716-b184-437f-96f5-061f786eb7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651861834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.651861834
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3767748790
Short name T406
Test name
Test status
Simulation time 144133289714 ps
CPU time 310.87 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:08:44 PM PDT 24
Peak memory 266916 kb
Host smart-578ec80c-916c-4d3f-bb1a-6065b1a419a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767748790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3767748790
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3832089609
Short name T26
Test name
Test status
Simulation time 3634398518 ps
CPU time 81.76 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:04:54 PM PDT 24
Peak memory 265412 kb
Host smart-23183a3e-4845-4b32-915a-0871149cfb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832089609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3832089609
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2650272804
Short name T286
Test name
Test status
Simulation time 2007814252 ps
CPU time 37.46 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:04:02 PM PDT 24
Peak memory 233788 kb
Host smart-824713f6-5014-491e-a5ac-ef8b1a18cc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650272804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2650272804
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3194165736
Short name T678
Test name
Test status
Simulation time 13405340090 ps
CPU time 14.31 seconds
Started Jun 21 07:03:19 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 225712 kb
Host smart-a8e7a790-3047-42c4-a701-178b32c959d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194165736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3194165736
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1137915640
Short name T791
Test name
Test status
Simulation time 5936949951 ps
CPU time 7.23 seconds
Started Jun 21 07:03:26 PM PDT 24
Finished Jun 21 07:03:41 PM PDT 24
Peak memory 225612 kb
Host smart-f6177215-620f-413e-8975-86bb2c045bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137915640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1137915640
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3715217952
Short name T688
Test name
Test status
Simulation time 31372782 ps
CPU time 1.12 seconds
Started Jun 21 07:03:26 PM PDT 24
Finished Jun 21 07:03:35 PM PDT 24
Peak memory 217628 kb
Host smart-f7488f39-232e-4733-a309-6cb5fb1506e2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715217952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3715217952
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1073298578
Short name T420
Test name
Test status
Simulation time 246682495 ps
CPU time 3.3 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:03:28 PM PDT 24
Peak memory 233772 kb
Host smart-52126813-4e2d-4d5e-b530-589d3aea09ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073298578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1073298578
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2044825610
Short name T773
Test name
Test status
Simulation time 4377524128 ps
CPU time 8.69 seconds
Started Jun 21 07:03:23 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 241464 kb
Host smart-f98149a9-a315-4fc7-8bff-c371f93cb056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044825610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2044825610
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.272752781
Short name T744
Test name
Test status
Simulation time 2179855706 ps
CPU time 6.37 seconds
Started Jun 21 07:03:26 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 221452 kb
Host smart-51f8287e-3c17-48ba-8253-8c008eafed10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=272752781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.272752781
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.797795772
Short name T684
Test name
Test status
Simulation time 194916019 ps
CPU time 0.84 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:03:30 PM PDT 24
Peak memory 207552 kb
Host smart-f56a1cfc-e15d-4583-8daf-cb956adcdcaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797795772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.797795772
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3130973089
Short name T432
Test name
Test status
Simulation time 7297166963 ps
CPU time 13.78 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 217540 kb
Host smart-68cb7948-2ba9-430c-aed5-1716c92201b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130973089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3130973089
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2966275829
Short name T339
Test name
Test status
Simulation time 14457442014 ps
CPU time 22.89 seconds
Started Jun 21 07:03:24 PM PDT 24
Finished Jun 21 07:03:55 PM PDT 24
Peak memory 217496 kb
Host smart-2af18be9-0ddf-4ff1-937e-a14467440c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966275829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2966275829
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3655834807
Short name T783
Test name
Test status
Simulation time 288705683 ps
CPU time 3.24 seconds
Started Jun 21 07:03:19 PM PDT 24
Finished Jun 21 07:03:26 PM PDT 24
Peak memory 217316 kb
Host smart-69ef18a0-7f91-4a43-a6ea-7c5fe6c72512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655834807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3655834807
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3721604862
Short name T337
Test name
Test status
Simulation time 48207815 ps
CPU time 0.77 seconds
Started Jun 21 07:03:23 PM PDT 24
Finished Jun 21 07:03:32 PM PDT 24
Peak memory 206864 kb
Host smart-340c1cb9-8ed8-49f7-aad7-3c1235abaa71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721604862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3721604862
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4212687048
Short name T272
Test name
Test status
Simulation time 2644116161 ps
CPU time 5.03 seconds
Started Jun 21 07:03:22 PM PDT 24
Finished Jun 21 07:03:34 PM PDT 24
Peak memory 225640 kb
Host smart-231abaee-faa8-41cf-b7e2-4018cf2f7578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212687048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4212687048
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1555674473
Short name T478
Test name
Test status
Simulation time 79186462 ps
CPU time 0.78 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:37 PM PDT 24
Peak memory 205748 kb
Host smart-697cbd48-d133-4fdd-b429-8448a8df4a9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555674473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1555674473
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3238701403
Short name T418
Test name
Test status
Simulation time 170754200 ps
CPU time 2.94 seconds
Started Jun 21 07:03:32 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 225516 kb
Host smart-21c8dd99-8fcf-4f51-b918-9066e85334d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238701403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3238701403
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.508286468
Short name T510
Test name
Test status
Simulation time 20763245 ps
CPU time 0.78 seconds
Started Jun 21 07:03:20 PM PDT 24
Finished Jun 21 07:03:26 PM PDT 24
Peak memory 207528 kb
Host smart-b4dd4e64-a865-4c74-8cc6-4c2058949625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508286468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.508286468
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3645690271
Short name T28
Test name
Test status
Simulation time 54792671386 ps
CPU time 376.99 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:09:55 PM PDT 24
Peak memory 269024 kb
Host smart-509a69a8-5cf9-4ba6-a862-74fe91b156c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645690271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3645690271
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2193827337
Short name T728
Test name
Test status
Simulation time 5388345347 ps
CPU time 72.36 seconds
Started Jun 21 07:03:28 PM PDT 24
Finished Jun 21 07:04:48 PM PDT 24
Peak memory 257532 kb
Host smart-c790c4a1-ecd0-445a-831b-858c7ad7c095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193827337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2193827337
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.220036765
Short name T934
Test name
Test status
Simulation time 1056599160 ps
CPU time 5.6 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:03:44 PM PDT 24
Peak memory 233792 kb
Host smart-01c93256-a6e4-4678-9997-6428c186d7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220036765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.220036765
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1936741567
Short name T517
Test name
Test status
Simulation time 1257555045 ps
CPU time 3.59 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 225616 kb
Host smart-ff17517b-e8a0-40b1-a6ab-439945c71e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936741567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1936741567
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1865438286
Short name T39
Test name
Test status
Simulation time 1748977313 ps
CPU time 20.43 seconds
Started Jun 21 07:03:28 PM PDT 24
Finished Jun 21 07:03:56 PM PDT 24
Peak memory 240260 kb
Host smart-b1063054-f4a5-4d5f-b3f2-ae5b1095f2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865438286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1865438286
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3246531719
Short name T963
Test name
Test status
Simulation time 60211584 ps
CPU time 1.11 seconds
Started Jun 21 07:03:32 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 217620 kb
Host smart-5e990a9c-d2ae-42a8-ad51-3d5e9d75d36b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246531719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3246531719
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.890513801
Short name T227
Test name
Test status
Simulation time 10701319489 ps
CPU time 23.17 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:59 PM PDT 24
Peak memory 233736 kb
Host smart-39275011-cff1-4701-b135-a89824cb9ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890513801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.890513801
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3808165566
Short name T254
Test name
Test status
Simulation time 9351146526 ps
CPU time 7.48 seconds
Started Jun 21 07:03:33 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 225560 kb
Host smart-8dea3dc1-68ea-4954-bdee-5e4a8033b9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808165566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3808165566
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.310319940
Short name T525
Test name
Test status
Simulation time 52675811 ps
CPU time 3.04 seconds
Started Jun 21 07:03:27 PM PDT 24
Finished Jun 21 07:03:39 PM PDT 24
Peak memory 221544 kb
Host smart-78cae972-0ed6-4cd5-a5d8-c05fd3123474
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310319940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.310319940
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1630222449
Short name T829
Test name
Test status
Simulation time 50526222 ps
CPU time 0.9 seconds
Started Jun 21 07:03:28 PM PDT 24
Finished Jun 21 07:03:37 PM PDT 24
Peak memory 206952 kb
Host smart-635d3e03-8bdc-4049-95c3-215f0f0d21d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630222449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1630222449
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2866155203
Short name T387
Test name
Test status
Simulation time 30192867887 ps
CPU time 27.71 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:04:06 PM PDT 24
Peak memory 217448 kb
Host smart-318cd938-311c-4f49-b71f-fa26fb84a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866155203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2866155203
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3332207492
Short name T872
Test name
Test status
Simulation time 10787873 ps
CPU time 0.71 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:37 PM PDT 24
Peak memory 206584 kb
Host smart-5f43eb41-4890-4095-aa07-ebe10b24f864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332207492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3332207492
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.513798774
Short name T846
Test name
Test status
Simulation time 118893196 ps
CPU time 2.97 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:41 PM PDT 24
Peak memory 217348 kb
Host smart-269361dd-a2bb-4262-9a2d-d73937a1140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513798774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.513798774
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.995595352
Short name T827
Test name
Test status
Simulation time 56618897 ps
CPU time 0.76 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:37 PM PDT 24
Peak memory 206860 kb
Host smart-b6345154-1133-4f8e-8563-1f3ec6c6ddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995595352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.995595352
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1997701803
Short name T831
Test name
Test status
Simulation time 195606748 ps
CPU time 4.76 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:41 PM PDT 24
Peak memory 225520 kb
Host smart-92ce95b4-987d-4f64-91e3-56cc489c2c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997701803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1997701803
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.488905520
Short name T863
Test name
Test status
Simulation time 10779249 ps
CPU time 0.69 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:03:39 PM PDT 24
Peak memory 206300 kb
Host smart-5e76de82-eef4-4df7-8eeb-629414b31553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488905520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.488905520
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2523851152
Short name T320
Test name
Test status
Simulation time 98390016 ps
CPU time 2.07 seconds
Started Jun 21 07:03:33 PM PDT 24
Finished Jun 21 07:03:42 PM PDT 24
Peak memory 224980 kb
Host smart-6ac28aa4-31c2-4447-97b9-752636e58e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523851152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2523851152
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1664461339
Short name T608
Test name
Test status
Simulation time 61614475 ps
CPU time 0.8 seconds
Started Jun 21 07:03:27 PM PDT 24
Finished Jun 21 07:03:36 PM PDT 24
Peak memory 207472 kb
Host smart-fbc4de1e-04db-407f-8c49-23ff6f6b3c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664461339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1664461339
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3636216959
Short name T528
Test name
Test status
Simulation time 1090281429 ps
CPU time 21.44 seconds
Started Jun 21 07:03:33 PM PDT 24
Finished Jun 21 07:04:01 PM PDT 24
Peak memory 250188 kb
Host smart-52dccc05-dfca-42dc-88e0-3dc458d7da30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636216959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3636216959
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3638273671
Short name T871
Test name
Test status
Simulation time 79532147303 ps
CPU time 793.98 seconds
Started Jun 21 07:03:28 PM PDT 24
Finished Jun 21 07:16:50 PM PDT 24
Peak memory 271032 kb
Host smart-2289fd4a-a77c-4aa8-a9c7-1a8fe7e1b1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638273671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3638273671
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3219589676
Short name T800
Test name
Test status
Simulation time 16667030660 ps
CPU time 58.41 seconds
Started Jun 21 07:03:34 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 238380 kb
Host smart-a5a1e116-3205-4c97-8155-0add4cbdea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219589676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3219589676
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3066121940
Short name T317
Test name
Test status
Simulation time 731781249 ps
CPU time 3.42 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:41 PM PDT 24
Peak memory 233784 kb
Host smart-f54f9ace-5423-43dc-b5af-8d316957d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066121940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3066121940
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.89425134
Short name T928
Test name
Test status
Simulation time 692711992 ps
CPU time 6.88 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:44 PM PDT 24
Peak memory 233776 kb
Host smart-60f048d5-e119-4f5a-91c2-17e7d914ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89425134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.89425134
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3484317111
Short name T595
Test name
Test status
Simulation time 1830494231 ps
CPU time 26 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 241544 kb
Host smart-7937947a-d9c1-4ae8-ad8f-76e985f786a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484317111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3484317111
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1038537630
Short name T535
Test name
Test status
Simulation time 27184521 ps
CPU time 1 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 217644 kb
Host smart-0fff25df-fca7-4bed-9b39-0844f1899ba7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038537630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1038537630
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2747632863
Short name T978
Test name
Test status
Simulation time 1083102195 ps
CPU time 6.99 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 233608 kb
Host smart-2bd050b1-6f38-4ced-bd3c-53f9c0756478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747632863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2747632863
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3841363351
Short name T833
Test name
Test status
Simulation time 3237253541 ps
CPU time 6.13 seconds
Started Jun 21 07:03:33 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 233864 kb
Host smart-c3cbf19e-d8cc-4355-977b-027ed5f60076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841363351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3841363351
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1112905881
Short name T134
Test name
Test status
Simulation time 1091005936 ps
CPU time 14.86 seconds
Started Jun 21 07:03:26 PM PDT 24
Finished Jun 21 07:03:49 PM PDT 24
Peak memory 222688 kb
Host smart-e1abb15c-a9e7-456b-9f59-426dc7e61f94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1112905881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1112905881
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.205104784
Short name T473
Test name
Test status
Simulation time 2041151864 ps
CPU time 17.54 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:55 PM PDT 24
Peak memory 220708 kb
Host smart-4423d9c9-f27c-4879-b0de-3a40cadc3f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205104784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.205104784
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1816359166
Short name T485
Test name
Test status
Simulation time 215053647 ps
CPU time 1.93 seconds
Started Jun 21 07:03:28 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 217072 kb
Host smart-6c0332e4-d8f1-4e71-8efe-d6f03d19af3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816359166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1816359166
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.234555810
Short name T810
Test name
Test status
Simulation time 48107821 ps
CPU time 0.84 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:37 PM PDT 24
Peak memory 207744 kb
Host smart-39861d88-48ef-4fd4-97f2-f0b85ad01ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234555810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.234555810
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3761835728
Short name T402
Test name
Test status
Simulation time 113582330 ps
CPU time 0.76 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 206892 kb
Host smart-8f8e06c8-eb64-42ba-ae8b-a39669ab9a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761835728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3761835728
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1474699001
Short name T665
Test name
Test status
Simulation time 3757373978 ps
CPU time 4.7 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 225620 kb
Host smart-b963c2ba-5a29-4c7a-ab22-f4dc3d8a286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474699001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1474699001
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.467850410
Short name T958
Test name
Test status
Simulation time 17427476 ps
CPU time 0.76 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:42 PM PDT 24
Peak memory 205744 kb
Host smart-a3a833b9-17b9-47a7-87d5-7d15bdee4b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467850410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.467850410
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2323723664
Short name T817
Test name
Test status
Simulation time 726399815 ps
CPU time 8.78 seconds
Started Jun 21 07:02:32 PM PDT 24
Finished Jun 21 07:02:46 PM PDT 24
Peak memory 233772 kb
Host smart-25e0b260-e46b-4df7-a6b1-dcaa6c88a4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323723664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2323723664
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2831264227
Short name T926
Test name
Test status
Simulation time 37419449 ps
CPU time 0.74 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:02:34 PM PDT 24
Peak memory 206820 kb
Host smart-9890b23d-b0bc-41a5-ab09-0e224ef1252a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831264227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2831264227
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3670078455
Short name T159
Test name
Test status
Simulation time 24976064704 ps
CPU time 55.45 seconds
Started Jun 21 07:02:30 PM PDT 24
Finished Jun 21 07:03:31 PM PDT 24
Peak memory 240300 kb
Host smart-6e8bbcdb-636a-46ee-9081-de3c3c55eb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670078455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3670078455
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4267992431
Short name T278
Test name
Test status
Simulation time 8961890548 ps
CPU time 121.29 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:04:35 PM PDT 24
Peak memory 251716 kb
Host smart-f091f96f-3535-4bab-96c1-0fbf165f9beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267992431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4267992431
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2415961135
Short name T911
Test name
Test status
Simulation time 2231190909 ps
CPU time 38.21 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 256612 kb
Host smart-32142c68-a1ae-4de3-900c-00eacb8caebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415961135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2415961135
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3031173904
Short name T720
Test name
Test status
Simulation time 142596476 ps
CPU time 3.42 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:02:35 PM PDT 24
Peak memory 233796 kb
Host smart-6b8af0ee-2455-4ad6-877a-0c97039a2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031173904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3031173904
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1416721082
Short name T196
Test name
Test status
Simulation time 5225649140 ps
CPU time 14.61 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:02:47 PM PDT 24
Peak memory 229520 kb
Host smart-e05ced1d-2a97-4d75-bd88-b281b27fc1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416721082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1416721082
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1265299095
Short name T663
Test name
Test status
Simulation time 1585794881 ps
CPU time 20.34 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 233708 kb
Host smart-9da0b95c-84bf-4154-832f-5904429bdf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265299095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1265299095
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1878275339
Short name T47
Test name
Test status
Simulation time 167461975 ps
CPU time 1 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:02:34 PM PDT 24
Peak memory 217620 kb
Host smart-876189ed-b11b-45ad-9e75-17c70c796489
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878275339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1878275339
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2538139597
Short name T758
Test name
Test status
Simulation time 2699874801 ps
CPU time 17.83 seconds
Started Jun 21 07:02:32 PM PDT 24
Finished Jun 21 07:02:55 PM PDT 24
Peak memory 249816 kb
Host smart-c3a9a42e-d1da-4a3d-9f7c-9e4a9bf22ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538139597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2538139597
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3981943214
Short name T415
Test name
Test status
Simulation time 32126036 ps
CPU time 2.61 seconds
Started Jun 21 07:02:29 PM PDT 24
Finished Jun 21 07:02:37 PM PDT 24
Peak memory 233488 kb
Host smart-68d7575a-a441-493b-820b-14bb2d1d2fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981943214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3981943214
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.990125536
Short name T944
Test name
Test status
Simulation time 3068132339 ps
CPU time 12.56 seconds
Started Jun 21 07:02:32 PM PDT 24
Finished Jun 21 07:02:50 PM PDT 24
Peak memory 220876 kb
Host smart-c20fb171-53bb-46c7-86c9-e1b940e35cd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=990125536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.990125536
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4275052702
Short name T59
Test name
Test status
Simulation time 99415735 ps
CPU time 0.94 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:44 PM PDT 24
Peak memory 236428 kb
Host smart-ab93e9cc-ab1f-4c4e-b5e5-3fefa10b6b4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275052702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4275052702
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1073438908
Short name T683
Test name
Test status
Simulation time 15735473694 ps
CPU time 25.08 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:02:56 PM PDT 24
Peak memory 217512 kb
Host smart-f339e67e-e1df-4873-9580-377e15b5b04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073438908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1073438908
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1960087985
Short name T975
Test name
Test status
Simulation time 2692568333 ps
CPU time 6.88 seconds
Started Jun 21 07:02:27 PM PDT 24
Finished Jun 21 07:02:39 PM PDT 24
Peak memory 217416 kb
Host smart-8086673b-b87d-4862-9c88-a152de0e4efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960087985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1960087985
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1294205278
Short name T515
Test name
Test status
Simulation time 4376343769 ps
CPU time 9.77 seconds
Started Jun 21 07:02:28 PM PDT 24
Finished Jun 21 07:02:43 PM PDT 24
Peak memory 217580 kb
Host smart-a0b59ce9-6864-40e1-9eb2-d77a27a52104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294205278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1294205278
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2006491393
Short name T25
Test name
Test status
Simulation time 108946334 ps
CPU time 0.78 seconds
Started Jun 21 07:02:31 PM PDT 24
Finished Jun 21 07:02:37 PM PDT 24
Peak memory 206888 kb
Host smart-f31ed980-b6b8-4a1c-aa5c-c0b7fdccb5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006491393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2006491393
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1206480844
Short name T851
Test name
Test status
Simulation time 9384928681 ps
CPU time 31.14 seconds
Started Jun 21 07:02:26 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 233796 kb
Host smart-1c8afc6d-abd2-4add-bd09-c3db904d3a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206480844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1206480844
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3983090004
Short name T392
Test name
Test status
Simulation time 33315508 ps
CPU time 0.74 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 206268 kb
Host smart-e4507a85-76f0-420d-b093-1772e1b5a35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983090004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3983090004
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2687280300
Short name T819
Test name
Test status
Simulation time 78599143 ps
CPU time 2.54 seconds
Started Jun 21 07:03:34 PM PDT 24
Finished Jun 21 07:03:44 PM PDT 24
Peak memory 225480 kb
Host smart-b652490b-b069-4f55-9bfc-2be25455af45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687280300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2687280300
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3734215669
Short name T342
Test name
Test status
Simulation time 23554147 ps
CPU time 0.77 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:39 PM PDT 24
Peak memory 207488 kb
Host smart-b1acea96-e3a0-40e0-bf0c-c0b40ff0e4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734215669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3734215669
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1768391131
Short name T165
Test name
Test status
Simulation time 9481259624 ps
CPU time 68.92 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:04:53 PM PDT 24
Peak memory 236260 kb
Host smart-838334ac-2d94-4927-80bc-4fe37798fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768391131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1768391131
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2013931062
Short name T297
Test name
Test status
Simulation time 241273957 ps
CPU time 2.99 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 218344 kb
Host smart-e232e145-375c-4eec-9005-0d8c7b4ac276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013931062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2013931062
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2364043726
Short name T952
Test name
Test status
Simulation time 20815299 ps
CPU time 0.83 seconds
Started Jun 21 07:03:39 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 218044 kb
Host smart-37452fdd-7340-4eca-bd23-e70aeca2b8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364043726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2364043726
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2057573946
Short name T314
Test name
Test status
Simulation time 1253512762 ps
CPU time 4.23 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:03:49 PM PDT 24
Peak memory 225492 kb
Host smart-eafd6cbf-d282-4a3d-936b-1516205b39bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057573946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2057573946
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3709766433
Short name T561
Test name
Test status
Simulation time 13825640942 ps
CPU time 10.23 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 225632 kb
Host smart-e75bd114-dfef-4beb-a272-cc8fed9b5957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709766433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3709766433
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1650607365
Short name T870
Test name
Test status
Simulation time 78028420 ps
CPU time 1.96 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 225444 kb
Host smart-b026ba0a-b2d4-48c0-8915-67fa5e21f3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650607365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1650607365
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1414631699
Short name T930
Test name
Test status
Simulation time 1776658577 ps
CPU time 3.95 seconds
Started Jun 21 07:03:28 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 225584 kb
Host smart-46945c3f-b907-4f46-a078-d530c6eda150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414631699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1414631699
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2107758583
Short name T516
Test name
Test status
Simulation time 462994698 ps
CPU time 5.82 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 241796 kb
Host smart-90da97ec-fcf7-4467-8991-65ba01029d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107758583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2107758583
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3221696350
Short name T974
Test name
Test status
Simulation time 930660059 ps
CPU time 4.35 seconds
Started Jun 21 07:03:34 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 221432 kb
Host smart-85fa95d6-28b9-4b2f-b461-0e364f2f0476
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3221696350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3221696350
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1936951404
Short name T123
Test name
Test status
Simulation time 77660228036 ps
CPU time 178.38 seconds
Started Jun 21 07:03:36 PM PDT 24
Finished Jun 21 07:06:41 PM PDT 24
Peak memory 274900 kb
Host smart-32caf8a1-b77f-414c-bf9b-3fa3ee306608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936951404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1936951404
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2044343290
Short name T569
Test name
Test status
Simulation time 303574698 ps
CPU time 4.2 seconds
Started Jun 21 07:03:32 PM PDT 24
Finished Jun 21 07:03:44 PM PDT 24
Peak memory 217372 kb
Host smart-627d68dc-20a6-49d8-85c4-a7068fbe3eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044343290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2044343290
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.176040784
Short name T743
Test name
Test status
Simulation time 603527520 ps
CPU time 1.87 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 208916 kb
Host smart-aa07cc46-b030-49af-9925-31ec021d2628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176040784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.176040784
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3232917653
Short name T790
Test name
Test status
Simulation time 73197811 ps
CPU time 2.39 seconds
Started Jun 21 07:03:30 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 217352 kb
Host smart-b4eeab95-45f2-41d2-93a3-6190f5c7ba98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232917653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3232917653
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1854092066
Short name T541
Test name
Test status
Simulation time 29760030 ps
CPU time 0.78 seconds
Started Jun 21 07:03:31 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 207020 kb
Host smart-b07475b1-a043-4025-bb50-1f8424eedaaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854092066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1854092066
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2732957196
Short name T172
Test name
Test status
Simulation time 217094032 ps
CPU time 3.13 seconds
Started Jun 21 07:03:29 PM PDT 24
Finished Jun 21 07:03:40 PM PDT 24
Peak memory 233780 kb
Host smart-3dbc6c2f-93b2-4902-917b-2ac520da92f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732957196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2732957196
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.560039173
Short name T780
Test name
Test status
Simulation time 41661800 ps
CPU time 0.83 seconds
Started Jun 21 07:03:35 PM PDT 24
Finished Jun 21 07:03:43 PM PDT 24
Peak memory 206280 kb
Host smart-4ff57bd4-79be-47df-837f-6d08a29cf2a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560039173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.560039173
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1727205975
Short name T681
Test name
Test status
Simulation time 295175141 ps
CPU time 3.76 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 233688 kb
Host smart-a585b126-5e14-42b8-ae9e-57a87224b534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727205975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1727205975
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2552083360
Short name T63
Test name
Test status
Simulation time 123788247 ps
CPU time 0.76 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:03:45 PM PDT 24
Peak memory 207512 kb
Host smart-d75ebb4f-a716-46a7-b3fd-31e02e5be4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552083360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2552083360
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.323309635
Short name T799
Test name
Test status
Simulation time 18221893668 ps
CPU time 68.72 seconds
Started Jun 21 07:03:36 PM PDT 24
Finished Jun 21 07:04:52 PM PDT 24
Peak memory 250292 kb
Host smart-7e596b5b-b709-4271-9f9d-d040f281f22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323309635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.323309635
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2677189621
Short name T620
Test name
Test status
Simulation time 6793848432 ps
CPU time 100.57 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:05:25 PM PDT 24
Peak memory 264220 kb
Host smart-e383b431-c57b-4fe9-8c83-86331fbade71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677189621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2677189621
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.543747403
Short name T953
Test name
Test status
Simulation time 3341547043 ps
CPU time 68.25 seconds
Started Jun 21 07:03:39 PM PDT 24
Finished Jun 21 07:04:54 PM PDT 24
Peak memory 251364 kb
Host smart-c96ec1d3-455f-4970-9c63-df109fd1221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543747403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.543747403
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3804314473
Short name T660
Test name
Test status
Simulation time 942773851 ps
CPU time 4.25 seconds
Started Jun 21 07:03:36 PM PDT 24
Finished Jun 21 07:03:47 PM PDT 24
Peak memory 233788 kb
Host smart-6e3837ab-7e20-486a-83bc-e92b165bc934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804314473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3804314473
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.983771089
Short name T246
Test name
Test status
Simulation time 1215834339 ps
CPU time 7.42 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:03:59 PM PDT 24
Peak memory 241440 kb
Host smart-e6ea51fa-c11b-42b6-803c-3e3fc86c9a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983771089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.983771089
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1745261778
Short name T263
Test name
Test status
Simulation time 232393104 ps
CPU time 3.74 seconds
Started Jun 21 07:03:36 PM PDT 24
Finished Jun 21 07:03:47 PM PDT 24
Peak memory 225616 kb
Host smart-23f09d22-5f59-4f9b-af49-8c021176c874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745261778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1745261778
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.558834433
Short name T530
Test name
Test status
Simulation time 8331871547 ps
CPU time 20.28 seconds
Started Jun 21 07:03:35 PM PDT 24
Finished Jun 21 07:04:03 PM PDT 24
Peak memory 225612 kb
Host smart-35779acd-d83f-4d02-b3bb-c1290c8db4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558834433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.558834433
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4127660368
Short name T316
Test name
Test status
Simulation time 633470133 ps
CPU time 9.12 seconds
Started Jun 21 07:03:41 PM PDT 24
Finished Jun 21 07:03:56 PM PDT 24
Peak memory 221316 kb
Host smart-960d39cd-1daf-4b94-b00f-0e104f6d41ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4127660368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4127660368
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2162411998
Short name T879
Test name
Test status
Simulation time 45506782 ps
CPU time 0.73 seconds
Started Jun 21 07:03:42 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 206648 kb
Host smart-ac562c51-ca7e-4123-a722-d0406c373e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162411998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2162411998
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1776162882
Short name T398
Test name
Test status
Simulation time 24648369845 ps
CPU time 16.88 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:04:00 PM PDT 24
Peak memory 218632 kb
Host smart-e599c620-1f2d-4b19-b057-dc346470987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776162882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1776162882
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2348849739
Short name T580
Test name
Test status
Simulation time 107551646 ps
CPU time 1.77 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:03:45 PM PDT 24
Peak memory 217304 kb
Host smart-340c4a96-5084-463f-ab42-f3179d3476ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348849739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2348849739
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4027277951
Short name T710
Test name
Test status
Simulation time 17368282 ps
CPU time 0.74 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:03:45 PM PDT 24
Peak memory 206896 kb
Host smart-7b693eb1-c57c-4424-ace2-9e27fc74ef5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027277951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4027277951
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.889827675
Short name T357
Test name
Test status
Simulation time 5919338237 ps
CPU time 20.02 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 241976 kb
Host smart-508795a2-7c1d-46c8-b58f-0ea6f9292e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889827675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.889827675
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1781537999
Short name T940
Test name
Test status
Simulation time 18313125 ps
CPU time 0.69 seconds
Started Jun 21 07:03:43 PM PDT 24
Finished Jun 21 07:03:50 PM PDT 24
Peak memory 205688 kb
Host smart-c5df21c5-b614-4e04-8af7-9acea8221294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781537999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1781537999
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.984529767
Short name T797
Test name
Test status
Simulation time 5134733681 ps
CPU time 6.69 seconds
Started Jun 21 07:03:40 PM PDT 24
Finished Jun 21 07:03:53 PM PDT 24
Peak memory 225596 kb
Host smart-30f1e121-6a0b-492f-b5b2-ab50cbb2e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984529767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.984529767
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.621885657
Short name T52
Test name
Test status
Simulation time 21241638 ps
CPU time 0.79 seconds
Started Jun 21 07:03:40 PM PDT 24
Finished Jun 21 07:03:47 PM PDT 24
Peak memory 207492 kb
Host smart-daed7ee2-37eb-4af7-934f-8bbebf5d8835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621885657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.621885657
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.881643494
Short name T646
Test name
Test status
Simulation time 26096597342 ps
CPU time 46.57 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:04:30 PM PDT 24
Peak memory 235816 kb
Host smart-60043f5c-0acf-4447-b7f1-77ce56ed2e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881643494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.881643494
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1002127948
Short name T571
Test name
Test status
Simulation time 32860144248 ps
CPU time 194.52 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:06:58 PM PDT 24
Peak memory 250468 kb
Host smart-be74da21-cde5-4091-ab7a-f874b75af069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002127948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1002127948
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3077932773
Short name T226
Test name
Test status
Simulation time 3089247285 ps
CPU time 35.22 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:04:20 PM PDT 24
Peak memory 239544 kb
Host smart-5524eb5c-5f1c-48b0-a9da-8a1517de1531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077932773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3077932773
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2991517205
Short name T440
Test name
Test status
Simulation time 863660962 ps
CPU time 6.98 seconds
Started Jun 21 07:03:40 PM PDT 24
Finished Jun 21 07:03:53 PM PDT 24
Peak memory 225540 kb
Host smart-c71bdf06-fc8c-475a-8b83-76638ccac3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991517205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2991517205
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1472998202
Short name T302
Test name
Test status
Simulation time 73513742 ps
CPU time 2.2 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 219424 kb
Host smart-0d4ece53-726c-4fea-b86b-e5bc19722c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472998202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1472998202
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2555401204
Short name T903
Test name
Test status
Simulation time 2036090781 ps
CPU time 20.15 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:04:05 PM PDT 24
Peak memory 236032 kb
Host smart-a48a069e-144b-453e-85ed-b8bafecec31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555401204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2555401204
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4240108052
Short name T544
Test name
Test status
Simulation time 8350861013 ps
CPU time 20.91 seconds
Started Jun 21 07:03:36 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 233904 kb
Host smart-ed6398f9-5c49-4c86-a966-f50a01865342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240108052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4240108052
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2675588427
Short name T549
Test name
Test status
Simulation time 6586324921 ps
CPU time 23.01 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:04:07 PM PDT 24
Peak memory 241820 kb
Host smart-2aaadcf6-0017-43a7-bd57-3134a7a46d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675588427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2675588427
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.653222130
Short name T372
Test name
Test status
Simulation time 2052663093 ps
CPU time 20.32 seconds
Started Jun 21 07:03:40 PM PDT 24
Finished Jun 21 07:04:06 PM PDT 24
Peak memory 223352 kb
Host smart-c0f330b2-6f11-4a91-9f5a-c8ddbf31e8b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=653222130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.653222130
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2136444196
Short name T145
Test name
Test status
Simulation time 87986566137 ps
CPU time 660.63 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:14:45 PM PDT 24
Peak memory 283188 kb
Host smart-ff337b5e-8925-4a05-bcd4-4b8e7cd5b9b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136444196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2136444196
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.141563510
Short name T774
Test name
Test status
Simulation time 9185283958 ps
CPU time 18.07 seconds
Started Jun 21 07:03:42 PM PDT 24
Finished Jun 21 07:04:06 PM PDT 24
Peak memory 217516 kb
Host smart-422bd6cf-b0ec-4255-a016-ca5cea510641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141563510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.141563510
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2928866726
Short name T845
Test name
Test status
Simulation time 630203145 ps
CPU time 1.53 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:03:45 PM PDT 24
Peak memory 208744 kb
Host smart-908deb78-74f4-42f0-8a94-aee887796501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928866726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2928866726
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.176875263
Short name T605
Test name
Test status
Simulation time 125776618 ps
CPU time 1.95 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 217388 kb
Host smart-dd35c957-4c64-41f8-ad1c-753ab6d2e9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176875263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.176875263
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1350961648
Short name T898
Test name
Test status
Simulation time 161031625 ps
CPU time 0.87 seconds
Started Jun 21 07:03:39 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 206920 kb
Host smart-fb2df402-a0c9-4cea-8a46-ee740948735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350961648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1350961648
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.307333216
Short name T959
Test name
Test status
Simulation time 910532602 ps
CPU time 9.27 seconds
Started Jun 21 07:03:42 PM PDT 24
Finished Jun 21 07:03:57 PM PDT 24
Peak memory 233712 kb
Host smart-2d3678a4-e01c-4ae5-b66c-7e26625f7fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307333216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.307333216
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2182374204
Short name T769
Test name
Test status
Simulation time 12858081 ps
CPU time 0.7 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:51 PM PDT 24
Peak memory 206316 kb
Host smart-e8e0d4d6-a79a-4770-b2d6-918db8d40b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182374204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2182374204
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1480679083
Short name T931
Test name
Test status
Simulation time 161269378 ps
CPU time 2.26 seconds
Started Jun 21 07:03:49 PM PDT 24
Finished Jun 21 07:04:01 PM PDT 24
Peak memory 225512 kb
Host smart-e7a25547-e4e1-45bc-8eb5-a9b5eef38728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480679083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1480679083
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3516263324
Short name T747
Test name
Test status
Simulation time 75025680 ps
CPU time 0.77 seconds
Started Jun 21 07:03:38 PM PDT 24
Finished Jun 21 07:03:45 PM PDT 24
Peak memory 207556 kb
Host smart-c02d82b6-57d9-409b-ae57-3df154d03abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516263324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3516263324
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1525820520
Short name T756
Test name
Test status
Simulation time 4077499396 ps
CPU time 41.26 seconds
Started Jun 21 07:03:47 PM PDT 24
Finished Jun 21 07:04:35 PM PDT 24
Peak memory 250292 kb
Host smart-8abf20d7-32c4-4ee5-aeee-8e36a18230b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525820520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1525820520
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4155698790
Short name T444
Test name
Test status
Simulation time 13743841279 ps
CPU time 126.84 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:05:57 PM PDT 24
Peak memory 250288 kb
Host smart-95fb1571-6490-4436-a36a-7af31d457845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155698790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4155698790
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4219643309
Short name T875
Test name
Test status
Simulation time 33755873302 ps
CPU time 143.15 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:06:13 PM PDT 24
Peak memory 251868 kb
Host smart-833a11ed-1c8a-40a8-9728-196af86217f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219643309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4219643309
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4239318967
Short name T637
Test name
Test status
Simulation time 1959177771 ps
CPU time 10 seconds
Started Jun 21 07:03:47 PM PDT 24
Finished Jun 21 07:04:05 PM PDT 24
Peak memory 233764 kb
Host smart-96307447-9cbf-48f6-8d81-af640d9f09eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239318967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4239318967
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1380787245
Short name T117
Test name
Test status
Simulation time 1201652730 ps
CPU time 5.17 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:55 PM PDT 24
Peak memory 233780 kb
Host smart-664e7af0-13db-41f6-9a93-b8a55b494c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380787245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1380787245
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.199470463
Short name T113
Test name
Test status
Simulation time 111908586 ps
CPU time 3.71 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 233740 kb
Host smart-5984c5a1-8349-4c68-b5ff-361507bb472d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199470463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.199470463
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3629518062
Short name T384
Test name
Test status
Simulation time 6675506123 ps
CPU time 7.33 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:58 PM PDT 24
Peak memory 233880 kb
Host smart-89cf9a1e-fc8f-41ed-83f0-afc34d000b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629518062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3629518062
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1449651287
Short name T355
Test name
Test status
Simulation time 3382857983 ps
CPU time 11.81 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 220552 kb
Host smart-293ef213-90bc-4499-810e-4405e1725fd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1449651287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1449651287
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1392259701
Short name T730
Test name
Test status
Simulation time 11590845292 ps
CPU time 33.6 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:04:25 PM PDT 24
Peak memory 217400 kb
Host smart-a3172e1e-d8fc-4486-a284-1860c4a6ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392259701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1392259701
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1967435674
Short name T699
Test name
Test status
Simulation time 1535696092 ps
CPU time 2.59 seconds
Started Jun 21 07:03:37 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 217400 kb
Host smart-b0f02ac3-1dd9-436c-9423-5209e948d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967435674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1967435674
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.481650411
Short name T600
Test name
Test status
Simulation time 726221868 ps
CPU time 4.7 seconds
Started Jun 21 07:03:39 PM PDT 24
Finished Jun 21 07:03:51 PM PDT 24
Peak memory 217544 kb
Host smart-09f2a517-bec4-4a68-a5ec-7da3123ddb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481650411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.481650411
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2964404052
Short name T583
Test name
Test status
Simulation time 316596963 ps
CPU time 0.78 seconds
Started Jun 21 07:03:39 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 206892 kb
Host smart-943bb2f8-fde4-44f8-a1f5-91aa61433d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964404052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2964404052
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2122384230
Short name T849
Test name
Test status
Simulation time 6619481141 ps
CPU time 7.65 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:04:02 PM PDT 24
Peak memory 233844 kb
Host smart-a5eca05c-ddfe-4b5d-980f-9940cc710fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122384230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2122384230
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3236637735
Short name T53
Test name
Test status
Simulation time 27877508 ps
CPU time 0.75 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:03:55 PM PDT 24
Peak memory 205736 kb
Host smart-b3a23f30-d9a6-4dd3-8d87-d46d26bf8810
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236637735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3236637735
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2677948152
Short name T400
Test name
Test status
Simulation time 802066845 ps
CPU time 4.17 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:03:58 PM PDT 24
Peak memory 233724 kb
Host smart-bac528b9-8811-4e23-9e36-ac57e08f4c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677948152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2677948152
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3290818848
Short name T460
Test name
Test status
Simulation time 15191148 ps
CPU time 0.77 seconds
Started Jun 21 07:03:43 PM PDT 24
Finished Jun 21 07:03:50 PM PDT 24
Peak memory 207440 kb
Host smart-a2d4f333-18fc-444d-900a-7f9d23146d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290818848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3290818848
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3616080397
Short name T470
Test name
Test status
Simulation time 22279425479 ps
CPU time 27.82 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 238644 kb
Host smart-5b6c4fc1-b090-4a80-8fe5-ac312716482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616080397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3616080397
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.501738070
Short name T956
Test name
Test status
Simulation time 34696981164 ps
CPU time 263.71 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:08:16 PM PDT 24
Peak memory 255776 kb
Host smart-73131b56-b340-4e3f-a1e0-c6ca90826733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501738070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.501738070
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2673970258
Short name T229
Test name
Test status
Simulation time 11703678420 ps
CPU time 150.6 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:06:21 PM PDT 24
Peak memory 268132 kb
Host smart-571ee11b-94db-41cf-a5d3-6064d71c1bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673970258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2673970258
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1166474318
Short name T858
Test name
Test status
Simulation time 1214754380 ps
CPU time 8.93 seconds
Started Jun 21 07:03:43 PM PDT 24
Finished Jun 21 07:03:58 PM PDT 24
Peak memory 225568 kb
Host smart-29a24c7e-c34d-4660-a5c5-65beb1664c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166474318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1166474318
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1852648316
Short name T514
Test name
Test status
Simulation time 289834025 ps
CPU time 3.24 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:03:56 PM PDT 24
Peak memory 225500 kb
Host smart-9cc79857-2785-4b4c-be73-b08e44a8b52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852648316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1852648316
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2490986218
Short name T185
Test name
Test status
Simulation time 23305252575 ps
CPU time 24.59 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:04:16 PM PDT 24
Peak memory 233788 kb
Host smart-6b565966-5ff5-426c-b804-53da2c47dcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490986218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2490986218
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.67555184
Short name T838
Test name
Test status
Simulation time 5970759066 ps
CPU time 19.63 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:04:10 PM PDT 24
Peak memory 250076 kb
Host smart-7cf5deda-3095-4823-b0c2-12ab111cebee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67555184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.67555184
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1331703673
Short name T178
Test name
Test status
Simulation time 3309388322 ps
CPU time 12.3 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:04:03 PM PDT 24
Peak memory 241488 kb
Host smart-95798901-f1ea-4c5f-bd15-801577e10d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331703673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1331703673
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2065391960
Short name T695
Test name
Test status
Simulation time 638191904 ps
CPU time 3.65 seconds
Started Jun 21 07:03:43 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 221792 kb
Host smart-27667995-a8a7-4bb2-9805-59c39b799427
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2065391960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2065391960
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.386523564
Short name T294
Test name
Test status
Simulation time 24690301812 ps
CPU time 33.9 seconds
Started Jun 21 07:03:47 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 217564 kb
Host smart-d9bb4054-9c46-4683-800d-6ae3be0ab92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386523564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.386523564
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3815953498
Short name T759
Test name
Test status
Simulation time 12572958 ps
CPU time 0.68 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:51 PM PDT 24
Peak memory 206620 kb
Host smart-87a46803-8223-4136-ba03-2db4105cb599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815953498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3815953498
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2008249347
Short name T623
Test name
Test status
Simulation time 54280089 ps
CPU time 0.78 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:51 PM PDT 24
Peak memory 207924 kb
Host smart-05604c22-d4b1-4f9e-962d-cf36107b9daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008249347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2008249347
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1477631688
Short name T566
Test name
Test status
Simulation time 125505998 ps
CPU time 0.83 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 206896 kb
Host smart-be241cf7-f7a7-43a7-9ee7-d71cd795bf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477631688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1477631688
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3719563231
Short name T476
Test name
Test status
Simulation time 5330611395 ps
CPU time 11.52 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 233844 kb
Host smart-715a5bd2-a802-48eb-bdb2-f881cf19554e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719563231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3719563231
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1926944955
Short name T951
Test name
Test status
Simulation time 11694378 ps
CPU time 0.72 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 205692 kb
Host smart-3a714dc6-b6fe-4a51-bfd2-a95b08e3738a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926944955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1926944955
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2210954409
Short name T907
Test name
Test status
Simulation time 169023987 ps
CPU time 2.8 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 233696 kb
Host smart-8d821977-2de7-4f09-b08b-a6128ffb6285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210954409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2210954409
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1215387901
Short name T334
Test name
Test status
Simulation time 37623477 ps
CPU time 0.82 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:51 PM PDT 24
Peak memory 207508 kb
Host smart-edba9e6b-a0e8-4ae2-b462-b67e1def2920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215387901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1215387901
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2174043821
Short name T481
Test name
Test status
Simulation time 147514743 ps
CPU time 0.73 seconds
Started Jun 21 07:03:49 PM PDT 24
Finished Jun 21 07:03:58 PM PDT 24
Peak memory 216808 kb
Host smart-0903fe9f-c5f8-403e-a22b-be348f4ee111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174043821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2174043821
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2253734202
Short name T547
Test name
Test status
Simulation time 65126161874 ps
CPU time 164.61 seconds
Started Jun 21 07:03:50 PM PDT 24
Finished Jun 21 07:06:44 PM PDT 24
Peak memory 257988 kb
Host smart-25f15f0e-d517-4182-8976-50c2ad21c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253734202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2253734202
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2217754787
Short name T231
Test name
Test status
Simulation time 52333153497 ps
CPU time 415.8 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:10:48 PM PDT 24
Peak memory 266824 kb
Host smart-2683d49a-43ff-4b22-8ce0-3724809d7443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217754787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2217754787
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2276492106
Short name T439
Test name
Test status
Simulation time 1577540813 ps
CPU time 5.16 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:55 PM PDT 24
Peak memory 225500 kb
Host smart-b8f0344c-cd9d-49c2-bb89-2fb556cd3dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276492106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2276492106
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2592823363
Short name T486
Test name
Test status
Simulation time 1462069639 ps
CPU time 6.18 seconds
Started Jun 21 07:03:50 PM PDT 24
Finished Jun 21 07:04:06 PM PDT 24
Peak memory 233764 kb
Host smart-cf75ffb6-d7f7-4e6e-bfd7-08316157257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592823363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2592823363
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4251073313
Short name T825
Test name
Test status
Simulation time 4038545704 ps
CPU time 8.1 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:04:01 PM PDT 24
Peak memory 236164 kb
Host smart-d77ecc75-ec86-41e9-9541-6e470353ce91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251073313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4251073313
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4105374492
Short name T375
Test name
Test status
Simulation time 2241831069 ps
CPU time 8.24 seconds
Started Jun 21 07:03:44 PM PDT 24
Finished Jun 21 07:03:58 PM PDT 24
Peak memory 225628 kb
Host smart-5684f99a-5435-45c1-80bc-08b304d52d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105374492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4105374492
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1679914450
Short name T751
Test name
Test status
Simulation time 431905588 ps
CPU time 4.55 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:03:56 PM PDT 24
Peak memory 222848 kb
Host smart-691909e1-c034-4e92-a2f7-cead0110f6fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1679914450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1679914450
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1462492315
Short name T250
Test name
Test status
Simulation time 6040889365 ps
CPU time 133.04 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:06:06 PM PDT 24
Peak memory 267912 kb
Host smart-579523ad-ac7b-4991-afab-3c8c7b84ae09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462492315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1462492315
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.374972966
Short name T73
Test name
Test status
Simulation time 34489753611 ps
CPU time 39.32 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:04:33 PM PDT 24
Peak memory 217464 kb
Host smart-4475de4f-75fb-4d87-9a76-8fb63c05d7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374972966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.374972966
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1565763040
Short name T425
Test name
Test status
Simulation time 1150058430 ps
CPU time 2.99 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:03:57 PM PDT 24
Peak memory 217408 kb
Host smart-46f7eed8-6c96-480a-b4ae-a0adcc26738e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565763040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1565763040
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2256452797
Short name T539
Test name
Test status
Simulation time 100290053 ps
CPU time 1.53 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:03:53 PM PDT 24
Peak memory 217328 kb
Host smart-51d8add1-4808-4c82-bca1-2bb7e68f00fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256452797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2256452797
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.312407954
Short name T305
Test name
Test status
Simulation time 49736568 ps
CPU time 0.91 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:03:53 PM PDT 24
Peak memory 207276 kb
Host smart-ec670d8e-c691-414e-a45a-4187c7e57278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312407954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.312407954
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2152313319
Short name T350
Test name
Test status
Simulation time 15083276328 ps
CPU time 14.08 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:04:06 PM PDT 24
Peak memory 241988 kb
Host smart-fcc5ee02-ef5b-4140-89f1-88eae4947e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152313319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2152313319
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3885459665
Short name T55
Test name
Test status
Simulation time 18139153 ps
CPU time 0.77 seconds
Started Jun 21 07:03:56 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 206304 kb
Host smart-9d89b11b-bb27-46e4-8c3f-6927af70d9ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885459665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3885459665
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3404698753
Short name T612
Test name
Test status
Simulation time 5495469303 ps
CPU time 14.31 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:23 PM PDT 24
Peak memory 233900 kb
Host smart-2156707f-7966-4f76-b474-6fb242d87715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404698753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3404698753
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1768248476
Short name T115
Test name
Test status
Simulation time 66431430 ps
CPU time 0.83 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:03:55 PM PDT 24
Peak memory 207508 kb
Host smart-79d6a51f-d4e3-4980-8211-d89e70b90223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768248476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1768248476
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.560611087
Short name T256
Test name
Test status
Simulation time 2114902332 ps
CPU time 40.9 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:47 PM PDT 24
Peak memory 250288 kb
Host smart-c3568f30-a220-47e9-bae0-cca35354f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560611087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.560611087
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2901879148
Short name T232
Test name
Test status
Simulation time 24105005184 ps
CPU time 175.55 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:07:04 PM PDT 24
Peak memory 251532 kb
Host smart-226b5043-9b68-43de-9f24-329ad65c457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901879148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2901879148
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3322752043
Short name T557
Test name
Test status
Simulation time 17583306809 ps
CPU time 130.67 seconds
Started Jun 21 07:03:52 PM PDT 24
Finished Jun 21 07:06:14 PM PDT 24
Peak memory 250324 kb
Host smart-64efbc09-a993-4f54-b07b-609db239dc02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322752043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3322752043
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1924076487
Short name T7
Test name
Test status
Simulation time 1741735257 ps
CPU time 6.47 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:12 PM PDT 24
Peak memory 236380 kb
Host smart-e6220318-7ade-49cd-8c67-7b5e4abb57df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924076487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1924076487
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2624962401
Short name T258
Test name
Test status
Simulation time 1319887058 ps
CPU time 7.1 seconds
Started Jun 21 07:03:52 PM PDT 24
Finished Jun 21 07:04:10 PM PDT 24
Peak memory 225528 kb
Host smart-4c3ec300-1d86-45e3-b3be-2f74b60f0f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624962401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2624962401
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2331215703
Short name T255
Test name
Test status
Simulation time 26545920003 ps
CPU time 63.08 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:05:09 PM PDT 24
Peak memory 233808 kb
Host smart-8f0d4d8d-8afc-4e98-bd39-f693439a34d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331215703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2331215703
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4212381912
Short name T921
Test name
Test status
Simulation time 339146441 ps
CPU time 3.62 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 233704 kb
Host smart-9677b89d-166f-4bad-8df0-18cce6e66280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212381912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4212381912
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.22879154
Short name T770
Test name
Test status
Simulation time 4210751875 ps
CPU time 17.13 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:23 PM PDT 24
Peak memory 242016 kb
Host smart-bae79fb7-75e2-45ca-ae1b-5ce424b7c4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22879154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.22879154
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1926893068
Short name T135
Test name
Test status
Simulation time 2479007728 ps
CPU time 4.23 seconds
Started Jun 21 07:03:52 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 223676 kb
Host smart-afe35800-ecf6-4807-9bbc-1b885fbfd39e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1926893068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1926893068
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2078046764
Short name T405
Test name
Test status
Simulation time 37699889 ps
CPU time 0.99 seconds
Started Jun 21 07:03:52 PM PDT 24
Finished Jun 21 07:04:04 PM PDT 24
Peak memory 207676 kb
Host smart-07530472-2d23-4d7e-aeb6-54b9a69b4346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078046764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2078046764
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2215139710
Short name T873
Test name
Test status
Simulation time 2449352997 ps
CPU time 6.56 seconds
Started Jun 21 07:03:46 PM PDT 24
Finished Jun 21 07:04:00 PM PDT 24
Peak memory 217828 kb
Host smart-77533e28-77da-43f5-a144-c809f7b71651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215139710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2215139710
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2313367015
Short name T574
Test name
Test status
Simulation time 390964109 ps
CPU time 0.97 seconds
Started Jun 21 07:03:45 PM PDT 24
Finished Jun 21 07:03:53 PM PDT 24
Peak memory 207044 kb
Host smart-afb59ae2-44f1-4466-bcc2-7e301474670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313367015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2313367015
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1573792589
Short name T299
Test name
Test status
Simulation time 865776540 ps
CPU time 2.45 seconds
Started Jun 21 07:03:53 PM PDT 24
Finished Jun 21 07:04:07 PM PDT 24
Peak memory 217296 kb
Host smart-6e908927-8536-4cd5-972b-4c05e7ca2125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573792589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1573792589
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.513074888
Short name T455
Test name
Test status
Simulation time 86731140 ps
CPU time 0.82 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:07 PM PDT 24
Peak memory 206892 kb
Host smart-1b6cc7c4-e68f-4d5e-9068-82f05b449fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513074888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.513074888
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2392698122
Short name T191
Test name
Test status
Simulation time 689133138 ps
CPU time 10.2 seconds
Started Jun 21 07:03:53 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 239868 kb
Host smart-4bc6f0cc-254e-4956-83f3-b9aabf0e54f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392698122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2392698122
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.654264388
Short name T584
Test name
Test status
Simulation time 19072085 ps
CPU time 0.74 seconds
Started Jun 21 07:03:53 PM PDT 24
Finished Jun 21 07:04:05 PM PDT 24
Peak memory 205756 kb
Host smart-55368410-2436-48b2-945c-e1167f9dbc7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654264388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.654264388
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3530766614
Short name T905
Test name
Test status
Simulation time 1218022266 ps
CPU time 5.04 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:11 PM PDT 24
Peak memory 233752 kb
Host smart-ab3429d0-0c78-4985-bc6e-89bf7f0c6aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530766614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3530766614
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3022694921
Short name T431
Test name
Test status
Simulation time 67557242 ps
CPU time 0.76 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 206692 kb
Host smart-808b8fd4-b45e-4c7f-b17f-879de985769a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022694921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3022694921
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3357251000
Short name T590
Test name
Test status
Simulation time 4290537873 ps
CPU time 13.62 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 238132 kb
Host smart-a65d929c-b99b-4e9a-9eeb-bd0e49765811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357251000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3357251000
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2351230571
Short name T877
Test name
Test status
Simulation time 3008167685 ps
CPU time 10.95 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:19 PM PDT 24
Peak memory 224700 kb
Host smart-9f0eb85d-61f2-4686-8c39-c6760f55a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351230571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2351230571
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.107632381
Short name T868
Test name
Test status
Simulation time 43933604820 ps
CPU time 223.69 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:07:52 PM PDT 24
Peak memory 257136 kb
Host smart-3a501f24-f79d-4cd4-89be-cdd28bd85f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107632381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.107632381
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_intercept.866840938
Short name T44
Test name
Test status
Simulation time 6001029067 ps
CPU time 15.59 seconds
Started Jun 21 07:03:53 PM PDT 24
Finished Jun 21 07:04:20 PM PDT 24
Peak memory 233912 kb
Host smart-e9bebb01-e145-45fc-aba7-08b0f8d62fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866840938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.866840938
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3784408804
Short name T836
Test name
Test status
Simulation time 32056221786 ps
CPU time 59.8 seconds
Started Jun 21 07:03:53 PM PDT 24
Finished Jun 21 07:05:04 PM PDT 24
Peak memory 241004 kb
Host smart-f2b5f6f6-e508-4bbb-874a-30e293afd5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784408804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3784408804
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.692665036
Short name T635
Test name
Test status
Simulation time 4225905454 ps
CPU time 6.7 seconds
Started Jun 21 07:03:52 PM PDT 24
Finished Jun 21 07:04:10 PM PDT 24
Peak memory 225648 kb
Host smart-90da707a-e388-4d1a-9e71-2df83b2ddabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692665036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.692665036
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2124757796
Short name T62
Test name
Test status
Simulation time 32430163805 ps
CPU time 23.57 seconds
Started Jun 21 07:03:53 PM PDT 24
Finished Jun 21 07:04:27 PM PDT 24
Peak memory 233840 kb
Host smart-4de82515-8bc2-4291-b79f-691643df5a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124757796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2124757796
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.715610436
Short name T131
Test name
Test status
Simulation time 1814666396 ps
CPU time 14.86 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:20 PM PDT 24
Peak memory 219924 kb
Host smart-d813d4cb-44f6-45c6-99fc-f4bb00694878
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=715610436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.715610436
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1725121386
Short name T703
Test name
Test status
Simulation time 48645611 ps
CPU time 1 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:07 PM PDT 24
Peak memory 207876 kb
Host smart-81a4ff04-7653-4a3f-bc0d-f86f62c94cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725121386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1725121386
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3036206519
Short name T311
Test name
Test status
Simulation time 1040048667 ps
CPU time 14.45 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 217288 kb
Host smart-a87e83d6-a031-4b03-bc88-419cae368eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036206519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3036206519
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1040520789
Short name T441
Test name
Test status
Simulation time 11838528529 ps
CPU time 15.84 seconds
Started Jun 21 07:03:52 PM PDT 24
Finished Jun 21 07:04:19 PM PDT 24
Peak memory 217516 kb
Host smart-5838fc8a-05d8-47e1-98fd-a7af9964e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040520789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1040520789
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3142307169
Short name T969
Test name
Test status
Simulation time 178094973 ps
CPU time 6.07 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 217296 kb
Host smart-11e1cc6b-109b-439c-8d77-659f350f324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142307169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3142307169
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4153607412
Short name T548
Test name
Test status
Simulation time 357766068 ps
CPU time 1.02 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 207888 kb
Host smart-a40c5d10-c7ca-4bcd-8e44-659d1ed74ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153607412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4153607412
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4050387461
Short name T805
Test name
Test status
Simulation time 268170882 ps
CPU time 3.4 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:12 PM PDT 24
Peak memory 233756 kb
Host smart-7521a51a-aec0-4900-aae5-dd3dc9499b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050387461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4050387461
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.79019027
Short name T480
Test name
Test status
Simulation time 38283301 ps
CPU time 0.76 seconds
Started Jun 21 07:04:04 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 206284 kb
Host smart-82512d93-aa56-4c37-a4d8-030727d44cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79019027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.79019027
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1080578515
Short name T275
Test name
Test status
Simulation time 166813629 ps
CPU time 2.38 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 225500 kb
Host smart-3ce21d8f-7b51-4ec2-8f7a-ca4b0013f45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080578515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1080578515
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.431524965
Short name T442
Test name
Test status
Simulation time 44894444 ps
CPU time 0.8 seconds
Started Jun 21 07:03:58 PM PDT 24
Finished Jun 21 07:04:10 PM PDT 24
Peak memory 207492 kb
Host smart-bc6cb06d-bc8d-409f-9087-d941cc41e1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431524965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.431524965
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.783495119
Short name T204
Test name
Test status
Simulation time 34944510921 ps
CPU time 125.09 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:06:19 PM PDT 24
Peak memory 250256 kb
Host smart-acebde27-faf0-4fff-9717-32d393092648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783495119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.783495119
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.290960369
Short name T396
Test name
Test status
Simulation time 15502775118 ps
CPU time 83.02 seconds
Started Jun 21 07:04:00 PM PDT 24
Finished Jun 21 07:05:33 PM PDT 24
Peak memory 253560 kb
Host smart-791825e5-60a4-4ad5-970a-d845dfcf52f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290960369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.290960369
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2881973638
Short name T176
Test name
Test status
Simulation time 11470578999 ps
CPU time 36.52 seconds
Started Jun 21 07:04:02 PM PDT 24
Finished Jun 21 07:04:48 PM PDT 24
Peak memory 250348 kb
Host smart-20ffefe4-2547-452c-96b1-40547e4fddd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881973638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2881973638
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3428087145
Short name T290
Test name
Test status
Simulation time 190952499 ps
CPU time 10.49 seconds
Started Jun 21 07:04:01 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 242388 kb
Host smart-b35ccdc3-7829-4888-ad92-4046156b1e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428087145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3428087145
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3158378867
Short name T954
Test name
Test status
Simulation time 95255943 ps
CPU time 2.3 seconds
Started Jun 21 07:03:53 PM PDT 24
Finished Jun 21 07:04:07 PM PDT 24
Peak memory 223984 kb
Host smart-875a1fce-3925-4ff5-a7c2-98fb00b0c2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158378867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3158378867
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3362945445
Short name T477
Test name
Test status
Simulation time 3524764119 ps
CPU time 17.06 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 237292 kb
Host smart-c9b31951-d0cf-4380-836a-f9e4b0eee849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362945445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3362945445
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3982410077
Short name T813
Test name
Test status
Simulation time 1355300847 ps
CPU time 6.6 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:11 PM PDT 24
Peak memory 233780 kb
Host smart-7de16121-0272-4e7e-98b9-4ce2602bfe59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982410077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3982410077
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.755691532
Short name T785
Test name
Test status
Simulation time 1497266955 ps
CPU time 3.02 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 225484 kb
Host smart-d13d9ae4-f4a0-4d06-bffc-f14fa194ba28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755691532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.755691532
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3848810897
Short name T133
Test name
Test status
Simulation time 24218143972 ps
CPU time 15.52 seconds
Started Jun 21 07:04:02 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 224248 kb
Host smart-af94d34c-2d5a-4010-9e5f-04bcd34305b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3848810897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3848810897
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2155775233
Short name T17
Test name
Test status
Simulation time 22503400956 ps
CPU time 93.11 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:05:47 PM PDT 24
Peak memory 258484 kb
Host smart-712e80ee-f13e-4b5a-af8a-9f1818c55a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155775233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2155775233
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1829770445
Short name T675
Test name
Test status
Simulation time 3547027359 ps
CPU time 27.05 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:34 PM PDT 24
Peak memory 217636 kb
Host smart-fa491d73-cfa4-4d99-8491-bfca710bf36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829770445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1829770445
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3747991805
Short name T766
Test name
Test status
Simulation time 1160746351 ps
CPU time 6.04 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:13 PM PDT 24
Peak memory 217360 kb
Host smart-211de69f-d707-4f92-ad4e-16880cbf1097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747991805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3747991805
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3290818359
Short name T862
Test name
Test status
Simulation time 34706975 ps
CPU time 1.55 seconds
Started Jun 21 07:03:57 PM PDT 24
Finished Jun 21 07:04:10 PM PDT 24
Peak memory 217372 kb
Host smart-2e9c1718-844e-4218-a3f2-6ab202a93efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290818359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3290818359
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1948246753
Short name T424
Test name
Test status
Simulation time 49827932 ps
CPU time 0.88 seconds
Started Jun 21 07:03:54 PM PDT 24
Finished Jun 21 07:04:07 PM PDT 24
Peak memory 206856 kb
Host smart-d3549665-947d-4d2a-910e-1e38e1435d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948246753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1948246753
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.193373305
Short name T472
Test name
Test status
Simulation time 50678750 ps
CPU time 2.15 seconds
Started Jun 21 07:03:55 PM PDT 24
Finished Jun 21 07:04:08 PM PDT 24
Peak memory 225548 kb
Host smart-4e408680-4092-4f90-af6f-b779705c789c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193373305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.193373305
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.140986016
Short name T916
Test name
Test status
Simulation time 43171884 ps
CPU time 0.71 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:13 PM PDT 24
Peak memory 205732 kb
Host smart-967daa2f-e237-4f09-b8a1-f41c18dc9321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140986016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.140986016
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.198367964
Short name T854
Test name
Test status
Simulation time 639776838 ps
CPU time 3.6 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:17 PM PDT 24
Peak memory 233748 kb
Host smart-3a60839e-300f-4b7f-bd56-ed8d8b6eaa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198367964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.198367964
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2862651953
Short name T306
Test name
Test status
Simulation time 116767412 ps
CPU time 0.78 seconds
Started Jun 21 07:04:01 PM PDT 24
Finished Jun 21 07:04:12 PM PDT 24
Peak memory 207848 kb
Host smart-e1b42672-5e3d-48ba-850d-ad7142779e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862651953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2862651953
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3531620444
Short name T210
Test name
Test status
Simulation time 133011577401 ps
CPU time 243.57 seconds
Started Jun 21 07:04:06 PM PDT 24
Finished Jun 21 07:08:20 PM PDT 24
Peak memory 256500 kb
Host smart-728bdaad-85ff-44b1-8c09-2872b68dcb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531620444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3531620444
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1993657257
Short name T414
Test name
Test status
Simulation time 35238373987 ps
CPU time 92.7 seconds
Started Jun 21 07:04:01 PM PDT 24
Finished Jun 21 07:05:44 PM PDT 24
Peak memory 250352 kb
Host smart-3e19a0ff-68a1-4d7d-b06b-29a5cc04f3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993657257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1993657257
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.927722227
Short name T181
Test name
Test status
Simulation time 8551411355 ps
CPU time 75.96 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:05:29 PM PDT 24
Peak memory 233956 kb
Host smart-b96d4aec-94a8-4824-8784-7df38bed4de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927722227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.927722227
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3771298112
Short name T752
Test name
Test status
Simulation time 1901436205 ps
CPU time 4.54 seconds
Started Jun 21 07:04:01 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 234088 kb
Host smart-d380cb3f-6346-4c3d-9654-c510d312787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771298112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3771298112
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3341949602
Short name T880
Test name
Test status
Simulation time 46782874 ps
CPU time 2.6 seconds
Started Jun 21 07:04:05 PM PDT 24
Finished Jun 21 07:04:18 PM PDT 24
Peak memory 233480 kb
Host smart-b4c1ba23-31cb-4985-a1db-b74c54b4ef4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341949602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3341949602
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3833598024
Short name T618
Test name
Test status
Simulation time 1299752864 ps
CPU time 16.41 seconds
Started Jun 21 07:04:00 PM PDT 24
Finished Jun 21 07:04:27 PM PDT 24
Peak memory 233712 kb
Host smart-c171e771-5f5d-47c9-9482-de3725cfbb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833598024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3833598024
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.406901599
Short name T844
Test name
Test status
Simulation time 45803852918 ps
CPU time 14.23 seconds
Started Jun 21 07:04:05 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 225580 kb
Host smart-63769107-2349-466e-966b-21f9b57c20dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406901599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.406901599
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1998263762
Short name T884
Test name
Test status
Simulation time 3443684635 ps
CPU time 13.64 seconds
Started Jun 21 07:04:01 PM PDT 24
Finished Jun 21 07:04:25 PM PDT 24
Peak memory 233816 kb
Host smart-a2004cf3-de87-42f3-94ed-1aa20cd5a6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998263762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1998263762
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1009018952
Short name T869
Test name
Test status
Simulation time 143734866 ps
CPU time 3.12 seconds
Started Jun 21 07:04:04 PM PDT 24
Finished Jun 21 07:04:18 PM PDT 24
Peak memory 219944 kb
Host smart-520da53e-5fc0-48eb-9ac7-cde9e4a5f5de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009018952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1009018952
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1870381822
Short name T205
Test name
Test status
Simulation time 373509259406 ps
CPU time 419.47 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:11:13 PM PDT 24
Peak memory 252896 kb
Host smart-db780fc2-d6b7-4617-88a4-1f5fae2ac4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870381822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1870381822
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.4096201169
Short name T919
Test name
Test status
Simulation time 1488901281 ps
CPU time 22.81 seconds
Started Jun 21 07:04:05 PM PDT 24
Finished Jun 21 07:04:38 PM PDT 24
Peak memory 220400 kb
Host smart-cacd8178-9170-4097-91ee-1ddceb43923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096201169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4096201169
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.460745036
Short name T727
Test name
Test status
Simulation time 7235416857 ps
CPU time 7.7 seconds
Started Jun 21 07:04:04 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 217512 kb
Host smart-949f4154-6d3f-4110-8b6d-4374e56aa1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460745036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.460745036
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3957020816
Short name T611
Test name
Test status
Simulation time 66678615 ps
CPU time 1.48 seconds
Started Jun 21 07:04:05 PM PDT 24
Finished Jun 21 07:04:17 PM PDT 24
Peak memory 217380 kb
Host smart-30ffe1f7-f257-4e68-ab68-51426012bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957020816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3957020816
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.4255247508
Short name T594
Test name
Test status
Simulation time 30692355 ps
CPU time 0.74 seconds
Started Jun 21 07:04:04 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 206908 kb
Host smart-35fe4a5e-f777-40bd-af1c-eaa701df67a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255247508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.4255247508
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.186135200
Short name T192
Test name
Test status
Simulation time 429410696 ps
CPU time 2.53 seconds
Started Jun 21 07:04:05 PM PDT 24
Finished Jun 21 07:04:18 PM PDT 24
Peak memory 225456 kb
Host smart-64589049-606f-4cb6-9d7d-3e58747f19b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186135200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.186135200
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1636949326
Short name T502
Test name
Test status
Simulation time 13922950 ps
CPU time 0.68 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:45 PM PDT 24
Peak memory 205456 kb
Host smart-8030f601-9169-4687-8454-1b70f620ef66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636949326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
636949326
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3857789292
Short name T634
Test name
Test status
Simulation time 251756083 ps
CPU time 3.49 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:45 PM PDT 24
Peak memory 225604 kb
Host smart-771449cd-a1c4-4b19-939d-b2363eb0ad80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857789292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3857789292
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.504278232
Short name T347
Test name
Test status
Simulation time 51062445 ps
CPU time 0.84 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:44 PM PDT 24
Peak memory 207472 kb
Host smart-f2567bd0-6208-40a0-9b70-640ff7b1b31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504278232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.504278232
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.858244319
Short name T626
Test name
Test status
Simulation time 148994437428 ps
CPU time 245.9 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:06:50 PM PDT 24
Peak memory 258456 kb
Host smart-a5a57229-f56e-4cc7-abd3-f328352c78c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858244319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.858244319
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.714604657
Short name T411
Test name
Test status
Simulation time 343123613 ps
CPU time 2.5 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:46 PM PDT 24
Peak memory 218336 kb
Host smart-d91edec5-4c34-4e67-a7cd-19df3ce38370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714604657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.714604657
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3004557778
Short name T779
Test name
Test status
Simulation time 11366862655 ps
CPU time 40.36 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:03:28 PM PDT 24
Peak memory 250304 kb
Host smart-a4c68cbe-05e6-430f-bbf9-755b736bc58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004557778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3004557778
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1293005550
Short name T842
Test name
Test status
Simulation time 482552374 ps
CPU time 11.6 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 241912 kb
Host smart-dc1125ee-562c-4089-9112-f75473992c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293005550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1293005550
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2796922319
Short name T839
Test name
Test status
Simulation time 168697825 ps
CPU time 3.36 seconds
Started Jun 21 07:02:34 PM PDT 24
Finished Jun 21 07:02:42 PM PDT 24
Peak memory 225528 kb
Host smart-7ecb1aae-cabd-40ec-b549-bc71f8027591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796922319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2796922319
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.872399260
Short name T673
Test name
Test status
Simulation time 14032266625 ps
CPU time 109.5 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:04:36 PM PDT 24
Peak memory 249860 kb
Host smart-cef5f21a-0ee3-4b41-9752-4c1faa141437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872399260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.872399260
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3874924375
Short name T882
Test name
Test status
Simulation time 16010631 ps
CPU time 0.99 seconds
Started Jun 21 07:02:35 PM PDT 24
Finished Jun 21 07:02:41 PM PDT 24
Peak memory 218860 kb
Host smart-4a6b9b89-0c92-4f7a-a8b0-b9e474bf4777
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874924375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3874924375
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2304616164
Short name T964
Test name
Test status
Simulation time 23367897296 ps
CPU time 19.62 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 233828 kb
Host smart-9bae8453-4281-4632-b469-ecb55364e379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304616164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2304616164
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.580208046
Short name T267
Test name
Test status
Simulation time 33031517094 ps
CPU time 13.73 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 225412 kb
Host smart-a4e194b6-6589-4902-b72a-3d4ea34a45e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580208046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.580208046
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3061721178
Short name T393
Test name
Test status
Simulation time 308677770 ps
CPU time 3.44 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:02:44 PM PDT 24
Peak memory 221324 kb
Host smart-ad201355-fced-461d-9249-c89b6e8edd15
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3061721178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3061721178
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2297388415
Short name T21
Test name
Test status
Simulation time 264614859 ps
CPU time 1.1 seconds
Started Jun 21 07:02:39 PM PDT 24
Finished Jun 21 07:02:46 PM PDT 24
Peak memory 236376 kb
Host smart-c3b42f26-dce0-4e76-8912-2a8834a64235
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297388415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2297388415
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3666191960
Short name T381
Test name
Test status
Simulation time 66562419224 ps
CPU time 299.38 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:07:46 PM PDT 24
Peak memory 256552 kb
Host smart-f96b13cf-381e-4f66-b4c1-cd4b4d1e45cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666191960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3666191960
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2553132326
Short name T945
Test name
Test status
Simulation time 15134407924 ps
CPU time 24.78 seconds
Started Jun 21 07:02:34 PM PDT 24
Finished Jun 21 07:03:04 PM PDT 24
Peak memory 217584 kb
Host smart-77dc7939-4171-4f22-8e76-11f11d93f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553132326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2553132326
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3040202444
Short name T577
Test name
Test status
Simulation time 1544088035 ps
CPU time 5.21 seconds
Started Jun 21 07:02:41 PM PDT 24
Finished Jun 21 07:02:53 PM PDT 24
Peak memory 217352 kb
Host smart-06fef6bf-50ff-422e-968b-15026f8ee424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040202444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3040202444
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2956812717
Short name T356
Test name
Test status
Simulation time 209833346 ps
CPU time 0.99 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:45 PM PDT 24
Peak memory 207968 kb
Host smart-2225d0ff-2605-49a1-a224-5c09e3b4072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956812717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2956812717
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1737992737
Short name T74
Test name
Test status
Simulation time 667785177 ps
CPU time 0.91 seconds
Started Jun 21 07:02:39 PM PDT 24
Finished Jun 21 07:02:47 PM PDT 24
Peak memory 207400 kb
Host smart-4b89b3ee-a7c4-4c78-9cab-1ec18acfaa9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737992737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1737992737
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1034469823
Short name T459
Test name
Test status
Simulation time 2284144648 ps
CPU time 9.25 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:02:50 PM PDT 24
Peak memory 225704 kb
Host smart-dc5e7ab1-d344-4710-801a-82939a9e60e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034469823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1034469823
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.216779068
Short name T847
Test name
Test status
Simulation time 50084158 ps
CPU time 0.73 seconds
Started Jun 21 07:04:05 PM PDT 24
Finished Jun 21 07:04:16 PM PDT 24
Peak memory 206356 kb
Host smart-5843d7c7-caed-4b34-9c04-64b1a3049020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216779068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.216779068
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3789556993
Short name T948
Test name
Test status
Simulation time 251996171 ps
CPU time 3.98 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:17 PM PDT 24
Peak memory 233664 kb
Host smart-21d32b91-c561-44f7-b62e-71adfe450062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789556993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3789556993
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2352268083
Short name T629
Test name
Test status
Simulation time 38945352 ps
CPU time 0.76 seconds
Started Jun 21 07:04:00 PM PDT 24
Finished Jun 21 07:04:11 PM PDT 24
Peak memory 206480 kb
Host smart-797db44e-a1ee-4d7b-8531-e59be4f692be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352268083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2352268083
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3791798185
Short name T641
Test name
Test status
Simulation time 1312358180 ps
CPU time 8.63 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 238800 kb
Host smart-51265b83-c0f9-4388-9e1d-57558a31a836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791798185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3791798185
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1564888815
Short name T277
Test name
Test status
Simulation time 81200884991 ps
CPU time 756.95 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:16:51 PM PDT 24
Peak memory 270284 kb
Host smart-64bf0e80-7ac6-48e8-937b-37ec799034e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564888815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1564888815
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4098144711
Short name T160
Test name
Test status
Simulation time 75911465176 ps
CPU time 423.18 seconds
Started Jun 21 07:04:02 PM PDT 24
Finished Jun 21 07:11:14 PM PDT 24
Peak memory 266712 kb
Host smart-a60b98e7-ba49-4ccb-8f03-7c0b13eaaadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098144711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4098144711
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4222420354
Short name T325
Test name
Test status
Simulation time 738582338 ps
CPU time 6.4 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:20 PM PDT 24
Peak memory 225496 kb
Host smart-bb4cb172-159f-40a3-b60a-f5c4b3ed89a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222420354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4222420354
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3408502815
Short name T260
Test name
Test status
Simulation time 1456084946 ps
CPU time 6.18 seconds
Started Jun 21 07:04:02 PM PDT 24
Finished Jun 21 07:04:19 PM PDT 24
Peak memory 233784 kb
Host smart-e9dea8e2-908b-4df1-a99c-5ff381d547f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408502815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3408502815
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.523425286
Short name T830
Test name
Test status
Simulation time 758307482 ps
CPU time 5.2 seconds
Started Jun 21 07:04:04 PM PDT 24
Finished Jun 21 07:04:20 PM PDT 24
Peak memory 225600 kb
Host smart-6b5447f8-cf28-4414-8b16-c625914e0380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523425286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.523425286
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.167885589
Short name T179
Test name
Test status
Simulation time 9543817828 ps
CPU time 6.07 seconds
Started Jun 21 07:04:05 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 225756 kb
Host smart-2c84a5be-f97d-4e1e-9927-2a4e40be436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167885589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.167885589
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3827169248
Short name T725
Test name
Test status
Simulation time 1188087897 ps
CPU time 4.17 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:17 PM PDT 24
Peak memory 225260 kb
Host smart-9addb675-1f5a-4ebf-aa1a-cc6a4ff343ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827169248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3827169248
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3048154857
Short name T77
Test name
Test status
Simulation time 1401396231 ps
CPU time 10.02 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:23 PM PDT 24
Peak memory 223780 kb
Host smart-b61f4472-01ed-45a2-889f-5dd0dabe3b01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3048154857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3048154857
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3653690854
Short name T298
Test name
Test status
Simulation time 5222628052 ps
CPU time 24.87 seconds
Started Jun 21 07:04:04 PM PDT 24
Finished Jun 21 07:04:39 PM PDT 24
Peak memory 217760 kb
Host smart-86ff13c2-c363-4f13-a1b1-82ae73d4a143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653690854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3653690854
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.864979930
Short name T591
Test name
Test status
Simulation time 9480840714 ps
CPU time 23.09 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:36 PM PDT 24
Peak memory 217468 kb
Host smart-6e72efe0-8837-4756-bcbf-2a2623f97564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864979930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.864979930
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3077645410
Short name T564
Test name
Test status
Simulation time 64726833 ps
CPU time 1.29 seconds
Started Jun 21 07:04:03 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 208976 kb
Host smart-a438dbd5-4c01-4fc7-a2ca-ceb6c19423eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077645410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3077645410
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2690740294
Short name T977
Test name
Test status
Simulation time 27932560 ps
CPU time 0.89 seconds
Started Jun 21 07:04:00 PM PDT 24
Finished Jun 21 07:04:11 PM PDT 24
Peak memory 207284 kb
Host smart-d8fbaba7-d4f6-4fab-8aff-3c1a62437dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690740294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2690740294
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.573493739
Short name T585
Test name
Test status
Simulation time 9257608890 ps
CPU time 10.73 seconds
Started Jun 21 07:04:02 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 225636 kb
Host smart-594efa47-8320-40f3-808d-5ab12969a84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573493739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.573493739
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.945487745
Short name T815
Test name
Test status
Simulation time 113131692 ps
CPU time 0.71 seconds
Started Jun 21 07:04:12 PM PDT 24
Finished Jun 21 07:04:22 PM PDT 24
Peak memory 206312 kb
Host smart-11dd4416-7636-4b6c-b106-18d8b0182775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945487745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.945487745
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2239611386
Short name T328
Test name
Test status
Simulation time 188589208 ps
CPU time 3 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:23 PM PDT 24
Peak memory 225556 kb
Host smart-a58162c6-c2c4-4542-a0dc-67f6baeb9f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239611386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2239611386
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3362554894
Short name T344
Test name
Test status
Simulation time 14292969 ps
CPU time 0.81 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:20 PM PDT 24
Peak memory 207440 kb
Host smart-6d37f00b-3423-4e7d-a6dd-6fafb7c22a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362554894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3362554894
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1573520399
Short name T217
Test name
Test status
Simulation time 10434043720 ps
CPU time 93.43 seconds
Started Jun 21 07:04:11 PM PDT 24
Finished Jun 21 07:05:53 PM PDT 24
Peak memory 251340 kb
Host smart-e8023ea1-f71e-4b41-9046-37d80077c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573520399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1573520399
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1899444329
Short name T283
Test name
Test status
Simulation time 209403801 ps
CPU time 6.66 seconds
Started Jun 21 07:04:11 PM PDT 24
Finished Jun 21 07:04:27 PM PDT 24
Peak memory 233732 kb
Host smart-dd9c8f49-2d6a-4686-9f3d-a5e65ab94e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899444329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1899444329
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4243793010
Short name T733
Test name
Test status
Simulation time 1694085676 ps
CPU time 14.18 seconds
Started Jun 21 07:04:09 PM PDT 24
Finished Jun 21 07:04:33 PM PDT 24
Peak memory 229536 kb
Host smart-61da902f-0a97-46e7-96ad-bc5007b38be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243793010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4243793010
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3958871512
Short name T253
Test name
Test status
Simulation time 27271822517 ps
CPU time 64.65 seconds
Started Jun 21 07:04:11 PM PDT 24
Finished Jun 21 07:05:25 PM PDT 24
Peak memory 225620 kb
Host smart-40b27862-23b4-4f00-8562-29e19ae5610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958871512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3958871512
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1193561351
Short name T508
Test name
Test status
Simulation time 5803914669 ps
CPU time 15.57 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:35 PM PDT 24
Peak memory 241892 kb
Host smart-df16ba42-21cd-43f2-b3f2-37dcafeb8ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193561351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1193561351
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2782872416
Short name T23
Test name
Test status
Simulation time 60204154 ps
CPU time 2.37 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 233492 kb
Host smart-4895c1f7-3ae6-48d4-b295-a2d9481c0221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782872416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2782872416
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.920603112
Short name T309
Test name
Test status
Simulation time 938093413 ps
CPU time 14.27 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:33 PM PDT 24
Peak memory 221096 kb
Host smart-fd2c4b6a-df59-488e-a4da-d86d2b274044
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=920603112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.920603112
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2966392214
Short name T913
Test name
Test status
Simulation time 38903593603 ps
CPU time 93.86 seconds
Started Jun 21 07:04:12 PM PDT 24
Finished Jun 21 07:05:55 PM PDT 24
Peak memory 267952 kb
Host smart-860aeda6-8e42-4495-93ed-10e9f2929787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966392214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2966392214
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3387805250
Short name T597
Test name
Test status
Simulation time 6253828391 ps
CPU time 30.08 seconds
Started Jun 21 07:04:09 PM PDT 24
Finished Jun 21 07:04:49 PM PDT 24
Peak memory 217696 kb
Host smart-3bc94df6-3d66-4852-a96a-86eb45601095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387805250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3387805250
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4205114279
Short name T324
Test name
Test status
Simulation time 5199665003 ps
CPU time 14.41 seconds
Started Jun 21 07:04:13 PM PDT 24
Finished Jun 21 07:04:36 PM PDT 24
Peak memory 217440 kb
Host smart-a00da11d-a79b-4a99-b6a1-888416847fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205114279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4205114279
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2858788208
Short name T49
Test name
Test status
Simulation time 325893255 ps
CPU time 1.22 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 217328 kb
Host smart-69bc809e-495c-49fb-8bf6-b9443eb15614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858788208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2858788208
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.538879904
Short name T832
Test name
Test status
Simulation time 111497841 ps
CPU time 1.09 seconds
Started Jun 21 07:04:11 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 207888 kb
Host smart-e7a57cbe-6de3-4040-833a-b799aafde291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538879904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.538879904
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.166328493
Short name T696
Test name
Test status
Simulation time 19842022344 ps
CPU time 19.35 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:38 PM PDT 24
Peak memory 233896 kb
Host smart-095b1b59-641e-4eee-87a8-fd5b69dbba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166328493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.166328493
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.759623301
Short name T385
Test name
Test status
Simulation time 37693190 ps
CPU time 0.73 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:31 PM PDT 24
Peak memory 206288 kb
Host smart-e65b7b50-4413-40c0-bc8f-fa8de66285d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759623301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.759623301
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.501516057
Short name T887
Test name
Test status
Simulation time 100953898 ps
CPU time 3.07 seconds
Started Jun 21 07:04:11 PM PDT 24
Finished Jun 21 07:04:24 PM PDT 24
Peak memory 225584 kb
Host smart-37f2a98b-d1ea-4754-9c88-696284ccec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501516057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.501516057
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1320114101
Short name T421
Test name
Test status
Simulation time 64712310 ps
CPU time 0.77 seconds
Started Jun 21 07:04:11 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 207504 kb
Host smart-81290bb4-5d79-48af-a25e-c5de8b6bf322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320114101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1320114101
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4014953248
Short name T748
Test name
Test status
Simulation time 35540157455 ps
CPU time 151.97 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:07:00 PM PDT 24
Peak memory 254512 kb
Host smart-5a29b4ff-53b8-46f0-b55b-81086ca33d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014953248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4014953248
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1511018285
Short name T247
Test name
Test status
Simulation time 2419703955 ps
CPU time 43.04 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 251580 kb
Host smart-ebf99da6-9a07-4790-a3ff-5299400e9264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511018285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1511018285
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.874413927
Short name T122
Test name
Test status
Simulation time 48353884311 ps
CPU time 129.47 seconds
Started Jun 21 07:04:24 PM PDT 24
Finished Jun 21 07:06:42 PM PDT 24
Peak memory 250348 kb
Host smart-bedbd567-c4ce-495b-984b-2c2f1c749a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874413927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.874413927
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3436131299
Short name T947
Test name
Test status
Simulation time 7655411785 ps
CPU time 50.7 seconds
Started Jun 21 07:04:08 PM PDT 24
Finished Jun 21 07:05:09 PM PDT 24
Peak memory 250280 kb
Host smart-3bd78269-dc1e-4f0d-8da8-b7fc9f0b79c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436131299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3436131299
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4101266261
Short name T512
Test name
Test status
Simulation time 386180346 ps
CPU time 2.86 seconds
Started Jun 21 07:04:12 PM PDT 24
Finished Jun 21 07:04:24 PM PDT 24
Peak memory 225468 kb
Host smart-e3b38f41-07d3-4de4-81a2-0047db7a3344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101266261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4101266261
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1576882651
Short name T908
Test name
Test status
Simulation time 639036883 ps
CPU time 3.41 seconds
Started Jun 21 07:04:08 PM PDT 24
Finished Jun 21 07:04:21 PM PDT 24
Peak memory 225596 kb
Host smart-85a7c630-0cad-4a19-b0c8-f714feb6daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576882651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1576882651
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3137219203
Short name T835
Test name
Test status
Simulation time 4178117539 ps
CPU time 6.99 seconds
Started Jun 21 07:04:13 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 233872 kb
Host smart-0cf038f7-df93-4f20-9457-7b7ba0b60e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137219203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3137219203
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2354727319
Short name T244
Test name
Test status
Simulation time 8947242418 ps
CPU time 24.67 seconds
Started Jun 21 07:04:10 PM PDT 24
Finished Jun 21 07:04:44 PM PDT 24
Peak memory 241524 kb
Host smart-34f76ae9-2886-416d-9ff2-f00028757138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354727319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2354727319
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1307996626
Short name T901
Test name
Test status
Simulation time 877073684 ps
CPU time 4.25 seconds
Started Jun 21 07:04:12 PM PDT 24
Finished Jun 21 07:04:25 PM PDT 24
Peak memory 221044 kb
Host smart-34bbb8d3-ea9d-4b4c-b9b8-78fe102619ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1307996626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1307996626
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3540445375
Short name T979
Test name
Test status
Simulation time 1238651891 ps
CPU time 27.18 seconds
Started Jun 21 07:04:21 PM PDT 24
Finished Jun 21 07:04:56 PM PDT 24
Peak memory 252936 kb
Host smart-f9f71200-ee53-4599-b558-13121ae803b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540445375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3540445375
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2703096366
Short name T521
Test name
Test status
Simulation time 15467811663 ps
CPU time 27.67 seconds
Started Jun 21 07:04:14 PM PDT 24
Finished Jun 21 07:04:49 PM PDT 24
Peak memory 217448 kb
Host smart-669a09f3-2776-4f83-9da1-507806a08f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703096366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2703096366
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3171714890
Short name T413
Test name
Test status
Simulation time 2156401790 ps
CPU time 6.22 seconds
Started Jun 21 07:04:12 PM PDT 24
Finished Jun 21 07:04:27 PM PDT 24
Peak memory 217472 kb
Host smart-c90f3779-6f22-4202-b9e1-1bbe794f08df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171714890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3171714890
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3816972700
Short name T24
Test name
Test status
Simulation time 67237807 ps
CPU time 2.4 seconds
Started Jun 21 07:04:12 PM PDT 24
Finished Jun 21 07:04:23 PM PDT 24
Peak memory 217396 kb
Host smart-c833aece-97d3-4f13-9d87-e634473bdeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816972700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3816972700
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2079931384
Short name T593
Test name
Test status
Simulation time 182564974 ps
CPU time 0.95 seconds
Started Jun 21 07:04:09 PM PDT 24
Finished Jun 21 07:04:19 PM PDT 24
Peak memory 206872 kb
Host smart-2f9204e9-b531-412d-a125-1daec3e05d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079931384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2079931384
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3092721339
Short name T917
Test name
Test status
Simulation time 1457278788 ps
CPU time 4.92 seconds
Started Jun 21 07:04:11 PM PDT 24
Finished Jun 21 07:04:25 PM PDT 24
Peak memory 233668 kb
Host smart-4b8d91e4-6a54-4418-8857-4ca796660f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092721339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3092721339
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2113317382
Short name T329
Test name
Test status
Simulation time 20850947 ps
CPU time 0.75 seconds
Started Jun 21 07:04:21 PM PDT 24
Finished Jun 21 07:04:30 PM PDT 24
Peak memory 205692 kb
Host smart-39fee0e6-33cf-4908-947e-8eb9b9987f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113317382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2113317382
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2591841538
Short name T910
Test name
Test status
Simulation time 432801709 ps
CPU time 5.63 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 225332 kb
Host smart-cb5e9ccf-d987-4097-ac73-e97a46733b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591841538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2591841538
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2990962888
Short name T399
Test name
Test status
Simulation time 36196944 ps
CPU time 0.78 seconds
Started Jun 21 07:04:19 PM PDT 24
Finished Jun 21 07:04:27 PM PDT 24
Peak memory 207492 kb
Host smart-919f0bbc-2de6-4d28-9402-6234be9b042d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990962888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2990962888
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2016400094
Short name T859
Test name
Test status
Simulation time 101102604688 ps
CPU time 383.44 seconds
Started Jun 21 07:04:19 PM PDT 24
Finished Jun 21 07:10:50 PM PDT 24
Peak memory 258532 kb
Host smart-2f45384d-69f6-4ee9-be21-76e8110d3982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016400094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2016400094
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1249947879
Short name T365
Test name
Test status
Simulation time 884908610 ps
CPU time 14.72 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:04:42 PM PDT 24
Peak memory 225516 kb
Host smart-7cffe0cb-d8b7-429e-bcde-3e976ec021a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249947879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1249947879
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.959172825
Short name T380
Test name
Test status
Simulation time 641982707 ps
CPU time 3.28 seconds
Started Jun 21 07:04:18 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 233784 kb
Host smart-590dbc16-e859-46fb-b8da-7d08ee6d3eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959172825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.959172825
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.853240448
Short name T939
Test name
Test status
Simulation time 290232411 ps
CPU time 6.77 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:04:38 PM PDT 24
Peak memory 233776 kb
Host smart-4386ef79-8670-4c22-9acd-e894fe01d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853240448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.853240448
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3349763710
Short name T22
Test name
Test status
Simulation time 28356344609 ps
CPU time 43.14 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:05:11 PM PDT 24
Peak memory 241516 kb
Host smart-f1d94f3d-b3cf-4072-9008-49c7083d02fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349763710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3349763710
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.824805869
Short name T261
Test name
Test status
Simulation time 1156167296 ps
CPU time 9.57 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:04:41 PM PDT 24
Peak memory 234868 kb
Host smart-06b09b93-5df7-448c-bd3a-f61bda62f2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824805869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.824805869
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1530267226
Short name T689
Test name
Test status
Simulation time 876521897 ps
CPU time 3.45 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:34 PM PDT 24
Peak memory 220232 kb
Host smart-0b4c8ebf-8426-473b-a458-6503a92d2c8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1530267226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1530267226
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.572701790
Short name T932
Test name
Test status
Simulation time 156002498 ps
CPU time 0.92 seconds
Started Jun 21 07:04:19 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 207948 kb
Host smart-f76b39a2-f992-4937-ba8c-fa33be168996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572701790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.572701790
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2743034854
Short name T795
Test name
Test status
Simulation time 12515705291 ps
CPU time 27.78 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:58 PM PDT 24
Peak memory 217568 kb
Host smart-1f1f99c6-3493-4ab9-9a7f-8b272ff98073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743034854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2743034854
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2212256279
Short name T304
Test name
Test status
Simulation time 913479537 ps
CPU time 5.66 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:04:37 PM PDT 24
Peak memory 217392 kb
Host smart-26975b41-b820-459e-b4fb-ceadf72b40aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212256279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2212256279
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1634880183
Short name T430
Test name
Test status
Simulation time 19445992 ps
CPU time 0.84 seconds
Started Jun 21 07:04:21 PM PDT 24
Finished Jun 21 07:04:30 PM PDT 24
Peak memory 206896 kb
Host smart-cb2aebd9-cba3-4612-8492-cdf396f262a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634880183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1634880183
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2185035053
Short name T449
Test name
Test status
Simulation time 42372625 ps
CPU time 0.92 seconds
Started Jun 21 07:04:21 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 206920 kb
Host smart-b8b995a8-9bcf-4b2e-aa49-c4a0709c77e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185035053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2185035053
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3142498234
Short name T654
Test name
Test status
Simulation time 1418366537 ps
CPU time 12.84 seconds
Started Jun 21 07:04:19 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 233720 kb
Host smart-035c036d-1871-49ca-bed9-48e4751c96f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142498234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3142498234
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1075033485
Short name T650
Test name
Test status
Simulation time 14971611 ps
CPU time 0.82 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:04:32 PM PDT 24
Peak memory 205736 kb
Host smart-cea77a3e-a740-47bc-8ae3-a4d10a132145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075033485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1075033485
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3474655192
Short name T274
Test name
Test status
Simulation time 312370385 ps
CPU time 3.12 seconds
Started Jun 21 07:04:19 PM PDT 24
Finished Jun 21 07:04:30 PM PDT 24
Peak memory 225504 kb
Host smart-9e3d9712-fd08-4450-b57e-cc4166f82d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474655192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3474655192
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.975772469
Short name T419
Test name
Test status
Simulation time 55299349 ps
CPU time 0.78 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:31 PM PDT 24
Peak memory 206432 kb
Host smart-73be0a81-a1a4-4ce2-b310-4a05d8e4d44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975772469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.975772469
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2284797265
Short name T409
Test name
Test status
Simulation time 2026873852 ps
CPU time 22.61 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:04:54 PM PDT 24
Peak memory 240424 kb
Host smart-efeb84b4-9e9e-4b7c-a056-d1cfaf3dc58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284797265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2284797265
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.455595100
Short name T266
Test name
Test status
Simulation time 13219245702 ps
CPU time 79.39 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:05:50 PM PDT 24
Peak memory 255044 kb
Host smart-38cf8b51-3f14-4e73-a237-b830f5c8c586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455595100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.455595100
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1373741338
Short name T187
Test name
Test status
Simulation time 14883255815 ps
CPU time 50.37 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:05:18 PM PDT 24
Peak memory 256200 kb
Host smart-633edca1-68bf-488c-bd42-8ec027a6eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373741338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1373741338
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4264580019
Short name T289
Test name
Test status
Simulation time 388307948 ps
CPU time 4.74 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:04:36 PM PDT 24
Peak memory 225508 kb
Host smart-e9b48384-c281-4df7-8f36-47942f907eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264580019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4264580019
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1012818333
Short name T526
Test name
Test status
Simulation time 37468604 ps
CPU time 2.57 seconds
Started Jun 21 07:04:18 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 233792 kb
Host smart-8bd9ba8a-cbb5-4596-a1fa-e89bce7add2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012818333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1012818333
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1943308192
Short name T273
Test name
Test status
Simulation time 3575358559 ps
CPU time 4.83 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:04:33 PM PDT 24
Peak memory 225660 kb
Host smart-efae5fb4-1da6-4418-963a-70a45dc85bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943308192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1943308192
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2784002437
Short name T633
Test name
Test status
Simulation time 192729817 ps
CPU time 2.62 seconds
Started Jun 21 07:04:24 PM PDT 24
Finished Jun 21 07:04:36 PM PDT 24
Peak memory 233800 kb
Host smart-9a0096b0-9194-4709-bb19-e9469e2f41fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784002437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2784002437
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.339125996
Short name T794
Test name
Test status
Simulation time 19390957577 ps
CPU time 44.25 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:05:16 PM PDT 24
Peak memory 234840 kb
Host smart-921f39ba-dba5-409f-ad5a-75efc53c0b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339125996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.339125996
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2516779245
Short name T343
Test name
Test status
Simulation time 295195291 ps
CPU time 3.84 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:34 PM PDT 24
Peak memory 224308 kb
Host smart-3f15d556-b5b7-4cdd-bf73-f206c495728b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2516779245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2516779245
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2927704763
Short name T762
Test name
Test status
Simulation time 13748555245 ps
CPU time 188.43 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:07:37 PM PDT 24
Peak memory 274848 kb
Host smart-79a42268-ccf1-4f6c-84ef-d380366ba866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927704763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2927704763
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1910808339
Short name T296
Test name
Test status
Simulation time 700837326 ps
CPU time 9.41 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:04:37 PM PDT 24
Peak memory 217748 kb
Host smart-46329dea-bd48-4152-8e6b-ef88a76b2c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910808339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1910808339
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4120075179
Short name T645
Test name
Test status
Simulation time 9255873598 ps
CPU time 13.02 seconds
Started Jun 21 07:04:21 PM PDT 24
Finished Jun 21 07:04:43 PM PDT 24
Peak memory 217452 kb
Host smart-38361004-dd0c-45ea-94e5-56618057fa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120075179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4120075179
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3497765405
Short name T621
Test name
Test status
Simulation time 178751137 ps
CPU time 1.43 seconds
Started Jun 21 07:04:19 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 217364 kb
Host smart-a65c4127-4d42-4593-be87-b03bb9f094d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497765405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3497765405
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1777843345
Short name T558
Test name
Test status
Simulation time 33187722 ps
CPU time 0.71 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 206536 kb
Host smart-cbb1ce9a-e1e6-4715-9561-7e1c24b667b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777843345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1777843345
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.59301169
Short name T943
Test name
Test status
Simulation time 20185870017 ps
CPU time 7.07 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:41 PM PDT 24
Peak memory 225668 kb
Host smart-97dff1c8-cbc2-40ad-a666-1b934ca53c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59301169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.59301169
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3223794403
Short name T391
Test name
Test status
Simulation time 78602706 ps
CPU time 0.72 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:35 PM PDT 24
Peak memory 206008 kb
Host smart-710d17ee-e4b0-43b2-ad9b-665f891f751e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223794403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3223794403
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4177514159
Short name T119
Test name
Test status
Simulation time 78886015 ps
CPU time 2.64 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:33 PM PDT 24
Peak memory 233856 kb
Host smart-d6cda5ce-5e6d-4ecb-89d5-0009ca4dbc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177514159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4177514159
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.601751499
Short name T341
Test name
Test status
Simulation time 36969710 ps
CPU time 0.77 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:04:28 PM PDT 24
Peak memory 207492 kb
Host smart-38152082-1a2d-4158-9c4d-199f5ca3469b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601751499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.601751499
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2487551586
Short name T487
Test name
Test status
Simulation time 23070704332 ps
CPU time 51.3 seconds
Started Jun 21 07:04:21 PM PDT 24
Finished Jun 21 07:05:21 PM PDT 24
Peak memory 242072 kb
Host smart-6f3f99f7-e179-4ab6-a8e5-b262a59a13b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487551586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2487551586
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1440194278
Short name T180
Test name
Test status
Simulation time 1671208435 ps
CPU time 30.35 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:05:02 PM PDT 24
Peak memory 241896 kb
Host smart-0847f467-3d29-454a-8f1f-2678b6322790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440194278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1440194278
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2802893170
Short name T610
Test name
Test status
Simulation time 1416908115 ps
CPU time 23.04 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:54 PM PDT 24
Peak memory 225708 kb
Host smart-4acd3bdb-732f-437e-9a9e-6661d0658319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802893170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2802893170
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3565472172
Short name T471
Test name
Test status
Simulation time 30987888 ps
CPU time 2.12 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:33 PM PDT 24
Peak memory 223876 kb
Host smart-56c54bb3-d1fa-444e-8bda-cbc65fd9c688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565472172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3565472172
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3929850270
Short name T761
Test name
Test status
Simulation time 8747799191 ps
CPU time 54.88 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:05:26 PM PDT 24
Peak memory 233832 kb
Host smart-45ebeeb1-ad99-49a4-abbb-6bde4f3cb507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929850270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3929850270
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1902665750
Short name T223
Test name
Test status
Simulation time 13373474690 ps
CPU time 13.86 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:04:41 PM PDT 24
Peak memory 233824 kb
Host smart-190df2b1-cf00-4120-be5f-179308968d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902665750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1902665750
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2522360438
Short name T507
Test name
Test status
Simulation time 351635071 ps
CPU time 2.29 seconds
Started Jun 21 07:04:19 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 224844 kb
Host smart-e52bf5c5-575a-4820-ac39-09acecb5fa1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522360438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2522360438
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3589175105
Short name T965
Test name
Test status
Simulation time 122090207 ps
CPU time 3.19 seconds
Started Jun 21 07:04:25 PM PDT 24
Finished Jun 21 07:04:37 PM PDT 24
Peak memory 219868 kb
Host smart-a2485a5f-8626-4981-80a0-540e37c9e6b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3589175105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3589175105
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1726169990
Short name T146
Test name
Test status
Simulation time 33105497021 ps
CPU time 271.43 seconds
Started Jun 21 07:04:24 PM PDT 24
Finished Jun 21 07:09:05 PM PDT 24
Peak memory 264064 kb
Host smart-1a0c61ea-ea60-4ac5-94ba-b699e4a5bfa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726169990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1726169990
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2426680425
Short name T443
Test name
Test status
Simulation time 963190693 ps
CPU time 3.93 seconds
Started Jun 21 07:04:24 PM PDT 24
Finished Jun 21 07:04:36 PM PDT 24
Peak memory 219352 kb
Host smart-0a18c9ef-e9d4-4259-9372-f3fcd08e1d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426680425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2426680425
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3211852158
Short name T303
Test name
Test status
Simulation time 899440431 ps
CPU time 5.28 seconds
Started Jun 21 07:04:25 PM PDT 24
Finished Jun 21 07:04:39 PM PDT 24
Peak memory 217392 kb
Host smart-3115e0cc-003b-4b5b-9a7b-97eff8bda989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211852158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3211852158
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3614244032
Short name T501
Test name
Test status
Simulation time 87372654 ps
CPU time 1.15 seconds
Started Jun 21 07:04:20 PM PDT 24
Finished Jun 21 07:04:29 PM PDT 24
Peak memory 208540 kb
Host smart-8537f105-c49a-4ada-bb18-db7aab21e207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614244032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3614244032
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2004545500
Short name T677
Test name
Test status
Simulation time 25797736 ps
CPU time 0.73 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:31 PM PDT 24
Peak memory 206900 kb
Host smart-c221d271-ce4c-4521-b60b-8c2c9b928ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004545500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2004545500
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.4116388476
Short name T628
Test name
Test status
Simulation time 13564708035 ps
CPU time 13.72 seconds
Started Jun 21 07:04:24 PM PDT 24
Finished Jun 21 07:04:47 PM PDT 24
Peak memory 233888 kb
Host smart-32aa568f-ba9e-4601-a336-9266952faf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116388476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.4116388476
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3536063662
Short name T955
Test name
Test status
Simulation time 19356693 ps
CPU time 0.72 seconds
Started Jun 21 07:04:30 PM PDT 24
Finished Jun 21 07:04:42 PM PDT 24
Peak memory 205732 kb
Host smart-9c37eb9d-fdaa-4954-8100-e9043f2b307b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536063662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3536063662
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.778467861
Short name T563
Test name
Test status
Simulation time 178493932 ps
CPU time 5.01 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 233724 kb
Host smart-97b29b7d-a8c1-4df0-ad25-3bde2450a08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778467861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.778467861
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3029809866
Short name T712
Test name
Test status
Simulation time 18911420 ps
CPU time 0.78 seconds
Started Jun 21 07:04:22 PM PDT 24
Finished Jun 21 07:04:31 PM PDT 24
Peak memory 207832 kb
Host smart-8fb48ea0-504d-418d-814f-85cf5f444f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029809866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3029809866
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2564350188
Short name T929
Test name
Test status
Simulation time 8767055267 ps
CPU time 130.62 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:06:45 PM PDT 24
Peak memory 265528 kb
Host smart-9cf90e9a-d16e-461e-a4ec-f0adf5b70d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564350188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2564350188
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2994350679
Short name T883
Test name
Test status
Simulation time 8563310757 ps
CPU time 21.33 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:05:00 PM PDT 24
Peak memory 233868 kb
Host smart-47b8f88d-f020-4e52-9865-9e1ed0c9ab62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994350679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2994350679
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3866861505
Short name T469
Test name
Test status
Simulation time 33684818 ps
CPU time 2.62 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:37 PM PDT 24
Peak memory 233532 kb
Host smart-3d697071-e1b9-44cb-a824-96edc067f32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866861505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3866861505
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1826041801
Short name T552
Test name
Test status
Simulation time 891972432 ps
CPU time 9.82 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:04:59 PM PDT 24
Peak memory 233496 kb
Host smart-ef697934-52c6-4a05-9a33-57716183000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826041801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1826041801
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.331314635
Short name T697
Test name
Test status
Simulation time 80779976 ps
CPU time 2.33 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:39 PM PDT 24
Peak memory 225524 kb
Host smart-c01a7ec3-bcff-4b20-b891-cd99904ecd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331314635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.331314635
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3998479803
Short name T760
Test name
Test status
Simulation time 2576278621 ps
CPU time 8.71 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:43 PM PDT 24
Peak memory 219720 kb
Host smart-055bdf21-ca98-4f95-9211-62e0ad890542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998479803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3998479803
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3066641512
Short name T546
Test name
Test status
Simulation time 473989224 ps
CPU time 3.77 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 219872 kb
Host smart-c1888074-4735-4944-ad2b-0bb096460b73
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066641512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3066641512
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2765814211
Short name T202
Test name
Test status
Simulation time 134788947701 ps
CPU time 266.56 seconds
Started Jun 21 07:04:31 PM PDT 24
Finished Jun 21 07:09:09 PM PDT 24
Peak memory 266172 kb
Host smart-2d0181f7-b44f-4472-82f9-7740b526b4d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765814211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2765814211
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2640639397
Short name T461
Test name
Test status
Simulation time 59479429 ps
CPU time 0.69 seconds
Started Jun 21 07:04:30 PM PDT 24
Finished Jun 21 07:04:41 PM PDT 24
Peak memory 206676 kb
Host smart-db39d2d8-498c-49ae-8d36-ccc999b35500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640639397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2640639397
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1031341932
Short name T886
Test name
Test status
Simulation time 7905092192 ps
CPU time 6.65 seconds
Started Jun 21 07:04:23 PM PDT 24
Finished Jun 21 07:04:38 PM PDT 24
Peak memory 217528 kb
Host smart-5cb24c9f-2c34-4ca6-9cac-a83095a1b7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031341932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1031341932
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4146407982
Short name T301
Test name
Test status
Simulation time 165645469 ps
CPU time 1.24 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:04:39 PM PDT 24
Peak memory 209224 kb
Host smart-1e6709cc-25c6-4ec5-b58c-01f86f2fe8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146407982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4146407982
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3245315733
Short name T685
Test name
Test status
Simulation time 39107388 ps
CPU time 0.85 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:36 PM PDT 24
Peak memory 206824 kb
Host smart-c7c24f1f-ae38-4f2a-af09-cea0c542899d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245315733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3245315733
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.389841566
Short name T183
Test name
Test status
Simulation time 90814824 ps
CPU time 2.35 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:04:42 PM PDT 24
Peak memory 225492 kb
Host smart-1eed7443-0951-44b2-ae82-26059bee258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389841566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.389841566
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1997895235
Short name T692
Test name
Test status
Simulation time 28251790 ps
CPU time 0.73 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:04:38 PM PDT 24
Peak memory 206584 kb
Host smart-bc7a9144-e68b-4a01-9b25-1c2e06eab622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997895235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1997895235
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3852128771
Short name T395
Test name
Test status
Simulation time 192412802 ps
CPU time 3.66 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 225544 kb
Host smart-7d4ff441-77f8-45f3-a941-77c7255592f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852128771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3852128771
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.512647341
Short name T333
Test name
Test status
Simulation time 60385506 ps
CPU time 0.8 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:04:39 PM PDT 24
Peak memory 207520 kb
Host smart-2d44f2f9-af9b-4815-9d6d-84da4cc3003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512647341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.512647341
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2376794629
Short name T824
Test name
Test status
Simulation time 32919357108 ps
CPU time 135.98 seconds
Started Jun 21 07:04:37 PM PDT 24
Finished Jun 21 07:07:06 PM PDT 24
Peak memory 250252 kb
Host smart-89c4193a-9321-464f-a48d-306518825c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376794629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2376794629
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2125683640
Short name T222
Test name
Test status
Simulation time 63920256623 ps
CPU time 110.49 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:06:26 PM PDT 24
Peak memory 250348 kb
Host smart-d3b140e1-070d-40bb-8da9-aaaacb56dfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125683640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2125683640
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2412456648
Short name T505
Test name
Test status
Simulation time 5193603343 ps
CPU time 23.75 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:05:02 PM PDT 24
Peak memory 218652 kb
Host smart-3e9b992e-27ec-4f34-a53d-c6de5284fd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412456648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2412456648
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.393875720
Short name T51
Test name
Test status
Simulation time 4302205051 ps
CPU time 41.75 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:05:18 PM PDT 24
Peak memory 240740 kb
Host smart-69f43710-3439-497e-afee-9a829575d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393875720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.393875720
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2104522957
Short name T822
Test name
Test status
Simulation time 320518180 ps
CPU time 2.16 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:38 PM PDT 24
Peak memory 225376 kb
Host smart-c3252b98-57ce-4787-86b4-e8c2e576f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104522957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2104522957
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.811953691
Short name T606
Test name
Test status
Simulation time 1312463745 ps
CPU time 9.79 seconds
Started Jun 21 07:04:31 PM PDT 24
Finished Jun 21 07:04:52 PM PDT 24
Peak memory 225488 kb
Host smart-9a24c8c6-4032-4a5b-b414-ee669be2e176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811953691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.811953691
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3874397165
Short name T224
Test name
Test status
Simulation time 7153046046 ps
CPU time 25.15 seconds
Started Jun 21 07:04:31 PM PDT 24
Finished Jun 21 07:05:08 PM PDT 24
Peak memory 233868 kb
Host smart-9c452393-37db-4530-8aad-0393aee4c47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874397165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3874397165
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1779139843
Short name T918
Test name
Test status
Simulation time 417171109 ps
CPU time 5.93 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:42 PM PDT 24
Peak memory 225500 kb
Host smart-dfb4a632-f261-40b0-98fd-ef1e6a1f8353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779139843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1779139843
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3371195794
Short name T370
Test name
Test status
Simulation time 6969000236 ps
CPU time 20.51 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:05:08 PM PDT 24
Peak memory 224228 kb
Host smart-d0aadd03-bb27-4b6f-b0cc-e0e05ad20e78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3371195794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3371195794
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1550085947
Short name T532
Test name
Test status
Simulation time 670955948141 ps
CPU time 441.88 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:12:00 PM PDT 24
Peak memory 256796 kb
Host smart-59d7e199-590b-4c0e-8a27-0235876b5b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550085947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1550085947
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3339657772
Short name T323
Test name
Test status
Simulation time 2328114011 ps
CPU time 4.49 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:04:44 PM PDT 24
Peak memory 217496 kb
Host smart-5c11adab-e5c9-41e8-be78-1ef8fb933a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339657772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3339657772
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2390023255
Short name T694
Test name
Test status
Simulation time 2682685623 ps
CPU time 2.4 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 209076 kb
Host smart-4c37f111-43b6-4a28-a929-4c8ced8fd834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390023255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2390023255
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2060273084
Short name T361
Test name
Test status
Simulation time 168376905 ps
CPU time 1.44 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:38 PM PDT 24
Peak memory 217372 kb
Host smart-a1c1ecfc-40d2-441a-b414-96eada64f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060273084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2060273084
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3462906488
Short name T750
Test name
Test status
Simulation time 34048315 ps
CPU time 0.81 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:35 PM PDT 24
Peak memory 206892 kb
Host smart-29edfe74-befa-4596-8ada-4ae9e394b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462906488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3462906488
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.413354562
Short name T410
Test name
Test status
Simulation time 305246760 ps
CPU time 4.08 seconds
Started Jun 21 07:04:30 PM PDT 24
Finished Jun 21 07:04:45 PM PDT 24
Peak memory 225556 kb
Host smart-56117fab-f3ba-44a7-b16b-169977748d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413354562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.413354562
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1170752610
Short name T949
Test name
Test status
Simulation time 52813127 ps
CPU time 0.69 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 206276 kb
Host smart-d83cd46f-6b02-44f3-bead-46c31904c803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170752610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1170752610
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.7940199
Short name T76
Test name
Test status
Simulation time 574696901 ps
CPU time 5.05 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:52 PM PDT 24
Peak memory 225576 kb
Host smart-ea4e634b-01b2-4415-80c6-ce1c204f4fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7940199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.7940199
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.620557420
Short name T360
Test name
Test status
Simulation time 294853189 ps
CPU time 0.76 seconds
Started Jun 21 07:04:34 PM PDT 24
Finished Jun 21 07:04:47 PM PDT 24
Peak memory 207500 kb
Host smart-9d2c9c83-1d8c-4bd9-b25b-2c34faaf7395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620557420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.620557420
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.112713677
Short name T914
Test name
Test status
Simulation time 6403779094 ps
CPU time 59.25 seconds
Started Jun 21 07:04:31 PM PDT 24
Finished Jun 21 07:05:42 PM PDT 24
Peak memory 250860 kb
Host smart-3a2e922e-88e7-4e83-a139-6b6065768a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112713677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.112713677
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3442241683
Short name T604
Test name
Test status
Simulation time 3279327887 ps
CPU time 5.2 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:53 PM PDT 24
Peak memory 225640 kb
Host smart-1ebea1a2-c2d3-4e58-9853-ad6c8f1d7140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442241683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3442241683
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2161676108
Short name T213
Test name
Test status
Simulation time 49288082806 ps
CPU time 445.06 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:12:04 PM PDT 24
Peak memory 266684 kb
Host smart-80e0822e-8a11-4fa8-9d5e-64f7f39d20f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161676108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2161676108
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3895341753
Short name T738
Test name
Test status
Simulation time 4040286290 ps
CPU time 10.58 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 233896 kb
Host smart-7377c8c9-2fb4-4fa3-8790-47a5738a974d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895341753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3895341753
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.20796961
Short name T555
Test name
Test status
Simulation time 414062835 ps
CPU time 2.23 seconds
Started Jun 21 07:04:32 PM PDT 24
Finished Jun 21 07:04:45 PM PDT 24
Peak memory 219300 kb
Host smart-04958485-3a83-4b4e-9c24-0f5836964d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20796961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.20796961
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.280613122
Short name T312
Test name
Test status
Simulation time 102880051 ps
CPU time 2.31 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:04:51 PM PDT 24
Peak memory 223524 kb
Host smart-18933e36-34d5-4025-adb0-172abafa5b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280613122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.280613122
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2678832463
Short name T906
Test name
Test status
Simulation time 172473493 ps
CPU time 2.55 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 233776 kb
Host smart-0a28e36e-bd59-427f-a0db-c5111b854898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678832463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2678832463
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.175874959
Short name T648
Test name
Test status
Simulation time 204934275 ps
CPU time 2.11 seconds
Started Jun 21 07:04:28 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 223928 kb
Host smart-729997ac-d587-4c4b-814c-d3716215af59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175874959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.175874959
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2183228344
Short name T498
Test name
Test status
Simulation time 102676481 ps
CPU time 3.85 seconds
Started Jun 21 07:04:30 PM PDT 24
Finished Jun 21 07:04:45 PM PDT 24
Peak memory 224084 kb
Host smart-d0950372-ec96-4f40-9c41-4d2bf336e4ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2183228344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2183228344
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2495575266
Short name T531
Test name
Test status
Simulation time 43845389 ps
CPU time 1.02 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:49 PM PDT 24
Peak memory 207900 kb
Host smart-7c1e6ec7-5784-43b2-894f-a857edd1f849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495575266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2495575266
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1961137345
Short name T638
Test name
Test status
Simulation time 37796864125 ps
CPU time 33.07 seconds
Started Jun 21 07:04:30 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 217492 kb
Host smart-6d5cfae3-ec0b-4332-a96b-f0137e085755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961137345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1961137345
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2287919332
Short name T672
Test name
Test status
Simulation time 17670419039 ps
CPU time 14.35 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:49 PM PDT 24
Peak memory 217524 kb
Host smart-4bd83ad1-724b-4431-9801-44bd16ba979a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287919332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2287919332
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2163012031
Short name T64
Test name
Test status
Simulation time 172625919 ps
CPU time 2.51 seconds
Started Jun 21 07:04:26 PM PDT 24
Finished Jun 21 07:04:37 PM PDT 24
Peak memory 217332 kb
Host smart-61c8abeb-3725-4b7c-9e80-7e2629a7026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163012031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2163012031
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2322070668
Short name T840
Test name
Test status
Simulation time 39215615 ps
CPU time 0.8 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:04:40 PM PDT 24
Peak memory 206892 kb
Host smart-c275b6d5-7656-4cd3-8d47-5b5110f17529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322070668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2322070668
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1622416201
Short name T639
Test name
Test status
Simulation time 6781546504 ps
CPU time 23.44 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 233844 kb
Host smart-782869f5-23b4-4d56-aa85-7628054e8d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622416201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1622416201
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.15361917
Short name T349
Test name
Test status
Simulation time 13474957 ps
CPU time 0.71 seconds
Started Jun 21 07:04:34 PM PDT 24
Finished Jun 21 07:04:47 PM PDT 24
Peak memory 206616 kb
Host smart-94804a5e-1592-4f85-a195-4fd5179b6872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15361917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.15361917
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.338786453
Short name T276
Test name
Test status
Simulation time 845838202 ps
CPU time 5.16 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:52 PM PDT 24
Peak memory 233772 kb
Host smart-5192bf8a-d406-416f-a3cd-406f4fa8c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338786453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.338786453
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3427951075
Short name T572
Test name
Test status
Simulation time 13985359 ps
CPU time 0.76 seconds
Started Jun 21 07:04:37 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 207448 kb
Host smart-9af7b4cc-99bd-4424-abcb-df4abd745b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427951075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3427951075
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.25471969
Short name T156
Test name
Test status
Simulation time 51791674756 ps
CPU time 194.96 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:08:04 PM PDT 24
Peak memory 250296 kb
Host smart-57a76f4f-67ad-46ed-b9a4-93310f603ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25471969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.25471969
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3131767164
Short name T499
Test name
Test status
Simulation time 4424949654 ps
CPU time 90.29 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:06:18 PM PDT 24
Peak memory 266872 kb
Host smart-224fb469-715b-43a3-a4a4-fd179d1de894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131767164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3131767164
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1864089356
Short name T121
Test name
Test status
Simulation time 23564248679 ps
CPU time 91.29 seconds
Started Jun 21 07:04:40 PM PDT 24
Finished Jun 21 07:06:23 PM PDT 24
Peak memory 252028 kb
Host smart-c4b5cc34-15ab-4a59-8f91-92e19cbcf3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864089356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1864089356
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1016506340
Short name T711
Test name
Test status
Simulation time 239112423 ps
CPU time 6.03 seconds
Started Jun 21 07:04:33 PM PDT 24
Finished Jun 21 07:04:51 PM PDT 24
Peak memory 233780 kb
Host smart-d408c18a-e604-4581-9e82-a678dc16fe25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016506340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1016506340
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1749011586
Short name T670
Test name
Test status
Simulation time 9373370908 ps
CPU time 14.78 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:05:04 PM PDT 24
Peak memory 233904 kb
Host smart-66155079-ad44-48e6-8915-2211585f94e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749011586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1749011586
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2939261897
Short name T265
Test name
Test status
Simulation time 3710569494 ps
CPU time 28.04 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:05:16 PM PDT 24
Peak memory 234988 kb
Host smart-be38cbbb-445a-4d5b-a233-d1ad6a0cb84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939261897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2939261897
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2002484939
Short name T233
Test name
Test status
Simulation time 27550060815 ps
CPU time 13.97 seconds
Started Jun 21 07:04:27 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 233872 kb
Host smart-8860446b-a334-4246-b6e2-92fe5f592776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002484939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2002484939
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3327619353
Short name T422
Test name
Test status
Simulation time 64273921 ps
CPU time 2.91 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:04:43 PM PDT 24
Peak memory 233880 kb
Host smart-a1039283-c53a-44b7-9783-d488edcf74d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327619353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3327619353
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.422089243
Short name T542
Test name
Test status
Simulation time 1397964877 ps
CPU time 11.79 seconds
Started Jun 21 07:04:33 PM PDT 24
Finished Jun 21 07:04:57 PM PDT 24
Peak memory 219964 kb
Host smart-33272cb2-9d3d-440c-b873-25ab70b93b64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=422089243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.422089243
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3226465925
Short name T148
Test name
Test status
Simulation time 27653712135 ps
CPU time 275.27 seconds
Started Jun 21 07:04:38 PM PDT 24
Finished Jun 21 07:09:26 PM PDT 24
Peak memory 267904 kb
Host smart-f74eb777-6ff7-4843-86df-47d15a6a10f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226465925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3226465925
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2527049638
Short name T1
Test name
Test status
Simulation time 3614013231 ps
CPU time 10.39 seconds
Started Jun 21 07:04:30 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 217436 kb
Host smart-3bfc2183-38af-4ba3-b7d4-e0e3f7a3a3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527049638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2527049638
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3764219718
Short name T523
Test name
Test status
Simulation time 51061316775 ps
CPU time 11.21 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:05:00 PM PDT 24
Peak memory 217404 kb
Host smart-992b4218-d88f-4a8c-9bd6-36e49d37958c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764219718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3764219718
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1258593197
Short name T625
Test name
Test status
Simulation time 19535122 ps
CPU time 1.08 seconds
Started Jun 21 07:04:31 PM PDT 24
Finished Jun 21 07:04:44 PM PDT 24
Peak memory 217268 kb
Host smart-48be8f59-e4eb-414b-99fe-92703001f241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258593197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1258593197
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2191650530
Short name T575
Test name
Test status
Simulation time 128928401 ps
CPU time 0.76 seconds
Started Jun 21 07:04:29 PM PDT 24
Finished Jun 21 07:04:41 PM PDT 24
Peak memory 206892 kb
Host smart-73ceb7b8-46f4-4b9d-bdd6-41ca9f6f22f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191650530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2191650530
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1974507240
Short name T717
Test name
Test status
Simulation time 57550895 ps
CPU time 2.65 seconds
Started Jun 21 07:04:34 PM PDT 24
Finished Jun 21 07:04:48 PM PDT 24
Peak memory 233772 kb
Host smart-4ad9cb2a-28ad-4127-abf9-ba0b56ae7be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974507240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1974507240
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2764426156
Short name T807
Test name
Test status
Simulation time 13427874 ps
CPU time 0.69 seconds
Started Jun 21 07:02:34 PM PDT 24
Finished Jun 21 07:02:39 PM PDT 24
Peak memory 206632 kb
Host smart-404ef7db-6e87-45bb-9810-cd52b93b9c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764426156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
764426156
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3932091639
Short name T565
Test name
Test status
Simulation time 1277296622 ps
CPU time 7.47 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:49 PM PDT 24
Peak memory 233688 kb
Host smart-fd7e1e94-0269-4470-844c-f1b6a8931bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932091639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3932091639
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3842354399
Short name T598
Test name
Test status
Simulation time 43451916 ps
CPU time 0.78 seconds
Started Jun 21 07:02:41 PM PDT 24
Finished Jun 21 07:02:48 PM PDT 24
Peak memory 207488 kb
Host smart-b50be36e-3969-4fb6-9c42-982786a824d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842354399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3842354399
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1932760593
Short name T60
Test name
Test status
Simulation time 595886847 ps
CPU time 12.21 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:56 PM PDT 24
Peak memory 242012 kb
Host smart-9b36f570-851f-4f0a-8d9d-3938e2f9da89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932760593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1932760593
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.292409617
Short name T416
Test name
Test status
Simulation time 2776144873 ps
CPU time 69.79 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:03:53 PM PDT 24
Peak memory 258120 kb
Host smart-8e2fe0e1-fb6e-4665-8a4c-78be8e1a23ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292409617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.292409617
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3546372254
Short name T125
Test name
Test status
Simulation time 2687813311 ps
CPU time 64.6 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:03:46 PM PDT 24
Peak memory 254528 kb
Host smart-f220c71f-0d6e-43b7-a757-8d77eecd13dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546372254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3546372254
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.403193714
Short name T364
Test name
Test status
Simulation time 364398403 ps
CPU time 4.83 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:47 PM PDT 24
Peak memory 225584 kb
Host smart-e9cc1455-d870-4211-988b-5b993e0ef5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403193714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.403193714
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1043055901
Short name T888
Test name
Test status
Simulation time 249515788 ps
CPU time 5.88 seconds
Started Jun 21 07:02:39 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 233792 kb
Host smart-95f400b9-6f79-4028-a838-e4de0e80d47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043055901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1043055901
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1143251734
Short name T149
Test name
Test status
Simulation time 4553708104 ps
CPU time 41.67 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:03:23 PM PDT 24
Peak memory 233788 kb
Host smart-039cf0b3-8e1c-47b0-9f2f-409335c7db74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143251734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1143251734
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1713316291
Short name T506
Test name
Test status
Simulation time 16562076 ps
CPU time 1.05 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:42 PM PDT 24
Peak memory 217644 kb
Host smart-d00a931d-16f2-4fd2-a4ab-5232f7b2cf25
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713316291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1713316291
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3879721242
Short name T616
Test name
Test status
Simulation time 35610997295 ps
CPU time 13.24 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:02:54 PM PDT 24
Peak memory 225708 kb
Host smart-6903ee26-865f-4f43-a5f3-633ac89d098f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879721242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3879721242
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2945961832
Short name T823
Test name
Test status
Simulation time 347796798 ps
CPU time 2.91 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:44 PM PDT 24
Peak memory 225500 kb
Host smart-f6cce354-70c1-4f56-ac6d-8b88b83caa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945961832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2945961832
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1774045978
Short name T383
Test name
Test status
Simulation time 4205671267 ps
CPU time 6.39 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:02:53 PM PDT 24
Peak memory 222260 kb
Host smart-bf0551a0-1f9b-4be4-8f9c-89ae5a6635b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1774045978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1774045978
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3121742872
Short name T16
Test name
Test status
Simulation time 75143054 ps
CPU time 0.98 seconds
Started Jun 21 07:02:42 PM PDT 24
Finished Jun 21 07:02:49 PM PDT 24
Peak memory 236572 kb
Host smart-373dd18d-850e-45b7-9e78-946a4620b086
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121742872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3121742872
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.590885757
Short name T772
Test name
Test status
Simulation time 161160911532 ps
CPU time 256.86 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:07:00 PM PDT 24
Peak memory 271064 kb
Host smart-e50dca9c-ba58-41a8-9dbb-963bf194525f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590885757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.590885757
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3088610273
Short name T295
Test name
Test status
Simulation time 28513089508 ps
CPU time 35.44 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:03:16 PM PDT 24
Peak memory 217496 kb
Host smart-aefb55b3-5454-4c47-b7e3-ac9347b2f9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088610273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3088610273
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3006386545
Short name T351
Test name
Test status
Simulation time 31933807598 ps
CPU time 13.04 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:02:54 PM PDT 24
Peak memory 217528 kb
Host smart-bf8fd763-d6c0-47c3-b9ed-5536c64dbbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006386545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3006386545
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4218141260
Short name T447
Test name
Test status
Simulation time 17784608 ps
CPU time 0.81 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:02:41 PM PDT 24
Peak memory 207916 kb
Host smart-eca036e1-3466-448a-917b-9797ab438dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218141260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4218141260
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3238880724
Short name T374
Test name
Test status
Simulation time 24816711 ps
CPU time 0.73 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:43 PM PDT 24
Peak memory 206896 kb
Host smart-30c6e122-ef0c-4ae0-94c2-96c0c46d99c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238880724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3238880724
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1681146952
Short name T262
Test name
Test status
Simulation time 564605711 ps
CPU time 5.29 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 225556 kb
Host smart-14b230b0-6510-4ccf-a3b2-20fdc2645852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681146952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1681146952
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1014057206
Short name T503
Test name
Test status
Simulation time 30002519 ps
CPU time 0.71 seconds
Started Jun 21 07:04:39 PM PDT 24
Finished Jun 21 07:04:52 PM PDT 24
Peak memory 206244 kb
Host smart-04392ee2-9a31-4d15-807f-fe1ed6c665e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014057206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1014057206
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3779908118
Short name T188
Test name
Test status
Simulation time 3060268610 ps
CPU time 9.72 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:56 PM PDT 24
Peak memory 225648 kb
Host smart-923d421e-9fa5-4c1c-8d23-0141f97c7c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779908118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3779908118
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1148272066
Short name T874
Test name
Test status
Simulation time 46457629 ps
CPU time 0.74 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:48 PM PDT 24
Peak memory 206476 kb
Host smart-16ba1ee2-9a46-4a8d-87be-16c91176b50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148272066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1148272066
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2501377215
Short name T200
Test name
Test status
Simulation time 2682062766 ps
CPU time 70.69 seconds
Started Jun 21 07:04:34 PM PDT 24
Finished Jun 21 07:05:56 PM PDT 24
Peak memory 266672 kb
Host smart-bf34cb67-d5d8-4f19-a907-24b1fc901efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501377215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2501377215
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2358698526
Short name T500
Test name
Test status
Simulation time 97969328716 ps
CPU time 213.07 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:08:22 PM PDT 24
Peak memory 252788 kb
Host smart-2082ccdc-fd3b-4350-9f7d-28208746ad77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358698526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2358698526
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2428055389
Short name T666
Test name
Test status
Simulation time 102844745 ps
CPU time 3.82 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:04:53 PM PDT 24
Peak memory 225504 kb
Host smart-ca3bffa5-5eb9-4bde-8545-a7f0bebe0d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428055389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2428055389
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3420784605
Short name T653
Test name
Test status
Simulation time 686702317 ps
CPU time 3.51 seconds
Started Jun 21 07:04:34 PM PDT 24
Finished Jun 21 07:04:49 PM PDT 24
Peak memory 225596 kb
Host smart-603bf7cc-16f4-40da-9400-aeedea52a654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420784605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3420784605
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1802164347
Short name T136
Test name
Test status
Simulation time 532894084 ps
CPU time 5.7 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:53 PM PDT 24
Peak memory 225592 kb
Host smart-788347ef-9c7b-4604-9af8-f0310df6d47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802164347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1802164347
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3811184910
Short name T281
Test name
Test status
Simulation time 1963579037 ps
CPU time 5.67 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:53 PM PDT 24
Peak memory 225584 kb
Host smart-10a06ccb-f946-4b01-9c81-63c0bbf0692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811184910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3811184910
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.534460105
Short name T742
Test name
Test status
Simulation time 792047086 ps
CPU time 2.49 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:04:51 PM PDT 24
Peak memory 225344 kb
Host smart-a0560637-bce6-4936-9f5c-acbfd62f6678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534460105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.534460105
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1967109892
Short name T321
Test name
Test status
Simulation time 2736374503 ps
CPU time 10.4 seconds
Started Jun 21 07:04:34 PM PDT 24
Finished Jun 21 07:04:57 PM PDT 24
Peak memory 221844 kb
Host smart-ae29f16f-9f2b-45f8-8540-2122dd4896f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1967109892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1967109892
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1986847331
Short name T19
Test name
Test status
Simulation time 9523197385 ps
CPU time 78.41 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:06:08 PM PDT 24
Peak memory 252404 kb
Host smart-ca6816fc-d378-4ff1-a625-584573f5bbde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986847331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1986847331
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2391220774
Short name T935
Test name
Test status
Simulation time 25127808354 ps
CPU time 37.26 seconds
Started Jun 21 07:04:40 PM PDT 24
Finished Jun 21 07:05:29 PM PDT 24
Peak memory 217532 kb
Host smart-7c918d3a-c157-4918-aa60-d34f1088a927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391220774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2391220774
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2012062688
Short name T586
Test name
Test status
Simulation time 2545292625 ps
CPU time 7.58 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:55 PM PDT 24
Peak memory 217412 kb
Host smart-bc2092b7-8012-4186-af8d-424c06c95ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012062688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2012062688
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.650502160
Short name T614
Test name
Test status
Simulation time 70183597 ps
CPU time 1.28 seconds
Started Jun 21 07:04:35 PM PDT 24
Finished Jun 21 07:04:49 PM PDT 24
Peak memory 209136 kb
Host smart-d42ebcaa-76c4-4a76-af7b-4cb08ee9bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650502160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.650502160
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2445565345
Short name T674
Test name
Test status
Simulation time 58884813 ps
CPU time 0.81 seconds
Started Jun 21 07:04:34 PM PDT 24
Finished Jun 21 07:04:47 PM PDT 24
Peak memory 206896 kb
Host smart-3a4be706-289d-40a2-a1a0-c8974f558e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445565345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2445565345
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.856420743
Short name T10
Test name
Test status
Simulation time 1876230859 ps
CPU time 8.18 seconds
Started Jun 21 07:04:40 PM PDT 24
Finished Jun 21 07:05:00 PM PDT 24
Peak memory 225528 kb
Host smart-fdd1c33e-9476-491e-8c22-c2d57892d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856420743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.856420743
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1657620640
Short name T534
Test name
Test status
Simulation time 42438507 ps
CPU time 0.71 seconds
Started Jun 21 07:04:46 PM PDT 24
Finished Jun 21 07:04:57 PM PDT 24
Peak memory 206260 kb
Host smart-5e1edf60-4d12-4d27-8680-4341bdb57189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657620640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1657620640
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1748906157
Short name T163
Test name
Test status
Simulation time 365659847 ps
CPU time 2.62 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 225504 kb
Host smart-90218e69-d384-4fa2-9271-2d88b78e2d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748906157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1748906157
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4135571635
Short name T644
Test name
Test status
Simulation time 23527905 ps
CPU time 0.77 seconds
Started Jun 21 07:04:36 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 207496 kb
Host smart-4a10d835-83f2-4a0d-ba5c-cde37d5f1a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135571635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4135571635
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2036111873
Short name T550
Test name
Test status
Simulation time 1829414070 ps
CPU time 16.98 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:05:13 PM PDT 24
Peak memory 225504 kb
Host smart-68d4c370-ddef-4381-ae07-d01d18574c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036111873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2036111873
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1210394458
Short name T922
Test name
Test status
Simulation time 1056880930 ps
CPU time 24.72 seconds
Started Jun 21 07:04:46 PM PDT 24
Finished Jun 21 07:05:21 PM PDT 24
Peak memory 240264 kb
Host smart-d0647ed1-dfa3-4149-898d-7d4e59d4db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210394458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1210394458
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1540934506
Short name T904
Test name
Test status
Simulation time 43919792257 ps
CPU time 78.66 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:06:14 PM PDT 24
Peak memory 253356 kb
Host smart-4a097dc1-ac40-4203-a16b-21037cc3fc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540934506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1540934506
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3794739794
Short name T293
Test name
Test status
Simulation time 1144687207 ps
CPU time 19.49 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 227104 kb
Host smart-23b2304e-db51-4a0b-842c-1362a9c5eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794739794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3794739794
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3360527108
Short name T746
Test name
Test status
Simulation time 13425369147 ps
CPU time 6.54 seconds
Started Jun 21 07:04:41 PM PDT 24
Finished Jun 21 07:04:59 PM PDT 24
Peak memory 225712 kb
Host smart-b7843bbf-741e-4377-b339-a874c165a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360527108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3360527108
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3648932912
Short name T636
Test name
Test status
Simulation time 26406566553 ps
CPU time 61.06 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:06:02 PM PDT 24
Peak memory 225624 kb
Host smart-ab3a533f-c186-4c3e-8f13-585a7e2b5c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648932912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3648932912
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.954456441
Short name T279
Test name
Test status
Simulation time 501630668 ps
CPU time 3.57 seconds
Started Jun 21 07:04:40 PM PDT 24
Finished Jun 21 07:04:56 PM PDT 24
Peak memory 241860 kb
Host smart-6c58da4b-40ca-4504-8cec-068508db6ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954456441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.954456441
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.758767440
Short name T936
Test name
Test status
Simulation time 66075648 ps
CPU time 2.47 seconds
Started Jun 21 07:04:40 PM PDT 24
Finished Jun 21 07:04:54 PM PDT 24
Peak memory 233720 kb
Host smart-cb92cea9-7709-465e-83b2-74655a3ca641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758767440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.758767440
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3823417331
Short name T376
Test name
Test status
Simulation time 160101309 ps
CPU time 4.05 seconds
Started Jun 21 07:04:48 PM PDT 24
Finished Jun 21 07:05:02 PM PDT 24
Peak memory 221836 kb
Host smart-32ab1e8c-e070-4257-bde6-4f9e45bbed27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3823417331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3823417331
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.918650872
Short name T843
Test name
Test status
Simulation time 613453896 ps
CPU time 0.98 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:04:56 PM PDT 24
Peak memory 207552 kb
Host smart-c5389ab7-483a-4956-95ff-97aa5e759044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918650872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.918650872
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1401349239
Short name T864
Test name
Test status
Simulation time 10176472913 ps
CPU time 10.22 seconds
Started Jun 21 07:04:42 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 217532 kb
Host smart-9d2a474a-b7a0-4f4d-a86d-6f18e48cc548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401349239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1401349239
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2453950182
Short name T749
Test name
Test status
Simulation time 772920447 ps
CPU time 1.89 seconds
Started Jun 21 07:04:38 PM PDT 24
Finished Jun 21 07:04:52 PM PDT 24
Peak memory 208940 kb
Host smart-3bf18faf-8aa3-4af9-844b-d2ff7be6c978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453950182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2453950182
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2446413987
Short name T354
Test name
Test status
Simulation time 129714236 ps
CPU time 3.33 seconds
Started Jun 21 07:04:40 PM PDT 24
Finished Jun 21 07:04:55 PM PDT 24
Peak memory 217300 kb
Host smart-2acf959c-8459-42d7-a544-c98726dea270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446413987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2446413987
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1317090950
Short name T588
Test name
Test status
Simulation time 32308667 ps
CPU time 0.75 seconds
Started Jun 21 07:04:40 PM PDT 24
Finished Jun 21 07:04:53 PM PDT 24
Peak memory 206896 kb
Host smart-264f8c13-29d6-4465-9e6b-9bbc50b35560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317090950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1317090950
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.560540578
Short name T622
Test name
Test status
Simulation time 12754008180 ps
CPU time 22.3 seconds
Started Jun 21 07:04:43 PM PDT 24
Finished Jun 21 07:05:16 PM PDT 24
Peak memory 233876 kb
Host smart-d1fcb641-f67f-416f-8003-50185b050348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560540578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.560540578
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2816864630
Short name T763
Test name
Test status
Simulation time 12826653 ps
CPU time 0.76 seconds
Started Jun 21 07:04:48 PM PDT 24
Finished Jun 21 07:04:59 PM PDT 24
Peak memory 206288 kb
Host smart-77ed89a8-010b-4912-80bc-26da7cd61ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816864630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2816864630
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1710648642
Short name T186
Test name
Test status
Simulation time 1016351312 ps
CPU time 5.11 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:04:59 PM PDT 24
Peak memory 225580 kb
Host smart-39b260f9-f889-4f85-a837-92b57c41590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710648642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1710648642
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3514993942
Short name T519
Test name
Test status
Simulation time 38786404 ps
CPU time 0.75 seconds
Started Jun 21 07:04:46 PM PDT 24
Finished Jun 21 07:04:57 PM PDT 24
Peak memory 207840 kb
Host smart-c2c0150d-1ea3-482a-8a1a-b6be5d2013b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514993942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3514993942
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.95073299
Short name T248
Test name
Test status
Simulation time 4439445052 ps
CPU time 60.25 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:05:56 PM PDT 24
Peak memory 257004 kb
Host smart-880804d5-b073-4a4f-865a-8f60a83e39ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95073299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.95073299
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3416940900
Short name T576
Test name
Test status
Simulation time 5367072038 ps
CPU time 84.37 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:06:18 PM PDT 24
Peak memory 266708 kb
Host smart-9b05269c-4711-43a9-8c32-d924a565b635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416940900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3416940900
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.90308444
Short name T38
Test name
Test status
Simulation time 19573365895 ps
CPU time 74.35 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:06:09 PM PDT 24
Peak memory 258080 kb
Host smart-203fd980-092d-4c3a-bf64-4e94b63b1072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90308444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.90308444
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2327609124
Short name T340
Test name
Test status
Simulation time 759239516 ps
CPU time 15.99 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:05:11 PM PDT 24
Peak memory 237240 kb
Host smart-7d9d6e12-e957-40d2-b36a-68a43e7d0068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327609124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2327609124
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.4128683126
Short name T651
Test name
Test status
Simulation time 865552701 ps
CPU time 5.49 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:05:00 PM PDT 24
Peak memory 225460 kb
Host smart-841d9f50-d4ff-4550-aae2-61838980af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128683126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.4128683126
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4161500176
Short name T268
Test name
Test status
Simulation time 347995469 ps
CPU time 2.24 seconds
Started Jun 21 07:04:46 PM PDT 24
Finished Jun 21 07:04:58 PM PDT 24
Peak memory 225512 kb
Host smart-98e2e7f2-287d-4098-8a97-8291d4e075ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161500176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4161500176
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2702782919
Short name T804
Test name
Test status
Simulation time 40182478 ps
CPU time 2.3 seconds
Started Jun 21 07:04:48 PM PDT 24
Finished Jun 21 07:05:01 PM PDT 24
Peak memory 225544 kb
Host smart-999b4f50-2fcc-48b9-9157-1c0ae88beda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702782919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2702782919
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1527050781
Short name T767
Test name
Test status
Simulation time 1132566730 ps
CPU time 5.84 seconds
Started Jun 21 07:04:48 PM PDT 24
Finished Jun 21 07:05:04 PM PDT 24
Peak memory 233696 kb
Host smart-75f93cfd-ea89-4592-8b8c-f440ef36c7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527050781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1527050781
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.956568788
Short name T560
Test name
Test status
Simulation time 607214187 ps
CPU time 8.23 seconds
Started Jun 21 07:04:48 PM PDT 24
Finished Jun 21 07:05:07 PM PDT 24
Peak memory 222880 kb
Host smart-5df60904-fa94-4f9b-814b-ab1a1fb77174
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=956568788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.956568788
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2513256210
Short name T718
Test name
Test status
Simulation time 118214104 ps
CPU time 0.97 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:04:55 PM PDT 24
Peak memory 207896 kb
Host smart-26498857-0b96-432e-b516-f7ba52e18175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513256210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2513256210
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.944042023
Short name T464
Test name
Test status
Simulation time 6761410798 ps
CPU time 12.17 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 217512 kb
Host smart-38d1544a-8d2f-47f9-8907-2b8d7b729588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944042023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.944042023
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3314890551
Short name T308
Test name
Test status
Simulation time 8483061055 ps
CPU time 25.52 seconds
Started Jun 21 07:04:48 PM PDT 24
Finished Jun 21 07:05:24 PM PDT 24
Peak memory 217420 kb
Host smart-c9512c60-f59e-4e36-97e2-95c3480c42f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314890551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3314890551
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3772335059
Short name T335
Test name
Test status
Simulation time 168922405 ps
CPU time 1.36 seconds
Started Jun 21 07:04:46 PM PDT 24
Finished Jun 21 07:04:58 PM PDT 24
Peak memory 217380 kb
Host smart-3bc350e4-4552-4591-ad89-477464a672a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772335059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3772335059
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4003525763
Short name T336
Test name
Test status
Simulation time 204114192 ps
CPU time 0.88 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:04:57 PM PDT 24
Peak memory 207932 kb
Host smart-629317e8-ca4c-4689-9440-d9c0877ecbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003525763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4003525763
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3186831978
Short name T474
Test name
Test status
Simulation time 932955558 ps
CPU time 7.61 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:05:04 PM PDT 24
Peak memory 233708 kb
Host smart-d593f95a-322d-4e20-a70c-41b55e71a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186831978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3186831978
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1249136621
Short name T741
Test name
Test status
Simulation time 56361748 ps
CPU time 0.73 seconds
Started Jun 21 07:04:54 PM PDT 24
Finished Jun 21 07:05:05 PM PDT 24
Peak memory 205732 kb
Host smart-057804de-a931-4641-94e8-efc72248c4f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249136621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1249136621
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2499978216
Short name T848
Test name
Test status
Simulation time 1404139223 ps
CPU time 5.38 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 225528 kb
Host smart-d7ba90c1-4f5f-4923-a070-d3f9bbfdc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499978216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2499978216
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2371489795
Short name T920
Test name
Test status
Simulation time 23704553 ps
CPU time 0.74 seconds
Started Jun 21 07:04:47 PM PDT 24
Finished Jun 21 07:04:58 PM PDT 24
Peak memory 207504 kb
Host smart-69376a2a-abda-4a55-9634-f20d9bf5f8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371489795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2371489795
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2388477105
Short name T777
Test name
Test status
Simulation time 1724359509 ps
CPU time 8.36 seconds
Started Jun 21 07:04:57 PM PDT 24
Finished Jun 21 07:05:15 PM PDT 24
Peak memory 237316 kb
Host smart-8e540cad-fef1-4c7b-bf18-45526d340aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388477105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2388477105
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.767833947
Short name T412
Test name
Test status
Simulation time 12181533214 ps
CPU time 121.91 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:07:03 PM PDT 24
Peak memory 250340 kb
Host smart-21f1c245-9365-4eeb-b42b-b2ab0bb579fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767833947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.767833947
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.962638527
Short name T496
Test name
Test status
Simulation time 39485212 ps
CPU time 2.96 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 233796 kb
Host smart-a83b5fe2-c0e7-4da8-9eef-37a3fbe0a9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962638527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.962638527
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3067727677
Short name T426
Test name
Test status
Simulation time 32575511527 ps
CPU time 22.94 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:05:18 PM PDT 24
Peak memory 225644 kb
Host smart-4682496a-1a04-43a1-8eb7-f3c9e1e29d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067727677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3067727677
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1451403820
Short name T640
Test name
Test status
Simulation time 284374871 ps
CPU time 4.88 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:05 PM PDT 24
Peak memory 233764 kb
Host smart-5b1f79ca-2501-4e37-b351-b4f4ceb8bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451403820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1451403820
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.318015308
Short name T161
Test name
Test status
Simulation time 722038069 ps
CPU time 9.18 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:05:05 PM PDT 24
Peak memory 233732 kb
Host smart-db88b1b9-79ae-4977-a7ca-141a9b580bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318015308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.318015308
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2141563497
Short name T259
Test name
Test status
Simulation time 10381726205 ps
CPU time 11.05 seconds
Started Jun 21 07:04:45 PM PDT 24
Finished Jun 21 07:05:07 PM PDT 24
Peak memory 233928 kb
Host smart-ef5e481b-ec87-47c4-8f39-28471ec040e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141563497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2141563497
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1490025011
Short name T75
Test name
Test status
Simulation time 453666290 ps
CPU time 3.45 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 220424 kb
Host smart-0f01b395-9428-45bf-9fd2-58909033e2ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1490025011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1490025011
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3925299465
Short name T456
Test name
Test status
Simulation time 3694437273 ps
CPU time 41.72 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:05:43 PM PDT 24
Peak memory 250368 kb
Host smart-d1d2bc6d-0aee-465c-a358-9049852355e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925299465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3925299465
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3144082452
Short name T386
Test name
Test status
Simulation time 5347111683 ps
CPU time 27.02 seconds
Started Jun 21 07:04:43 PM PDT 24
Finished Jun 21 07:05:20 PM PDT 24
Peak memory 217516 kb
Host smart-179315bb-f988-49f4-9dda-1b9a47f9a146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144082452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3144082452
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2918613192
Short name T368
Test name
Test status
Simulation time 32822791 ps
CPU time 0.71 seconds
Started Jun 21 07:04:46 PM PDT 24
Finished Jun 21 07:04:57 PM PDT 24
Peak memory 206628 kb
Host smart-d06b92ff-10df-44cc-a47d-47083c9605bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918613192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2918613192
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.208170511
Short name T483
Test name
Test status
Simulation time 32313114 ps
CPU time 0.95 seconds
Started Jun 21 07:04:44 PM PDT 24
Finished Jun 21 07:04:55 PM PDT 24
Peak memory 207556 kb
Host smart-e6ae4161-4bef-4afa-beb6-e3fb634a5e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208170511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.208170511
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4248327817
Short name T724
Test name
Test status
Simulation time 40102684 ps
CPU time 0.67 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:00 PM PDT 24
Peak memory 206524 kb
Host smart-95d342b2-dd7b-43c8-9b09-af4457d267d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248327817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4248327817
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.351973898
Short name T454
Test name
Test status
Simulation time 946240655 ps
CPU time 3.29 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 225576 kb
Host smart-ce16af0b-c481-4a9b-966e-d4aaafd0d112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351973898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.351973898
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.607693170
Short name T715
Test name
Test status
Simulation time 63139723 ps
CPU time 0.7 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:05:01 PM PDT 24
Peak memory 205700 kb
Host smart-405cb8e6-a346-4fc2-b032-a50cccba51a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607693170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.607693170
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2981286766
Short name T655
Test name
Test status
Simulation time 879536611 ps
CPU time 9.59 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:12 PM PDT 24
Peak memory 225568 kb
Host smart-ad2a6fa8-2e37-4763-8dfe-06000fd29539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981286766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2981286766
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3507860055
Short name T680
Test name
Test status
Simulation time 58678438 ps
CPU time 0.81 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:04 PM PDT 24
Peak memory 206824 kb
Host smart-64feb34d-7a85-4c06-9af6-83053cf33321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507860055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3507860055
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3343323393
Short name T208
Test name
Test status
Simulation time 48382874110 ps
CPU time 147.76 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:07:30 PM PDT 24
Peak memory 266020 kb
Host smart-58c20751-98cb-4378-9a6d-eb404ae428d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343323393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3343323393
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.89519121
Short name T581
Test name
Test status
Simulation time 4690759186 ps
CPU time 47.32 seconds
Started Jun 21 07:04:55 PM PDT 24
Finished Jun 21 07:05:53 PM PDT 24
Peak memory 251520 kb
Host smart-732a30ae-b931-4a9b-9b55-7d956f6731d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89519121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.89519121
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.331900938
Short name T540
Test name
Test status
Simulation time 162954389 ps
CPU time 2.9 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 225596 kb
Host smart-9c16e046-bfdf-494f-89f2-a63367fc4c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331900938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.331900938
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.293155449
Short name T3
Test name
Test status
Simulation time 479250257 ps
CPU time 6.37 seconds
Started Jun 21 07:04:54 PM PDT 24
Finished Jun 21 07:05:10 PM PDT 24
Peak memory 225512 kb
Host smart-c3aaa925-80bf-4d17-b580-0b5d452276c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293155449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.293155449
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3126108308
Short name T957
Test name
Test status
Simulation time 2039081458 ps
CPU time 26.19 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:29 PM PDT 24
Peak memory 233696 kb
Host smart-c32117c9-b9b8-4f94-b5a3-2e8c80b3b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126108308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3126108308
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2939156568
Short name T878
Test name
Test status
Simulation time 5353751588 ps
CPU time 18.94 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:19 PM PDT 24
Peak memory 249912 kb
Host smart-7d0a4821-2f7c-4483-9659-660f9ca0786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939156568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2939156568
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2809552966
Short name T436
Test name
Test status
Simulation time 125362792 ps
CPU time 2.9 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:05 PM PDT 24
Peak memory 233776 kb
Host smart-b3f392ec-726f-4bdb-a75a-3433a5170407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809552966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2809552966
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3546399343
Short name T463
Test name
Test status
Simulation time 2420609326 ps
CPU time 6.06 seconds
Started Jun 21 07:04:54 PM PDT 24
Finished Jun 21 07:05:10 PM PDT 24
Peak memory 218916 kb
Host smart-8c6b964a-9115-4996-b78c-49cc6200e139
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3546399343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3546399343
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2961807260
Short name T554
Test name
Test status
Simulation time 29504948841 ps
CPU time 25.58 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:25 PM PDT 24
Peak memory 221260 kb
Host smart-a606d523-b9b6-4ec9-8600-7cf601e8591d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961807260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2961807260
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2184170982
Short name T894
Test name
Test status
Simulation time 659360721 ps
CPU time 3.11 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:05 PM PDT 24
Peak memory 217412 kb
Host smart-d104adad-4c4b-408d-a155-e5ecbf1c92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184170982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2184170982
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2781206652
Short name T533
Test name
Test status
Simulation time 418080028 ps
CPU time 1.32 seconds
Started Jun 21 07:04:56 PM PDT 24
Finished Jun 21 07:05:07 PM PDT 24
Peak memory 217324 kb
Host smart-402dc153-0717-4a61-a07f-aa7ec483e1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781206652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2781206652
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4079960459
Short name T446
Test name
Test status
Simulation time 114837106 ps
CPU time 0.74 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 206848 kb
Host smart-235f3bcc-1684-4354-9713-2f0f5113f7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079960459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4079960459
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2011139002
Short name T592
Test name
Test status
Simulation time 4572327024 ps
CPU time 14.52 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:05:16 PM PDT 24
Peak memory 225680 kb
Host smart-470d920b-db5b-4723-b266-d287abd6e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011139002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2011139002
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4216537619
Short name T484
Test name
Test status
Simulation time 19541785 ps
CPU time 0.7 seconds
Started Jun 21 07:04:55 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 206288 kb
Host smart-fbaadad5-f252-4796-b187-4bcc3843cc62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216537619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4216537619
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4188020981
Short name T568
Test name
Test status
Simulation time 1603894886 ps
CPU time 6.49 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:10 PM PDT 24
Peak memory 225608 kb
Host smart-445daba3-c368-40f1-8666-8d2f588019a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188020981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4188020981
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2140735640
Short name T615
Test name
Test status
Simulation time 19037206 ps
CPU time 0.86 seconds
Started Jun 21 07:04:50 PM PDT 24
Finished Jun 21 07:05:01 PM PDT 24
Peak memory 207780 kb
Host smart-bf770068-2389-4a0e-a009-cc44a9a12c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140735640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2140735640
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3416299576
Short name T206
Test name
Test status
Simulation time 25613985309 ps
CPU time 69.51 seconds
Started Jun 21 07:04:51 PM PDT 24
Finished Jun 21 07:06:11 PM PDT 24
Peak memory 265936 kb
Host smart-60e200ac-ab24-4821-ad51-915758ec993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416299576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3416299576
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1169300844
Short name T707
Test name
Test status
Simulation time 24475031741 ps
CPU time 67.07 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:06:09 PM PDT 24
Peak memory 236312 kb
Host smart-711c3269-e64b-4415-8bc5-0289ecbe674e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169300844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1169300844
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.965934730
Short name T927
Test name
Test status
Simulation time 2458708181 ps
CPU time 25.7 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:28 PM PDT 24
Peak memory 242048 kb
Host smart-f9bcc441-d13c-4d96-83ac-f78cb2500a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965934730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.965934730
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.954753708
Short name T120
Test name
Test status
Simulation time 2031607709 ps
CPU time 6.92 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:09 PM PDT 24
Peak memory 233764 kb
Host smart-65321ba3-cf17-4fa8-9de7-b26c49b8e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954753708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.954753708
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2278400427
Short name T475
Test name
Test status
Simulation time 633099438 ps
CPU time 3.4 seconds
Started Jun 21 07:04:54 PM PDT 24
Finished Jun 21 07:05:08 PM PDT 24
Peak memory 225512 kb
Host smart-9f72e2c5-fdb2-4830-9ffd-4d0d4ef85691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278400427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2278400427
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4288909427
Short name T169
Test name
Test status
Simulation time 7615314648 ps
CPU time 7.77 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:15 PM PDT 24
Peak memory 225668 kb
Host smart-928262b6-fabf-4d5e-a4b1-6e13c5441a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288909427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4288909427
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.890704650
Short name T631
Test name
Test status
Simulation time 2638187695 ps
CPU time 9.77 seconds
Started Jun 21 07:04:54 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 241476 kb
Host smart-661714cf-a97d-429c-9ff0-2ec3ccbfbc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890704650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.890704650
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2525227177
Short name T12
Test name
Test status
Simulation time 3848200634 ps
CPU time 20.05 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:22 PM PDT 24
Peak memory 221708 kb
Host smart-a9385ed9-7976-4102-b9b9-4ee056d67aa6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2525227177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2525227177
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2437925558
Short name T207
Test name
Test status
Simulation time 10537431625 ps
CPU time 127.24 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:07:09 PM PDT 24
Peak memory 266696 kb
Host smart-5e45107d-68fc-4171-be96-86bc1cbffb92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437925558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2437925558
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3886526835
Short name T806
Test name
Test status
Simulation time 807891446 ps
CPU time 11.1 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 220956 kb
Host smart-e7a7e4f7-7d76-4440-9496-81993bcd197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886526835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3886526835
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.961400831
Short name T390
Test name
Test status
Simulation time 23378644 ps
CPU time 0.78 seconds
Started Jun 21 07:04:52 PM PDT 24
Finished Jun 21 07:05:03 PM PDT 24
Peak memory 206628 kb
Host smart-76661444-ab64-453d-9212-ef1715d73679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961400831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.961400831
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.474481919
Short name T322
Test name
Test status
Simulation time 247450010 ps
CPU time 2.62 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 217400 kb
Host smart-68be3e33-8741-4857-8075-c7f0bbf555b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474481919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.474481919
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1841256824
Short name T493
Test name
Test status
Simulation time 506059254 ps
CPU time 0.93 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:04 PM PDT 24
Peak memory 206888 kb
Host smart-8028d2d1-8297-41e4-a71f-9061001ef688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841256824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1841256824
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3971554462
Short name T511
Test name
Test status
Simulation time 2006767616 ps
CPU time 9.13 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:12 PM PDT 24
Peak memory 225484 kb
Host smart-c65834e6-4f4e-4a40-baef-f47734866011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971554462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3971554462
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3498070523
Short name T467
Test name
Test status
Simulation time 31889081 ps
CPU time 0.69 seconds
Started Jun 21 07:05:05 PM PDT 24
Finished Jun 21 07:05:15 PM PDT 24
Peak memory 205716 kb
Host smart-4c3cdb31-fea6-40cd-9671-a53c38d1d602
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498070523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3498070523
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1439430971
Short name T45
Test name
Test status
Simulation time 453110797 ps
CPU time 6.65 seconds
Started Jun 21 07:05:02 PM PDT 24
Finished Jun 21 07:05:18 PM PDT 24
Peak memory 225596 kb
Host smart-1c09b86f-c803-46da-aaa7-b99dac25c44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439430971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1439430971
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.472594822
Short name T643
Test name
Test status
Simulation time 14758560 ps
CPU time 0.76 seconds
Started Jun 21 07:04:55 PM PDT 24
Finished Jun 21 07:05:06 PM PDT 24
Peak memory 206500 kb
Host smart-656faab1-57e9-4211-9223-ad39010de1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472594822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.472594822
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1800884160
Short name T450
Test name
Test status
Simulation time 11867022 ps
CPU time 0.76 seconds
Started Jun 21 07:05:01 PM PDT 24
Finished Jun 21 07:05:12 PM PDT 24
Peak memory 216852 kb
Host smart-d0253e8e-5059-492f-9982-788ce707b5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800884160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1800884160
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4111568636
Short name T171
Test name
Test status
Simulation time 28065168307 ps
CPU time 161.54 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:07:53 PM PDT 24
Peak memory 253636 kb
Host smart-b9e31c63-984d-42dd-991e-beabdf72057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111568636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4111568636
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.887729367
Short name T808
Test name
Test status
Simulation time 8527621100 ps
CPU time 40.47 seconds
Started Jun 21 07:05:04 PM PDT 24
Finished Jun 21 07:05:53 PM PDT 24
Peak memory 233948 kb
Host smart-22aa22fa-e678-498b-8afd-b805ab0cf8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887729367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.887729367
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.863193711
Short name T812
Test name
Test status
Simulation time 310271393 ps
CPU time 2.12 seconds
Started Jun 21 07:05:04 PM PDT 24
Finished Jun 21 07:05:15 PM PDT 24
Peak memory 225488 kb
Host smart-464e6bff-a752-43b3-ad2a-a047c588c728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863193711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.863193711
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.897058826
Short name T522
Test name
Test status
Simulation time 1166421533 ps
CPU time 14.74 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:24 PM PDT 24
Peak memory 236160 kb
Host smart-2082eb68-2434-4f79-906b-cf37d61de681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897058826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.897058826
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4132292235
Short name T686
Test name
Test status
Simulation time 11351373411 ps
CPU time 10.4 seconds
Started Jun 21 07:05:00 PM PDT 24
Finished Jun 21 07:05:20 PM PDT 24
Peak memory 233888 kb
Host smart-4b56289d-4e40-46ad-b5ed-45fa7450d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132292235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4132292235
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3495058339
Short name T781
Test name
Test status
Simulation time 69921617995 ps
CPU time 17.51 seconds
Started Jun 21 07:05:04 PM PDT 24
Finished Jun 21 07:05:31 PM PDT 24
Peak memory 241700 kb
Host smart-25c8dcd9-0e6c-4a04-a8c9-9e645a086fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495058339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3495058339
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.502626022
Short name T527
Test name
Test status
Simulation time 826618546 ps
CPU time 10.1 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:19 PM PDT 24
Peak memory 219792 kb
Host smart-5bb2e05e-b780-4a03-b8c9-1645e859e21c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=502626022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.502626022
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.370725935
Short name T489
Test name
Test status
Simulation time 7958702928 ps
CPU time 64.61 seconds
Started Jun 21 07:05:05 PM PDT 24
Finished Jun 21 07:06:19 PM PDT 24
Peak memory 252844 kb
Host smart-cb3468ec-f535-4792-aff1-6c3f40dc61cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370725935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.370725935
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.936641561
Short name T11
Test name
Test status
Simulation time 8705482735 ps
CPU time 22.1 seconds
Started Jun 21 07:05:06 PM PDT 24
Finished Jun 21 07:05:37 PM PDT 24
Peak memory 217500 kb
Host smart-ef40057e-3fb7-43af-bb9c-aaa751e01daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936641561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.936641561
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2301202969
Short name T850
Test name
Test status
Simulation time 1124188266 ps
CPU time 4.19 seconds
Started Jun 21 07:04:53 PM PDT 24
Finished Jun 21 07:05:07 PM PDT 24
Peak memory 217408 kb
Host smart-1879a88b-3c46-498e-873d-caf1bca08bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301202969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2301202969
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3648103287
Short name T722
Test name
Test status
Simulation time 42151547 ps
CPU time 0.7 seconds
Started Jun 21 07:05:01 PM PDT 24
Finished Jun 21 07:05:11 PM PDT 24
Peak memory 206548 kb
Host smart-bc6d4abc-21f7-40ce-8085-dd313c6787da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648103287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3648103287
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3014151724
Short name T976
Test name
Test status
Simulation time 70805839 ps
CPU time 0.87 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:13 PM PDT 24
Peak memory 206892 kb
Host smart-e76319a0-72b4-4475-a938-50ce62f0f31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014151724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3014151724
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3871574130
Short name T853
Test name
Test status
Simulation time 17292984245 ps
CPU time 13.19 seconds
Started Jun 21 07:05:02 PM PDT 24
Finished Jun 21 07:05:24 PM PDT 24
Peak memory 252724 kb
Host smart-3b7d52dc-9073-4e2f-950e-e5e73482cf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871574130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3871574130
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2798570197
Short name T434
Test name
Test status
Simulation time 52135965 ps
CPU time 0.74 seconds
Started Jun 21 07:05:00 PM PDT 24
Finished Jun 21 07:05:10 PM PDT 24
Peak memory 205748 kb
Host smart-44c5c8d2-4ffd-4793-92fd-320785ecef4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798570197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2798570197
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2716958903
Short name T690
Test name
Test status
Simulation time 5093649044 ps
CPU time 14.45 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:24 PM PDT 24
Peak memory 225700 kb
Host smart-054aafcd-eeeb-4118-8208-7cbf370425c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716958903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2716958903
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3396860447
Short name T348
Test name
Test status
Simulation time 14151365 ps
CPU time 0.82 seconds
Started Jun 21 07:05:06 PM PDT 24
Finished Jun 21 07:05:15 PM PDT 24
Peak memory 207496 kb
Host smart-49155ecc-acd4-4137-96af-a7ae1569dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396860447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3396860447
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2480056006
Short name T197
Test name
Test status
Simulation time 293692611201 ps
CPU time 499.61 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:13:29 PM PDT 24
Peak memory 266500 kb
Host smart-c99a48f3-7820-4298-bcef-547314c8cee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480056006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2480056006
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2140009654
Short name T41
Test name
Test status
Simulation time 223621823425 ps
CPU time 525.62 seconds
Started Jun 21 07:05:06 PM PDT 24
Finished Jun 21 07:14:00 PM PDT 24
Peak memory 266740 kb
Host smart-93e9dbb5-786d-4c63-a325-c6c4bb1a93ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140009654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2140009654
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3544037093
Short name T264
Test name
Test status
Simulation time 4258861727 ps
CPU time 77.61 seconds
Started Jun 21 07:05:01 PM PDT 24
Finished Jun 21 07:06:28 PM PDT 24
Peak memory 257748 kb
Host smart-5b891b31-88a9-479c-a9a8-0ffc3ebabac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544037093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3544037093
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3221223629
Short name T536
Test name
Test status
Simulation time 3807413839 ps
CPU time 15.44 seconds
Started Jun 21 07:05:00 PM PDT 24
Finished Jun 21 07:05:25 PM PDT 24
Peak memory 225636 kb
Host smart-2fc8892c-90b7-43b1-8d93-414c3484823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221223629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3221223629
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1064601505
Short name T497
Test name
Test status
Simulation time 2058131827 ps
CPU time 7.26 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:16 PM PDT 24
Peak memory 225520 kb
Host smart-5547d870-de13-4787-b49b-d8e4a217a49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064601505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1064601505
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2969404082
Short name T855
Test name
Test status
Simulation time 18830700544 ps
CPU time 86.11 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:06:38 PM PDT 24
Peak memory 225636 kb
Host smart-4f64e8e1-541f-4a07-b1ac-55dc9137f14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969404082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2969404082
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4005696483
Short name T866
Test name
Test status
Simulation time 34485336 ps
CPU time 2.41 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 233524 kb
Host smart-42532588-8ae5-41ad-89bb-ee05c64fd78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005696483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4005696483
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4262485543
Short name T617
Test name
Test status
Simulation time 2591888392 ps
CPU time 9.77 seconds
Started Jun 21 07:05:00 PM PDT 24
Finished Jun 21 07:05:19 PM PDT 24
Peak memory 233880 kb
Host smart-019c4801-d0e4-4eac-b829-70dbee3adba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262485543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4262485543
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.558129944
Short name T793
Test name
Test status
Simulation time 5440734727 ps
CPU time 6.65 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:18 PM PDT 24
Peak memory 224252 kb
Host smart-153cb189-3252-4654-9491-da301a2f57d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=558129944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.558129944
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.425957138
Short name T195
Test name
Test status
Simulation time 3980414868 ps
CPU time 22.64 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:35 PM PDT 24
Peak memory 225680 kb
Host smart-eeb077f8-ae52-4c2e-a91f-b821282afcc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425957138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.425957138
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4101590096
Short name T893
Test name
Test status
Simulation time 3953098476 ps
CPU time 22.75 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:35 PM PDT 24
Peak memory 217592 kb
Host smart-76a89660-9b1e-4068-aaea-96b8a3cadaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101590096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4101590096
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3216723960
Short name T889
Test name
Test status
Simulation time 3335196230 ps
CPU time 4.11 seconds
Started Jun 21 07:05:01 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 217536 kb
Host smart-cf5c8754-dd82-4df4-9096-c3d70713d282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216723960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3216723960
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.222449477
Short name T627
Test name
Test status
Simulation time 60775979 ps
CPU time 0.83 seconds
Started Jun 21 07:05:05 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 206904 kb
Host smart-f8f73a4d-9ed5-4b15-891f-43de1a0933b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222449477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.222449477
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2220298976
Short name T937
Test name
Test status
Simulation time 31242393 ps
CPU time 0.84 seconds
Started Jun 21 07:04:58 PM PDT 24
Finished Jun 21 07:05:09 PM PDT 24
Peak memory 207144 kb
Host smart-58a59585-e992-4744-a3cf-852aa9b4028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220298976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2220298976
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4281912722
Short name T269
Test name
Test status
Simulation time 15115419697 ps
CPU time 22.24 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:34 PM PDT 24
Peak memory 225580 kb
Host smart-9fc01207-b27a-42b6-99a1-9c47bc4130e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281912722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4281912722
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2966262935
Short name T841
Test name
Test status
Simulation time 22872012 ps
CPU time 0.77 seconds
Started Jun 21 07:05:01 PM PDT 24
Finished Jun 21 07:05:12 PM PDT 24
Peak memory 205736 kb
Host smart-6ea538ab-af3e-451a-9433-cfa5e87ad1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966262935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2966262935
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2661514770
Short name T704
Test name
Test status
Simulation time 133248441 ps
CPU time 2.35 seconds
Started Jun 21 07:05:02 PM PDT 24
Finished Jun 21 07:05:13 PM PDT 24
Peak memory 233760 kb
Host smart-83faeb1e-f112-43a9-be7c-a30d57d5bc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661514770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2661514770
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2378384124
Short name T941
Test name
Test status
Simulation time 19044401 ps
CPU time 0.74 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:13 PM PDT 24
Peak memory 206484 kb
Host smart-216eb469-0744-496e-9d0b-c87156570e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378384124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2378384124
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.126606506
Short name T408
Test name
Test status
Simulation time 168466126 ps
CPU time 0.9 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:12 PM PDT 24
Peak memory 217108 kb
Host smart-80f4886b-83db-4f93-b459-6d1973dddf2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126606506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.126606506
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2491153715
Short name T973
Test name
Test status
Simulation time 8011725282 ps
CPU time 113.5 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:07:01 PM PDT 24
Peak memory 272000 kb
Host smart-c2bca2ce-fd1c-4dbf-9057-0580966fe27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491153715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2491153715
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.185144068
Short name T811
Test name
Test status
Simulation time 50643248314 ps
CPU time 496.05 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:13:28 PM PDT 24
Peak memory 258528 kb
Host smart-61951e68-6ab6-4648-88ec-a89897ef7c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185144068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.185144068
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2161177206
Short name T667
Test name
Test status
Simulation time 151781697 ps
CPU time 3.47 seconds
Started Jun 21 07:05:06 PM PDT 24
Finished Jun 21 07:05:18 PM PDT 24
Peak memory 233668 kb
Host smart-ee12561e-8c6b-424c-bd8b-6bb270214b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161177206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2161177206
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3937997436
Short name T700
Test name
Test status
Simulation time 152526835 ps
CPU time 4.94 seconds
Started Jun 21 07:05:00 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 233788 kb
Host smart-69f641c9-e927-4fca-97e0-9d6d0a087818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937997436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3937997436
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.925273791
Short name T801
Test name
Test status
Simulation time 8180926228 ps
CPU time 31.48 seconds
Started Jun 21 07:05:02 PM PDT 24
Finished Jun 21 07:05:42 PM PDT 24
Peak memory 233896 kb
Host smart-340474c3-5db3-40d2-a308-8b1a2954fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925273791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.925273791
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2534656102
Short name T778
Test name
Test status
Simulation time 4396763416 ps
CPU time 8.23 seconds
Started Jun 21 07:05:06 PM PDT 24
Finished Jun 21 07:05:23 PM PDT 24
Peak memory 241668 kb
Host smart-25c4966d-5e15-4f32-b0d0-2f4db1f63948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534656102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2534656102
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2688984525
Short name T656
Test name
Test status
Simulation time 31240649 ps
CPU time 2.22 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:10 PM PDT 24
Peak memory 233540 kb
Host smart-805f98d3-be31-4e0b-b9bb-651efa4c9d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688984525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2688984525
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4052593447
Short name T388
Test name
Test status
Simulation time 1370878894 ps
CPU time 5.23 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 222924 kb
Host smart-f65e611f-80e1-4458-b7aa-66995c9b9045
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4052593447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4052593447
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.73896641
Short name T705
Test name
Test status
Simulation time 18190597262 ps
CPU time 112.42 seconds
Started Jun 21 07:05:02 PM PDT 24
Finished Jun 21 07:07:03 PM PDT 24
Peak memory 254572 kb
Host smart-075f39d6-98c7-4eb0-ae06-dd735f1bab0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73896641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress
_all.73896641
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1755850028
Short name T545
Test name
Test status
Simulation time 16645794532 ps
CPU time 10.21 seconds
Started Jun 21 07:05:00 PM PDT 24
Finished Jun 21 07:05:20 PM PDT 24
Peak memory 220812 kb
Host smart-7064084d-3eab-47a0-8910-be898e4302da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755850028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1755850028
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2655616086
Short name T482
Test name
Test status
Simulation time 5219611024 ps
CPU time 14.17 seconds
Started Jun 21 07:05:04 PM PDT 24
Finished Jun 21 07:05:27 PM PDT 24
Peak memory 217528 kb
Host smart-e4ab1e83-e308-4a25-ac64-eaf638833f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655616086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2655616086
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1671002307
Short name T754
Test name
Test status
Simulation time 15100650 ps
CPU time 0.7 seconds
Started Jun 21 07:05:04 PM PDT 24
Finished Jun 21 07:05:14 PM PDT 24
Peak memory 206536 kb
Host smart-c8c53a3b-5409-47cc-8a47-27bb794e89b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671002307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1671002307
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2083935349
Short name T613
Test name
Test status
Simulation time 98145688 ps
CPU time 0.8 seconds
Started Jun 21 07:05:05 PM PDT 24
Finished Jun 21 07:05:15 PM PDT 24
Peak memory 206876 kb
Host smart-a94023a2-370c-473b-8d1e-e846ede27c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083935349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2083935349
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.654814365
Short name T698
Test name
Test status
Simulation time 863576017 ps
CPU time 8.05 seconds
Started Jun 21 07:05:05 PM PDT 24
Finished Jun 21 07:05:22 PM PDT 24
Peak memory 225536 kb
Host smart-430cf561-56fe-4ede-b12b-f4b47fbc386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654814365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.654814365
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.839948786
Short name T538
Test name
Test status
Simulation time 14656388 ps
CPU time 0.71 seconds
Started Jun 21 07:05:15 PM PDT 24
Finished Jun 21 07:05:21 PM PDT 24
Peak memory 206708 kb
Host smart-9ae54816-97b2-410f-8e58-9a7e94b9bc29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839948786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.839948786
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.520776847
Short name T65
Test name
Test status
Simulation time 179388091 ps
CPU time 3.62 seconds
Started Jun 21 07:05:14 PM PDT 24
Finished Jun 21 07:05:23 PM PDT 24
Peak memory 225600 kb
Host smart-8ae51ee6-430e-400a-a7d8-fc19638dad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520776847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.520776847
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.887697207
Short name T776
Test name
Test status
Simulation time 17356867 ps
CPU time 0.8 seconds
Started Jun 21 07:05:00 PM PDT 24
Finished Jun 21 07:05:10 PM PDT 24
Peak memory 207608 kb
Host smart-6c285eb3-0d05-4c05-b4bb-ea7e223fc7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887697207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.887697207
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.804346814
Short name T821
Test name
Test status
Simulation time 25065899666 ps
CPU time 85.8 seconds
Started Jun 21 07:05:15 PM PDT 24
Finished Jun 21 07:06:46 PM PDT 24
Peak memory 254096 kb
Host smart-8c59ef75-08b9-4c1a-a9d4-2f71545716a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804346814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.804346814
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2541720203
Short name T950
Test name
Test status
Simulation time 68182407090 ps
CPU time 85.25 seconds
Started Jun 21 07:05:15 PM PDT 24
Finished Jun 21 07:06:45 PM PDT 24
Peak memory 252948 kb
Host smart-4db61131-fb81-43ec-a647-c6beeb487251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541720203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2541720203
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2473785999
Short name T890
Test name
Test status
Simulation time 105943666814 ps
CPU time 272.94 seconds
Started Jun 21 07:05:15 PM PDT 24
Finished Jun 21 07:09:53 PM PDT 24
Peak memory 266120 kb
Host smart-2b90d398-a02e-4e3b-8942-20f40a90e2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473785999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2473785999
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1615378661
Short name T885
Test name
Test status
Simulation time 884847905 ps
CPU time 15.32 seconds
Started Jun 21 07:05:13 PM PDT 24
Finished Jun 21 07:05:35 PM PDT 24
Peak memory 241952 kb
Host smart-4dbf3759-78b7-4369-8c67-b2e636578949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615378661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1615378661
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.163044423
Short name T702
Test name
Test status
Simulation time 867464305 ps
CPU time 5.58 seconds
Started Jun 21 07:05:06 PM PDT 24
Finished Jun 21 07:05:20 PM PDT 24
Peak memory 225524 kb
Host smart-d3da42dc-25a4-4e94-8748-c5b320c469dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163044423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.163044423
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.461377797
Short name T175
Test name
Test status
Simulation time 901775159 ps
CPU time 10.47 seconds
Started Jun 21 07:05:13 PM PDT 24
Finished Jun 21 07:05:29 PM PDT 24
Peak memory 233716 kb
Host smart-dd81f749-7651-4c40-969f-0eb530056ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461377797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.461377797
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3033365455
Short name T971
Test name
Test status
Simulation time 74354733 ps
CPU time 2.16 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:15 PM PDT 24
Peak memory 224016 kb
Host smart-410a5683-9d62-4a32-956b-cce77ece1145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033365455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3033365455
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2572171274
Short name T397
Test name
Test status
Simulation time 2160516234 ps
CPU time 7.72 seconds
Started Jun 21 07:05:04 PM PDT 24
Finished Jun 21 07:05:21 PM PDT 24
Peak memory 242024 kb
Host smart-a4bba727-82c0-445c-a86c-d769b89ab553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572171274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2572171274
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.960531481
Short name T378
Test name
Test status
Simulation time 151527500 ps
CPU time 4.29 seconds
Started Jun 21 07:05:16 PM PDT 24
Finished Jun 21 07:05:25 PM PDT 24
Peak memory 224192 kb
Host smart-74cde9f8-ee42-44d6-a062-93e453350280
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=960531481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.960531481
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.500025328
Short name T143
Test name
Test status
Simulation time 369287582154 ps
CPU time 928.83 seconds
Started Jun 21 07:05:14 PM PDT 24
Finished Jun 21 07:20:49 PM PDT 24
Peak memory 290596 kb
Host smart-2288acac-d007-4127-b8ef-f00a3c47d148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500025328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.500025328
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3094141798
Short name T567
Test name
Test status
Simulation time 16432481923 ps
CPU time 21.73 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:34 PM PDT 24
Peak memory 217448 kb
Host smart-f3f0dc2f-3434-4250-8004-deb597c9fe34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094141798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3094141798
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1606320251
Short name T649
Test name
Test status
Simulation time 858347569 ps
CPU time 4.03 seconds
Started Jun 21 07:04:59 PM PDT 24
Finished Jun 21 07:05:12 PM PDT 24
Peak memory 217368 kb
Host smart-8e0d8eda-1e13-4a0e-81aa-d435f4088825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606320251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1606320251
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3611182395
Short name T352
Test name
Test status
Simulation time 47581697 ps
CPU time 0.98 seconds
Started Jun 21 07:05:06 PM PDT 24
Finished Jun 21 07:05:16 PM PDT 24
Peak memory 209004 kb
Host smart-82c6d45a-30c3-4888-8b8a-09c358e161e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611182395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3611182395
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3134673658
Short name T736
Test name
Test status
Simulation time 85730403 ps
CPU time 0.78 seconds
Started Jun 21 07:05:03 PM PDT 24
Finished Jun 21 07:05:12 PM PDT 24
Peak memory 206896 kb
Host smart-f1972c74-2f3a-49ba-bcca-30ddd2a0b893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134673658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3134673658
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2955666757
Short name T338
Test name
Test status
Simulation time 20243212881 ps
CPU time 12.22 seconds
Started Jun 21 07:05:13 PM PDT 24
Finished Jun 21 07:05:31 PM PDT 24
Peak memory 233868 kb
Host smart-688de11e-16f3-4976-b3e9-a43bbf7be9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955666757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2955666757
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.238869607
Short name T962
Test name
Test status
Simulation time 11963573 ps
CPU time 0.75 seconds
Started Jun 21 07:02:46 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 205840 kb
Host smart-434fb3a4-efee-4a92-b535-fa5e00e7215b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238869607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.238869607
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3556416467
Short name T895
Test name
Test status
Simulation time 466904051 ps
CPU time 2.92 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:02:55 PM PDT 24
Peak memory 225640 kb
Host smart-1ef777b3-b85f-481f-8051-9bac86bd36ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556416467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3556416467
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1312303571
Short name T865
Test name
Test status
Simulation time 16511694 ps
CPU time 0.75 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:44 PM PDT 24
Peak memory 206520 kb
Host smart-ce5c6ed7-f801-4cdc-bb60-f9abdbe4ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312303571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1312303571
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3627304938
Short name T158
Test name
Test status
Simulation time 4223607247 ps
CPU time 17.66 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:03:07 PM PDT 24
Peak memory 250300 kb
Host smart-908d5e42-eb91-41f4-a4fc-78e08221bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627304938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3627304938
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.632770246
Short name T723
Test name
Test status
Simulation time 710948916 ps
CPU time 6.47 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:02:56 PM PDT 24
Peak memory 218512 kb
Host smart-217c3626-386f-49df-bbc3-cd85d6d9c357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632770246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.632770246
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.124766549
Short name T809
Test name
Test status
Simulation time 1632390724 ps
CPU time 12.81 seconds
Started Jun 21 07:02:42 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 225604 kb
Host smart-a812ec6b-352f-4977-bc25-764f3f551417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124766549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
124766549
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.927573554
Short name T706
Test name
Test status
Simulation time 249643856 ps
CPU time 6.73 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:02:56 PM PDT 24
Peak memory 233812 kb
Host smart-ed5ab8a2-2dc7-4030-9fdf-f9e2a2822fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927573554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.927573554
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3390983753
Short name T788
Test name
Test status
Simulation time 477554659 ps
CPU time 4.52 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:02:45 PM PDT 24
Peak memory 225600 kb
Host smart-9c7a81fe-b113-41db-ab2c-f6b13c332322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390983753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3390983753
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.260622427
Short name T252
Test name
Test status
Simulation time 863105597 ps
CPU time 6.6 seconds
Started Jun 21 07:02:36 PM PDT 24
Finished Jun 21 07:02:48 PM PDT 24
Peak memory 225592 kb
Host smart-96f4fc71-31e7-404b-bbbe-2b9b0cb87c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260622427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.260622427
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2969512557
Short name T970
Test name
Test status
Simulation time 47832858 ps
CPU time 1.03 seconds
Started Jun 21 07:02:35 PM PDT 24
Finished Jun 21 07:02:41 PM PDT 24
Peak memory 218876 kb
Host smart-ac63da59-2f0c-486a-b87b-f2cc752784bc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969512557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2969512557
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.434690622
Short name T257
Test name
Test status
Simulation time 45558962395 ps
CPU time 26.65 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 241964 kb
Host smart-4c8e5157-a381-4cc9-8bde-ad7185067838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434690622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.434690622
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2816870303
Short name T326
Test name
Test status
Simulation time 961890884 ps
CPU time 6.01 seconds
Started Jun 21 07:02:50 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 223236 kb
Host smart-29bb5254-5ff2-4f00-b208-b5b1599b7ba1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2816870303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2816870303
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2685092428
Short name T729
Test name
Test status
Simulation time 767338477 ps
CPU time 6.62 seconds
Started Jun 21 07:02:38 PM PDT 24
Finished Jun 21 07:02:50 PM PDT 24
Peak memory 219340 kb
Host smart-a2914a6d-2aba-4cd7-b4d8-74948bef17c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685092428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2685092428
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.167912853
Short name T373
Test name
Test status
Simulation time 20550798 ps
CPU time 0.7 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:43 PM PDT 24
Peak memory 206604 kb
Host smart-619e38a4-577b-4b01-a135-8d35cb4ab974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167912853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.167912853
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3613937204
Short name T972
Test name
Test status
Simulation time 394845768 ps
CPU time 2.14 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:02:49 PM PDT 24
Peak memory 217360 kb
Host smart-0ae4fcf0-c90b-4a4e-9ef7-a1bfb90f06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613937204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3613937204
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.458026953
Short name T771
Test name
Test status
Simulation time 129639360 ps
CPU time 0.89 seconds
Started Jun 21 07:02:37 PM PDT 24
Finished Jun 21 07:02:43 PM PDT 24
Peak memory 207024 kb
Host smart-ed396e35-156e-4103-8d8a-8c80bbf316e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458026953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.458026953
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2030474044
Short name T731
Test name
Test status
Simulation time 38580972247 ps
CPU time 26.45 seconds
Started Jun 21 07:02:40 PM PDT 24
Finished Jun 21 07:03:13 PM PDT 24
Peak memory 225632 kb
Host smart-af757653-0b19-4d0c-8b54-e39929f16537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030474044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2030474044
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3355846340
Short name T451
Test name
Test status
Simulation time 31828508 ps
CPU time 0.71 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:02:50 PM PDT 24
Peak memory 206296 kb
Host smart-a12978bf-a748-45d6-b184-2fcd31f7766d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355846340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
355846340
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3602792400
Short name T734
Test name
Test status
Simulation time 162121213 ps
CPU time 2.34 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:53 PM PDT 24
Peak memory 225580 kb
Host smart-29139c3b-9162-4c88-a1e4-4cd738b9e63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602792400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3602792400
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3354122651
Short name T438
Test name
Test status
Simulation time 132359958 ps
CPU time 0.77 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:02:50 PM PDT 24
Peak memory 207840 kb
Host smart-e5023d17-7a38-41cc-b951-3374d1f10361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354122651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3354122651
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1381513107
Short name T816
Test name
Test status
Simulation time 15419770963 ps
CPU time 57.55 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:03:48 PM PDT 24
Peak memory 250224 kb
Host smart-88cec7a6-ce0f-4bc3-82f0-0b44e8ca1d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381513107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1381513107
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2383355971
Short name T857
Test name
Test status
Simulation time 75409749767 ps
CPU time 102.32 seconds
Started Jun 21 07:02:43 PM PDT 24
Finished Jun 21 07:04:31 PM PDT 24
Peak memory 242076 kb
Host smart-2918c07e-91cf-4876-9804-65e4f8afd184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383355971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2383355971
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2216714811
Short name T184
Test name
Test status
Simulation time 37126710425 ps
CPU time 83.62 seconds
Started Jun 21 07:02:46 PM PDT 24
Finished Jun 21 07:04:15 PM PDT 24
Peak memory 242072 kb
Host smart-9d270001-1148-4899-8d3c-9d792cbc1410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216714811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2216714811
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1420120233
Short name T596
Test name
Test status
Simulation time 1224774698 ps
CPU time 7.01 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:03:00 PM PDT 24
Peak memory 225584 kb
Host smart-cc190df5-4d82-43ed-b609-73de7492dff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420120233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1420120233
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4092812266
Short name T582
Test name
Test status
Simulation time 339602421 ps
CPU time 5.16 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 233772 kb
Host smart-ad6f1acb-34f8-4cf0-8b9d-fe1634a0a98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092812266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4092812266
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1127581699
Short name T693
Test name
Test status
Simulation time 11503213051 ps
CPU time 12.11 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:03:05 PM PDT 24
Peak memory 225628 kb
Host smart-9b91e6a5-044c-4678-9b0f-d6a11efdf530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127581699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1127581699
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3938378699
Short name T32
Test name
Test status
Simulation time 55942240 ps
CPU time 1.13 seconds
Started Jun 21 07:02:51 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 217588 kb
Host smart-5b4cdcf1-50a2-4cf7-97e1-3e18d5c7c75b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938378699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3938378699
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3570223061
Short name T228
Test name
Test status
Simulation time 12497463439 ps
CPU time 12.05 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:03:03 PM PDT 24
Peak memory 233828 kb
Host smart-d691ab19-448c-4254-a81f-ceb033034fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570223061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3570223061
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2271121970
Short name T270
Test name
Test status
Simulation time 12771631971 ps
CPU time 20.39 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:03:10 PM PDT 24
Peak memory 233864 kb
Host smart-62ddce4f-6b87-40af-a9f4-7bfd15bb8479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271121970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2271121970
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2002826066
Short name T732
Test name
Test status
Simulation time 1387488944 ps
CPU time 7.36 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 223652 kb
Host smart-9590ae51-90af-4536-8ba8-b487a00e4362
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2002826066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2002826066
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1640168703
Short name T144
Test name
Test status
Simulation time 17886544419 ps
CPU time 65.14 seconds
Started Jun 21 07:02:43 PM PDT 24
Finished Jun 21 07:03:54 PM PDT 24
Peak memory 242152 kb
Host smart-fb7d6f0a-2bb6-4168-a97e-e415f9853eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640168703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1640168703
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.49323751
Short name T369
Test name
Test status
Simulation time 321077766 ps
CPU time 3.12 seconds
Started Jun 21 07:02:49 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 217532 kb
Host smart-98f16f91-d920-4c4e-b6a7-8495b9a9efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49323751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.49323751
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3404079619
Short name T72
Test name
Test status
Simulation time 300128261 ps
CPU time 2.12 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:02:55 PM PDT 24
Peak memory 208896 kb
Host smart-539be27f-b89a-456e-8b5f-e7c4fcbae5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404079619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3404079619
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2611169513
Short name T721
Test name
Test status
Simulation time 153170751 ps
CPU time 1.82 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 217252 kb
Host smart-fc79f9cf-f40a-47dd-ac35-061a55769e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611169513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2611169513
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.4042889474
Short name T579
Test name
Test status
Simulation time 38028305 ps
CPU time 0.86 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 206920 kb
Host smart-5c8ff62b-c0c7-4623-8049-f7f43451dedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042889474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.4042889474
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1905689354
Short name T194
Test name
Test status
Simulation time 20416071251 ps
CPU time 15 seconds
Started Jun 21 07:02:46 PM PDT 24
Finished Jun 21 07:03:06 PM PDT 24
Peak memory 233836 kb
Host smart-e1392cc3-c16d-46d8-900d-ec19939ec177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905689354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1905689354
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1541140910
Short name T679
Test name
Test status
Simulation time 18022739 ps
CPU time 0.73 seconds
Started Jun 21 07:02:51 PM PDT 24
Finished Jun 21 07:02:57 PM PDT 24
Peak memory 206588 kb
Host smart-e086f5df-7898-4980-9f04-fce137105367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541140910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
541140910
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1204870051
Short name T319
Test name
Test status
Simulation time 2098271344 ps
CPU time 5.66 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:02:55 PM PDT 24
Peak memory 233712 kb
Host smart-cde5a2f4-5ad8-490d-9e01-d53f6d6a89db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204870051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1204870051
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.864897084
Short name T891
Test name
Test status
Simulation time 18680644 ps
CPU time 0.78 seconds
Started Jun 21 07:02:43 PM PDT 24
Finished Jun 21 07:02:49 PM PDT 24
Peak memory 206460 kb
Host smart-a7880d0c-3f2c-41c3-8cfd-d5d61bb47fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864897084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.864897084
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3589517717
Short name T218
Test name
Test status
Simulation time 193903427766 ps
CPU time 121.06 seconds
Started Jun 21 07:02:43 PM PDT 24
Finished Jun 21 07:04:50 PM PDT 24
Peak memory 250304 kb
Host smart-42c86be1-77f7-4601-9fff-f7524a3b8003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589517717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3589517717
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1800632158
Short name T9
Test name
Test status
Simulation time 291818844012 ps
CPU time 165.45 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:05:38 PM PDT 24
Peak memory 251156 kb
Host smart-0edd8db8-493e-43d7-8c82-4bb80885afaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800632158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1800632158
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3704574986
Short name T960
Test name
Test status
Simulation time 15246744855 ps
CPU time 97.08 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:04:30 PM PDT 24
Peak memory 266512 kb
Host smart-3fe0c321-16dd-4d62-9437-f8e1dfcd8f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704574986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3704574986
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1167954020
Short name T924
Test name
Test status
Simulation time 1347810845 ps
CPU time 15.55 seconds
Started Jun 21 07:02:43 PM PDT 24
Finished Jun 21 07:03:05 PM PDT 24
Peak memory 233832 kb
Host smart-afc6b056-7560-4298-b9d6-4398d63667f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167954020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1167954020
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2340858797
Short name T786
Test name
Test status
Simulation time 789625078 ps
CPU time 7.22 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:03:00 PM PDT 24
Peak memory 233788 kb
Host smart-14509f6e-5366-47f4-94f0-b0b6ddd51c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340858797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2340858797
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2161098252
Short name T359
Test name
Test status
Simulation time 2877765987 ps
CPU time 30.5 seconds
Started Jun 21 07:02:47 PM PDT 24
Finished Jun 21 07:03:23 PM PDT 24
Peak memory 233864 kb
Host smart-07f44f6e-116a-46c5-9c8e-b561de078e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161098252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2161098252
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2979341722
Short name T551
Test name
Test status
Simulation time 25186832 ps
CPU time 1.02 seconds
Started Jun 21 07:02:48 PM PDT 24
Finished Jun 21 07:02:55 PM PDT 24
Peak memory 217588 kb
Host smart-ed8dddbd-c12a-4282-b7e3-8809f8cb33b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979341722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2979341722
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3604055575
Short name T713
Test name
Test status
Simulation time 9565724976 ps
CPU time 7.79 seconds
Started Jun 21 07:02:49 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 233828 kb
Host smart-31c5f61a-109f-41ca-adb3-e1d4897578a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604055575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3604055575
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2509838047
Short name T537
Test name
Test status
Simulation time 35409862 ps
CPU time 2.35 seconds
Started Jun 21 07:02:44 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 233500 kb
Host smart-7d396935-1258-4895-8752-4b9c5d501e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509838047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2509838047
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3141389271
Short name T379
Test name
Test status
Simulation time 696511185 ps
CPU time 6.95 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 219852 kb
Host smart-724b1a0a-a4fe-429e-9db1-76ba7ac038f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3141389271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3141389271
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.40195080
Short name T942
Test name
Test status
Simulation time 1876934369 ps
CPU time 43.62 seconds
Started Jun 21 07:02:42 PM PDT 24
Finished Jun 21 07:03:32 PM PDT 24
Peak memory 250228 kb
Host smart-afb85463-a7e3-4d52-8942-75c9f6680050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_
all.40195080
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.487131313
Short name T980
Test name
Test status
Simulation time 14872696 ps
CPU time 0.71 seconds
Started Jun 21 07:02:43 PM PDT 24
Finished Jun 21 07:02:49 PM PDT 24
Peak memory 206640 kb
Host smart-ae8ecd24-f362-4ffc-b938-69396c3475ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487131313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.487131313
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4153692414
Short name T457
Test name
Test status
Simulation time 907207744 ps
CPU time 4.06 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:55 PM PDT 24
Peak memory 217296 kb
Host smart-0e67f44e-f7d7-4db3-9d3c-49c8eba5ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153692414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4153692414
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.169180433
Short name T814
Test name
Test status
Simulation time 15397008 ps
CPU time 0.71 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:51 PM PDT 24
Peak memory 206876 kb
Host smart-4d8e1401-ba5d-4970-b4ad-989eacac662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169180433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.169180433
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4066851750
Short name T765
Test name
Test status
Simulation time 11081868 ps
CPU time 0.69 seconds
Started Jun 21 07:02:51 PM PDT 24
Finished Jun 21 07:02:57 PM PDT 24
Peak memory 206492 kb
Host smart-b441ed16-b744-4afc-96db-e1cb0325d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066851750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4066851750
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2049687477
Short name T152
Test name
Test status
Simulation time 1238415518 ps
CPU time 6.11 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:57 PM PDT 24
Peak memory 233784 kb
Host smart-f1ed2618-b0b3-4a15-9d1c-0b7be2085edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049687477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2049687477
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.109699341
Short name T659
Test name
Test status
Simulation time 38472528 ps
CPU time 0.68 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 206280 kb
Host smart-fef7ca8e-05ae-4063-bd63-aa1576fef601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109699341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.109699341
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3458478445
Short name T556
Test name
Test status
Simulation time 97050583 ps
CPU time 2.1 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:02 PM PDT 24
Peak memory 224124 kb
Host smart-df0a547d-7ca8-4b26-8c43-0760a1d5d7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458478445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3458478445
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3395600723
Short name T367
Test name
Test status
Simulation time 76112185 ps
CPU time 0.72 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:51 PM PDT 24
Peak memory 206732 kb
Host smart-eae7aef5-029c-4a52-9b02-b1646d74cba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395600723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3395600723
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1997174744
Short name T37
Test name
Test status
Simulation time 46722908243 ps
CPU time 372.63 seconds
Started Jun 21 07:02:56 PM PDT 24
Finished Jun 21 07:09:15 PM PDT 24
Peak memory 267656 kb
Host smart-af044b73-fd5e-4c68-a7bd-94a20ee73f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997174744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1997174744
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1548114185
Short name T40
Test name
Test status
Simulation time 4907984815 ps
CPU time 79.99 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:04:19 PM PDT 24
Peak memory 250472 kb
Host smart-2dc80772-60c4-4cda-9b9b-7d43ab5cf708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548114185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1548114185
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3423750408
Short name T892
Test name
Test status
Simulation time 1961228172 ps
CPU time 29.72 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:38 PM PDT 24
Peak memory 235196 kb
Host smart-bdbaef05-981d-435d-a73b-b6d514e13133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423750408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3423750408
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2797868665
Short name T291
Test name
Test status
Simulation time 1121640818 ps
CPU time 18.7 seconds
Started Jun 21 07:02:55 PM PDT 24
Finished Jun 21 07:03:21 PM PDT 24
Peak memory 250772 kb
Host smart-5d4d7831-07a6-4a9c-962e-fdd18de03861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797868665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2797868665
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2595139658
Short name T757
Test name
Test status
Simulation time 919722368 ps
CPU time 3.92 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:03 PM PDT 24
Peak memory 233796 kb
Host smart-215f50f9-39a3-43eb-b093-abd61d846bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595139658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2595139658
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2279707287
Short name T573
Test name
Test status
Simulation time 1131435836 ps
CPU time 16.41 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:03:14 PM PDT 24
Peak memory 225508 kb
Host smart-db651f23-b6c9-44df-a3c6-839eb2e99f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279707287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2279707287
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.4274940142
Short name T30
Test name
Test status
Simulation time 16700517 ps
CPU time 1 seconds
Started Jun 21 07:02:45 PM PDT 24
Finished Jun 21 07:02:52 PM PDT 24
Peak memory 217632 kb
Host smart-21d90b64-e2d6-4474-aaad-d55071f165e3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274940142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.4274940142
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3478483406
Short name T220
Test name
Test status
Simulation time 19254172915 ps
CPU time 10.39 seconds
Started Jun 21 07:02:55 PM PDT 24
Finished Jun 21 07:03:12 PM PDT 24
Peak memory 225628 kb
Host smart-57cc4488-a9ac-4f5b-a6b8-43e73d5a2699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478483406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3478483406
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4253455012
Short name T429
Test name
Test status
Simulation time 519108060 ps
CPU time 6.72 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:07 PM PDT 24
Peak memory 241456 kb
Host smart-110dc51c-4b5e-4625-9744-8351632b81bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253455012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4253455012
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2302471969
Short name T492
Test name
Test status
Simulation time 175434093 ps
CPU time 3.52 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 220464 kb
Host smart-5f578c1e-47c3-4036-ade3-ec1b005bf7b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2302471969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2302471969
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1515934144
Short name T147
Test name
Test status
Simulation time 266637433 ps
CPU time 1.13 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:00 PM PDT 24
Peak memory 208764 kb
Host smart-55c34f44-2f1f-4d7d-9432-a7db153b2e1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515934144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1515934144
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1198844478
Short name T961
Test name
Test status
Simulation time 14631493647 ps
CPU time 24.05 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:25 PM PDT 24
Peak memory 220932 kb
Host smart-f9ae3fb8-05fa-481a-8531-2fb242db2c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198844478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1198844478
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.241780688
Short name T494
Test name
Test status
Simulation time 1292797976 ps
CPU time 3.28 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:04 PM PDT 24
Peak memory 217344 kb
Host smart-b9c39e8c-5b7b-4562-9a8c-5a33648e136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241780688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.241780688
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1823945280
Short name T578
Test name
Test status
Simulation time 386204034 ps
CPU time 5.05 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:03:03 PM PDT 24
Peak memory 217384 kb
Host smart-4a2c6dc0-3016-498f-a0db-4932ea5e70a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823945280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1823945280
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3453698723
Short name T828
Test name
Test status
Simulation time 81000550 ps
CPU time 0.73 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 206912 kb
Host smart-854bfbca-96c7-47a8-afb0-976fecf5732a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453698723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3453698723
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3929046796
Short name T803
Test name
Test status
Simulation time 398563862 ps
CPU time 6.16 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:03:04 PM PDT 24
Peak memory 225596 kb
Host smart-52bf04b6-51c3-4ba5-bca8-4f89eac906b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929046796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3929046796
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.73141473
Short name T915
Test name
Test status
Simulation time 34903631 ps
CPU time 0.68 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 206244 kb
Host smart-4f678837-ec9f-453b-b5a8-71fe5ed0707f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73141473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.73141473
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1676387101
Short name T242
Test name
Test status
Simulation time 747436628 ps
CPU time 4.28 seconds
Started Jun 21 07:02:51 PM PDT 24
Finished Jun 21 07:03:01 PM PDT 24
Peak memory 225576 kb
Host smart-f1051656-44f5-4fa0-a73f-b524c43e1e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676387101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1676387101
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1948050680
Short name T587
Test name
Test status
Simulation time 64612750 ps
CPU time 0.74 seconds
Started Jun 21 07:03:02 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 206464 kb
Host smart-ee28a3a2-faad-432a-868e-b2ccae17b0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948050680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1948050680
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4236357212
Short name T33
Test name
Test status
Simulation time 14991836249 ps
CPU time 69.93 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:04:09 PM PDT 24
Peak memory 266364 kb
Host smart-474db087-5e5d-4be6-b951-f6063ad9b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236357212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4236357212
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2990664319
Short name T714
Test name
Test status
Simulation time 10554598753 ps
CPU time 28.62 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:28 PM PDT 24
Peak memory 232756 kb
Host smart-2a680334-02fc-4392-a4d5-8d0f0ee40bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990664319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2990664319
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2989574544
Short name T837
Test name
Test status
Simulation time 2215416524 ps
CPU time 22.74 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:22 PM PDT 24
Peak memory 218552 kb
Host smart-0593f701-8a46-4aee-9960-2556b546089e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989574544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2989574544
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.113508990
Short name T284
Test name
Test status
Simulation time 3780483714 ps
CPU time 12.64 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:13 PM PDT 24
Peak memory 236452 kb
Host smart-1f9a1b63-105b-45ab-9ab2-1b70875ea7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113508990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.113508990
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3259665822
Short name T495
Test name
Test status
Simulation time 3719807347 ps
CPU time 17.44 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:16 PM PDT 24
Peak memory 233908 kb
Host smart-98bfc3bb-ac15-4da8-88bd-e4f2c9010395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259665822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3259665822
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.564613176
Short name T682
Test name
Test status
Simulation time 446302351 ps
CPU time 7.49 seconds
Started Jun 21 07:03:01 PM PDT 24
Finished Jun 21 07:03:15 PM PDT 24
Peak memory 225516 kb
Host smart-a63458f5-0f8f-4362-9f56-b51208bd41a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564613176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.564613176
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3537553851
Short name T933
Test name
Test status
Simulation time 27641696 ps
CPU time 1.02 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:00 PM PDT 24
Peak memory 217548 kb
Host smart-d27356d4-bd4d-46dd-b2e6-6f84269f4392
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537553851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3537553851
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3349741994
Short name T897
Test name
Test status
Simulation time 9232704757 ps
CPU time 12.82 seconds
Started Jun 21 07:02:50 PM PDT 24
Finished Jun 21 07:03:09 PM PDT 24
Peak memory 233836 kb
Host smart-6557ed56-dfd8-4e1b-8de2-24a01f4135dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349741994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3349741994
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1640025642
Short name T458
Test name
Test status
Simulation time 27886226049 ps
CPU time 21.55 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:03:22 PM PDT 24
Peak memory 233848 kb
Host smart-77fa88bb-f805-4e25-9c37-785698900cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640025642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1640025642
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2227607359
Short name T35
Test name
Test status
Simulation time 2058097113 ps
CPU time 9.6 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 221188 kb
Host smart-7069725d-ac58-4f5e-ac70-6604e75fc0d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2227607359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2227607359
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1820613830
Short name T212
Test name
Test status
Simulation time 12995357576 ps
CPU time 62.56 seconds
Started Jun 21 07:02:54 PM PDT 24
Finished Jun 21 07:04:03 PM PDT 24
Peak memory 250392 kb
Host smart-3e83e6a6-0fa9-4bee-80d6-b46b1d0537d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820613830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1820613830
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2003969184
Short name T861
Test name
Test status
Simulation time 14007084602 ps
CPU time 27.66 seconds
Started Jun 21 07:02:55 PM PDT 24
Finished Jun 21 07:03:29 PM PDT 24
Peak memory 217464 kb
Host smart-2f4174b9-67e2-4140-8925-b5f037d11cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003969184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2003969184
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.232162918
Short name T313
Test name
Test status
Simulation time 4779873933 ps
CPU time 13.83 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:13 PM PDT 24
Peak memory 217380 kb
Host smart-abec6303-3311-48d7-9565-cde46ad4e566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232162918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.232162918
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1491383615
Short name T435
Test name
Test status
Simulation time 76142240 ps
CPU time 1.57 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:02:59 PM PDT 24
Peak memory 217316 kb
Host smart-c5c23d92-f328-4af8-81d8-346be2e2c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491383615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1491383615
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3930608633
Short name T358
Test name
Test status
Simulation time 13848335 ps
CPU time 0.75 seconds
Started Jun 21 07:02:52 PM PDT 24
Finished Jun 21 07:02:58 PM PDT 24
Peak memory 206892 kb
Host smart-98b13189-ab99-46bc-93de-0c4fc1ee8a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930608633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3930608633
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2946012752
Short name T251
Test name
Test status
Simulation time 667340144 ps
CPU time 8.46 seconds
Started Jun 21 07:02:53 PM PDT 24
Finished Jun 21 07:03:08 PM PDT 24
Peak memory 225536 kb
Host smart-a8bc01a8-b8ec-4f4f-89cb-8656d2fe9969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946012752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2946012752
Directory /workspace/9.spi_device_upload/latest
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