Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3528608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3904701

1

T1

886

T2

15

T3

1141

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4222724	1			T1	5		T2	1		T3	525
values[0x0]	1605922	1			T1	443		T2	18		T3	458
values[0x1]	1604663	1			T1	442		T2	4		T3	432

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2504816	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4928493

1

T1

887

T2

16

T3

1195

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26819	1			T3	10		T7	252		T8	12
valid_sources[0x01]	31813	1			T3	4		T7	233		T8	5
valid_sources[0x02]	30103	1			T3	7		T7	263		T8	5
valid_sources[0x03]	27215	1			T3	10		T7	169		T8	7
valid_sources[0x04]	27593	1			T3	9		T7	241		T9	3
valid_sources[0x05]	29268	1			T3	1		T7	239		T8	3
valid_sources[0x06]	33384	1			T3	1		T7	267		T8	4
valid_sources[0x07]	27752	1			T3	2		T7	237		T8	1
valid_sources[0x08]	27352	1			T3	6		T7	295		T8	5
valid_sources[0x09]	25509	1			T3	7		T7	258		T8	6
valid_sources[0x0a]	28969	1			T3	6		T7	227		T8	6
valid_sources[0x0b]	25651	1			T3	3		T7	236		T8	4
valid_sources[0x0c]	31954	1			T3	3		T7	254		T8	3
valid_sources[0x0d]	25703	1			T3	5		T7	242		T8	3
valid_sources[0x0e]	26499	1			T3	1		T7	246		T8	6
valid_sources[0x0f]	26779	1			T3	7		T7	240		T8	5
valid_sources[0x10]	31544	1			T3	10		T7	222		T8	4
valid_sources[0x11]	30293	1			T3	2		T7	246		T8	4
valid_sources[0x12]	27943	1			T3	14		T7	279		T8	1
valid_sources[0x13]	26213	1			T3	2		T7	282		T8	1
valid_sources[0x14]	26560	1			T3	4		T7	193		T8	6
valid_sources[0x15]	29954	1			T3	8		T7	272		T8	3
valid_sources[0x16]	29113	1			T3	5		T7	205		T8	3
valid_sources[0x17]	32465	1			T3	4		T7	200		T8	2
valid_sources[0x18]	27467	1			T3	7		T7	213		T8	3
valid_sources[0x19]	25715	1			T3	6		T7	224		T9	6
valid_sources[0x1a]	31316	1			T3	9		T7	181		T8	3
valid_sources[0x1b]	28373	1			T3	7		T7	228		T8	2
valid_sources[0x1c]	28026	1			T3	8		T7	260		T8	1
valid_sources[0x1d]	29547	1			T3	2		T7	259		T8	10
valid_sources[0x1e]	26538	1			T3	5		T7	254		T8	3
valid_sources[0x1f]	29433	1			T3	7		T7	263		T8	8
valid_sources[0x20]	25706	1			T3	6		T7	265		T8	5
valid_sources[0x21]	25240	1			T3	6		T7	180		T8	4
valid_sources[0x22]	26004	1			T3	2		T7	194		T9	5
valid_sources[0x23]	43292	1			T3	5		T7	186		T9	3
valid_sources[0x24]	26105	1			T3	7		T7	264		T8	7
valid_sources[0x25]	26863	1			T3	2		T6	39		T7	206
valid_sources[0x26]	26708	1			T3	3		T7	266		T8	5
valid_sources[0x27]	27233	1			T3	3		T7	287		T8	5
valid_sources[0x28]	30679	1			T3	9		T7	203		T9	6
valid_sources[0x29]	32217	1			T3	8		T7	238		T8	1
valid_sources[0x2a]	28821	1			T3	13		T7	249		T8	3
valid_sources[0x2b]	31473	1			T3	10		T7	198		T8	8
valid_sources[0x2c]	24880	1			T3	8		T7	179		T8	5
valid_sources[0x2d]	28622	1			T3	2		T7	278		T8	5
valid_sources[0x2e]	27263	1			T3	8		T4	451		T7	163
valid_sources[0x2f]	28261	1			T3	7		T7	227		T8	3
valid_sources[0x30]	26295	1			T3	2		T7	215		T8	2
valid_sources[0x31]	38441	1			T7	240		T8	3		T9	4
valid_sources[0x32]	28246	1			T3	8		T7	202		T8	5
valid_sources[0x33]	29819	1			T3	7		T7	226		T8	2
valid_sources[0x34]	25021	1			T3	5		T7	281		T8	1
valid_sources[0x35]	26080	1			T3	1		T7	211		T8	8
valid_sources[0x36]	43940	1			T3	5		T7	261		T8	2
valid_sources[0x37]	25600	1			T3	7		T7	209		T8	4
valid_sources[0x38]	26836	1			T3	7		T7	196		T8	3
valid_sources[0x39]	24436	1			T3	1		T7	241		T8	1
valid_sources[0x3a]	26431	1			T3	6		T7	302		T8	5
valid_sources[0x3b]	30552	1			T3	5		T7	234		T8	4
valid_sources[0x3c]	30364	1			T3	4		T4	1		T7	337
valid_sources[0x3d]	27080	1			T3	3		T7	269		T8	1
valid_sources[0x3e]	25984	1			T3	2		T7	259		T8	6
valid_sources[0x3f]	28557	1			T3	6		T4	1		T7	257
valid_sources[0x40]	29281	1			T3	3		T7	240		T8	1
valid_sources[0x41]	26582	1			T3	10		T7	246		T8	2
valid_sources[0x42]	28031	1			T3	5		T7	241		T9	9
valid_sources[0x43]	27221	1			T3	5		T7	270		T8	6
valid_sources[0x44]	26055	1			T3	8		T7	257		T9	7
valid_sources[0x45]	26553	1			T3	6		T7	192		T8	1
valid_sources[0x46]	28697	1			T3	4		T7	240		T8	2
valid_sources[0x47]	30753	1			T3	6		T7	266		T8	9
valid_sources[0x48]	25702	1			T3	9		T7	289		T8	1
valid_sources[0x49]	26028	1			T3	6		T7	250		T8	4
valid_sources[0x4a]	26893	1			T3	5		T7	254		T8	5
valid_sources[0x4b]	28124	1			T3	4		T7	250		T8	6
valid_sources[0x4c]	26541	1			T3	6		T7	241		T8	2
valid_sources[0x4d]	34674	1			T3	2		T7	244		T9	1
valid_sources[0x4e]	27958	1			T3	7		T7	254		T8	7
valid_sources[0x4f]	25169	1			T3	6		T7	231		T8	3
valid_sources[0x50]	27259	1			T3	9		T7	284		T9	7
valid_sources[0x51]	27903	1			T3	4		T7	224		T8	3
valid_sources[0x52]	26661	1			T3	3		T7	245		T8	1
valid_sources[0x53]	28909	1			T1	890		T3	4		T7	228
valid_sources[0x54]	26826	1			T3	4		T7	209		T8	7
valid_sources[0x55]	31070	1			T3	8		T7	210		T8	9
valid_sources[0x56]	28559	1			T3	6		T7	234		T9	5
valid_sources[0x57]	28973	1			T3	11		T7	245		T8	4
valid_sources[0x58]	26682	1			T3	9		T7	239		T8	4
valid_sources[0x59]	27133	1			T3	8		T7	263		T8	6
valid_sources[0x5a]	29799	1			T3	9		T7	219		T8	6
valid_sources[0x5b]	27152	1			T3	4		T7	216		T8	2
valid_sources[0x5c]	27457	1			T3	5		T7	142		T8	7
valid_sources[0x5d]	26093	1			T3	5		T7	200		T8	2
valid_sources[0x5e]	26244	1			T3	3		T7	346		T8	6
valid_sources[0x5f]	31817	1			T3	3		T7	143		T9	3
valid_sources[0x60]	31518	1			T3	5		T7	278		T8	4
valid_sources[0x61]	26778	1			T3	6		T7	222		T8	2
valid_sources[0x62]	25659	1			T3	3		T7	255		T8	1
valid_sources[0x63]	24178	1			T3	4		T7	184		T9	5
valid_sources[0x64]	30511	1			T3	5		T7	214		T9	3
valid_sources[0x65]	32296	1			T3	4		T4	165		T7	155
valid_sources[0x66]	35043	1			T3	1		T7	376		T8	2
valid_sources[0x67]	28229	1			T3	6		T7	247		T8	3
valid_sources[0x68]	29145	1			T3	5		T7	185		T8	4
valid_sources[0x69]	31443	1			T3	6		T7	225		T8	1
valid_sources[0x6a]	25760	1			T3	9		T7	275		T8	5
valid_sources[0x6b]	27791	1			T3	2		T7	188		T8	3
valid_sources[0x6c]	28322	1			T3	7		T7	196		T8	5
valid_sources[0x6d]	40523	1			T3	2		T7	299		T8	12
valid_sources[0x6e]	27193	1			T3	2		T7	215		T8	2
valid_sources[0x6f]	27577	1			T3	5		T7	179		T8	9
valid_sources[0x70]	27844	1			T3	6		T7	197		T9	2
valid_sources[0x71]	39373	1			T3	8		T7	200		T8	12
valid_sources[0x72]	27450	1			T3	3		T7	196		T8	3
valid_sources[0x73]	27125	1			T3	13		T7	205		T8	10
valid_sources[0x74]	26835	1			T3	5		T7	178		T8	9
valid_sources[0x75]	26795	1			T3	13		T7	238		T9	4
valid_sources[0x76]	31201	1			T3	3		T7	245		T8	3
valid_sources[0x77]	26784	1			T3	2		T7	225		T8	7
valid_sources[0x78]	30586	1			T3	7		T7	180		T8	5
valid_sources[0x79]	29311	1			T3	3		T7	269		T9	6
valid_sources[0x7a]	44196	1			T3	6		T7	201		T8	1
valid_sources[0x7b]	28821	1			T3	7		T7	195		T8	5
valid_sources[0x7c]	30453	1			T3	7		T7	295		T8	1
valid_sources[0x7d]	24693	1			T3	11		T7	203		T8	2
valid_sources[0x7e]	27081	1			T3	2		T7	244		T8	3
valid_sources[0x7f]	25410	1			T3	3		T7	256		T8	12
valid_sources[0x80]	31379	1			T3	6		T7	216		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1021001

1

T1

4

T3

260

T4

330

values[0x0]

all_enables

biggest_size

1454811

1

T1

443

T2

12

T3

451

values[0x1]

all_enables

biggest_size

1428889

1

T1

439

T2

3

T3

430