Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3550755

1

T1

4

T2

8

T3

274

full_word

3903916

1

T1

886

T2

15

T3

1141

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7454281	1			T1	890		T2	23		T3	1415
auto[TlIntgErrCmd]	122	1			T91	13		T92	1		T93	8
auto[TlIntgErrData]	127	1			T91	6		T92	2		T93	12
auto[TlIntgErrBoth]	141	1			T91	11		T92	7		T93	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4224375

1

T1

5

T2

1

T3

525

auto[1]

3230296

1

T1

885

T2

22

T3

890

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3203083	1			T1	1		T2	1		T3	265
auto[TlIntgErrNone]	partial	auto[1]	347310	1			T1	3		T2	7		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	1021119	1			T1	4		T3	260		T4	330
auto[TlIntgErrNone]	full_word	auto[1]	2882769	1			T1	882		T2	15		T3	881
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T91	6		T92	1		T93	1
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T91	7		T93	7		T103	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T165	1		T166	1		T167	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T168	1		T169	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1			T91	3		T93	7		T103	3
auto[TlIntgErrData]	partial	auto[1]	60	1			T91	3		T92	2		T93	5
auto[TlIntgErrData]	full_word	auto[0]	8	1			T162	1		T170	1		T171	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T99	1		T165	1		T172	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T91	3		T92	1		T93	6
auto[TlIntgErrBoth]	partial	auto[1]	80	1			T91	8		T92	5		T93	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T93	1		T162	1		T99	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T92	1		T170	1		T99	1