Unified Coverage Report :: Module :: prim_pulse_sync

Module : prim_pulse_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_upload.u_payloadptr_clr_psync	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T7
1	0	Covered	T3,T4,T7
1	1	Covered	T3,T4,T7

---

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1189877712	2482	0	0
SrcPulseCheck_M	385524048	2482	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1189877712	2482	0	0
T3	33278	7	0	0
T4	52838	3	0	0
T5	79354	0	0	0
T6	419824	0	0	0
T7	849798	16	0	0
T8	15159	0	0	0
T9	1090119	0	0	0
T10	919893	16	0	0
T11	462906	2	0	0
T12	2439	0	0	0
T13	0	42	0	0
T22	1175160	0	0	0
T23	425478	0	0	0
T24	262915	7	0	0
T25	292985	2	0	0
T26	0	12	0	0
T29	0	6	0	0
T36	0	7	0	0
T38	0	10	0	0
T39	0	7	0	0
T40	0	3	0	0
T82	0	3	0	0
T135	0	7	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	0	7	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	385524048	2482	0	0
T3	17396	7	0	0
T4	126952	3	0	0
T5	9728	0	0	0
T6	68512	0	0	0
T7	1692090	16	0	0
T8	2346	0	0	0
T9	135072	0	0	0
T10	2960367	16	0	0
T11	375150	2	0	0
T12	432	0	0	0
T13	0	42	0	0
T22	145116	0	0	0
T23	84382	0	0	0
T24	108090	7	0	0
T25	141382	2	0	0
T26	0	12	0	0
T29	0	6	0	0
T36	0	7	0	0
T38	0	10	0	0
T39	0	7	0	0
T40	0	3	0	0
T82	0	3	0	0
T135	0	7	0	0
T136	0	7	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	0	7	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T38
1	0	Covered	T3,T4,T38
1	1	Covered	T3,T4,T38

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T38
1	0	Covered	T3,T4,T38
1	1	Covered	T3,T4,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	396625904	182	0	0
SrcPulseCheck_M	128508016	182	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	182	0	0
T3	16639	2	0	0
T4	26419	2	0	0
T5	39677	0	0	0
T6	209912	0	0	0
T7	283266	0	0	0
T8	5053	0	0	0
T9	363373	0	0	0
T10	306631	0	0	0
T11	154302	0	0	0
T22	391720	0	0	0
T38	0	5	0	0
T39	0	2	0	0
T82	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	182	0	0
T3	8698	2	0	0
T4	63476	2	0	0
T5	4864	0	0	0
T6	34256	0	0	0
T7	564030	0	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	0	0	0
T22	48372	0	0	0
T38	0	5	0	0
T39	0	2	0	0
T82	0	2	0	0
T135	0	2	0	0
T136	0	2	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T38
1	0	Covered	T3,T4,T38
1	1	Covered	T3,T38,T39

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T38
1	0	Covered	T3,T38,T39
1	1	Covered	T3,T4,T38

---

Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	396625904	321	0	0
SrcPulseCheck_M	128508016	321	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	321	0	0
T3	16639	5	0	0
T4	26419	1	0	0
T5	39677	0	0	0
T6	209912	0	0	0
T7	283266	0	0	0
T8	5053	0	0	0
T9	363373	0	0	0
T10	306631	0	0	0
T11	154302	0	0	0
T22	391720	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T82	0	1	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	5	0	0
T139	0	5	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	321	0	0
T3	8698	5	0	0
T4	63476	1	0	0
T5	4864	0	0	0
T6	34256	0	0	0
T7	564030	0	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	0	0	0
T22	48372	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T82	0	1	0	0
T135	0	5	0	0
T136	0	5	0	0
T137	0	5	0	0
T138	0	5	0	0
T139	0	5	0	0

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T7,T10,T11
1	1	Covered	T7,T10,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T7,T10,T11
1	1	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	396625904	1979	0	0
SrcPulseCheck_M	128508016	1979	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1979	0	0
T7	283266	16	0	0
T8	5053	0	0	0
T9	363373	0	0	0
T10	306631	16	0	0
T11	154302	2	0	0
T12	2439	0	0	0
T13	0	42	0	0
T22	391720	0	0	0
T23	425478	0	0	0
T24	262915	7	0	0
T25	292985	2	0	0
T26	0	12	0	0
T29	0	6	0	0
T36	0	7	0	0
T40	0	3	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	1979	0	0
T7	564030	16	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	16	0	0
T11	125050	2	0	0
T12	432	0	0	0
T13	0	42	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	7	0	0
T25	141382	2	0	0
T26	0	12	0	0
T29	0	6	0	0
T36	0	7	0	0
T40	0	3	0	0