Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399230258	2438750	0	0
DepthKnown_A	399230258	399103378	0	0
RvalidKnown_A	399230258	399103378	0	0
WreadyKnown_A	399230258	399103378	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	2438750	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	2182	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	12481	0	0
T8	5053	1663	0	0
T9	363373	1663	0	0
T10	306631	13316	0	0
T11	0	1665	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399230258	2618784	0	0
DepthKnown_A	399230258	399103378	0	0
RvalidKnown_A	399230258	399103378	0	0
WreadyKnown_A	399230258	399103378	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	2618784	0	0
T1	242371	3668	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1097	0	0
T5	39677	3864	0	0
T6	209912	832	0	0
T7	283266	10647	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	24471	0	0
T11	0	834	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399230258	176923	0	0
DepthKnown_A	399230258	399103378	0	0
RvalidKnown_A	399230258	399103378	0	0
WreadyKnown_A	399230258	399103378	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	176923	0	0
T7	283266	1244	0	0
T8	5053	0	0	0
T9	363373	0	0	0
T10	306631	320	0	0
T11	154302	365	0	0
T12	2439	0	0	0
T13	0	3696	0	0
T22	391720	0	0	0
T23	425478	0	0	0
T24	262915	160	0	0
T25	292985	492	0	0
T26	0	657	0	0
T27	0	17	0	0
T29	0	1173	0	0
T36	0	129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399230258	372465	0	0
DepthKnown_A	399230258	399103378	0	0
RvalidKnown_A	399230258	399103378	0	0
WreadyKnown_A	399230258	399103378	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	372465	0	0
T7	283266	4874	0	0
T8	5053	0	0	0
T9	363373	0	0	0
T10	306631	997	0	0
T11	154302	1144	0	0
T12	2439	0	0	0
T13	0	3695	0	0
T22	391720	0	0	0
T23	425478	0	0	0
T24	262915	758	0	0
T25	292985	492	0	0
T26	0	1975	0	0
T27	0	17	0	0
T29	0	5062	0	0
T36	0	585	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399230258	6010483	0	0
DepthKnown_A	399230258	399103378	0	0
RvalidKnown_A	399230258	399103378	0	0
WreadyKnown_A	399230258	399103378	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	6010483	0	0
T1	242371	58	0	0
T2	4287	23	0	0
T3	16639	583	0	0
T4	26419	675	0	0
T5	39677	762	0	0
T6	209912	411	0	0
T7	283266	56976	0	0
T8	5053	120	0	0
T9	363373	561	0	0
T10	306631	5240	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	399230258	11358670	0	0
DepthKnown_A	399230258	399103378	0	0
RvalidKnown_A	399230258	399103378	0	0
WreadyKnown_A	399230258	399103378	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	11358670	0	0
T1	242371	232	0	0
T2	4287	23	0	0
T3	16639	583	0	0
T4	26419	2171	0	0
T5	39677	3268	0	0
T6	209912	411	0	0
T7	283266	192992	0	0
T8	5053	120	0	0
T9	363373	2402	0	0
T10	306631	15917	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399230258	399103378	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0