Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T25
1	0	Covered	T7,T11,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Unreachable
1	1	Covered	T7,T11,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T7,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T7,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	653641936	523770402	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	653641936	3284036	0	0
GntImpliesValid_A	653641936	3284036	0	0
GrantKnown_A	653641936	523770402	0	0
IdxKnown_A	653641936	523770402	0	0
IndexIsCorrect_A	653641936	3284036	0	0
LockArbDecision_A	653641936	0	0	0
NoReadyValidNoGrant_A	653641936	0	0	0
ReadyAndValidImplyGrant_A	653641936	3284036	0	0
ReqAndReadyImplyGrant_A	653641936	3284036	0	0
ReqImpliesValid_A	653641936	3284036	0	0
ReqStaysHighUntilGranted0_M	653641936	0	0	0
RoundRobin_A	653641936	3	0	926
ValidKnown_A	653641936	523770402	0	0
gen_data_port_assertion.DataFlow_A	653641936	3284036	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	523770402	0	0
T1	319470	318964	0	0
T2	5295	4725	0	0
T3	34035	25247	0	0
T4	153371	89491	0	0
T5	49405	44473	0	0
T6	278424	244068	0	0
T7	1411326	842987	0	0
T8	6617	5297	0	0
T9	453421	408308	0	0
T10	2280209	1289690	0	0
T11	125050	122361	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3284036	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	1411326	21493	0	0
T8	6617	832	0	0
T9	453421	832	0	0
T10	2280209	15889	0	0
T11	250100	3762	0	0
T12	864	0	0	0
T13	0	30280	0	0
T22	96744	0	0	0
T23	168764	0	0	0
T24	216180	2760	0	0
T25	282764	2965	0	0
T26	0	8669	0	0
T27	0	73	0	0
T29	0	6140	0	0
T36	0	529	0	0
T40	0	6136	0	0
T41	0	2218	0	0
T42	0	5056	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3284036	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	1411326	21493	0	0
T8	6617	832	0	0
T9	453421	832	0	0
T10	2280209	15889	0	0
T11	250100	3762	0	0
T12	864	0	0	0
T13	0	30280	0	0
T22	96744	0	0	0
T23	168764	0	0	0
T24	216180	2760	0	0
T25	282764	2965	0	0
T26	0	8669	0	0
T27	0	73	0	0
T29	0	6140	0	0
T36	0	529	0	0
T40	0	6136	0	0
T41	0	2218	0	0
T42	0	5056	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	523770402	0	0
T1	319470	318964	0	0
T2	5295	4725	0	0
T3	34035	25247	0	0
T4	153371	89491	0	0
T5	49405	44473	0	0
T6	278424	244068	0	0
T7	1411326	842987	0	0
T8	6617	5297	0	0
T9	453421	408308	0	0
T10	2280209	1289690	0	0
T11	125050	122361	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	523770402	0	0
T1	319470	318964	0	0
T2	5295	4725	0	0
T3	34035	25247	0	0
T4	153371	89491	0	0
T5	49405	44473	0	0
T6	278424	244068	0	0
T7	1411326	842987	0	0
T8	6617	5297	0	0
T9	453421	408308	0	0
T10	2280209	1289690	0	0
T11	125050	122361	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3284036	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	1411326	21493	0	0
T8	6617	832	0	0
T9	453421	832	0	0
T10	2280209	15889	0	0
T11	250100	3762	0	0
T12	864	0	0	0
T13	0	30280	0	0
T22	96744	0	0	0
T23	168764	0	0	0
T24	216180	2760	0	0
T25	282764	2965	0	0
T26	0	8669	0	0
T27	0	73	0	0
T29	0	6140	0	0
T36	0	529	0	0
T40	0	6136	0	0
T41	0	2218	0	0
T42	0	5056	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3284036	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	1411326	21493	0	0
T8	6617	832	0	0
T9	453421	832	0	0
T10	2280209	15889	0	0
T11	250100	3762	0	0
T12	864	0	0	0
T13	0	30280	0	0
T22	96744	0	0	0
T23	168764	0	0	0
T24	216180	2760	0	0
T25	282764	2965	0	0
T26	0	8669	0	0
T27	0	73	0	0
T29	0	6140	0	0
T36	0	529	0	0
T40	0	6136	0	0
T41	0	2218	0	0
T42	0	5056	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3284036	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	1411326	21493	0	0
T8	6617	832	0	0
T9	453421	832	0	0
T10	2280209	15889	0	0
T11	250100	3762	0	0
T12	864	0	0	0
T13	0	30280	0	0
T22	96744	0	0	0
T23	168764	0	0	0
T24	216180	2760	0	0
T25	282764	2965	0	0
T26	0	8669	0	0
T27	0	73	0	0
T29	0	6140	0	0
T36	0	529	0	0
T40	0	6136	0	0
T41	0	2218	0	0
T42	0	5056	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3284036	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	1411326	21493	0	0
T8	6617	832	0	0
T9	453421	832	0	0
T10	2280209	15889	0	0
T11	250100	3762	0	0
T12	864	0	0	0
T13	0	30280	0	0
T22	96744	0	0	0
T23	168764	0	0	0
T24	216180	2760	0	0
T25	282764	2965	0	0
T26	0	8669	0	0
T27	0	73	0	0
T29	0	6140	0	0
T36	0	529	0	0
T40	0	6136	0	0
T41	0	2218	0	0
T42	0	5056	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3	0	926
T47	436744	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	48933	0	0	1
T51	846	0	0	1
T52	545274	0	0	1
T53	67095	0	0	1
T54	10636	0	0	1
T55	329242	0	0	1
T56	103522	0	0	1
T57	13916	0	0	1
T58	6513	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	523770402	0	0
T1	319470	318964	0	0
T2	5295	4725	0	0
T3	34035	25247	0	0
T4	153371	89491	0	0
T5	49405	44473	0	0
T6	278424	244068	0	0
T7	1411326	842987	0	0
T8	6617	5297	0	0
T9	453421	408308	0	0
T10	2280209	1289690	0	0
T11	125050	122361	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653641936	3284036	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	1411326	21493	0	0
T8	6617	832	0	0
T9	453421	832	0	0
T10	2280209	15889	0	0
T11	250100	3762	0	0
T12	864	0	0	0
T13	0	30280	0	0
T22	96744	0	0	0
T23	168764	0	0	0
T24	216180	2760	0	0
T25	282764	2965	0	0
T26	0	8669	0	0
T27	0	73	0	0
T29	0	6140	0	0
T36	0	529	0	0
T40	0	6136	0	0
T41	0	2218	0	0
T42	0	5056	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T11,T25
1	0	Covered	T7,T11,T25

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Unreachable
1	1	Covered	T7,T11,T25

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T11,T25
0	0	1	Unreachable
0	0	0	Covered	T2,T7,T11

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T25
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T25
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128508016	27313830	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	128508016	627409	0	0
GntImpliesValid_A	128508016	627409	0	0
GrantKnown_A	128508016	27313830	0	0
IdxKnown_A	128508016	27313830	0	0
IndexIsCorrect_A	128508016	627409	0	0
LockArbDecision_A	128508016	0	0	0
NoReadyValidNoGrant_A	128508016	0	0	0
ReadyAndValidImplyGrant_A	128508016	627409	0	0
ReqAndReadyImplyGrant_A	128508016	627409	0	0
ReqImpliesValid_A	128508016	627409	0	0
ReqStaysHighUntilGranted0_M	128508016	0	0	0
RoundRobin_A	128508016	0	0	0
ValidKnown_A	128508016	27313830	0	0
gen_data_port_assertion.DataFlow_A	128508016	627409	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	27313830	0	0
T2	504	504	0	0
T3	8698	0	0	0
T4	63476	0	0	0
T5	4864	0	0	0
T6	34256	0	0	0
T7	564030	112784	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	79664	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	627409	0	0
T7	564030	4669	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	2019	0	0
T12	432	0	0	0
T13	0	13510	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	0	0	0
T25	141382	2961	0	0
T26	0	1436	0	0
T27	0	73	0	0
T29	0	4721	0	0
T40	0	1936	0	0
T41	0	2218	0	0
T42	0	5056	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	627409	0	0
T7	564030	4669	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	2019	0	0
T12	432	0	0	0
T13	0	13510	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	0	0	0
T25	141382	2961	0	0
T26	0	1436	0	0
T27	0	73	0	0
T29	0	4721	0	0
T40	0	1936	0	0
T41	0	2218	0	0
T42	0	5056	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	27313830	0	0
T2	504	504	0	0
T3	8698	0	0	0
T4	63476	0	0	0
T5	4864	0	0	0
T6	34256	0	0	0
T7	564030	112784	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	79664	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	27313830	0	0
T2	504	504	0	0
T3	8698	0	0	0
T4	63476	0	0	0
T5	4864	0	0	0
T6	34256	0	0	0
T7	564030	112784	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	79664	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	627409	0	0
T7	564030	4669	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	2019	0	0
T12	432	0	0	0
T13	0	13510	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	0	0	0
T25	141382	2961	0	0
T26	0	1436	0	0
T27	0	73	0	0
T29	0	4721	0	0
T40	0	1936	0	0
T41	0	2218	0	0
T42	0	5056	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	627409	0	0
T7	564030	4669	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	2019	0	0
T12	432	0	0	0
T13	0	13510	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	0	0	0
T25	141382	2961	0	0
T26	0	1436	0	0
T27	0	73	0	0
T29	0	4721	0	0
T40	0	1936	0	0
T41	0	2218	0	0
T42	0	5056	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	627409	0	0
T7	564030	4669	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	2019	0	0
T12	432	0	0	0
T13	0	13510	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	0	0	0
T25	141382	2961	0	0
T26	0	1436	0	0
T27	0	73	0	0
T29	0	4721	0	0
T40	0	1936	0	0
T41	0	2218	0	0
T42	0	5056	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	627409	0	0
T7	564030	4669	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	2019	0	0
T12	432	0	0	0
T13	0	13510	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	0	0	0
T25	141382	2961	0	0
T26	0	1436	0	0
T27	0	73	0	0
T29	0	4721	0	0
T40	0	1936	0	0
T41	0	2218	0	0
T42	0	5056	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	27313830	0	0
T2	504	504	0	0
T3	8698	0	0	0
T4	63476	0	0	0
T5	4864	0	0	0
T6	34256	0	0	0
T7	564030	112784	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	79664	0	0
T12	0	432	0	0
T13	0	740904	0	0
T25	0	88040	0	0
T26	0	34608	0	0
T27	0	856	0	0
T28	0	504	0	0
T29	0	226120	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	627409	0	0
T7	564030	4669	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	0	0	0
T11	125050	2019	0	0
T12	432	0	0	0
T13	0	13510	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	0	0	0
T25	141382	2961	0	0
T26	0	1436	0	0
T27	0	73	0	0
T29	0	4721	0	0
T40	0	1936	0	0
T41	0	2218	0	0
T42	0	5056	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T7,T10,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T7,T10,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T10,T11
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	128508016	99912679	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	128508016	696052	0	0
GntImpliesValid_A	128508016	696052	0	0
GrantKnown_A	128508016	99912679	0	0
IdxKnown_A	128508016	99912679	0	0
IndexIsCorrect_A	128508016	696052	0	0
LockArbDecision_A	128508016	0	0	0
NoReadyValidNoGrant_A	128508016	0	0	0
ReadyAndValidImplyGrant_A	128508016	696052	0	0
ReqAndReadyImplyGrant_A	128508016	696052	0	0
ReqImpliesValid_A	128508016	696052	0	0
ReqStaysHighUntilGranted0_M	128508016	0	0	0
RoundRobin_A	128508016	0	0	0
ValidKnown_A	128508016	99912679	0	0
gen_data_port_assertion.DataFlow_A	128508016	696052	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	99912679	0	0
T1	77099	76654	0	0
T2	504	0	0	0
T3	8698	8698	0	0
T4	63476	63160	0	0
T5	4864	4864	0	0
T6	34256	34256	0	0
T7	564030	446956	0	0
T8	782	320	0	0
T9	45024	45024	0	0
T10	986789	983067	0	0
T11	0	42697	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	696052	0	0
T7	564030	6407	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	5556	0	0
T11	125050	4	0	0
T12	432	0	0	0
T13	0	16770	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	2760	0	0
T25	141382	4	0	0
T26	0	7233	0	0
T29	0	1419	0	0
T36	0	529	0	0
T40	0	4200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	696052	0	0
T7	564030	6407	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	5556	0	0
T11	125050	4	0	0
T12	432	0	0	0
T13	0	16770	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	2760	0	0
T25	141382	4	0	0
T26	0	7233	0	0
T29	0	1419	0	0
T36	0	529	0	0
T40	0	4200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	99912679	0	0
T1	77099	76654	0	0
T2	504	0	0	0
T3	8698	8698	0	0
T4	63476	63160	0	0
T5	4864	4864	0	0
T6	34256	34256	0	0
T7	564030	446956	0	0
T8	782	320	0	0
T9	45024	45024	0	0
T10	986789	983067	0	0
T11	0	42697	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	99912679	0	0
T1	77099	76654	0	0
T2	504	0	0	0
T3	8698	8698	0	0
T4	63476	63160	0	0
T5	4864	4864	0	0
T6	34256	34256	0	0
T7	564030	446956	0	0
T8	782	320	0	0
T9	45024	45024	0	0
T10	986789	983067	0	0
T11	0	42697	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	696052	0	0
T7	564030	6407	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	5556	0	0
T11	125050	4	0	0
T12	432	0	0	0
T13	0	16770	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	2760	0	0
T25	141382	4	0	0
T26	0	7233	0	0
T29	0	1419	0	0
T36	0	529	0	0
T40	0	4200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	696052	0	0
T7	564030	6407	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	5556	0	0
T11	125050	4	0	0
T12	432	0	0	0
T13	0	16770	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	2760	0	0
T25	141382	4	0	0
T26	0	7233	0	0
T29	0	1419	0	0
T36	0	529	0	0
T40	0	4200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	696052	0	0
T7	564030	6407	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	5556	0	0
T11	125050	4	0	0
T12	432	0	0	0
T13	0	16770	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	2760	0	0
T25	141382	4	0	0
T26	0	7233	0	0
T29	0	1419	0	0
T36	0	529	0	0
T40	0	4200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	696052	0	0
T7	564030	6407	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	5556	0	0
T11	125050	4	0	0
T12	432	0	0	0
T13	0	16770	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	2760	0	0
T25	141382	4	0	0
T26	0	7233	0	0
T29	0	1419	0	0
T36	0	529	0	0
T40	0	4200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	99912679	0	0
T1	77099	76654	0	0
T2	504	0	0	0
T3	8698	8698	0	0
T4	63476	63160	0	0
T5	4864	4864	0	0
T6	34256	34256	0	0
T7	564030	446956	0	0
T8	782	320	0	0
T9	45024	45024	0	0
T10	986789	983067	0	0
T11	0	42697	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	128508016	696052	0	0
T7	564030	6407	0	0
T8	782	0	0	0
T9	45024	0	0	0
T10	986789	5556	0	0
T11	125050	4	0	0
T12	432	0	0	0
T13	0	16770	0	0
T22	48372	0	0	0
T23	84382	0	0	0
T24	108090	2760	0	0
T25	141382	4	0	0
T26	0	7233	0	0
T29	0	1419	0	0
T36	0	529	0	0
T40	0	4200	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T10,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T10,T11
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396625904	396543893	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	396625904	1960575	0	0
GntImpliesValid_A	396625904	1960575	0	0
GrantKnown_A	396625904	396543893	0	0
IdxKnown_A	396625904	396543893	0	0
IndexIsCorrect_A	396625904	1960575	0	0
LockArbDecision_A	396625904	0	0	0
NoReadyValidNoGrant_A	396625904	0	0	0
ReadyAndValidImplyGrant_A	396625904	1960575	0	0
ReqAndReadyImplyGrant_A	396625904	1960575	0	0
ReqImpliesValid_A	396625904	1960575	0	0
ReqStaysHighUntilGranted0_M	396625904	0	0	0
RoundRobin_A	396625904	3	0	926
ValidKnown_A	396625904	396543893	0	0
gen_data_port_assertion.DataFlow_A	396625904	1960575	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	396543893	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1960575	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	10417	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	10333	0	0
T11	0	1739	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1960575	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	10417	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	10333	0	0
T11	0	1739	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	396543893	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	396543893	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1960575	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	10417	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	10333	0	0
T11	0	1739	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1960575	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	10417	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	10333	0	0
T11	0	1739	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1960575	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	10417	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	10333	0	0
T11	0	1739	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1960575	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	10417	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	10333	0	0
T11	0	1739	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	3	0	926
T47	436744	1	0	1
T48	0	1	0	0
T49	0	1	0	0
T50	48933	0	0	1
T51	846	0	0	1
T52	545274	0	0	1
T53	67095	0	0	1
T54	10636	0	0	1
T55	329242	0	0	1
T56	103522	0	0	1
T57	13916	0	0	1
T58	6513	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	396543893	0	0
T1	242371	242310	0	0
T2	4287	4221	0	0
T3	16639	16549	0	0
T4	26419	26331	0	0
T5	39677	39609	0	0
T6	209912	209812	0	0
T7	283266	283247	0	0
T8	5053	4977	0	0
T9	363373	363284	0	0
T10	306631	306623	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396625904	1960575	0	0
T1	242371	832	0	0
T2	4287	0	0	0
T3	16639	832	0	0
T4	26419	1088	0	0
T5	39677	832	0	0
T6	209912	832	0	0
T7	283266	10417	0	0
T8	5053	832	0	0
T9	363373	832	0	0
T10	306631	10333	0	0
T11	0	1739	0	0