Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4472 |
0 |
0 |
T88 |
14393 |
253 |
0 |
0 |
T89 |
13965 |
215 |
0 |
0 |
T90 |
5395 |
279 |
0 |
0 |
T91 |
81067 |
4 |
0 |
0 |
T92 |
31529 |
2 |
0 |
0 |
T94 |
17678 |
269 |
0 |
0 |
T95 |
16933 |
314 |
0 |
0 |
T97 |
15564 |
232 |
0 |
0 |
T101 |
5197 |
8 |
0 |
0 |
T102 |
4447 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1898 |
0 |
0 |
T92 |
31529 |
35 |
0 |
0 |
T93 |
93125 |
21 |
0 |
0 |
T106 |
3563 |
7 |
0 |
0 |
T108 |
11299 |
11 |
0 |
0 |
T110 |
6959 |
7 |
0 |
0 |
T113 |
7577 |
8 |
0 |
0 |
T114 |
3858 |
5 |
0 |
0 |
T115 |
234364 |
450 |
0 |
0 |
T140 |
19697 |
58 |
0 |
0 |
T141 |
13582 |
20 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2098 |
0 |
0 |
T92 |
31529 |
17 |
0 |
0 |
T93 |
93125 |
100 |
0 |
0 |
T106 |
3563 |
8 |
0 |
0 |
T108 |
11299 |
10 |
0 |
0 |
T110 |
6959 |
12 |
0 |
0 |
T113 |
7577 |
8 |
0 |
0 |
T114 |
3858 |
6 |
0 |
0 |
T115 |
234364 |
404 |
0 |
0 |
T140 |
19697 |
144 |
0 |
0 |
T141 |
13582 |
12 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2403 |
0 |
0 |
T92 |
31529 |
37 |
0 |
0 |
T93 |
93125 |
103 |
0 |
0 |
T106 |
3563 |
5 |
0 |
0 |
T108 |
11299 |
25 |
0 |
0 |
T110 |
6959 |
14 |
0 |
0 |
T113 |
7577 |
28 |
0 |
0 |
T114 |
3858 |
3 |
0 |
0 |
T115 |
234364 |
443 |
0 |
0 |
T140 |
19697 |
30 |
0 |
0 |
T141 |
13582 |
20 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
8833 |
0 |
0 |
T92 |
31529 |
326 |
0 |
0 |
T93 |
93125 |
855 |
0 |
0 |
T108 |
11299 |
223 |
0 |
0 |
T110 |
6959 |
10 |
0 |
0 |
T113 |
7577 |
104 |
0 |
0 |
T114 |
3858 |
3 |
0 |
0 |
T115 |
234364 |
460 |
0 |
0 |
T140 |
19697 |
48 |
0 |
0 |
T141 |
13582 |
69 |
0 |
0 |
T142 |
20321 |
54 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
9733 |
0 |
0 |
T89 |
13965 |
2 |
0 |
0 |
T92 |
31529 |
208 |
0 |
0 |
T93 |
93125 |
873 |
0 |
0 |
T108 |
11299 |
225 |
0 |
0 |
T110 |
6959 |
236 |
0 |
0 |
T113 |
7577 |
271 |
0 |
0 |
T114 |
3858 |
116 |
0 |
0 |
T115 |
234364 |
385 |
0 |
0 |
T140 |
19697 |
65 |
0 |
0 |
T141 |
13582 |
175 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
9853 |
0 |
0 |
T92 |
31529 |
333 |
0 |
0 |
T93 |
93125 |
1264 |
0 |
0 |
T106 |
3563 |
47 |
0 |
0 |
T108 |
11299 |
120 |
0 |
0 |
T110 |
6959 |
16 |
0 |
0 |
T113 |
7577 |
113 |
0 |
0 |
T114 |
3858 |
124 |
0 |
0 |
T115 |
234364 |
425 |
0 |
0 |
T140 |
19697 |
70 |
0 |
0 |
T141 |
13582 |
234 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
9622 |
0 |
0 |
T92 |
31529 |
300 |
0 |
0 |
T93 |
93125 |
854 |
0 |
0 |
T94 |
17678 |
4 |
0 |
0 |
T106 |
3563 |
71 |
0 |
0 |
T108 |
11299 |
282 |
0 |
0 |
T110 |
6959 |
6 |
0 |
0 |
T113 |
7577 |
133 |
0 |
0 |
T114 |
3858 |
6 |
0 |
0 |
T140 |
19697 |
86 |
0 |
0 |
T141 |
13582 |
169 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
9231 |
0 |
0 |
T92 |
31529 |
281 |
0 |
0 |
T93 |
93125 |
1092 |
0 |
0 |
T97 |
15564 |
1 |
0 |
0 |
T106 |
3563 |
82 |
0 |
0 |
T108 |
11299 |
312 |
0 |
0 |
T110 |
6959 |
257 |
0 |
0 |
T113 |
7577 |
136 |
0 |
0 |
T114 |
3858 |
7 |
0 |
0 |
T140 |
19697 |
46 |
0 |
0 |
T141 |
13582 |
92 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
9620 |
0 |
0 |
T92 |
31529 |
328 |
0 |
0 |
T93 |
93125 |
1164 |
0 |
0 |
T106 |
3563 |
82 |
0 |
0 |
T108 |
11299 |
140 |
0 |
0 |
T110 |
6959 |
94 |
0 |
0 |
T113 |
7577 |
264 |
0 |
0 |
T114 |
3858 |
1 |
0 |
0 |
T115 |
234364 |
412 |
0 |
0 |
T140 |
19697 |
72 |
0 |
0 |
T141 |
13582 |
25 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
8710 |
0 |
0 |
T92 |
31529 |
466 |
0 |
0 |
T93 |
93125 |
864 |
0 |
0 |
T106 |
3563 |
35 |
0 |
0 |
T108 |
11299 |
7 |
0 |
0 |
T110 |
6959 |
234 |
0 |
0 |
T113 |
7577 |
126 |
0 |
0 |
T114 |
3858 |
6 |
0 |
0 |
T115 |
234364 |
309 |
0 |
0 |
T140 |
19697 |
70 |
0 |
0 |
T141 |
13582 |
85 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
8203 |
0 |
0 |
T92 |
31529 |
547 |
0 |
0 |
T93 |
93125 |
1031 |
0 |
0 |
T106 |
3563 |
58 |
0 |
0 |
T108 |
11299 |
6 |
0 |
0 |
T110 |
6959 |
8 |
0 |
0 |
T113 |
7577 |
141 |
0 |
0 |
T114 |
3858 |
126 |
0 |
0 |
T115 |
234364 |
407 |
0 |
0 |
T140 |
19697 |
30 |
0 |
0 |
T141 |
13582 |
102 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
5084 |
0 |
0 |
T92 |
31529 |
107 |
0 |
0 |
T93 |
93125 |
518 |
0 |
0 |
T106 |
3563 |
32 |
0 |
0 |
T108 |
11299 |
79 |
0 |
0 |
T110 |
6959 |
72 |
0 |
0 |
T113 |
7577 |
50 |
0 |
0 |
T114 |
3858 |
6 |
0 |
0 |
T115 |
234364 |
435 |
0 |
0 |
T140 |
19697 |
47 |
0 |
0 |
T141 |
13582 |
61 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4788 |
0 |
0 |
T92 |
31529 |
238 |
0 |
0 |
T93 |
93125 |
448 |
0 |
0 |
T106 |
3563 |
37 |
0 |
0 |
T108 |
11299 |
67 |
0 |
0 |
T110 |
6959 |
68 |
0 |
0 |
T113 |
7577 |
66 |
0 |
0 |
T114 |
3858 |
1 |
0 |
0 |
T115 |
234364 |
448 |
0 |
0 |
T140 |
19697 |
87 |
0 |
0 |
T141 |
13582 |
27 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
5017 |
0 |
0 |
T92 |
31529 |
42 |
0 |
0 |
T93 |
93125 |
568 |
0 |
0 |
T106 |
3563 |
3 |
0 |
0 |
T108 |
11299 |
78 |
0 |
0 |
T110 |
6959 |
50 |
0 |
0 |
T113 |
7577 |
123 |
0 |
0 |
T114 |
3858 |
5 |
0 |
0 |
T115 |
234364 |
477 |
0 |
0 |
T140 |
19697 |
75 |
0 |
0 |
T141 |
13582 |
86 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
5254 |
0 |
0 |
T92 |
31529 |
208 |
0 |
0 |
T93 |
93125 |
509 |
0 |
0 |
T96 |
19442 |
6 |
0 |
0 |
T108 |
11299 |
76 |
0 |
0 |
T110 |
6959 |
110 |
0 |
0 |
T113 |
7577 |
12 |
0 |
0 |
T114 |
3858 |
66 |
0 |
0 |
T115 |
234364 |
374 |
0 |
0 |
T140 |
19697 |
7 |
0 |
0 |
T141 |
13582 |
55 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
5426 |
0 |
0 |
T92 |
31529 |
89 |
0 |
0 |
T93 |
93125 |
322 |
0 |
0 |
T106 |
3563 |
15 |
0 |
0 |
T108 |
11299 |
148 |
0 |
0 |
T110 |
6959 |
58 |
0 |
0 |
T113 |
7577 |
61 |
0 |
0 |
T114 |
3858 |
64 |
0 |
0 |
T115 |
234364 |
395 |
0 |
0 |
T140 |
19697 |
99 |
0 |
0 |
T141 |
13582 |
71 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4875 |
0 |
0 |
T92 |
31529 |
148 |
0 |
0 |
T93 |
93125 |
450 |
0 |
0 |
T106 |
3563 |
19 |
0 |
0 |
T108 |
11299 |
33 |
0 |
0 |
T110 |
6959 |
60 |
0 |
0 |
T113 |
7577 |
99 |
0 |
0 |
T114 |
3858 |
47 |
0 |
0 |
T115 |
234364 |
376 |
0 |
0 |
T140 |
19697 |
102 |
0 |
0 |
T141 |
13582 |
82 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4644 |
0 |
0 |
T92 |
31529 |
98 |
0 |
0 |
T93 |
93125 |
363 |
0 |
0 |
T108 |
11299 |
91 |
0 |
0 |
T110 |
6959 |
38 |
0 |
0 |
T113 |
7577 |
63 |
0 |
0 |
T114 |
3858 |
48 |
0 |
0 |
T115 |
234364 |
427 |
0 |
0 |
T140 |
19697 |
92 |
0 |
0 |
T141 |
13582 |
30 |
0 |
0 |
T142 |
20321 |
59 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4631 |
0 |
0 |
T92 |
31529 |
160 |
0 |
0 |
T93 |
93125 |
375 |
0 |
0 |
T108 |
11299 |
61 |
0 |
0 |
T110 |
6959 |
66 |
0 |
0 |
T113 |
7577 |
3 |
0 |
0 |
T114 |
3858 |
2 |
0 |
0 |
T115 |
234364 |
442 |
0 |
0 |
T140 |
19697 |
74 |
0 |
0 |
T141 |
13582 |
23 |
0 |
0 |
T142 |
20321 |
42 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4735 |
0 |
0 |
T92 |
31529 |
198 |
0 |
0 |
T93 |
93125 |
221 |
0 |
0 |
T106 |
3563 |
15 |
0 |
0 |
T108 |
11299 |
70 |
0 |
0 |
T110 |
6959 |
121 |
0 |
0 |
T113 |
7577 |
78 |
0 |
0 |
T114 |
3858 |
4 |
0 |
0 |
T115 |
234364 |
451 |
0 |
0 |
T140 |
19697 |
70 |
0 |
0 |
T141 |
13582 |
30 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4777 |
0 |
0 |
T92 |
31529 |
145 |
0 |
0 |
T93 |
93125 |
406 |
0 |
0 |
T108 |
11299 |
124 |
0 |
0 |
T110 |
6959 |
60 |
0 |
0 |
T113 |
7577 |
62 |
0 |
0 |
T114 |
3858 |
52 |
0 |
0 |
T115 |
234364 |
411 |
0 |
0 |
T140 |
19697 |
90 |
0 |
0 |
T141 |
13582 |
118 |
0 |
0 |
T142 |
20321 |
62 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4435 |
0 |
0 |
T92 |
31529 |
165 |
0 |
0 |
T93 |
93125 |
416 |
0 |
0 |
T106 |
3563 |
4 |
0 |
0 |
T108 |
11299 |
56 |
0 |
0 |
T110 |
6959 |
90 |
0 |
0 |
T113 |
7577 |
126 |
0 |
0 |
T114 |
3858 |
48 |
0 |
0 |
T115 |
234364 |
383 |
0 |
0 |
T140 |
19697 |
77 |
0 |
0 |
T141 |
13582 |
27 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4716 |
0 |
0 |
T92 |
31529 |
159 |
0 |
0 |
T93 |
93125 |
275 |
0 |
0 |
T97 |
15564 |
3 |
0 |
0 |
T108 |
11299 |
52 |
0 |
0 |
T110 |
6959 |
8 |
0 |
0 |
T113 |
7577 |
100 |
0 |
0 |
T114 |
3858 |
36 |
0 |
0 |
T115 |
234364 |
373 |
0 |
0 |
T140 |
19697 |
60 |
0 |
0 |
T141 |
13582 |
35 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4871 |
0 |
0 |
T92 |
31529 |
80 |
0 |
0 |
T93 |
93125 |
511 |
0 |
0 |
T108 |
11299 |
61 |
0 |
0 |
T110 |
6959 |
62 |
0 |
0 |
T113 |
7577 |
13 |
0 |
0 |
T114 |
3858 |
4 |
0 |
0 |
T115 |
234364 |
432 |
0 |
0 |
T140 |
19697 |
48 |
0 |
0 |
T141 |
13582 |
73 |
0 |
0 |
T142 |
20321 |
112 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4367 |
0 |
0 |
T92 |
31529 |
87 |
0 |
0 |
T93 |
93125 |
394 |
0 |
0 |
T108 |
11299 |
106 |
0 |
0 |
T110 |
6959 |
4 |
0 |
0 |
T113 |
7577 |
127 |
0 |
0 |
T114 |
3858 |
4 |
0 |
0 |
T115 |
234364 |
398 |
0 |
0 |
T140 |
19697 |
46 |
0 |
0 |
T141 |
13582 |
95 |
0 |
0 |
T142 |
20321 |
58 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
5113 |
0 |
0 |
T92 |
31529 |
225 |
0 |
0 |
T93 |
93125 |
441 |
0 |
0 |
T108 |
11299 |
91 |
0 |
0 |
T110 |
6959 |
2 |
0 |
0 |
T113 |
7577 |
153 |
0 |
0 |
T114 |
3858 |
2 |
0 |
0 |
T115 |
234364 |
381 |
0 |
0 |
T140 |
19697 |
46 |
0 |
0 |
T141 |
13582 |
47 |
0 |
0 |
T142 |
20321 |
64 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4421 |
0 |
0 |
T92 |
31529 |
132 |
0 |
0 |
T93 |
93125 |
439 |
0 |
0 |
T106 |
3563 |
3 |
0 |
0 |
T108 |
11299 |
153 |
0 |
0 |
T110 |
6959 |
47 |
0 |
0 |
T113 |
7577 |
60 |
0 |
0 |
T114 |
3858 |
52 |
0 |
0 |
T115 |
234364 |
443 |
0 |
0 |
T140 |
19697 |
47 |
0 |
0 |
T141 |
13582 |
84 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4616 |
0 |
0 |
T92 |
31529 |
191 |
0 |
0 |
T93 |
93125 |
340 |
0 |
0 |
T106 |
3563 |
1 |
0 |
0 |
T108 |
11299 |
120 |
0 |
0 |
T110 |
6959 |
15 |
0 |
0 |
T113 |
7577 |
66 |
0 |
0 |
T114 |
3858 |
3 |
0 |
0 |
T115 |
234364 |
323 |
0 |
0 |
T140 |
19697 |
45 |
0 |
0 |
T141 |
13582 |
71 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4786 |
0 |
0 |
T92 |
31529 |
209 |
0 |
0 |
T93 |
93125 |
555 |
0 |
0 |
T108 |
11299 |
75 |
0 |
0 |
T110 |
6959 |
35 |
0 |
0 |
T113 |
7577 |
7 |
0 |
0 |
T115 |
234364 |
382 |
0 |
0 |
T140 |
19697 |
48 |
0 |
0 |
T141 |
13582 |
4 |
0 |
0 |
T142 |
20321 |
58 |
0 |
0 |
T143 |
14897 |
109 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4678 |
0 |
0 |
T92 |
31529 |
161 |
0 |
0 |
T93 |
93125 |
369 |
0 |
0 |
T108 |
11299 |
59 |
0 |
0 |
T110 |
6959 |
91 |
0 |
0 |
T113 |
7577 |
54 |
0 |
0 |
T114 |
3858 |
52 |
0 |
0 |
T115 |
234364 |
378 |
0 |
0 |
T140 |
19697 |
52 |
0 |
0 |
T141 |
13582 |
77 |
0 |
0 |
T142 |
20321 |
70 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4823 |
0 |
0 |
T92 |
31529 |
194 |
0 |
0 |
T93 |
93125 |
357 |
0 |
0 |
T106 |
3563 |
16 |
0 |
0 |
T108 |
11299 |
109 |
0 |
0 |
T110 |
6959 |
59 |
0 |
0 |
T113 |
7577 |
12 |
0 |
0 |
T114 |
3858 |
8 |
0 |
0 |
T115 |
234364 |
407 |
0 |
0 |
T140 |
19697 |
46 |
0 |
0 |
T141 |
13582 |
53 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4839 |
0 |
0 |
T92 |
31529 |
118 |
0 |
0 |
T93 |
93125 |
320 |
0 |
0 |
T106 |
3563 |
1 |
0 |
0 |
T108 |
11299 |
108 |
0 |
0 |
T110 |
6959 |
16 |
0 |
0 |
T113 |
7577 |
10 |
0 |
0 |
T114 |
3858 |
53 |
0 |
0 |
T115 |
234364 |
457 |
0 |
0 |
T140 |
19697 |
59 |
0 |
0 |
T141 |
13582 |
50 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4929 |
0 |
0 |
T92 |
31529 |
185 |
0 |
0 |
T93 |
93125 |
407 |
0 |
0 |
T106 |
3563 |
45 |
0 |
0 |
T108 |
11299 |
105 |
0 |
0 |
T110 |
6959 |
68 |
0 |
0 |
T113 |
7577 |
68 |
0 |
0 |
T114 |
3858 |
7 |
0 |
0 |
T115 |
234364 |
403 |
0 |
0 |
T140 |
19697 |
74 |
0 |
0 |
T141 |
13582 |
41 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4500 |
0 |
0 |
T92 |
31529 |
181 |
0 |
0 |
T93 |
93125 |
250 |
0 |
0 |
T106 |
3563 |
4 |
0 |
0 |
T108 |
11299 |
65 |
0 |
0 |
T110 |
6959 |
7 |
0 |
0 |
T113 |
7577 |
3 |
0 |
0 |
T114 |
3858 |
57 |
0 |
0 |
T115 |
234364 |
348 |
0 |
0 |
T140 |
19697 |
67 |
0 |
0 |
T141 |
13582 |
47 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4588 |
0 |
0 |
T92 |
31529 |
113 |
0 |
0 |
T93 |
93125 |
322 |
0 |
0 |
T106 |
3563 |
26 |
0 |
0 |
T108 |
11299 |
64 |
0 |
0 |
T110 |
6959 |
61 |
0 |
0 |
T113 |
7577 |
94 |
0 |
0 |
T114 |
3858 |
1 |
0 |
0 |
T115 |
234364 |
378 |
0 |
0 |
T140 |
19697 |
26 |
0 |
0 |
T141 |
13582 |
26 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2130 |
0 |
0 |
T92 |
31529 |
18 |
0 |
0 |
T93 |
93125 |
123 |
0 |
0 |
T108 |
11299 |
8 |
0 |
0 |
T110 |
6959 |
16 |
0 |
0 |
T113 |
7577 |
10 |
0 |
0 |
T115 |
234364 |
406 |
0 |
0 |
T140 |
19697 |
38 |
0 |
0 |
T141 |
13582 |
22 |
0 |
0 |
T142 |
20321 |
72 |
0 |
0 |
T143 |
14897 |
28 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2124 |
0 |
0 |
T92 |
31529 |
48 |
0 |
0 |
T93 |
93125 |
83 |
0 |
0 |
T97 |
15564 |
1 |
0 |
0 |
T108 |
11299 |
18 |
0 |
0 |
T110 |
6959 |
9 |
0 |
0 |
T113 |
7577 |
3 |
0 |
0 |
T114 |
3858 |
14 |
0 |
0 |
T115 |
234364 |
379 |
0 |
0 |
T140 |
19697 |
66 |
0 |
0 |
T141 |
13582 |
25 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2132 |
0 |
0 |
T92 |
31529 |
29 |
0 |
0 |
T93 |
93125 |
90 |
0 |
0 |
T108 |
11299 |
22 |
0 |
0 |
T110 |
6959 |
8 |
0 |
0 |
T113 |
7577 |
10 |
0 |
0 |
T114 |
3858 |
5 |
0 |
0 |
T115 |
234364 |
365 |
0 |
0 |
T140 |
19697 |
82 |
0 |
0 |
T141 |
13582 |
21 |
0 |
0 |
T142 |
20321 |
68 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2320 |
0 |
0 |
T92 |
31529 |
45 |
0 |
0 |
T93 |
93125 |
96 |
0 |
0 |
T106 |
3563 |
6 |
0 |
0 |
T108 |
11299 |
34 |
0 |
0 |
T110 |
6959 |
23 |
0 |
0 |
T113 |
7577 |
20 |
0 |
0 |
T114 |
3858 |
15 |
0 |
0 |
T115 |
234364 |
400 |
0 |
0 |
T140 |
19697 |
50 |
0 |
0 |
T141 |
13582 |
7 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2518 |
0 |
0 |
T92 |
31529 |
57 |
0 |
0 |
T93 |
93125 |
137 |
0 |
0 |
T108 |
11299 |
19 |
0 |
0 |
T110 |
6959 |
7 |
0 |
0 |
T113 |
7577 |
4 |
0 |
0 |
T114 |
3858 |
16 |
0 |
0 |
T115 |
234364 |
432 |
0 |
0 |
T140 |
19697 |
71 |
0 |
0 |
T141 |
13582 |
19 |
0 |
0 |
T142 |
20321 |
62 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
4156 |
0 |
0 |
T18 |
6821 |
69 |
0 |
0 |
T19 |
4475 |
0 |
0 |
0 |
T20 |
165496 |
0 |
0 |
0 |
T47 |
0 |
59 |
0 |
0 |
T68 |
1834 |
0 |
0 |
0 |
T69 |
194528 |
0 |
0 |
0 |
T70 |
1361 |
0 |
0 |
0 |
T71 |
20861 |
0 |
0 |
0 |
T72 |
300491 |
0 |
0 |
0 |
T129 |
0 |
83 |
0 |
0 |
T132 |
0 |
21 |
0 |
0 |
T144 |
0 |
17 |
0 |
0 |
T145 |
0 |
10 |
0 |
0 |
T146 |
0 |
29 |
0 |
0 |
T147 |
0 |
35 |
0 |
0 |
T148 |
0 |
111 |
0 |
0 |
T149 |
0 |
24 |
0 |
0 |
T150 |
10870 |
0 |
0 |
0 |
T151 |
119678 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2266 |
0 |
0 |
T92 |
31529 |
27 |
0 |
0 |
T93 |
93125 |
97 |
0 |
0 |
T108 |
11299 |
16 |
0 |
0 |
T110 |
6959 |
12 |
0 |
0 |
T113 |
7577 |
16 |
0 |
0 |
T114 |
3858 |
6 |
0 |
0 |
T115 |
234364 |
453 |
0 |
0 |
T140 |
19697 |
98 |
0 |
0 |
T141 |
13582 |
15 |
0 |
0 |
T142 |
20321 |
67 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2275 |
0 |
0 |
T92 |
31529 |
56 |
0 |
0 |
T93 |
93125 |
115 |
0 |
0 |
T106 |
3563 |
3 |
0 |
0 |
T108 |
11299 |
30 |
0 |
0 |
T110 |
6959 |
14 |
0 |
0 |
T113 |
7577 |
12 |
0 |
0 |
T114 |
3858 |
1 |
0 |
0 |
T115 |
234364 |
420 |
0 |
0 |
T140 |
19697 |
58 |
0 |
0 |
T141 |
13582 |
18 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1936 |
0 |
0 |
T92 |
31529 |
31 |
0 |
0 |
T93 |
93125 |
47 |
0 |
0 |
T108 |
11299 |
8 |
0 |
0 |
T110 |
6959 |
7 |
0 |
0 |
T113 |
7577 |
5 |
0 |
0 |
T115 |
234364 |
415 |
0 |
0 |
T140 |
19697 |
80 |
0 |
0 |
T141 |
13582 |
24 |
0 |
0 |
T142 |
20321 |
53 |
0 |
0 |
T143 |
14897 |
24 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1993 |
0 |
0 |
T92 |
31529 |
17 |
0 |
0 |
T93 |
93125 |
40 |
0 |
0 |
T106 |
3563 |
7 |
0 |
0 |
T108 |
11299 |
6 |
0 |
0 |
T110 |
6959 |
1 |
0 |
0 |
T113 |
7577 |
14 |
0 |
0 |
T114 |
3858 |
7 |
0 |
0 |
T115 |
234364 |
441 |
0 |
0 |
T140 |
19697 |
48 |
0 |
0 |
T141 |
13582 |
9 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1866 |
0 |
0 |
T92 |
31529 |
13 |
0 |
0 |
T93 |
93125 |
57 |
0 |
0 |
T108 |
11299 |
16 |
0 |
0 |
T110 |
6959 |
13 |
0 |
0 |
T113 |
7577 |
5 |
0 |
0 |
T114 |
3858 |
9 |
0 |
0 |
T115 |
234364 |
423 |
0 |
0 |
T140 |
19697 |
41 |
0 |
0 |
T141 |
13582 |
4 |
0 |
0 |
T142 |
20321 |
97 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1739 |
0 |
0 |
T92 |
31529 |
35 |
0 |
0 |
T93 |
93125 |
38 |
0 |
0 |
T108 |
11299 |
14 |
0 |
0 |
T110 |
6959 |
10 |
0 |
0 |
T113 |
7577 |
7 |
0 |
0 |
T114 |
3858 |
3 |
0 |
0 |
T115 |
234364 |
399 |
0 |
0 |
T140 |
19697 |
61 |
0 |
0 |
T141 |
13582 |
20 |
0 |
0 |
T142 |
20321 |
64 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2650 |
0 |
0 |
T92 |
31529 |
18 |
0 |
0 |
T93 |
93125 |
159 |
0 |
0 |
T106 |
3563 |
1 |
0 |
0 |
T108 |
11299 |
34 |
0 |
0 |
T110 |
6959 |
24 |
0 |
0 |
T113 |
7577 |
10 |
0 |
0 |
T114 |
3858 |
1 |
0 |
0 |
T115 |
234364 |
416 |
0 |
0 |
T140 |
19697 |
49 |
0 |
0 |
T141 |
13582 |
35 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1983 |
0 |
0 |
T92 |
31529 |
24 |
0 |
0 |
T93 |
93125 |
70 |
0 |
0 |
T108 |
11299 |
23 |
0 |
0 |
T110 |
6959 |
8 |
0 |
0 |
T113 |
7577 |
8 |
0 |
0 |
T114 |
3858 |
8 |
0 |
0 |
T115 |
234364 |
377 |
0 |
0 |
T140 |
19697 |
72 |
0 |
0 |
T141 |
13582 |
7 |
0 |
0 |
T142 |
20321 |
49 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2940 |
0 |
0 |
T92 |
31529 |
51 |
0 |
0 |
T93 |
93125 |
221 |
0 |
0 |
T106 |
3563 |
4 |
0 |
0 |
T108 |
11299 |
35 |
0 |
0 |
T110 |
6959 |
10 |
0 |
0 |
T113 |
7577 |
38 |
0 |
0 |
T115 |
234364 |
419 |
0 |
0 |
T140 |
19697 |
85 |
0 |
0 |
T141 |
13582 |
19 |
0 |
0 |
T142 |
20321 |
59 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2263 |
0 |
0 |
T92 |
31529 |
27 |
0 |
0 |
T93 |
93125 |
104 |
0 |
0 |
T106 |
3563 |
9 |
0 |
0 |
T108 |
11299 |
21 |
0 |
0 |
T110 |
6959 |
13 |
0 |
0 |
T113 |
7577 |
4 |
0 |
0 |
T114 |
3858 |
15 |
0 |
0 |
T115 |
234364 |
347 |
0 |
0 |
T140 |
19697 |
63 |
0 |
0 |
T141 |
13582 |
11 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1889 |
0 |
0 |
T92 |
31529 |
19 |
0 |
0 |
T93 |
93125 |
48 |
0 |
0 |
T108 |
11299 |
10 |
0 |
0 |
T110 |
6959 |
13 |
0 |
0 |
T113 |
7577 |
4 |
0 |
0 |
T114 |
3858 |
7 |
0 |
0 |
T115 |
234364 |
387 |
0 |
0 |
T140 |
19697 |
77 |
0 |
0 |
T141 |
13582 |
13 |
0 |
0 |
T142 |
20321 |
53 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1807 |
0 |
0 |
T92 |
31529 |
26 |
0 |
0 |
T93 |
93125 |
34 |
0 |
0 |
T106 |
3563 |
3 |
0 |
0 |
T108 |
11299 |
9 |
0 |
0 |
T110 |
6959 |
9 |
0 |
0 |
T113 |
7577 |
5 |
0 |
0 |
T114 |
3858 |
5 |
0 |
0 |
T115 |
234364 |
376 |
0 |
0 |
T140 |
19697 |
80 |
0 |
0 |
T141 |
13582 |
12 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1999 |
0 |
0 |
T89 |
13965 |
2 |
0 |
0 |
T92 |
31529 |
5 |
0 |
0 |
T93 |
93125 |
66 |
0 |
0 |
T106 |
3563 |
1 |
0 |
0 |
T108 |
11299 |
11 |
0 |
0 |
T110 |
6959 |
9 |
0 |
0 |
T113 |
7577 |
2 |
0 |
0 |
T114 |
3858 |
3 |
0 |
0 |
T140 |
19697 |
98 |
0 |
0 |
T141 |
13582 |
2 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1906 |
0 |
0 |
T92 |
31529 |
22 |
0 |
0 |
T93 |
93125 |
56 |
0 |
0 |
T106 |
3563 |
8 |
0 |
0 |
T108 |
11299 |
15 |
0 |
0 |
T110 |
6959 |
5 |
0 |
0 |
T113 |
7577 |
4 |
0 |
0 |
T114 |
3858 |
1 |
0 |
0 |
T115 |
234364 |
463 |
0 |
0 |
T140 |
19697 |
115 |
0 |
0 |
T141 |
13582 |
19 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
2055 |
0 |
0 |
T92 |
31529 |
16 |
0 |
0 |
T93 |
93125 |
65 |
0 |
0 |
T106 |
3563 |
5 |
0 |
0 |
T108 |
11299 |
23 |
0 |
0 |
T110 |
6959 |
6 |
0 |
0 |
T113 |
7577 |
4 |
0 |
0 |
T114 |
3858 |
4 |
0 |
0 |
T115 |
234364 |
413 |
0 |
0 |
T140 |
19697 |
42 |
0 |
0 |
T141 |
13582 |
12 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
399230258 |
1805 |
0 |
0 |
T92 |
31529 |
14 |
0 |
0 |
T93 |
93125 |
67 |
0 |
0 |
T106 |
3563 |
9 |
0 |
0 |
T108 |
11299 |
9 |
0 |
0 |
T110 |
6959 |
12 |
0 |
0 |
T113 |
7577 |
5 |
0 |
0 |
T114 |
3858 |
2 |
0 |
0 |
T115 |
234364 |
370 |
0 |
0 |
T140 |
19697 |
35 |
0 |
0 |
T141 |
13582 |
2 |
0 |
0 |