Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3790993	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4046050

1

T1

2912

T2

1882

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4561429	1			T1	4045		T2	1989		T3	1
values[0x0]	1639079	1			T1	474		T2	437		T3	2
values[0x1]	1636535	1			T1	438		T2	454		T4	480

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2691238	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5145805

1

T1

3288

T2

2083

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29342	1			T2	66		T5	288		T8	3
valid_sources[0x01]	29443	1			T1	31		T5	333		T8	5
valid_sources[0x02]	31605	1			T1	4		T2	15		T5	352
valid_sources[0x03]	30202	1			T1	16		T2	13		T4	1265
valid_sources[0x04]	34699	1			T1	3		T2	54		T5	314
valid_sources[0x05]	30073	1			T1	35		T2	26		T5	388
valid_sources[0x06]	37031	1			T1	32		T5	387		T8	3
valid_sources[0x07]	27302	1			T1	13		T5	316		T6	1
valid_sources[0x08]	31522	1			T1	32		T2	5		T5	365
valid_sources[0x09]	26870	1			T1	27		T5	354		T6	2
valid_sources[0x0a]	36122	1			T1	16		T2	28		T5	372
valid_sources[0x0b]	35250	1			T1	17		T5	411		T6	1
valid_sources[0x0c]	30721	1			T1	2		T5	357		T8	11
valid_sources[0x0d]	27796	1			T1	31		T2	32		T5	328
valid_sources[0x0e]	35250	1			T1	35		T5	389		T6	1
valid_sources[0x0f]	31377	1			T1	12		T2	144		T5	337
valid_sources[0x10]	31549	1			T1	9		T5	318		T8	3
valid_sources[0x11]	29441	1			T1	27		T5	385		T6	1
valid_sources[0x12]	27428	1			T1	30		T5	327		T8	4
valid_sources[0x13]	29655	1			T1	28		T2	28		T5	304
valid_sources[0x14]	31630	1			T1	16		T5	357		T8	3
valid_sources[0x15]	29742	1			T1	36		T5	348		T8	6
valid_sources[0x16]	33794	1			T1	11		T5	333		T6	2
valid_sources[0x17]	27997	1			T1	18		T2	51		T5	368
valid_sources[0x18]	29265	1			T1	4		T5	395		T6	1
valid_sources[0x19]	31899	1			T1	5		T5	382		T6	1
valid_sources[0x1a]	30270	1			T1	2		T5	275		T6	1
valid_sources[0x1b]	35007	1			T1	49		T2	88		T5	321
valid_sources[0x1c]	30709	1			T1	18		T5	324		T6	1
valid_sources[0x1d]	27407	1			T1	16		T5	363		T6	1
valid_sources[0x1e]	29491	1			T1	9		T5	302		T8	9
valid_sources[0x1f]	33540	1			T1	19		T5	339		T6	1
valid_sources[0x20]	27430	1			T1	11		T2	12		T5	312
valid_sources[0x21]	27428	1			T1	9		T5	321		T6	1
valid_sources[0x22]	55973	1			T1	11		T5	308		T6	1
valid_sources[0x23]	30138	1			T1	5		T5	354		T8	2
valid_sources[0x24]	27503	1			T1	5		T2	19		T5	388
valid_sources[0x25]	32826	1			T1	14		T5	380		T8	3
valid_sources[0x26]	28688	1			T1	31		T2	78		T5	354
valid_sources[0x27]	30932	1			T5	284		T8	8		T9	5
valid_sources[0x28]	30483	1			T1	43		T2	31		T5	353
valid_sources[0x29]	31870	1			T1	65		T5	370		T6	1
valid_sources[0x2a]	30057	1			T1	38		T5	391		T6	1
valid_sources[0x2b]	29219	1			T1	18		T5	297		T8	10
valid_sources[0x2c]	29681	1			T1	22		T5	360		T6	2
valid_sources[0x2d]	28801	1			T1	41		T2	18		T5	399
valid_sources[0x2e]	35296	1			T1	14		T5	300		T6	1
valid_sources[0x2f]	32749	1			T1	28		T5	340		T6	1
valid_sources[0x30]	39090	1			T1	37		T2	3		T5	324
valid_sources[0x31]	30908	1			T1	9		T5	311		T8	3
valid_sources[0x32]	34146	1			T1	3		T5	305		T6	1
valid_sources[0x33]	28499	1			T1	47		T5	259		T6	2
valid_sources[0x34]	29734	1			T1	8		T5	400		T8	9
valid_sources[0x35]	30369	1			T1	9		T2	6		T5	368
valid_sources[0x36]	27746	1			T1	31		T5	330		T6	2
valid_sources[0x37]	28024	1			T1	4		T2	97		T5	331
valid_sources[0x38]	35899	1			T1	7		T5	344		T6	1
valid_sources[0x39]	29901	1			T1	39		T5	330		T8	4
valid_sources[0x3a]	32444	1			T1	22		T5	375		T6	2
valid_sources[0x3b]	29080	1			T1	14		T2	35		T5	366
valid_sources[0x3c]	31170	1			T1	10		T5	341		T6	1
valid_sources[0x3d]	32703	1			T1	14		T5	316		T6	1
valid_sources[0x3e]	31614	1			T1	6		T2	5		T5	337
valid_sources[0x3f]	29873	1			T1	1		T5	378		T6	1
valid_sources[0x40]	28230	1			T1	12		T5	270		T8	4
valid_sources[0x41]	27859	1			T1	7		T2	14		T5	385
valid_sources[0x42]	31080	1			T1	18		T2	1		T5	353
valid_sources[0x43]	27317	1			T1	39		T2	25		T5	302
valid_sources[0x44]	28604	1			T1	22		T5	351		T6	1
valid_sources[0x45]	30235	1			T1	30		T5	423		T6	1
valid_sources[0x46]	32395	1			T1	16		T2	4		T5	291
valid_sources[0x47]	30939	1			T1	7		T5	268		T6	1
valid_sources[0x48]	36662	1			T5	347		T8	8		T10	27
valid_sources[0x49]	28193	1			T1	24		T5	344		T8	3
valid_sources[0x4a]	33635	1			T1	9		T5	294		T6	2
valid_sources[0x4b]	29856	1			T1	4		T5	335		T8	5
valid_sources[0x4c]	30705	1			T5	355		T8	6		T9	5
valid_sources[0x4d]	29278	1			T1	11		T2	37		T5	395
valid_sources[0x4e]	31092	1			T1	16		T3	1		T5	421
valid_sources[0x4f]	45095	1			T1	14		T5	327		T6	1
valid_sources[0x50]	29180	1			T1	3		T5	309		T8	6
valid_sources[0x51]	29796	1			T1	22		T5	388		T6	1
valid_sources[0x52]	28983	1			T1	42		T5	367		T8	16
valid_sources[0x53]	29666	1			T1	6		T5	432		T8	8
valid_sources[0x54]	29477	1			T1	8		T2	5		T5	288
valid_sources[0x55]	29384	1			T1	46		T2	15		T5	280
valid_sources[0x56]	30726	1			T1	9		T5	308		T8	6
valid_sources[0x57]	30356	1			T1	14		T5	384		T8	7
valid_sources[0x58]	28523	1			T1	25		T5	302		T8	6
valid_sources[0x59]	27426	1			T1	33		T5	330		T8	3
valid_sources[0x5a]	29086	1			T1	40		T2	64		T5	323
valid_sources[0x5b]	28845	1			T1	19		T5	373		T8	5
valid_sources[0x5c]	31697	1			T1	20		T5	294		T6	1
valid_sources[0x5d]	29315	1			T1	4		T5	343		T6	2
valid_sources[0x5e]	29542	1			T1	51		T2	3		T5	360
valid_sources[0x5f]	28642	1			T1	7		T2	33		T5	320
valid_sources[0x60]	30765	1			T1	57		T5	401		T6	1
valid_sources[0x61]	29730	1			T1	3		T2	10		T5	380
valid_sources[0x62]	28474	1			T1	29		T5	424		T8	7
valid_sources[0x63]	28728	1			T1	6		T5	365		T6	2
valid_sources[0x64]	30861	1			T5	272		T8	8		T9	13
valid_sources[0x65]	28842	1			T1	2		T2	1		T3	1
valid_sources[0x66]	28833	1			T1	9		T5	315		T8	1
valid_sources[0x67]	35321	1			T1	40		T2	61		T5	369
valid_sources[0x68]	31288	1			T1	36		T4	469		T5	349
valid_sources[0x69]	32138	1			T1	17		T5	331		T8	4
valid_sources[0x6a]	29351	1			T5	353		T8	3		T9	10
valid_sources[0x6b]	31397	1			T1	3		T5	369		T6	1
valid_sources[0x6c]	28494	1			T1	27		T2	49		T5	293
valid_sources[0x6d]	30197	1			T1	22		T5	310		T8	3
valid_sources[0x6e]	28489	1			T1	15		T5	372		T8	8
valid_sources[0x6f]	28853	1			T1	30		T5	341		T6	3
valid_sources[0x70]	30196	1			T1	22		T5	352		T8	10
valid_sources[0x71]	28501	1			T2	28		T5	328		T6	1
valid_sources[0x72]	39513	1			T1	11		T2	28		T5	275
valid_sources[0x73]	29726	1			T1	19		T5	300		T8	13
valid_sources[0x74]	32200	1			T1	29		T5	364		T8	4
valid_sources[0x75]	30073	1			T1	44		T5	398		T6	1
valid_sources[0x76]	28294	1			T1	25		T5	333		T7	906
valid_sources[0x77]	29811	1			T1	75		T5	334		T6	2
valid_sources[0x78]	31266	1			T2	29		T5	323		T6	1
valid_sources[0x79]	29257	1			T1	21		T5	306		T6	1
valid_sources[0x7a]	50125	1			T1	3		T5	315		T6	1
valid_sources[0x7b]	29472	1			T1	29		T2	29		T5	319
valid_sources[0x7c]	29026	1			T1	6		T5	394		T6	3
valid_sources[0x7d]	26641	1			T1	37		T5	320		T8	8
valid_sources[0x7e]	30007	1			T1	1		T2	3		T5	284
valid_sources[0x7f]	27492	1			T1	27		T5	308		T6	1
valid_sources[0x80]	29516	1			T1	26		T2	85		T5	362

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1107419

1

T1

2010

T2

1002

T3

1

values[0x0]

all_enables

biggest_size

1482368

1

T1

471

T2

433

T3

1

values[0x1]

all_enables

biggest_size

1456263

1

T1

431

T2

447

T4

474