Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3810369

1

T1

2045

T2

998

T3

1

full_word

4045060

1

T1

2912

T2

1882

T3

2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7855059	1			T1	4957		T2	2880		T3	3
auto[TlIntgErrCmd]	116	1			T89	13		T93	3		T94	7
auto[TlIntgErrData]	132	1			T89	6		T93	5		T94	11
auto[TlIntgErrBoth]	122	1			T89	11		T93	2		T94	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4562548

1

T1

4045

T2

1989

T3

1

auto[1]

3292881

1

T1

912

T2

891

T3

2

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3454885	1			T1	2035		T2	987		T4	662
auto[TlIntgErrNone]	partial	auto[1]	355145	1			T1	10		T2	11		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	1107496	1			T1	2010		T2	1002		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	2937533	1			T1	902		T2	880		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T89	6		T93	1		T94	4
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T89	7		T93	1		T94	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T93	1		T94	1		T109	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T107	1		T163	3		T162	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T89	3		T93	2		T94	7
auto[TlIntgErrData]	partial	auto[1]	60	1			T89	2		T93	3		T94	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T89	1		T164	1		T165	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T103	1		T164	1		T165	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T89	4		T93	1		T94	3
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T89	7		T94	8		T107	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T94	1		T107	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T93	1		T107	2		T162	1