Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410570707	2442521	0	0
DepthKnown_A	410570707	410443847	0	0
RvalidKnown_A	410570707	410443847	0	0
WreadyKnown_A	410570707	410443847	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	2442521	0	0
T1	95006	1663	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	1663	0	0
T5	424309	10812	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	1663	0	0
T10	158688	0	0	0
T11	0	1663	0	0
T13	0	9160	0	0
T14	0	14139	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410570707	2618691	0	0
DepthKnown_A	410570707	410443847	0	0
RvalidKnown_A	410570707	410443847	0	0
WreadyKnown_A	410570707	410443847	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	2618691	0	0
T1	95006	832	0	0
T2	79593	3842	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	7488	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	3735	0	0
T9	31615	832	0	0
T10	158688	0	0	0
T11	0	832	0	0
T13	0	21744	0	0
T14	0	9984	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410570707	172107	0	0
DepthKnown_A	410570707	410443847	0	0
RvalidKnown_A	410570707	410443847	0	0
WreadyKnown_A	410570707	410443847	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	172107	0	0
T5	424309	1158	0	0
T6	3932	0	0	0
T7	284084	0	0	0
T8	30308	0	0	0
T9	31615	0	0	0
T10	158688	817	0	0
T11	123673	0	0	0
T12	5101	16	0	0
T13	281496	929	0	0
T14	523954	769	0	0
T15	0	2968	0	0
T26	0	378	0	0
T29	0	78	0	0
T38	0	416	0	0
T39	0	99	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410570707	400103	0	0
DepthKnown_A	410570707	410443847	0	0
RvalidKnown_A	410570707	410443847	0	0
WreadyKnown_A	410570707	410443847	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	400103	0	0
T5	424309	1158	0	0
T6	3932	0	0	0
T7	284084	0	0	0
T8	30308	0	0	0
T9	31615	0	0	0
T10	158688	3731	0	0
T11	123673	0	0	0
T12	5101	65	0	0
T13	281496	4289	0	0
T14	523954	769	0	0
T15	0	12639	0	0
T26	0	1167	0	0
T29	0	207	0	0
T38	0	1263	0	0
T39	0	293	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410570707	6495989	0	0
DepthKnown_A	410570707	410443847	0	0
RvalidKnown_A	410570707	410443847	0	0
WreadyKnown_A	410570707	410443847	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	6495989	0	0
T1	95006	4125	0	0
T2	79593	2048	0	0
T3	847	3	0	0
T4	41530	1361	0	0
T5	424309	78911	0	0
T6	3932	170	0	0
T7	284084	74	0	0
T8	30308	653	0	0
T9	31615	1033	0	0
T10	158688	6413	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	410570707	13339484	0	0
DepthKnown_A	410570707	410443847	0	0
RvalidKnown_A	410570707	410443847	0	0
WreadyKnown_A	410570707	410443847	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	13339484	0	0
T1	95006	4125	0	0
T2	79593	8862	0	0
T3	847	17	0	0
T4	41530	5590	0	0
T5	424309	78525	0	0
T6	3932	170	0	0
T7	284084	74	0	0
T8	30308	2887	0	0
T9	31615	1033	0	0
T10	158688	26357	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410570707	410443847	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0