Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Unreachable
1	1	Covered	T5,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T14
1	0	Covered	T5,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	669318460	537621969	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	669318460	3213093	0	0
GntImpliesValid_A	669318460	3213093	0	0
GrantKnown_A	669318460	537621969	0	0
IdxKnown_A	669318460	537621969	0	0
IndexIsCorrect_A	669318460	3213093	0	0
LockArbDecision_A	669318460	0	0	0
NoReadyValidNoGrant_A	669318460	0	0	0
ReadyAndValidImplyGrant_A	669318460	3213093	0	0
ReqAndReadyImplyGrant_A	669318460	3213093	0	0
ReqImpliesValid_A	669318460	3213093	0	0
ReqStaysHighUntilGranted0_M	669318460	0	0	0
RoundRobin_A	669318460	4	0	926
ValidKnown_A	669318460	537621969	0	0
gen_data_port_assertion.DataFlow_A	669318460	3213093	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	537621969	0	0
T1	185343	184978	0	0
T2	96759	96186	0	0
T3	847	792	0	0
T4	48920	48625	0	0
T5	2106325	1259329	0	0
T6	3932	3793	0	0
T7	421122	352133	0	0
T8	161124	95303	0	0
T9	58655	44618	0	0
T10	1031476	592139	0	0
T11	40334	19970	0	0
T12	1280	640	0	0
T13	470602	465860	0	0
T14	809546	805771	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	3213093	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	2106325	19059	0	0
T6	3932	0	0	0
T7	421122	832	0	0
T8	161124	832	0	0
T9	58655	832	0	0
T10	1031476	7934	0	0
T11	40334	832	0	0
T12	1280	83	0	0
T13	941204	7142	0	0
T14	1619092	11956	0	0
T15	0	18293	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T38	0	3888	0	0
T39	0	403	0	0
T43	0	11	0	0
T47	79928	0	0	0
T50	0	1933	0	0
T51	0	5373	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	3213093	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	2106325	19059	0	0
T6	3932	0	0	0
T7	421122	832	0	0
T8	161124	832	0	0
T9	58655	832	0	0
T10	1031476	7934	0	0
T11	40334	832	0	0
T12	1280	83	0	0
T13	941204	7142	0	0
T14	1619092	11956	0	0
T15	0	18293	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T38	0	3888	0	0
T39	0	403	0	0
T43	0	11	0	0
T47	79928	0	0	0
T50	0	1933	0	0
T51	0	5373	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	537621969	0	0
T1	185343	184978	0	0
T2	96759	96186	0	0
T3	847	792	0	0
T4	48920	48625	0	0
T5	2106325	1259329	0	0
T6	3932	3793	0	0
T7	421122	352133	0	0
T8	161124	95303	0	0
T9	58655	44618	0	0
T10	1031476	592139	0	0
T11	40334	19970	0	0
T12	1280	640	0	0
T13	470602	465860	0	0
T14	809546	805771	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	537621969	0	0
T1	185343	184978	0	0
T2	96759	96186	0	0
T3	847	792	0	0
T4	48920	48625	0	0
T5	2106325	1259329	0	0
T6	3932	3793	0	0
T7	421122	352133	0	0
T8	161124	95303	0	0
T9	58655	44618	0	0
T10	1031476	592139	0	0
T11	40334	19970	0	0
T12	1280	640	0	0
T13	470602	465860	0	0
T14	809546	805771	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	3213093	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	2106325	19059	0	0
T6	3932	0	0	0
T7	421122	832	0	0
T8	161124	832	0	0
T9	58655	832	0	0
T10	1031476	7934	0	0
T11	40334	832	0	0
T12	1280	83	0	0
T13	941204	7142	0	0
T14	1619092	11956	0	0
T15	0	18293	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T38	0	3888	0	0
T39	0	403	0	0
T43	0	11	0	0
T47	79928	0	0	0
T50	0	1933	0	0
T51	0	5373	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	3213093	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	2106325	19059	0	0
T6	3932	0	0	0
T7	421122	832	0	0
T8	161124	832	0	0
T9	58655	832	0	0
T10	1031476	7934	0	0
T11	40334	832	0	0
T12	1280	83	0	0
T13	941204	7142	0	0
T14	1619092	11956	0	0
T15	0	18293	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T38	0	3888	0	0
T39	0	403	0	0
T43	0	11	0	0
T47	79928	0	0	0
T50	0	1933	0	0
T51	0	5373	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	3213093	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	2106325	19059	0	0
T6	3932	0	0	0
T7	421122	832	0	0
T8	161124	832	0	0
T9	58655	832	0	0
T10	1031476	7934	0	0
T11	40334	832	0	0
T12	1280	83	0	0
T13	941204	7142	0	0
T14	1619092	11956	0	0
T15	0	18293	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T38	0	3888	0	0
T39	0	403	0	0
T43	0	11	0	0
T47	79928	0	0	0
T50	0	1933	0	0
T51	0	5373	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	3213093	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	2106325	19059	0	0
T6	3932	0	0	0
T7	421122	832	0	0
T8	161124	832	0	0
T9	58655	832	0	0
T10	1031476	7934	0	0
T11	40334	832	0	0
T12	1280	83	0	0
T13	941204	7142	0	0
T14	1619092	11956	0	0
T15	0	18293	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T38	0	3888	0	0
T39	0	403	0	0
T43	0	11	0	0
T47	79928	0	0	0
T50	0	1933	0	0
T51	0	5373	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	4	0	926
T15	183519	1	0	1
T35	1439	0	0	1
T40	502790	0	0	1
T50	733896	0	0	1
T51	884605	0	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	448823	0	0	1
T56	234550	0	0	1
T57	211774	0	0	1
T58	63788	0	0	1
T59	1381	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	537621969	0	0
T1	185343	184978	0	0
T2	96759	96186	0	0
T3	847	792	0	0
T4	48920	48625	0	0
T5	2106325	1259329	0	0
T6	3932	3793	0	0
T7	421122	352133	0	0
T8	161124	95303	0	0
T9	58655	44618	0	0
T10	1031476	592139	0	0
T11	40334	19970	0	0
T12	1280	640	0	0
T13	470602	465860	0	0
T14	809546	805771	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	669318460	3213093	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	2106325	19059	0	0
T6	3932	0	0	0
T7	421122	832	0	0
T8	161124	832	0	0
T9	58655	832	0	0
T10	1031476	7934	0	0
T11	40334	832	0	0
T12	1280	83	0	0
T13	941204	7142	0	0
T14	1619092	11956	0	0
T15	0	18293	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T38	0	3888	0	0
T39	0	403	0	0
T43	0	11	0	0
T47	79928	0	0	0
T50	0	1933	0	0
T51	0	5373	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T5,T10,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T12
1	0	Unreachable
1	1	Covered	T5,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T10,T12
0	0	1	Unreachable
0	0	0	Covered	T5,T10,T12

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	130393436	25379751	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	130393436	596096	0	0
GntImpliesValid_A	130393436	596096	0	0
GrantKnown_A	130393436	25379751	0	0
IdxKnown_A	130393436	25379751	0	0
IndexIsCorrect_A	130393436	596096	0	0
LockArbDecision_A	130393436	0	0	0
NoReadyValidNoGrant_A	130393436	0	0	0
ReadyAndValidImplyGrant_A	130393436	596096	0	0
ReqAndReadyImplyGrant_A	130393436	596096	0	0
ReqImpliesValid_A	130393436	596096	0	0
ReqStaysHighUntilGranted0_M	130393436	0	0	0
RoundRobin_A	130393436	0	0	0
ValidKnown_A	130393436	25379751	0	0
gen_data_port_assertion.DataFlow_A	130393436	596096	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	25379751	0	0
T5	841008	124200	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	433512	0	0
T11	20167	0	0	0
T12	640	640	0	0
T13	470602	81432	0	0
T14	809546	0	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	596096	0	0
T5	841008	5476	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	5217	0	0
T11	20167	0	0	0
T12	640	66	0	0
T13	470602	3650	0	0
T14	809546	0	0	0
T15	0	15148	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T47	39964	0	0	0
T50	0	803	0	0
T51	0	5373	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	596096	0	0
T5	841008	5476	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	5217	0	0
T11	20167	0	0	0
T12	640	66	0	0
T13	470602	3650	0	0
T14	809546	0	0	0
T15	0	15148	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T47	39964	0	0	0
T50	0	803	0	0
T51	0	5373	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	25379751	0	0
T5	841008	124200	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	433512	0	0
T11	20167	0	0	0
T12	640	640	0	0
T13	470602	81432	0	0
T14	809546	0	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	25379751	0	0
T5	841008	124200	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	433512	0	0
T11	20167	0	0	0
T12	640	640	0	0
T13	470602	81432	0	0
T14	809546	0	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	596096	0	0
T5	841008	5476	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	5217	0	0
T11	20167	0	0	0
T12	640	66	0	0
T13	470602	3650	0	0
T14	809546	0	0	0
T15	0	15148	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T47	39964	0	0	0
T50	0	803	0	0
T51	0	5373	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	596096	0	0
T5	841008	5476	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	5217	0	0
T11	20167	0	0	0
T12	640	66	0	0
T13	470602	3650	0	0
T14	809546	0	0	0
T15	0	15148	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T47	39964	0	0	0
T50	0	803	0	0
T51	0	5373	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	596096	0	0
T5	841008	5476	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	5217	0	0
T11	20167	0	0	0
T12	640	66	0	0
T13	470602	3650	0	0
T14	809546	0	0	0
T15	0	15148	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T47	39964	0	0	0
T50	0	803	0	0
T51	0	5373	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	596096	0	0
T5	841008	5476	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	5217	0	0
T11	20167	0	0	0
T12	640	66	0	0
T13	470602	3650	0	0
T14	809546	0	0	0
T15	0	15148	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T47	39964	0	0	0
T50	0	803	0	0
T51	0	5373	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	25379751	0	0
T5	841008	124200	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	433512	0	0
T11	20167	0	0	0
T12	640	640	0	0
T13	470602	81432	0	0
T14	809546	0	0	0
T24	0	216	0	0
T25	0	160	0	0
T26	0	71144	0	0
T27	0	119000	0	0
T28	0	576	0	0
T29	0	13520	0	0
T47	39964	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	596096	0	0
T5	841008	5476	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	5217	0	0
T11	20167	0	0	0
T12	640	66	0	0
T13	470602	3650	0	0
T14	809546	0	0	0
T15	0	15148	0	0
T25	0	4	0	0
T26	0	1936	0	0
T29	0	472	0	0
T47	39964	0	0	0
T50	0	803	0	0
T51	0	5373	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T13,T14
1	0	Covered	T5,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T13,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	130393436	103794983	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	130393436	672366	0	0
GntImpliesValid_A	130393436	672366	0	0
GrantKnown_A	130393436	103794983	0	0
IdxKnown_A	130393436	103794983	0	0
IndexIsCorrect_A	130393436	672366	0	0
LockArbDecision_A	130393436	0	0	0
NoReadyValidNoGrant_A	130393436	0	0	0
ReadyAndValidImplyGrant_A	130393436	672366	0	0
ReqAndReadyImplyGrant_A	130393436	672366	0	0
ReqImpliesValid_A	130393436	672366	0	0
ReqStaysHighUntilGranted0_M	130393436	0	0	0
RoundRobin_A	130393436	0	0	0
ValidKnown_A	130393436	103794983	0	0
gen_data_port_assertion.DataFlow_A	130393436	672366	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	103794983	0	0
T1	90337	90054	0	0
T2	17166	16662	0	0
T4	7390	7152	0	0
T5	841008	710826	0	0
T7	68519	68112	0	0
T8	65408	65072	0	0
T9	13520	13096	0	0
T10	436394	0	0	0
T11	20167	19970	0	0
T12	640	0	0	0
T13	0	384428	0	0
T14	0	805771	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	672366	0	0
T5	841008	3078	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	0	0	0
T11	20167	0	0	0
T12	640	0	0	0
T13	470602	3492	0	0
T14	809546	11956	0	0
T15	0	3145	0	0
T16	0	8569	0	0
T38	0	3888	0	0
T39	0	403	0	0
T40	0	2285	0	0
T43	0	11	0	0
T47	39964	0	0	0
T50	0	1130	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	672366	0	0
T5	841008	3078	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	0	0	0
T11	20167	0	0	0
T12	640	0	0	0
T13	470602	3492	0	0
T14	809546	11956	0	0
T15	0	3145	0	0
T16	0	8569	0	0
T38	0	3888	0	0
T39	0	403	0	0
T40	0	2285	0	0
T43	0	11	0	0
T47	39964	0	0	0
T50	0	1130	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	103794983	0	0
T1	90337	90054	0	0
T2	17166	16662	0	0
T4	7390	7152	0	0
T5	841008	710826	0	0
T7	68519	68112	0	0
T8	65408	65072	0	0
T9	13520	13096	0	0
T10	436394	0	0	0
T11	20167	19970	0	0
T12	640	0	0	0
T13	0	384428	0	0
T14	0	805771	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	103794983	0	0
T1	90337	90054	0	0
T2	17166	16662	0	0
T4	7390	7152	0	0
T5	841008	710826	0	0
T7	68519	68112	0	0
T8	65408	65072	0	0
T9	13520	13096	0	0
T10	436394	0	0	0
T11	20167	19970	0	0
T12	640	0	0	0
T13	0	384428	0	0
T14	0	805771	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	672366	0	0
T5	841008	3078	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	0	0	0
T11	20167	0	0	0
T12	640	0	0	0
T13	470602	3492	0	0
T14	809546	11956	0	0
T15	0	3145	0	0
T16	0	8569	0	0
T38	0	3888	0	0
T39	0	403	0	0
T40	0	2285	0	0
T43	0	11	0	0
T47	39964	0	0	0
T50	0	1130	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	672366	0	0
T5	841008	3078	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	0	0	0
T11	20167	0	0	0
T12	640	0	0	0
T13	470602	3492	0	0
T14	809546	11956	0	0
T15	0	3145	0	0
T16	0	8569	0	0
T38	0	3888	0	0
T39	0	403	0	0
T40	0	2285	0	0
T43	0	11	0	0
T47	39964	0	0	0
T50	0	1130	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	672366	0	0
T5	841008	3078	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	0	0	0
T11	20167	0	0	0
T12	640	0	0	0
T13	470602	3492	0	0
T14	809546	11956	0	0
T15	0	3145	0	0
T16	0	8569	0	0
T38	0	3888	0	0
T39	0	403	0	0
T40	0	2285	0	0
T43	0	11	0	0
T47	39964	0	0	0
T50	0	1130	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	672366	0	0
T5	841008	3078	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	0	0	0
T11	20167	0	0	0
T12	640	0	0	0
T13	470602	3492	0	0
T14	809546	11956	0	0
T15	0	3145	0	0
T16	0	8569	0	0
T38	0	3888	0	0
T39	0	403	0	0
T40	0	2285	0	0
T43	0	11	0	0
T47	39964	0	0	0
T50	0	1130	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	103794983	0	0
T1	90337	90054	0	0
T2	17166	16662	0	0
T4	7390	7152	0	0
T5	841008	710826	0	0
T7	68519	68112	0	0
T8	65408	65072	0	0
T9	13520	13096	0	0
T10	436394	0	0	0
T11	20167	19970	0	0
T12	640	0	0	0
T13	0	384428	0	0
T14	0	805771	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130393436	672366	0	0
T5	841008	3078	0	0
T7	68519	0	0	0
T8	65408	0	0	0
T9	13520	0	0	0
T10	436394	0	0	0
T11	20167	0	0	0
T12	640	0	0	0
T13	470602	3492	0	0
T14	809546	11956	0	0
T15	0	3145	0	0
T16	0	8569	0	0
T38	0	3888	0	0
T39	0	403	0	0
T40	0	2285	0	0
T43	0	11	0	0
T47	39964	0	0	0
T50	0	1130	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T10,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T10,T12
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408531588	408447235	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	408531588	1944631	0	0
GntImpliesValid_A	408531588	1944631	0	0
GrantKnown_A	408531588	408447235	0	0
IdxKnown_A	408531588	408447235	0	0
IndexIsCorrect_A	408531588	1944631	0	0
LockArbDecision_A	408531588	0	0	0
NoReadyValidNoGrant_A	408531588	0	0	0
ReadyAndValidImplyGrant_A	408531588	1944631	0	0
ReqAndReadyImplyGrant_A	408531588	1944631	0	0
ReqImpliesValid_A	408531588	1944631	0	0
ReqStaysHighUntilGranted0_M	408531588	0	0	0
RoundRobin_A	408531588	4	0	926
ValidKnown_A	408531588	408447235	0	0
gen_data_port_assertion.DataFlow_A	408531588	1944631	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	408447235	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	1944631	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	10505	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	832	0	0
T10	158688	2717	0	0
T11	0	832	0	0
T12	0	17	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	1944631	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	10505	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	832	0	0
T10	158688	2717	0	0
T11	0	832	0	0
T12	0	17	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	408447235	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	408447235	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	1944631	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	10505	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	832	0	0
T10	158688	2717	0	0
T11	0	832	0	0
T12	0	17	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	1944631	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	10505	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	832	0	0
T10	158688	2717	0	0
T11	0	832	0	0
T12	0	17	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	1944631	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	10505	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	832	0	0
T10	158688	2717	0	0
T11	0	832	0	0
T12	0	17	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	1944631	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	10505	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	832	0	0
T10	158688	2717	0	0
T11	0	832	0	0
T12	0	17	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	4	0	926
T15	183519	1	0	1
T35	1439	0	0	1
T40	502790	0	0	1
T50	733896	0	0	1
T51	884605	0	0	1
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	448823	0	0	1
T56	234550	0	0	1
T57	211774	0	0	1
T58	63788	0	0	1
T59	1381	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	408447235	0	0
T1	95006	94924	0	0
T2	79593	79524	0	0
T3	847	792	0	0
T4	41530	41473	0	0
T5	424309	424303	0	0
T6	3932	3793	0	0
T7	284084	284021	0	0
T8	30308	30231	0	0
T9	31615	31522	0	0
T10	158688	158627	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408531588	1944631	0	0
T1	95006	832	0	0
T2	79593	832	0	0
T3	847	0	0	0
T4	41530	832	0	0
T5	424309	10505	0	0
T6	3932	0	0	0
T7	284084	832	0	0
T8	30308	832	0	0
T9	31615	832	0	0
T10	158688	2717	0	0
T11	0	832	0	0
T12	0	17	0	0