Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3569638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3877642

1

T1

7307

T2

891

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4181119	1			T1	5582		T2	7		T3	1
values[0x0]	1632805	1			T1	3178		T2	428		T3	14
values[0x1]	1633356	1			T1	3222		T2	462		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2520219	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4927061

1

T1

8743

T2

892

T3

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28184	1			T1	40		T5	1		T7	36
valid_sources[0x01]	26626	1			T1	46		T5	11		T7	39
valid_sources[0x02]	34414	1			T1	49		T5	4		T6	1
valid_sources[0x03]	28780	1			T1	50		T5	15		T6	9
valid_sources[0x04]	31689	1			T1	40		T5	18		T6	2
valid_sources[0x05]	29872	1			T1	47		T3	2		T5	12
valid_sources[0x06]	28086	1			T1	29		T5	7		T7	40
valid_sources[0x07]	28389	1			T1	42		T5	18		T7	33
valid_sources[0x08]	29758	1			T1	40		T5	8		T7	51
valid_sources[0x09]	29368	1			T1	45		T5	5		T6	4
valid_sources[0x0a]	30881	1			T1	58		T5	5		T7	36
valid_sources[0x0b]	27917	1			T1	61		T5	3		T7	31
valid_sources[0x0c]	26729	1			T1	37		T6	1		T7	39
valid_sources[0x0d]	29834	1			T1	56		T5	11		T7	33
valid_sources[0x0e]	27728	1			T1	52		T5	1		T7	41
valid_sources[0x0f]	26277	1			T1	38		T5	8		T7	45
valid_sources[0x10]	27278	1			T1	35		T5	8		T6	3
valid_sources[0x11]	27548	1			T1	35		T5	7		T7	45
valid_sources[0x12]	29061	1			T1	47		T5	13		T7	37
valid_sources[0x13]	27227	1			T1	43		T5	3		T6	1
valid_sources[0x14]	27439	1			T1	50		T5	6		T7	44
valid_sources[0x15]	30319	1			T1	49		T5	9		T6	3
valid_sources[0x16]	27938	1			T1	62		T5	3		T7	27
valid_sources[0x17]	28210	1			T1	40		T5	3		T6	2
valid_sources[0x18]	27929	1			T1	38		T7	55		T8	4
valid_sources[0x19]	31458	1			T1	55		T5	1		T6	3
valid_sources[0x1a]	33470	1			T1	43		T7	52		T8	5
valid_sources[0x1b]	28071	1			T1	43		T3	2		T5	18
valid_sources[0x1c]	30935	1			T1	52		T5	6		T7	48
valid_sources[0x1d]	27364	1			T1	55		T5	2		T6	1
valid_sources[0x1e]	27177	1			T1	44		T5	2		T6	2
valid_sources[0x1f]	26528	1			T1	43		T5	4		T7	31
valid_sources[0x20]	28295	1			T1	44		T5	2		T7	41
valid_sources[0x21]	35310	1			T1	33		T5	3		T6	1
valid_sources[0x22]	25778	1			T1	53		T6	9		T7	50
valid_sources[0x23]	26120	1			T1	50		T5	3		T7	29
valid_sources[0x24]	27991	1			T1	50		T5	6		T7	43
valid_sources[0x25]	28708	1			T1	39		T5	3		T6	5
valid_sources[0x26]	27308	1			T1	40		T5	1		T6	2
valid_sources[0x27]	31304	1			T1	49		T5	5		T7	36
valid_sources[0x28]	27749	1			T1	48		T6	1		T7	44
valid_sources[0x29]	28617	1			T1	34		T7	36		T8	2
valid_sources[0x2a]	26182	1			T1	50		T5	3		T7	31
valid_sources[0x2b]	28276	1			T1	39		T5	13		T7	42
valid_sources[0x2c]	30167	1			T1	41		T5	1		T6	3
valid_sources[0x2d]	26341	1			T1	42		T5	13		T7	54
valid_sources[0x2e]	26002	1			T1	49		T5	15		T7	41
valid_sources[0x2f]	32056	1			T1	39		T5	4		T7	44
valid_sources[0x30]	26444	1			T1	51		T5	3		T7	36
valid_sources[0x31]	29354	1			T1	55		T5	3		T6	3
valid_sources[0x32]	65764	1			T1	43		T6	4		T7	47
valid_sources[0x33]	27680	1			T1	34		T5	1		T6	3
valid_sources[0x34]	29493	1			T1	54		T5	13		T7	39
valid_sources[0x35]	29050	1			T1	48		T5	6		T6	8
valid_sources[0x36]	26347	1			T1	43		T5	2		T7	42
valid_sources[0x37]	28050	1			T1	72		T5	2		T6	2
valid_sources[0x38]	27311	1			T1	34		T5	12		T6	2
valid_sources[0x39]	26446	1			T1	50		T7	37		T8	2
valid_sources[0x3a]	27254	1			T1	45		T5	17		T7	39
valid_sources[0x3b]	26199	1			T1	42		T6	2		T7	57
valid_sources[0x3c]	25453	1			T1	45		T5	3		T7	31
valid_sources[0x3d]	28466	1			T1	50		T5	1		T7	43
valid_sources[0x3e]	29649	1			T1	35		T5	7		T7	60
valid_sources[0x3f]	27943	1			T1	58		T5	5		T7	56
valid_sources[0x40]	26243	1			T1	38		T6	4		T7	48
valid_sources[0x41]	26056	1			T1	43		T5	5		T7	34
valid_sources[0x42]	30213	1			T1	50		T5	8		T7	55
valid_sources[0x43]	27393	1			T1	34		T5	6		T7	24
valid_sources[0x44]	29296	1			T1	55		T5	2		T7	45
valid_sources[0x45]	31836	1			T1	47		T5	7		T7	35
valid_sources[0x46]	28637	1			T1	47		T6	9		T7	38
valid_sources[0x47]	31536	1			T1	50		T7	45		T8	2
valid_sources[0x48]	27832	1			T1	48		T5	3		T6	1
valid_sources[0x49]	31118	1			T1	47		T4	451		T5	2
valid_sources[0x4a]	25997	1			T1	50		T5	10		T7	36
valid_sources[0x4b]	28581	1			T1	71		T5	9		T7	45
valid_sources[0x4c]	29504	1			T1	51		T5	9		T7	49
valid_sources[0x4d]	24886	1			T1	49		T5	1		T7	40
valid_sources[0x4e]	27914	1			T1	47		T7	47		T8	3
valid_sources[0x4f]	28160	1			T1	59		T5	5		T6	8
valid_sources[0x50]	30500	1			T1	52		T5	5		T6	2
valid_sources[0x51]	31146	1			T1	59		T5	4		T7	50
valid_sources[0x52]	25690	1			T1	46		T5	1		T7	41
valid_sources[0x53]	27626	1			T1	47		T6	2		T7	49
valid_sources[0x54]	29276	1			T1	58		T5	4		T6	3
valid_sources[0x55]	27903	1			T1	56		T5	6		T7	27
valid_sources[0x56]	27910	1			T1	38		T5	9		T7	44
valid_sources[0x57]	26090	1			T1	51		T5	4		T6	1
valid_sources[0x58]	26921	1			T1	51		T5	3		T7	44
valid_sources[0x59]	32826	1			T1	35		T5	18		T6	1
valid_sources[0x5a]	29841	1			T1	55		T5	3		T6	1
valid_sources[0x5b]	27199	1			T1	57		T5	6		T7	43
valid_sources[0x5c]	28693	1			T1	45		T5	7		T7	35
valid_sources[0x5d]	30164	1			T1	41		T6	1		T7	38
valid_sources[0x5e]	28871	1			T1	48		T6	4		T7	61
valid_sources[0x5f]	26930	1			T1	46		T5	20		T6	1
valid_sources[0x60]	27950	1			T1	57		T5	15		T6	4
valid_sources[0x61]	26844	1			T1	65		T5	20		T7	32
valid_sources[0x62]	31512	1			T1	54		T7	58		T8	2
valid_sources[0x63]	26127	1			T1	65		T5	4		T7	40
valid_sources[0x64]	28842	1			T1	54		T5	1		T6	7
valid_sources[0x65]	28676	1			T1	52		T3	1		T5	4
valid_sources[0x66]	28835	1			T1	43		T5	10		T6	5
valid_sources[0x67]	30856	1			T1	40		T5	4		T7	45
valid_sources[0x68]	26922	1			T1	45		T5	6		T6	2
valid_sources[0x69]	27781	1			T1	39		T3	1		T5	4
valid_sources[0x6a]	25158	1			T1	42		T6	3		T7	38
valid_sources[0x6b]	35942	1			T1	43		T6	4		T7	57
valid_sources[0x6c]	26814	1			T1	36		T5	7		T7	31
valid_sources[0x6d]	28799	1			T1	43		T7	42		T8	6
valid_sources[0x6e]	28618	1			T1	44		T7	35		T8	4
valid_sources[0x6f]	26684	1			T1	52		T5	6		T7	27
valid_sources[0x70]	29569	1			T1	45		T5	8		T7	43
valid_sources[0x71]	29237	1			T1	57		T5	2		T6	7
valid_sources[0x72]	27998	1			T1	61		T5	9		T7	60
valid_sources[0x73]	28682	1			T1	45		T5	6		T7	31
valid_sources[0x74]	26717	1			T1	40		T5	6		T6	9
valid_sources[0x75]	28530	1			T1	45		T7	32		T8	4
valid_sources[0x76]	25087	1			T1	47		T7	43		T8	3
valid_sources[0x77]	25492	1			T1	42		T7	40		T8	5
valid_sources[0x78]	30608	1			T1	49		T5	5		T7	42
valid_sources[0x79]	27024	1			T1	46		T5	6		T7	35
valid_sources[0x7a]	27746	1			T1	39		T5	6		T7	45
valid_sources[0x7b]	27111	1			T1	54		T5	10		T7	38
valid_sources[0x7c]	32106	1			T1	39		T5	7		T6	3
valid_sources[0x7d]	27325	1			T1	54		T7	38		T8	6
valid_sources[0x7e]	28598	1			T1	47		T5	3		T6	2
valid_sources[0x7f]	28038	1			T1	49		T7	39		T8	6
valid_sources[0x80]	30607	1			T1	37		T7	56		T8	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

944367

1

T1

1383

T2

4

T3

1

values[0x0]

all_enables

biggest_size

1478030

1

T1

2960

T2

426

T3

6

values[0x1]

all_enables

biggest_size

1455245

1

T1

2964

T2

461

T3

2