Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3587856

1

T1

4675

T2

6

T3

17

full_word

3876660

1

T1

7307

T2

891

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7464136	1			T1	11982		T2	897		T3	26
auto[TlIntgErrCmd]	139	1			T95	2		T96	8		T97	3
auto[TlIntgErrData]	124	1			T95	2		T96	5		T97	4
auto[TlIntgErrBoth]	117	1			T95	6		T96	7		T97	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4182158

1

T1

5582

T2

7

T3

1

auto[1]

3282358

1

T1

6400

T2

890

T3

25

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3237602	1			T1	4199		T2	3		T4	4614
auto[TlIntgErrNone]	partial	auto[1]	349907	1			T1	476		T2	3		T3	17
auto[TlIntgErrNone]	full_word	auto[0]	944405	1			T1	1383		T2	4		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	2932222	1			T1	5924		T2	887		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T95	1		T96	2		T97	2
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T96	6		T97	1		T109	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T95	1		T145	1		T104	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T109	1		T168	1		T144	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T96	1		T97	2		T109	1
auto[TlIntgErrData]	partial	auto[1]	63	1			T95	2		T96	3		T97	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T96	1		T168	2		T144	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T97	1		T167	1		T145	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T95	2		T96	3		T97	2
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T95	3		T96	4		T97	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T144	1		T167	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T95	1		T109	1		T144	1