Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411613258	2439185	0	0
DepthKnown_A	411613258	411488391	0	0
RvalidKnown_A	411613258	411488391	0	0
WreadyKnown_A	411613258	411488391	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	2439185	0	0
T1	915000	6653	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	1663	0	0
T5	133658	1663	0	0
T6	218974	0	0	0
T7	834855	13306	0	0
T8	3125	1663	0	0
T9	102435	1663	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411613258	2592837	0	0
DepthKnown_A	411613258	411488391	0	0
RvalidKnown_A	411613258	411488391	0	0
WreadyKnown_A	411613258	411488391	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	2592837	0	0
T1	915000	4160	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	832	0	0
T6	218974	0	0	0
T7	834855	8320	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411613258	168142	0	0
DepthKnown_A	411613258	411488391	0	0
RvalidKnown_A	411613258	411488391	0	0
WreadyKnown_A	411613258	411488391	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	168142	0	0
T1	915000	640	0	0
T2	75303	0	0	0
T3	1040	0	0	0
T4	314147	0	0	0
T5	133658	256	0	0
T6	218974	0	0	0
T7	834855	684	0	0
T8	3125	0	0	0
T9	102435	0	0	0
T10	1486	0	0	0
T15	0	100	0	0
T18	0	1112	0	0
T29	0	520	0	0
T30	0	27	0	0
T32	0	16	0	0
T43	0	100	0	0
T47	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411613258	383287	0	0
DepthKnown_A	411613258	411488391	0	0
RvalidKnown_A	411613258	411488391	0	0
WreadyKnown_A	411613258	411488391	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	383287	0	0
T1	915000	640	0	0
T2	75303	0	0	0
T3	1040	0	0	0
T4	314147	0	0	0
T5	133658	1184	0	0
T6	218974	0	0	0
T7	834855	684	0	0
T8	3125	0	0	0
T9	102435	0	0	0
T10	1486	0	0	0
T15	0	100	0	0
T18	0	1112	0	0
T29	0	520	0	0
T30	0	27	0	0
T32	0	16	0	0
T43	0	100	0	0
T47	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411613258	6128304	0	0
DepthKnown_A	411613258	411488391	0	0
RvalidKnown_A	411613258	411488391	0	0
WreadyKnown_A	411613258	411488391	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	6128304	0	0
T1	915000	7249	0	0
T2	75303	65	0	0
T3	1040	26	0	0
T4	314147	9358	0	0
T5	133658	296	0	0
T6	218974	374	0	0
T7	834855	1859	0	0
T8	3125	45	0	0
T9	102435	3745	0	0
T10	1486	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	411613258	13555135	0	0
DepthKnown_A	411613258	411488391	0	0
RvalidKnown_A	411613258	411488391	0	0
WreadyKnown_A	411613258	411488391	0	0
gen_passthru_fifo.paramCheckPass	1100	1100	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	13555135	0	0
T1	915000	7182	0	0
T2	75303	65	0	0
T3	1040	96	0	0
T4	314147	9358	0	0
T5	133658	1303	0	0
T6	218974	1723	0	0
T7	834855	1857	0	0
T8	3125	45	0	0
T9	102435	11291	0	0
T10	1486	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	411613258	411488391	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1100	1100	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0