Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T32,T15
1	0	Covered	T1,T15,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T12
1	0	Unreachable
1	1	Covered	T1,T32,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	663378893	535134229	0	0
CheckNGreaterZero_A	2775	2775	0	0
GntImpliesReady_A	663378893	3222856	0	0
GntImpliesValid_A	663378893	3222856	0	0
GrantKnown_A	663378893	535134229	0	0
IdxKnown_A	663378893	535134229	0	0
IndexIsCorrect_A	663378893	3222856	0	0
LockArbDecision_A	663378893	0	0	0
NoReadyValidNoGrant_A	663378893	0	0	0
ReadyAndValidImplyGrant_A	663378893	3222856	0	0
ReqAndReadyImplyGrant_A	663378893	3222856	0	0
ReqImpliesValid_A	663378893	3222856	0	0
ReqStaysHighUntilGranted0_M	663378893	0	0	0
RoundRobin_A	663378893	4	0	925
ValidKnown_A	663378893	535134229	0	0
gen_data_port_assertion.DataFlow_A	663378893	3222856	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	535134229	0	0
T1	1273292	1092404	0	0
T2	211723	143415	0	0
T3	1040	975	0	0
T4	403011	358480	0	0
T5	371250	252370	0	0
T6	326350	270822	0	0
T7	2358363	1593189	0	0
T8	3125	3030	0	0
T9	127299	114770	0	0
T10	1486	1390	0	0
T11	30864	15432	0	0
T12	2114	936	0	0
T13	87756	41512	0	0
T14	0	5280	0	0
T15	0	586208	0	0
T16	0	40048	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2775	2775	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	3222856	0	0
T1	1273292	8924	0	0
T2	211723	832	0	0
T3	1040	0	0	0
T4	403011	832	0	0
T5	371250	7484	0	0
T6	326350	0	0	0
T7	2358363	23012	0	0
T8	3125	832	0	0
T9	127299	832	0	0
T10	1486	0	0	0
T11	30864	832	0	0
T12	2114	0	0	0
T13	87756	0	0	0
T14	0	832	0	0
T15	0	688	0	0
T18	0	7160	0	0
T19	0	9171	0	0
T29	0	5260	0	0
T30	0	143	0	0
T32	0	64	0	0
T43	0	200	0	0
T46	0	792	0	0
T47	0	5606	0	0
T55	0	2861	0	0
T56	0	3928	0	0
T57	0	3744	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	3222856	0	0
T1	1273292	8924	0	0
T2	211723	832	0	0
T3	1040	0	0	0
T4	403011	832	0	0
T5	371250	7484	0	0
T6	326350	0	0	0
T7	2358363	23012	0	0
T8	3125	832	0	0
T9	127299	832	0	0
T10	1486	0	0	0
T11	30864	832	0	0
T12	2114	0	0	0
T13	87756	0	0	0
T14	0	832	0	0
T15	0	688	0	0
T18	0	7160	0	0
T19	0	9171	0	0
T29	0	5260	0	0
T30	0	143	0	0
T32	0	64	0	0
T43	0	200	0	0
T46	0	792	0	0
T47	0	5606	0	0
T55	0	2861	0	0
T56	0	3928	0	0
T57	0	3744	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	535134229	0	0
T1	1273292	1092404	0	0
T2	211723	143415	0	0
T3	1040	975	0	0
T4	403011	358480	0	0
T5	371250	252370	0	0
T6	326350	270822	0	0
T7	2358363	1593189	0	0
T8	3125	3030	0	0
T9	127299	114770	0	0
T10	1486	1390	0	0
T11	30864	15432	0	0
T12	2114	936	0	0
T13	87756	41512	0	0
T14	0	5280	0	0
T15	0	586208	0	0
T16	0	40048	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	535134229	0	0
T1	1273292	1092404	0	0
T2	211723	143415	0	0
T3	1040	975	0	0
T4	403011	358480	0	0
T5	371250	252370	0	0
T6	326350	270822	0	0
T7	2358363	1593189	0	0
T8	3125	3030	0	0
T9	127299	114770	0	0
T10	1486	1390	0	0
T11	30864	15432	0	0
T12	2114	936	0	0
T13	87756	41512	0	0
T14	0	5280	0	0
T15	0	586208	0	0
T16	0	40048	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	3222856	0	0
T1	1273292	8924	0	0
T2	211723	832	0	0
T3	1040	0	0	0
T4	403011	832	0	0
T5	371250	7484	0	0
T6	326350	0	0	0
T7	2358363	23012	0	0
T8	3125	832	0	0
T9	127299	832	0	0
T10	1486	0	0	0
T11	30864	832	0	0
T12	2114	0	0	0
T13	87756	0	0	0
T14	0	832	0	0
T15	0	688	0	0
T18	0	7160	0	0
T19	0	9171	0	0
T29	0	5260	0	0
T30	0	143	0	0
T32	0	64	0	0
T43	0	200	0	0
T46	0	792	0	0
T47	0	5606	0	0
T55	0	2861	0	0
T56	0	3928	0	0
T57	0	3744	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	3222856	0	0
T1	1273292	8924	0	0
T2	211723	832	0	0
T3	1040	0	0	0
T4	403011	832	0	0
T5	371250	7484	0	0
T6	326350	0	0	0
T7	2358363	23012	0	0
T8	3125	832	0	0
T9	127299	832	0	0
T10	1486	0	0	0
T11	30864	832	0	0
T12	2114	0	0	0
T13	87756	0	0	0
T14	0	832	0	0
T15	0	688	0	0
T18	0	7160	0	0
T19	0	9171	0	0
T29	0	5260	0	0
T30	0	143	0	0
T32	0	64	0	0
T43	0	200	0	0
T46	0	792	0	0
T47	0	5606	0	0
T55	0	2861	0	0
T56	0	3928	0	0
T57	0	3744	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	3222856	0	0
T1	1273292	8924	0	0
T2	211723	832	0	0
T3	1040	0	0	0
T4	403011	832	0	0
T5	371250	7484	0	0
T6	326350	0	0	0
T7	2358363	23012	0	0
T8	3125	832	0	0
T9	127299	832	0	0
T10	1486	0	0	0
T11	30864	832	0	0
T12	2114	0	0	0
T13	87756	0	0	0
T14	0	832	0	0
T15	0	688	0	0
T18	0	7160	0	0
T19	0	9171	0	0
T29	0	5260	0	0
T30	0	143	0	0
T32	0	64	0	0
T43	0	200	0	0
T46	0	792	0	0
T47	0	5606	0	0
T55	0	2861	0	0
T56	0	3928	0	0
T57	0	3744	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	3222856	0	0
T1	1273292	8924	0	0
T2	211723	832	0	0
T3	1040	0	0	0
T4	403011	832	0	0
T5	371250	7484	0	0
T6	326350	0	0	0
T7	2358363	23012	0	0
T8	3125	832	0	0
T9	127299	832	0	0
T10	1486	0	0	0
T11	30864	832	0	0
T12	2114	0	0	0
T13	87756	0	0	0
T14	0	832	0	0
T15	0	688	0	0
T18	0	7160	0	0
T19	0	9171	0	0
T29	0	5260	0	0
T30	0	143	0	0
T32	0	64	0	0
T43	0	200	0	0
T46	0	792	0	0
T47	0	5606	0	0
T55	0	2861	0	0
T56	0	3928	0	0
T57	0	3744	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	4	0	925
T24	4634	0	0	1
T58	443477	1	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	46686	0	0	1
T63	1603	0	0	1
T64	69847	0	0	1
T65	8573	0	0	1
T66	287864	0	0	1
T67	1887	0	0	1
T68	4804	0	0	1
T69	1436	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	535134229	0	0
T1	1273292	1092404	0	0
T2	211723	143415	0	0
T3	1040	975	0	0
T4	403011	358480	0	0
T5	371250	252370	0	0
T6	326350	270822	0	0
T7	2358363	1593189	0	0
T8	3125	3030	0	0
T9	127299	114770	0	0
T10	1486	1390	0	0
T11	30864	15432	0	0
T12	2114	936	0	0
T13	87756	41512	0	0
T14	0	5280	0	0
T15	0	586208	0	0
T16	0	40048	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	663378893	3222856	0	0
T1	1273292	8924	0	0
T2	211723	832	0	0
T3	1040	0	0	0
T4	403011	832	0	0
T5	371250	7484	0	0
T6	326350	0	0	0
T7	2358363	23012	0	0
T8	3125	832	0	0
T9	127299	832	0	0
T10	1486	0	0	0
T11	30864	832	0	0
T12	2114	0	0	0
T13	87756	0	0	0
T14	0	832	0	0
T15	0	688	0	0
T18	0	7160	0	0
T19	0	9171	0	0
T29	0	5260	0	0
T30	0	143	0	0
T32	0	64	0	0
T43	0	200	0	0
T46	0	792	0	0
T47	0	5606	0	0
T55	0	2861	0	0
T56	0	3928	0	0
T57	0	3744	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T32,T15
1	0	Covered	T1,T15,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T12
1	0	Unreachable
1	1	Covered	T1,T32,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T32,T15
0	0	1	Unreachable
0	0	0	Covered	T1,T6,T12

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126913957	27279256	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	126913957	603710	0	0
GntImpliesValid_A	126913957	603710	0	0
GrantKnown_A	126913957	27279256	0	0
IdxKnown_A	126913957	27279256	0	0
IndexIsCorrect_A	126913957	603710	0	0
LockArbDecision_A	126913957	0	0	0
NoReadyValidNoGrant_A	126913957	0	0	0
ReadyAndValidImplyGrant_A	126913957	603710	0	0
ReqAndReadyImplyGrant_A	126913957	603710	0	0
ReqImpliesValid_A	126913957	603710	0	0
ReqStaysHighUntilGranted0_M	126913957	0	0	0
RoundRobin_A	126913957	0	0	0
ValidKnown_A	126913957	27279256	0	0
gen_data_port_assertion.DataFlow_A	126913957	603710	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	27279256	0	0
T1	179146	19376	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	51944	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	936	0	0
T13	43878	41512	0	0
T15	0	15768	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	603710	0	0
T1	179146	766	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	0	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	419	0	0
T18	0	2279	0	0
T19	0	5533	0	0
T29	0	1898	0	0
T30	0	143	0	0
T32	0	64	0	0
T55	0	2861	0	0
T56	0	3282	0	0
T57	0	3744	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	603710	0	0
T1	179146	766	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	0	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	419	0	0
T18	0	2279	0	0
T19	0	5533	0	0
T29	0	1898	0	0
T30	0	143	0	0
T32	0	64	0	0
T55	0	2861	0	0
T56	0	3282	0	0
T57	0	3744	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	27279256	0	0
T1	179146	19376	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	51944	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	936	0	0
T13	43878	41512	0	0
T15	0	15768	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	27279256	0	0
T1	179146	19376	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	51944	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	936	0	0
T13	43878	41512	0	0
T15	0	15768	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	603710	0	0
T1	179146	766	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	0	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	419	0	0
T18	0	2279	0	0
T19	0	5533	0	0
T29	0	1898	0	0
T30	0	143	0	0
T32	0	64	0	0
T55	0	2861	0	0
T56	0	3282	0	0
T57	0	3744	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	603710	0	0
T1	179146	766	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	0	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	419	0	0
T18	0	2279	0	0
T19	0	5533	0	0
T29	0	1898	0	0
T30	0	143	0	0
T32	0	64	0	0
T55	0	2861	0	0
T56	0	3282	0	0
T57	0	3744	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	603710	0	0
T1	179146	766	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	0	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	419	0	0
T18	0	2279	0	0
T19	0	5533	0	0
T29	0	1898	0	0
T30	0	143	0	0
T32	0	64	0	0
T55	0	2861	0	0
T56	0	3282	0	0
T57	0	3744	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	603710	0	0
T1	179146	766	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	0	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	419	0	0
T18	0	2279	0	0
T19	0	5533	0	0
T29	0	1898	0	0
T30	0	143	0	0
T32	0	64	0	0
T55	0	2861	0	0
T56	0	3282	0	0
T57	0	3744	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	27279256	0	0
T1	179146	19376	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	51944	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	936	0	0
T13	43878	41512	0	0
T15	0	15768	0	0
T18	0	49712	0	0
T28	0	360	0	0
T29	0	79176	0	0
T30	0	2672	0	0
T32	0	552	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	603710	0	0
T1	179146	766	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	0	0	0
T6	53688	0	0	0
T7	761754	0	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	419	0	0
T18	0	2279	0	0
T19	0	5533	0	0
T29	0	1898	0	0
T30	0	143	0	0
T32	0	64	0	0
T55	0	2861	0	0
T56	0	3282	0	0
T57	0	3744	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	126913957	98385149	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	126913957	674334	0	0
GntImpliesValid_A	126913957	674334	0	0
GrantKnown_A	126913957	98385149	0	0
IdxKnown_A	126913957	98385149	0	0
IndexIsCorrect_A	126913957	674334	0	0
LockArbDecision_A	126913957	0	0	0
NoReadyValidNoGrant_A	126913957	0	0	0
ReadyAndValidImplyGrant_A	126913957	674334	0	0
ReqAndReadyImplyGrant_A	126913957	674334	0	0
ReqImpliesValid_A	126913957	674334	0	0
ReqStaysHighUntilGranted0_M	126913957	0	0	0
RoundRobin_A	126913957	0	0	0
ValidKnown_A	126913957	98385149	0	0
gen_data_port_assertion.DataFlow_A	126913957	674334	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	98385149	0	0
T1	179146	158091	0	0
T2	68210	68210	0	0
T4	44432	44432	0	0
T5	118796	118796	0	0
T6	53688	0	0	0
T7	761754	758392	0	0
T9	12432	12432	0	0
T11	15432	15432	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T14	0	5280	0	0
T15	0	570440	0	0
T16	0	40048	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	674334	0	0
T1	179146	3015	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	6388	0	0
T6	53688	0	0	0
T7	761754	13981	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	269	0	0
T18	0	4881	0	0
T19	0	3638	0	0
T29	0	3362	0	0
T46	0	792	0	0
T47	0	5606	0	0
T56	0	646	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	674334	0	0
T1	179146	3015	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	6388	0	0
T6	53688	0	0	0
T7	761754	13981	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	269	0	0
T18	0	4881	0	0
T19	0	3638	0	0
T29	0	3362	0	0
T46	0	792	0	0
T47	0	5606	0	0
T56	0	646	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	98385149	0	0
T1	179146	158091	0	0
T2	68210	68210	0	0
T4	44432	44432	0	0
T5	118796	118796	0	0
T6	53688	0	0	0
T7	761754	758392	0	0
T9	12432	12432	0	0
T11	15432	15432	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T14	0	5280	0	0
T15	0	570440	0	0
T16	0	40048	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	98385149	0	0
T1	179146	158091	0	0
T2	68210	68210	0	0
T4	44432	44432	0	0
T5	118796	118796	0	0
T6	53688	0	0	0
T7	761754	758392	0	0
T9	12432	12432	0	0
T11	15432	15432	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T14	0	5280	0	0
T15	0	570440	0	0
T16	0	40048	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	674334	0	0
T1	179146	3015	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	6388	0	0
T6	53688	0	0	0
T7	761754	13981	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	269	0	0
T18	0	4881	0	0
T19	0	3638	0	0
T29	0	3362	0	0
T46	0	792	0	0
T47	0	5606	0	0
T56	0	646	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	674334	0	0
T1	179146	3015	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	6388	0	0
T6	53688	0	0	0
T7	761754	13981	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	269	0	0
T18	0	4881	0	0
T19	0	3638	0	0
T29	0	3362	0	0
T46	0	792	0	0
T47	0	5606	0	0
T56	0	646	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	674334	0	0
T1	179146	3015	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	6388	0	0
T6	53688	0	0	0
T7	761754	13981	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	269	0	0
T18	0	4881	0	0
T19	0	3638	0	0
T29	0	3362	0	0
T46	0	792	0	0
T47	0	5606	0	0
T56	0	646	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	674334	0	0
T1	179146	3015	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	6388	0	0
T6	53688	0	0	0
T7	761754	13981	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	269	0	0
T18	0	4881	0	0
T19	0	3638	0	0
T29	0	3362	0	0
T46	0	792	0	0
T47	0	5606	0	0
T56	0	646	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	98385149	0	0
T1	179146	158091	0	0
T2	68210	68210	0	0
T4	44432	44432	0	0
T5	118796	118796	0	0
T6	53688	0	0	0
T7	761754	758392	0	0
T9	12432	12432	0	0
T11	15432	15432	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T14	0	5280	0	0
T15	0	570440	0	0
T16	0	40048	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126913957	674334	0	0
T1	179146	3015	0	0
T2	68210	0	0	0
T4	44432	0	0	0
T5	118796	6388	0	0
T6	53688	0	0	0
T7	761754	13981	0	0
T9	12432	0	0	0
T11	15432	0	0	0
T12	1057	0	0	0
T13	43878	0	0	0
T15	0	269	0	0
T18	0	4881	0	0
T19	0	3638	0	0
T29	0	3362	0	0
T46	0	792	0	0
T47	0	5606	0	0
T56	0	646	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	409550979	409469824	0	0
CheckNGreaterZero_A	925	925	0	0
GntImpliesReady_A	409550979	1944812	0	0
GntImpliesValid_A	409550979	1944812	0	0
GrantKnown_A	409550979	409469824	0	0
IdxKnown_A	409550979	409469824	0	0
IndexIsCorrect_A	409550979	1944812	0	0
LockArbDecision_A	409550979	0	0	0
NoReadyValidNoGrant_A	409550979	0	0	0
ReadyAndValidImplyGrant_A	409550979	1944812	0	0
ReqAndReadyImplyGrant_A	409550979	1944812	0	0
ReqImpliesValid_A	409550979	1944812	0	0
ReqStaysHighUntilGranted0_M	409550979	0	0	0
RoundRobin_A	409550979	4	0	925
ValidKnown_A	409550979	409469824	0	0
gen_data_port_assertion.DataFlow_A	409550979	1944812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	409469824	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	925	925	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	1944812	0	0
T1	915000	5143	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	1096	0	0
T6	218974	0	0	0
T7	834855	9031	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	200	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	1944812	0	0
T1	915000	5143	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	1096	0	0
T6	218974	0	0	0
T7	834855	9031	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	200	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	409469824	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	409469824	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	1944812	0	0
T1	915000	5143	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	1096	0	0
T6	218974	0	0	0
T7	834855	9031	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	200	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	1944812	0	0
T1	915000	5143	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	1096	0	0
T6	218974	0	0	0
T7	834855	9031	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	200	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	1944812	0	0
T1	915000	5143	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	1096	0	0
T6	218974	0	0	0
T7	834855	9031	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	200	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	1944812	0	0
T1	915000	5143	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	1096	0	0
T6	218974	0	0	0
T7	834855	9031	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	200	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	4	0	925
T24	4634	0	0	1
T58	443477	1	0	1
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	46686	0	0	1
T63	1603	0	0	1
T64	69847	0	0	1
T65	8573	0	0	1
T66	287864	0	0	1
T67	1887	0	0	1
T68	4804	0	0	1
T69	1436	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	409469824	0	0
T1	915000	914937	0	0
T2	75303	75205	0	0
T3	1040	975	0	0
T4	314147	314048	0	0
T5	133658	133574	0	0
T6	218974	218878	0	0
T7	834855	834797	0	0
T8	3125	3030	0	0
T9	102435	102338	0	0
T10	1486	1390	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409550979	1944812	0	0
T1	915000	5143	0	0
T2	75303	832	0	0
T3	1040	0	0	0
T4	314147	832	0	0
T5	133658	1096	0	0
T6	218974	0	0	0
T7	834855	9031	0	0
T8	3125	832	0	0
T9	102435	832	0	0
T10	1486	0	0	0
T11	0	832	0	0
T14	0	832	0	0
T43	0	200	0	0