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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.20


Total test records in report: 1100
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1017 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1596421569 Jun 24 05:04:56 PM PDT 24 Jun 24 05:04:58 PM PDT 24 38224598 ps
T1018 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1899253629 Jun 24 05:04:19 PM PDT 24 Jun 24 05:04:22 PM PDT 24 104034143 ps
T1019 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1551357748 Jun 24 05:04:34 PM PDT 24 Jun 24 05:04:36 PM PDT 24 24209161 ps
T1020 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4221953556 Jun 24 05:04:13 PM PDT 24 Jun 24 05:04:15 PM PDT 24 11043803 ps
T144 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2781286440 Jun 24 05:04:40 PM PDT 24 Jun 24 05:05:04 PM PDT 24 2055275671 ps
T167 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1242762114 Jun 24 05:04:42 PM PDT 24 Jun 24 05:05:06 PM PDT 24 907637936 ps
T146 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3907059028 Jun 24 05:04:40 PM PDT 24 Jun 24 05:04:43 PM PDT 24 57680693 ps
T1021 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1832852736 Jun 24 05:04:45 PM PDT 24 Jun 24 05:04:47 PM PDT 24 14249969 ps
T119 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3759247829 Jun 24 05:04:45 PM PDT 24 Jun 24 05:04:48 PM PDT 24 97595490 ps
T106 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.296688031 Jun 24 05:04:26 PM PDT 24 Jun 24 05:04:31 PM PDT 24 644392920 ps
T1022 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3304667726 Jun 24 05:04:55 PM PDT 24 Jun 24 05:04:57 PM PDT 24 18148203 ps
T164 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1767217576 Jun 24 05:04:20 PM PDT 24 Jun 24 05:04:35 PM PDT 24 737259016 ps
T145 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.484761207 Jun 24 05:04:51 PM PDT 24 Jun 24 05:05:08 PM PDT 24 5741430854 ps
T104 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3534650633 Jun 24 05:04:08 PM PDT 24 Jun 24 05:04:27 PM PDT 24 289030157 ps
T147 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.406804268 Jun 24 05:04:34 PM PDT 24 Jun 24 05:04:38 PM PDT 24 519302250 ps
T1023 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2603947182 Jun 24 05:04:06 PM PDT 24 Jun 24 05:04:08 PM PDT 24 19163811 ps
T1024 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4036213027 Jun 24 05:04:07 PM PDT 24 Jun 24 05:04:16 PM PDT 24 385329933 ps
T1025 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3134835310 Jun 24 05:04:27 PM PDT 24 Jun 24 05:04:30 PM PDT 24 123202856 ps
T1026 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1771064505 Jun 24 05:04:58 PM PDT 24 Jun 24 05:05:00 PM PDT 24 82617909 ps
T1027 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2992129513 Jun 24 05:04:43 PM PDT 24 Jun 24 05:04:46 PM PDT 24 24966181 ps
T1028 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2758959654 Jun 24 05:04:08 PM PDT 24 Jun 24 05:04:12 PM PDT 24 107009848 ps
T1029 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.627779225 Jun 24 05:04:49 PM PDT 24 Jun 24 05:04:54 PM PDT 24 120042193 ps
T1030 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4143317176 Jun 24 05:04:14 PM PDT 24 Jun 24 05:04:30 PM PDT 24 843663738 ps
T1031 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3558868225 Jun 24 05:04:08 PM PDT 24 Jun 24 05:04:12 PM PDT 24 788778561 ps
T1032 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.662608907 Jun 24 05:04:20 PM PDT 24 Jun 24 05:04:25 PM PDT 24 58147684 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2592274786 Jun 24 05:04:20 PM PDT 24 Jun 24 05:04:23 PM PDT 24 21797083 ps
T82 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.903509255 Jun 24 05:04:15 PM PDT 24 Jun 24 05:04:17 PM PDT 24 141640973 ps
T1033 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1613797590 Jun 24 05:04:39 PM PDT 24 Jun 24 05:04:40 PM PDT 24 24263989 ps
T1034 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.702274996 Jun 24 05:04:50 PM PDT 24 Jun 24 05:04:52 PM PDT 24 17853957 ps
T1035 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2744978639 Jun 24 05:04:19 PM PDT 24 Jun 24 05:04:20 PM PDT 24 30513690 ps
T1036 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.356078026 Jun 24 05:04:45 PM PDT 24 Jun 24 05:04:49 PM PDT 24 407860258 ps
T1037 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2283269045 Jun 24 05:04:26 PM PDT 24 Jun 24 05:04:29 PM PDT 24 102480755 ps
T1038 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.923201049 Jun 24 05:04:49 PM PDT 24 Jun 24 05:04:53 PM PDT 24 255375916 ps
T122 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1748470371 Jun 24 05:04:08 PM PDT 24 Jun 24 05:04:12 PM PDT 24 64950458 ps
T1039 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3018242436 Jun 24 05:04:44 PM PDT 24 Jun 24 05:04:48 PM PDT 24 306729879 ps
T1040 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3326248495 Jun 24 05:04:42 PM PDT 24 Jun 24 05:04:46 PM PDT 24 44530503 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3772979357 Jun 24 05:04:07 PM PDT 24 Jun 24 05:04:22 PM PDT 24 2440384888 ps
T1042 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.388223666 Jun 24 05:04:27 PM PDT 24 Jun 24 05:04:32 PM PDT 24 217205747 ps
T165 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.24344477 Jun 24 05:04:22 PM PDT 24 Jun 24 05:04:29 PM PDT 24 431855444 ps
T1043 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1172416452 Jun 24 05:04:59 PM PDT 24 Jun 24 05:05:01 PM PDT 24 58837960 ps
T1044 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.206831787 Jun 24 05:04:35 PM PDT 24 Jun 24 05:04:38 PM PDT 24 93863036 ps
T1045 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1653862794 Jun 24 05:04:33 PM PDT 24 Jun 24 05:04:57 PM PDT 24 3352747858 ps
T123 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1905979843 Jun 24 05:04:07 PM PDT 24 Jun 24 05:04:10 PM PDT 24 125186086 ps
T1046 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2763006047 Jun 24 05:04:42 PM PDT 24 Jun 24 05:04:44 PM PDT 24 166177079 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3661944666 Jun 24 05:04:20 PM PDT 24 Jun 24 05:04:46 PM PDT 24 8659709594 ps
T1048 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3316743972 Jun 24 05:04:08 PM PDT 24 Jun 24 05:04:17 PM PDT 24 1400747138 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1183903705 Jun 24 05:04:51 PM PDT 24 Jun 24 05:04:57 PM PDT 24 397240747 ps
T166 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3364978468 Jun 24 05:04:14 PM PDT 24 Jun 24 05:04:35 PM PDT 24 298496189 ps
T1050 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2999126433 Jun 24 05:04:40 PM PDT 24 Jun 24 05:04:44 PM PDT 24 1653558878 ps
T1051 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.961886744 Jun 24 05:04:33 PM PDT 24 Jun 24 05:04:34 PM PDT 24 41729057 ps
T1052 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2917632479 Jun 24 05:04:43 PM PDT 24 Jun 24 05:04:50 PM PDT 24 350468237 ps
T1053 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1745830393 Jun 24 05:04:07 PM PDT 24 Jun 24 05:04:12 PM PDT 24 161200210 ps
T1054 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1775476177 Jun 24 05:04:50 PM PDT 24 Jun 24 05:04:55 PM PDT 24 713475683 ps
T1055 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1731568367 Jun 24 05:04:33 PM PDT 24 Jun 24 05:04:35 PM PDT 24 72360687 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.332555161 Jun 24 05:04:07 PM PDT 24 Jun 24 05:04:32 PM PDT 24 1284611017 ps
T1057 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2050994765 Jun 24 05:04:35 PM PDT 24 Jun 24 05:04:39 PM PDT 24 167922325 ps
T1058 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.683135737 Jun 24 05:05:02 PM PDT 24 Jun 24 05:05:03 PM PDT 24 32092315 ps
T1059 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4211695551 Jun 24 05:04:25 PM PDT 24 Jun 24 05:04:28 PM PDT 24 190554730 ps
T1060 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2676429006 Jun 24 05:04:36 PM PDT 24 Jun 24 05:04:49 PM PDT 24 192118325 ps
T1061 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.840492458 Jun 24 05:04:49 PM PDT 24 Jun 24 05:04:53 PM PDT 24 28316686 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3559837882 Jun 24 05:04:51 PM PDT 24 Jun 24 05:04:53 PM PDT 24 14988583 ps
T1063 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4178924339 Jun 24 05:04:58 PM PDT 24 Jun 24 05:05:00 PM PDT 24 43578201 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3034232676 Jun 24 05:04:15 PM PDT 24 Jun 24 05:04:19 PM PDT 24 228831904 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.590821904 Jun 24 05:04:33 PM PDT 24 Jun 24 05:04:39 PM PDT 24 2857064022 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2566961062 Jun 24 05:04:34 PM PDT 24 Jun 24 05:04:38 PM PDT 24 85345111 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2787929405 Jun 24 05:04:36 PM PDT 24 Jun 24 05:04:41 PM PDT 24 808400826 ps
T1068 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1619292264 Jun 24 05:04:58 PM PDT 24 Jun 24 05:05:00 PM PDT 24 51999867 ps
T1069 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.992947440 Jun 24 05:04:39 PM PDT 24 Jun 24 05:04:53 PM PDT 24 204098064 ps
T163 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.130292756 Jun 24 05:04:20 PM PDT 24 Jun 24 05:04:26 PM PDT 24 178479915 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3475261892 Jun 24 05:04:21 PM PDT 24 Jun 24 05:04:25 PM PDT 24 357093255 ps
T1071 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1164620595 Jun 24 05:04:40 PM PDT 24 Jun 24 05:04:42 PM PDT 24 86020979 ps
T1072 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.879581267 Jun 24 05:04:58 PM PDT 24 Jun 24 05:05:00 PM PDT 24 32071178 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3249170765 Jun 24 05:04:27 PM PDT 24 Jun 24 05:04:31 PM PDT 24 139248895 ps
T1074 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3305999307 Jun 24 05:04:31 PM PDT 24 Jun 24 05:04:34 PM PDT 24 33668126 ps
T1075 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1716425437 Jun 24 05:04:41 PM PDT 24 Jun 24 05:04:43 PM PDT 24 79699423 ps
T1076 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.154013732 Jun 24 05:04:40 PM PDT 24 Jun 24 05:04:42 PM PDT 24 74706992 ps
T1077 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3614471181 Jun 24 05:04:06 PM PDT 24 Jun 24 05:04:07 PM PDT 24 14177959 ps
T1078 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4182948965 Jun 24 05:04:41 PM PDT 24 Jun 24 05:04:44 PM PDT 24 40796291 ps
T1079 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2970968413 Jun 24 05:04:40 PM PDT 24 Jun 24 05:04:44 PM PDT 24 251376363 ps
T1080 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.52569009 Jun 24 05:04:50 PM PDT 24 Jun 24 05:05:05 PM PDT 24 201526573 ps
T1081 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3680757648 Jun 24 05:04:58 PM PDT 24 Jun 24 05:05:01 PM PDT 24 32966064 ps
T1082 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.867011962 Jun 24 05:04:40 PM PDT 24 Jun 24 05:04:41 PM PDT 24 35247645 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4038607214 Jun 24 05:04:24 PM PDT 24 Jun 24 05:04:27 PM PDT 24 290067699 ps
T1084 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.707465936 Jun 24 05:04:21 PM PDT 24 Jun 24 05:04:23 PM PDT 24 123680961 ps
T1085 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2635845240 Jun 24 05:04:32 PM PDT 24 Jun 24 05:04:36 PM PDT 24 154465741 ps
T1086 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1531914406 Jun 24 05:04:50 PM PDT 24 Jun 24 05:04:55 PM PDT 24 173602695 ps
T1087 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.276401807 Jun 24 05:05:05 PM PDT 24 Jun 24 05:05:07 PM PDT 24 15892458 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2678340001 Jun 24 05:04:14 PM PDT 24 Jun 24 05:04:18 PM PDT 24 1335533465 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2329391164 Jun 24 05:04:19 PM PDT 24 Jun 24 05:04:43 PM PDT 24 1050548691 ps
T1090 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2978794648 Jun 24 05:04:26 PM PDT 24 Jun 24 05:04:29 PM PDT 24 22620350 ps
T1091 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1668165842 Jun 24 05:04:49 PM PDT 24 Jun 24 05:04:58 PM PDT 24 371475369 ps
T1092 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2791355020 Jun 24 05:04:40 PM PDT 24 Jun 24 05:04:43 PM PDT 24 1293597045 ps
T1093 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.370175734 Jun 24 05:04:41 PM PDT 24 Jun 24 05:04:44 PM PDT 24 76279634 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.336000190 Jun 24 05:04:05 PM PDT 24 Jun 24 05:04:29 PM PDT 24 745970066 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2048064273 Jun 24 05:04:08 PM PDT 24 Jun 24 05:04:10 PM PDT 24 47798424 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3405411859 Jun 24 05:04:07 PM PDT 24 Jun 24 05:04:10 PM PDT 24 62746157 ps
T1097 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2476741691 Jun 24 05:04:55 PM PDT 24 Jun 24 05:04:57 PM PDT 24 47167907 ps
T1098 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1866946663 Jun 24 05:04:42 PM PDT 24 Jun 24 05:04:47 PM PDT 24 108515896 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3564270560 Jun 24 05:04:14 PM PDT 24 Jun 24 05:04:16 PM PDT 24 14748998 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.544508607 Jun 24 05:04:15 PM PDT 24 Jun 24 05:04:17 PM PDT 24 36595363 ps

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.741951296
Short name T1
Test name
Test status
Simulation time 36600049389 ps
CPU time 81.68 seconds
Started Jun 24 05:12:08 PM PDT 24
Finished Jun 24 05:13:31 PM PDT 24
Peak memory 252364 kb
Host smart-7b028a38-f781-4e76-aac6-0bc95539e906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741951296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.741951296
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.717105294
Short name T20
Test name
Test status
Simulation time 274721928578 ps
CPU time 491.31 seconds
Started Jun 24 05:13:46 PM PDT 24
Finished Jun 24 05:21:59 PM PDT 24
Peak memory 274344 kb
Host smart-dce725dc-3896-4284-986a-74c03efde1e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717105294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.717105294
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3832422419
Short name T7
Test name
Test status
Simulation time 17037747594 ps
CPU time 120.61 seconds
Started Jun 24 05:12:31 PM PDT 24
Finished Jun 24 05:14:33 PM PDT 24
Peak memory 274756 kb
Host smart-4c68e262-a141-4930-82df-a3041052def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832422419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3832422419
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2029076419
Short name T93
Test name
Test status
Simulation time 152662128 ps
CPU time 3.74 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:13 PM PDT 24
Peak memory 217320 kb
Host smart-b67f996d-b754-4055-98a9-34dfa7ad8232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029076419 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2029076419
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.353582402
Short name T34
Test name
Test status
Simulation time 134721022547 ps
CPU time 351.13 seconds
Started Jun 24 05:11:09 PM PDT 24
Finished Jun 24 05:17:01 PM PDT 24
Peak memory 270604 kb
Host smart-64f3e52b-5098-421e-882f-58d09e060b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353582402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.353582402
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.968725204
Short name T72
Test name
Test status
Simulation time 29589305 ps
CPU time 0.78 seconds
Started Jun 24 05:10:11 PM PDT 24
Finished Jun 24 05:10:13 PM PDT 24
Peak memory 217096 kb
Host smart-2de07e98-476c-4c7e-bf9e-ba3a34767d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968725204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.968725204
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1277306846
Short name T23
Test name
Test status
Simulation time 37922881962 ps
CPU time 447.84 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:20:55 PM PDT 24
Peak memory 264960 kb
Host smart-c45c6076-4926-49a6-9e51-c7947390aef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277306846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1277306846
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2656834530
Short name T41
Test name
Test status
Simulation time 308748734405 ps
CPU time 704.74 seconds
Started Jun 24 05:11:23 PM PDT 24
Finished Jun 24 05:23:10 PM PDT 24
Peak memory 274172 kb
Host smart-f0021a39-f5ea-4363-8671-9368934b0f42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656834530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2656834530
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1773493973
Short name T129
Test name
Test status
Simulation time 461642296071 ps
CPU time 1041.11 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:30:46 PM PDT 24
Peak memory 289716 kb
Host smart-4fa8aea7-b66d-4094-81a0-07b39299fe62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773493973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1773493973
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.336479934
Short name T17
Test name
Test status
Simulation time 256344620 ps
CPU time 1.05 seconds
Started Jun 24 05:10:28 PM PDT 24
Finished Jun 24 05:10:31 PM PDT 24
Peak memory 235996 kb
Host smart-c2a98abd-5558-4d02-b539-d484fa661dd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336479934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.336479934
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1161200023
Short name T172
Test name
Test status
Simulation time 60695633115 ps
CPU time 521.35 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:20:23 PM PDT 24
Peak memory 257252 kb
Host smart-9bb50249-5473-453c-989e-07fd122de55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161200023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1161200023
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.478534012
Short name T19
Test name
Test status
Simulation time 9955822639 ps
CPU time 153.23 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:15:00 PM PDT 24
Peak memory 266712 kb
Host smart-c378223e-ddf6-411c-afdd-3f6826112f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478534012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.478534012
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3691265631
Short name T138
Test name
Test status
Simulation time 2309304723 ps
CPU time 17.94 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 233900 kb
Host smart-ee06eb8a-0de7-4258-bbf8-cac4f74c0093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691265631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3691265631
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.281061706
Short name T22
Test name
Test status
Simulation time 3561826831 ps
CPU time 77.09 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:11:34 PM PDT 24
Peak memory 256008 kb
Host smart-7fc372a1-f292-4c4e-8db4-6ab4fd97ba8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281061706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.281061706
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2781286440
Short name T144
Test name
Test status
Simulation time 2055275671 ps
CPU time 23.15 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:05:04 PM PDT 24
Peak memory 215324 kb
Host smart-fe832803-50f5-4188-aa69-90eb25d36863
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781286440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2781286440
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.47019419
Short name T128
Test name
Test status
Simulation time 23646467114 ps
CPU time 376.53 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:19:14 PM PDT 24
Peak memory 290084 kb
Host smart-b57c9927-283d-448d-8e28-309b87dc8f0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47019419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress
_all.47019419
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3281885463
Short name T98
Test name
Test status
Simulation time 563263765 ps
CPU time 3.34 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:25 PM PDT 24
Peak memory 215392 kb
Host smart-338686c4-ae66-4abe-b062-b0024513b1e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281885463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
281885463
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2982322205
Short name T173
Test name
Test status
Simulation time 8211348146 ps
CPU time 108.34 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:15:02 PM PDT 24
Peak memory 250288 kb
Host smart-fa4f1922-7dbc-412d-a8e5-6630d43b07e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982322205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2982322205
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1579519127
Short name T81
Test name
Test status
Simulation time 28457522 ps
CPU time 1.33 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:16 PM PDT 24
Peak memory 216208 kb
Host smart-7daf3e95-2efc-4004-b915-5e67da5cb20c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579519127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1579519127
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3362126163
Short name T43
Test name
Test status
Simulation time 28512374 ps
CPU time 1.07 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:10:18 PM PDT 24
Peak memory 217600 kb
Host smart-baa85c2a-387b-4c16-b502-abd6649f4ecd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362126163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3362126163
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1296288865
Short name T59
Test name
Test status
Simulation time 151639709701 ps
CPU time 402.42 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:19:02 PM PDT 24
Peak memory 257592 kb
Host smart-1f99bc5c-29e1-4b22-8449-372dbbf85557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296288865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1296288865
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.857333612
Short name T162
Test name
Test status
Simulation time 75487591334 ps
CPU time 283.23 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:16:53 PM PDT 24
Peak memory 266580 kb
Host smart-c049225a-876c-4add-9e45-0b9304404f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857333612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.857333612
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.10449212
Short name T195
Test name
Test status
Simulation time 76191780999 ps
CPU time 717.53 seconds
Started Jun 24 05:12:31 PM PDT 24
Finished Jun 24 05:24:30 PM PDT 24
Peak memory 264308 kb
Host smart-8661bec0-dda1-429f-8e41-0728d36e9529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10449212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.10449212
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2913679752
Short name T332
Test name
Test status
Simulation time 28486654 ps
CPU time 0.68 seconds
Started Jun 24 05:10:20 PM PDT 24
Finished Jun 24 05:10:22 PM PDT 24
Peak memory 206240 kb
Host smart-7c4265b5-7bf3-41fe-84c7-b1665239c5ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913679752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
913679752
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1678923901
Short name T46
Test name
Test status
Simulation time 170280531626 ps
CPU time 339.46 seconds
Started Jun 24 05:11:08 PM PDT 24
Finished Jun 24 05:16:49 PM PDT 24
Peak memory 250240 kb
Host smart-e7064e41-4a80-4743-8991-ee109047dea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678923901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1678923901
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.52569009
Short name T1080
Test name
Test status
Simulation time 201526573 ps
CPU time 12.84 seconds
Started Jun 24 05:04:50 PM PDT 24
Finished Jun 24 05:05:05 PM PDT 24
Peak memory 215272 kb
Host smart-fe92dff8-0e88-406f-9942-787521f2f620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52569009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_
tl_intg_err.52569009
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2620084209
Short name T201
Test name
Test status
Simulation time 8911957544 ps
CPU time 86.67 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:12:44 PM PDT 24
Peak memory 256988 kb
Host smart-10c7d467-a420-41b8-ac44-6dbc368fb692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620084209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2620084209
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.810343896
Short name T217
Test name
Test status
Simulation time 53935178099 ps
CPU time 443.52 seconds
Started Jun 24 05:12:15 PM PDT 24
Finished Jun 24 05:19:40 PM PDT 24
Peak memory 270096 kb
Host smart-dbf70037-4976-4464-8f36-55cf08848947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810343896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.810343896
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3837819451
Short name T178
Test name
Test status
Simulation time 81830644334 ps
CPU time 171.57 seconds
Started Jun 24 05:10:50 PM PDT 24
Finished Jun 24 05:13:43 PM PDT 24
Peak memory 254832 kb
Host smart-fed0a7c4-94bd-46da-9969-a854df1ad230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837819451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3837819451
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1764255648
Short name T403
Test name
Test status
Simulation time 6734516359 ps
CPU time 39.46 seconds
Started Jun 24 05:11:10 PM PDT 24
Finished Jun 24 05:11:51 PM PDT 24
Peak memory 250596 kb
Host smart-88fa8990-878d-4484-b89c-6f21af4ab6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764255648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1764255648
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1959718084
Short name T280
Test name
Test status
Simulation time 20960261936 ps
CPU time 24.99 seconds
Started Jun 24 05:12:38 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 233876 kb
Host smart-853874cf-d512-4cac-a535-75f58b8dd372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959718084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1959718084
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2519160798
Short name T15
Test name
Test status
Simulation time 30140115149 ps
CPU time 267.21 seconds
Started Jun 24 05:13:35 PM PDT 24
Finished Jun 24 05:18:04 PM PDT 24
Peak memory 250324 kb
Host smart-24f2916c-b52f-4169-825e-f61af8c77c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519160798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2519160798
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.130292756
Short name T163
Test name
Test status
Simulation time 178479915 ps
CPU time 4.89 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:26 PM PDT 24
Peak memory 216468 kb
Host smart-42ac5c1f-2fcc-48b2-a947-c3f16245775d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130292756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.130292756
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1857122279
Short name T566
Test name
Test status
Simulation time 380832563 ps
CPU time 4.53 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:11:22 PM PDT 24
Peak memory 219916 kb
Host smart-4e0b9fbe-8307-4941-8dea-057665324e27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1857122279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1857122279
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1281378451
Short name T21
Test name
Test status
Simulation time 30592042869 ps
CPU time 337.3 seconds
Started Jun 24 05:11:53 PM PDT 24
Finished Jun 24 05:17:31 PM PDT 24
Peak memory 268192 kb
Host smart-27a46a89-1c0b-4a29-bc9b-0a217b1dc7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281378451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1281378451
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3747499120
Short name T39
Test name
Test status
Simulation time 6574176843 ps
CPU time 4.96 seconds
Started Jun 24 05:12:38 PM PDT 24
Finished Jun 24 05:12:44 PM PDT 24
Peak memory 225652 kb
Host smart-568a1e6a-da32-46ba-8906-6e2802dc02a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747499120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3747499120
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2451680888
Short name T261
Test name
Test status
Simulation time 24014629557 ps
CPU time 239.39 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:14:13 PM PDT 24
Peak memory 255736 kb
Host smart-f5e7aeac-722e-4885-8c14-d4069d882842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451680888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2451680888
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2300678010
Short name T602
Test name
Test status
Simulation time 33053105812 ps
CPU time 62.88 seconds
Started Jun 24 05:10:13 PM PDT 24
Finished Jun 24 05:11:17 PM PDT 24
Peak memory 242068 kb
Host smart-b2a89d4f-6698-47b1-b5ce-386c196c282e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300678010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2300678010
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3342453308
Short name T13
Test name
Test status
Simulation time 3495093378 ps
CPU time 6.61 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:20 PM PDT 24
Peak memory 217480 kb
Host smart-fbc1073c-7764-4e22-adfa-65ab36f2a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342453308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3342453308
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3216727387
Short name T505
Test name
Test status
Simulation time 1735942813 ps
CPU time 30.51 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:11:35 PM PDT 24
Peak memory 225552 kb
Host smart-8c327330-527f-4dae-857c-5cecb857bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216727387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3216727387
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3221183847
Short name T285
Test name
Test status
Simulation time 533159694 ps
CPU time 10.59 seconds
Started Jun 24 05:11:15 PM PDT 24
Finished Jun 24 05:11:27 PM PDT 24
Peak memory 236812 kb
Host smart-48c79d02-c387-4e56-a88a-cbdd1a72fe36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221183847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3221183847
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3825686399
Short name T179
Test name
Test status
Simulation time 4829093214 ps
CPU time 100.95 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:13:44 PM PDT 24
Peak memory 264868 kb
Host smart-a101bd78-02d8-4df8-9b26-f4652ea6f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825686399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3825686399
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2380209277
Short name T198
Test name
Test status
Simulation time 568186804395 ps
CPU time 813.41 seconds
Started Jun 24 05:11:56 PM PDT 24
Finished Jun 24 05:25:31 PM PDT 24
Peak memory 270060 kb
Host smart-0a9a952a-e5ff-43b1-af0b-410aab3f0555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380209277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2380209277
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1362863086
Short name T250
Test name
Test status
Simulation time 88342090569 ps
CPU time 101.28 seconds
Started Jun 24 05:12:46 PM PDT 24
Finished Jun 24 05:14:29 PM PDT 24
Peak memory 250216 kb
Host smart-5836536b-7297-4185-acb9-7c6781ee54cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362863086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1362863086
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3635870342
Short name T66
Test name
Test status
Simulation time 7196647427 ps
CPU time 73.49 seconds
Started Jun 24 05:13:19 PM PDT 24
Finished Jun 24 05:14:33 PM PDT 24
Peak memory 265308 kb
Host smart-148d6af1-3752-4a8d-8ecb-fa4160b9c4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635870342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3635870342
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1468105919
Short name T270
Test name
Test status
Simulation time 187171997694 ps
CPU time 894.83 seconds
Started Jun 24 05:14:03 PM PDT 24
Finished Jun 24 05:28:59 PM PDT 24
Peak memory 265484 kb
Host smart-318ec4fe-1754-43ad-b0f4-c34f850ab29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468105919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1468105919
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.590821904
Short name T1065
Test name
Test status
Simulation time 2857064022 ps
CPU time 4.9 seconds
Started Jun 24 05:04:33 PM PDT 24
Finished Jun 24 05:04:39 PM PDT 24
Peak memory 215500 kb
Host smart-fabe3075-9259-4e38-ab17-e62479259ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590821904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.590821904
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3534650633
Short name T104
Test name
Test status
Simulation time 289030157 ps
CPU time 17.55 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:27 PM PDT 24
Peak memory 215248 kb
Host smart-addf9ba5-e1c3-4d26-848c-ea084a4d4e41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534650633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3534650633
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1503437016
Short name T90
Test name
Test status
Simulation time 4118892102 ps
CPU time 9.5 seconds
Started Jun 24 05:11:42 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 233796 kb
Host smart-6739a129-94ad-417e-9219-fe982fbd475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503437016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1503437016
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.219124887
Short name T116
Test name
Test status
Simulation time 411921803 ps
CPU time 8.94 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:18 PM PDT 24
Peak memory 215260 kb
Host smart-ad39630c-aea9-49af-ac22-9419e4d2e2fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219124887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.219124887
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3772979357
Short name T1041
Test name
Test status
Simulation time 2440384888 ps
CPU time 13.93 seconds
Started Jun 24 05:04:07 PM PDT 24
Finished Jun 24 05:04:22 PM PDT 24
Peak memory 207100 kb
Host smart-52cd367b-8dae-47a6-9832-4c84a429dfb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772979357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3772979357
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3347651032
Short name T80
Test name
Test status
Simulation time 163525476 ps
CPU time 1.36 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:11 PM PDT 24
Peak memory 216280 kb
Host smart-02d6d5b6-aa51-4a3e-9171-14ab54a8224e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347651032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3347651032
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2678340001
Short name T1088
Test name
Test status
Simulation time 1335533465 ps
CPU time 2.98 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:18 PM PDT 24
Peak memory 216608 kb
Host smart-8db68e37-aa8f-46e4-908c-363e6681196d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678340001 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2678340001
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2846204755
Short name T111
Test name
Test status
Simulation time 88357432 ps
CPU time 2.54 seconds
Started Jun 24 05:04:09 PM PDT 24
Finished Jun 24 05:04:13 PM PDT 24
Peak memory 215332 kb
Host smart-3f10c2aa-f672-4b5e-b9c4-a33e0f6f5379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846204755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
846204755
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2048064273
Short name T1095
Test name
Test status
Simulation time 47798424 ps
CPU time 0.72 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:10 PM PDT 24
Peak memory 203956 kb
Host smart-00a46a74-8af8-42c3-b120-4164c8dff0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048064273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
048064273
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3405411859
Short name T1096
Test name
Test status
Simulation time 62746157 ps
CPU time 1.27 seconds
Started Jun 24 05:04:07 PM PDT 24
Finished Jun 24 05:04:10 PM PDT 24
Peak memory 215284 kb
Host smart-dffb6f1c-4270-486b-be49-476a521b3f20
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405411859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3405411859
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3073844037
Short name T997
Test name
Test status
Simulation time 13029274 ps
CPU time 0.67 seconds
Started Jun 24 05:04:05 PM PDT 24
Finished Jun 24 05:04:07 PM PDT 24
Peak memory 203464 kb
Host smart-56844fbe-4857-4434-acd7-f7ee3cd5a56a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073844037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3073844037
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3558868225
Short name T1031
Test name
Test status
Simulation time 788778561 ps
CPU time 2.79 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:12 PM PDT 24
Peak memory 215620 kb
Host smart-4e5f0ccd-7871-4c17-be81-f8f2ce07ca7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558868225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3558868225
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1698918000
Short name T101
Test name
Test status
Simulation time 27154936 ps
CPU time 2.05 seconds
Started Jun 24 05:04:04 PM PDT 24
Finished Jun 24 05:04:07 PM PDT 24
Peak memory 215400 kb
Host smart-6a135c66-7229-4951-815a-b6fc11670031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698918000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
698918000
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3316743972
Short name T1048
Test name
Test status
Simulation time 1400747138 ps
CPU time 7.61 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:17 PM PDT 24
Peak memory 215216 kb
Host smart-75fd1965-eefb-4cbb-b217-8c25c33ec422
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316743972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3316743972
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.332555161
Short name T1056
Test name
Test status
Simulation time 1284611017 ps
CPU time 24.24 seconds
Started Jun 24 05:04:07 PM PDT 24
Finished Jun 24 05:04:32 PM PDT 24
Peak memory 215236 kb
Host smart-3ccab0a7-a89f-421b-a084-6c7077f2a43f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332555161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.332555161
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.336000190
Short name T1094
Test name
Test status
Simulation time 745970066 ps
CPU time 22.41 seconds
Started Jun 24 05:04:05 PM PDT 24
Finished Jun 24 05:04:29 PM PDT 24
Peak memory 206932 kb
Host smart-7f780a7c-4cd9-4373-abd0-957867b18450
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336000190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.336000190
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1905979843
Short name T123
Test name
Test status
Simulation time 125186086 ps
CPU time 1.2 seconds
Started Jun 24 05:04:07 PM PDT 24
Finished Jun 24 05:04:10 PM PDT 24
Peak memory 206896 kb
Host smart-a9200ee6-a5a8-49cc-b739-ee63c5002be7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905979843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1905979843
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3830138918
Short name T1010
Test name
Test status
Simulation time 242276190 ps
CPU time 2.56 seconds
Started Jun 24 05:04:13 PM PDT 24
Finished Jun 24 05:04:17 PM PDT 24
Peak memory 215276 kb
Host smart-7eb1aa54-32ae-4d18-895f-13aca9d4a2b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830138918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
830138918
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3190034986
Short name T1016
Test name
Test status
Simulation time 55220604 ps
CPU time 0.73 seconds
Started Jun 24 05:04:05 PM PDT 24
Finished Jun 24 05:04:06 PM PDT 24
Peak memory 203680 kb
Host smart-32354c64-4e35-4328-8112-5a7ec038ad37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190034986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
190034986
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1748470371
Short name T122
Test name
Test status
Simulation time 64950458 ps
CPU time 1.8 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:12 PM PDT 24
Peak memory 215360 kb
Host smart-879daac2-9137-4658-aa22-dfa7a8453f46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748470371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1748470371
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2603947182
Short name T1023
Test name
Test status
Simulation time 19163811 ps
CPU time 0.66 seconds
Started Jun 24 05:04:06 PM PDT 24
Finished Jun 24 05:04:08 PM PDT 24
Peak memory 203464 kb
Host smart-ec84bcdc-df62-4f8c-8c38-97613cc7ddb6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603947182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2603947182
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1745830393
Short name T1053
Test name
Test status
Simulation time 161200210 ps
CPU time 4.1 seconds
Started Jun 24 05:04:07 PM PDT 24
Finished Jun 24 05:04:12 PM PDT 24
Peak memory 215384 kb
Host smart-3d53a4b6-7812-45a6-ab8b-7daf8057423e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745830393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1745830393
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2758959654
Short name T1028
Test name
Test status
Simulation time 107009848 ps
CPU time 3.03 seconds
Started Jun 24 05:04:08 PM PDT 24
Finished Jun 24 05:04:12 PM PDT 24
Peak memory 216364 kb
Host smart-fdd68b58-7d99-4908-9bc3-58a14546f213
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758959654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
758959654
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.406804268
Short name T147
Test name
Test status
Simulation time 519302250 ps
CPU time 3.51 seconds
Started Jun 24 05:04:34 PM PDT 24
Finished Jun 24 05:04:38 PM PDT 24
Peak memory 216332 kb
Host smart-76ef9e50-22de-4f0e-98d3-c0c98f2c197f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406804268 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.406804268
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2791355020
Short name T1092
Test name
Test status
Simulation time 1293597045 ps
CPU time 1.9 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:43 PM PDT 24
Peak memory 215304 kb
Host smart-44d684d4-30d5-42cb-ad60-091e296cb70d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791355020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2791355020
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1613797590
Short name T1033
Test name
Test status
Simulation time 24263989 ps
CPU time 0.74 seconds
Started Jun 24 05:04:39 PM PDT 24
Finished Jun 24 05:04:40 PM PDT 24
Peak memory 203652 kb
Host smart-0db8f86b-4e96-4cf1-b8df-87364faa56ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613797590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1613797590
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2050994765
Short name T1057
Test name
Test status
Simulation time 167922325 ps
CPU time 2.96 seconds
Started Jun 24 05:04:35 PM PDT 24
Finished Jun 24 05:04:39 PM PDT 24
Peak memory 215292 kb
Host smart-acf460ec-f10b-4b71-a7d0-962ce1b4088f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050994765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2050994765
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.206831787
Short name T1044
Test name
Test status
Simulation time 93863036 ps
CPU time 2.72 seconds
Started Jun 24 05:04:35 PM PDT 24
Finished Jun 24 05:04:38 PM PDT 24
Peak memory 215412 kb
Host smart-d6bc8852-a505-4a01-a94e-ab59f7746a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206831787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.206831787
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1653862794
Short name T1045
Test name
Test status
Simulation time 3352747858 ps
CPU time 23.07 seconds
Started Jun 24 05:04:33 PM PDT 24
Finished Jun 24 05:04:57 PM PDT 24
Peak memory 215624 kb
Host smart-f47e3cb8-70e8-4c60-9eaf-1320d75550ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653862794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1653862794
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1551357748
Short name T1019
Test name
Test status
Simulation time 24209161 ps
CPU time 1.64 seconds
Started Jun 24 05:04:34 PM PDT 24
Finished Jun 24 05:04:36 PM PDT 24
Peak memory 216428 kb
Host smart-49e1ca20-a723-4699-9c66-552be1594522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551357748 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1551357748
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2635845240
Short name T1085
Test name
Test status
Simulation time 154465741 ps
CPU time 2.67 seconds
Started Jun 24 05:04:32 PM PDT 24
Finished Jun 24 05:04:36 PM PDT 24
Peak memory 215208 kb
Host smart-4a188876-9aed-47db-90c9-702b92eeccc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635845240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2635845240
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3380517967
Short name T1001
Test name
Test status
Simulation time 13465034 ps
CPU time 0.76 seconds
Started Jun 24 05:04:37 PM PDT 24
Finished Jun 24 05:04:38 PM PDT 24
Peak memory 203584 kb
Host smart-f5c0881e-f75d-4f89-a094-ad39cc85c888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380517967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3380517967
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2130029469
Short name T985
Test name
Test status
Simulation time 78622429 ps
CPU time 2.71 seconds
Started Jun 24 05:04:37 PM PDT 24
Finished Jun 24 05:04:40 PM PDT 24
Peak memory 215324 kb
Host smart-bbdc0825-f6bf-420d-8bb8-1d7622e23f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130029469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2130029469
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2676429006
Short name T1060
Test name
Test status
Simulation time 192118325 ps
CPU time 12.51 seconds
Started Jun 24 05:04:36 PM PDT 24
Finished Jun 24 05:04:49 PM PDT 24
Peak memory 215256 kb
Host smart-f42b1d21-b5e6-4745-9c0d-c3f3070b77bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676429006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2676429006
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3304530586
Short name T91
Test name
Test status
Simulation time 30081631 ps
CPU time 2.11 seconds
Started Jun 24 05:04:39 PM PDT 24
Finished Jun 24 05:04:42 PM PDT 24
Peak memory 216336 kb
Host smart-d376b7d7-c352-4378-828b-7c623ad7131b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304530586 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3304530586
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1731568367
Short name T1055
Test name
Test status
Simulation time 72360687 ps
CPU time 2.02 seconds
Started Jun 24 05:04:33 PM PDT 24
Finished Jun 24 05:04:35 PM PDT 24
Peak memory 207180 kb
Host smart-95990246-212f-4275-82af-8bb8a033ff2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731568367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1731568367
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.961886744
Short name T1051
Test name
Test status
Simulation time 41729057 ps
CPU time 0.7 seconds
Started Jun 24 05:04:33 PM PDT 24
Finished Jun 24 05:04:34 PM PDT 24
Peak memory 203860 kb
Host smart-47b37ac7-ba98-433f-8260-684c42f4fbfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961886744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.961886744
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1340073324
Short name T981
Test name
Test status
Simulation time 229312922 ps
CPU time 4.27 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:45 PM PDT 24
Peak memory 215328 kb
Host smart-3d4cea6b-58e1-48a1-b2f5-810af031775f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340073324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1340073324
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2787929405
Short name T1067
Test name
Test status
Simulation time 808400826 ps
CPU time 4.63 seconds
Started Jun 24 05:04:36 PM PDT 24
Finished Jun 24 05:04:41 PM PDT 24
Peak memory 215408 kb
Host smart-334fd65c-d0a2-4722-a30a-ffd168160010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787929405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2787929405
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.992947440
Short name T1069
Test name
Test status
Simulation time 204098064 ps
CPU time 13.21 seconds
Started Jun 24 05:04:39 PM PDT 24
Finished Jun 24 05:04:53 PM PDT 24
Peak memory 215260 kb
Host smart-70e14291-0cb7-4f6d-933b-f06a84bfe1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992947440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.992947440
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3907059028
Short name T146
Test name
Test status
Simulation time 57680693 ps
CPU time 1.75 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:43 PM PDT 24
Peak memory 216372 kb
Host smart-732ee6fe-7bcd-48c4-bdf6-64243ecf812a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907059028 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3907059028
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1401639953
Short name T112
Test name
Test status
Simulation time 301363409 ps
CPU time 2.05 seconds
Started Jun 24 05:04:41 PM PDT 24
Finished Jun 24 05:04:44 PM PDT 24
Peak memory 215192 kb
Host smart-8c2b77d3-6805-4ca4-8998-4c7a1749c007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401639953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1401639953
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3498396833
Short name T986
Test name
Test status
Simulation time 41992785 ps
CPU time 0.75 seconds
Started Jun 24 05:04:41 PM PDT 24
Finished Jun 24 05:04:43 PM PDT 24
Peak memory 203656 kb
Host smart-907d8982-8ce0-4472-8b0c-36e3eaff0c0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498396833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3498396833
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3326248495
Short name T1040
Test name
Test status
Simulation time 44530503 ps
CPU time 3.1 seconds
Started Jun 24 05:04:42 PM PDT 24
Finished Jun 24 05:04:46 PM PDT 24
Peak memory 215252 kb
Host smart-3fda5a95-7327-4516-8012-5fada8293417
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326248495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3326248495
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2566961062
Short name T1066
Test name
Test status
Simulation time 85345111 ps
CPU time 2.61 seconds
Started Jun 24 05:04:34 PM PDT 24
Finished Jun 24 05:04:38 PM PDT 24
Peak memory 215440 kb
Host smart-1ca665f0-734c-420b-b677-50304264fad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566961062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2566961062
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1866946663
Short name T1098
Test name
Test status
Simulation time 108515896 ps
CPU time 4.3 seconds
Started Jun 24 05:04:42 PM PDT 24
Finished Jun 24 05:04:47 PM PDT 24
Peak memory 217536 kb
Host smart-7973da2a-21e8-468d-a9ce-a459a0de7a7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866946663 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1866946663
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3759247829
Short name T119
Test name
Test status
Simulation time 97595490 ps
CPU time 2.76 seconds
Started Jun 24 05:04:45 PM PDT 24
Finished Jun 24 05:04:48 PM PDT 24
Peak memory 207296 kb
Host smart-1c52c66f-4865-4787-a8f1-133be6ce141f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759247829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3759247829
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.713803606
Short name T1006
Test name
Test status
Simulation time 24175535 ps
CPU time 0.72 seconds
Started Jun 24 05:04:42 PM PDT 24
Finished Jun 24 05:04:44 PM PDT 24
Peak memory 203616 kb
Host smart-2ec0cde7-23ed-4bbd-81ab-99cb7d324236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713803606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.713803606
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3018242436
Short name T1039
Test name
Test status
Simulation time 306729879 ps
CPU time 3.44 seconds
Started Jun 24 05:04:44 PM PDT 24
Finished Jun 24 05:04:48 PM PDT 24
Peak memory 215640 kb
Host smart-54c063a1-7c03-4438-b481-6f5f0b99b002
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018242436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3018242436
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.455714227
Short name T105
Test name
Test status
Simulation time 95641391 ps
CPU time 3.65 seconds
Started Jun 24 05:04:44 PM PDT 24
Finished Jun 24 05:04:49 PM PDT 24
Peak memory 215484 kb
Host smart-cb20e3f0-0bf4-4389-b208-da1a58a490fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455714227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.455714227
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1242762114
Short name T167
Test name
Test status
Simulation time 907637936 ps
CPU time 22.2 seconds
Started Jun 24 05:04:42 PM PDT 24
Finished Jun 24 05:05:06 PM PDT 24
Peak memory 215388 kb
Host smart-2c90400d-f1aa-46a0-8896-ebda49f78ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242762114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1242762114
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1716425437
Short name T1075
Test name
Test status
Simulation time 79699423 ps
CPU time 1.63 seconds
Started Jun 24 05:04:41 PM PDT 24
Finished Jun 24 05:04:43 PM PDT 24
Peak memory 215388 kb
Host smart-b439cb8d-6430-4907-bd8c-a24c3c85cac6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716425437 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1716425437
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2763006047
Short name T1046
Test name
Test status
Simulation time 166177079 ps
CPU time 1.44 seconds
Started Jun 24 05:04:42 PM PDT 24
Finished Jun 24 05:04:44 PM PDT 24
Peak memory 207016 kb
Host smart-f98b4831-c6fe-41c6-a46f-5476b602131c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763006047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2763006047
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1832852736
Short name T1021
Test name
Test status
Simulation time 14249969 ps
CPU time 0.76 seconds
Started Jun 24 05:04:45 PM PDT 24
Finished Jun 24 05:04:47 PM PDT 24
Peak memory 203680 kb
Host smart-61153b94-cc52-4f85-84cc-4c5debe7abc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832852736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1832852736
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4182948965
Short name T1078
Test name
Test status
Simulation time 40796291 ps
CPU time 1.82 seconds
Started Jun 24 05:04:41 PM PDT 24
Finished Jun 24 05:04:44 PM PDT 24
Peak memory 207156 kb
Host smart-d8407b47-3b34-4b88-a082-913aeabac8d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182948965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4182948965
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2992129513
Short name T1027
Test name
Test status
Simulation time 24966181 ps
CPU time 1.59 seconds
Started Jun 24 05:04:43 PM PDT 24
Finished Jun 24 05:04:46 PM PDT 24
Peak memory 215412 kb
Host smart-3d68f7a7-1394-4b93-a2e2-fc6b62dc52f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992129513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2992129513
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1357839088
Short name T96
Test name
Test status
Simulation time 834308948 ps
CPU time 13.07 seconds
Started Jun 24 05:04:42 PM PDT 24
Finished Jun 24 05:04:56 PM PDT 24
Peak memory 215948 kb
Host smart-3ac4ba11-70bf-412f-a0ba-f8efa9a133df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357839088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1357839088
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1531914406
Short name T1086
Test name
Test status
Simulation time 173602695 ps
CPU time 3.38 seconds
Started Jun 24 05:04:50 PM PDT 24
Finished Jun 24 05:04:55 PM PDT 24
Peak memory 217960 kb
Host smart-a51457bf-d757-4110-9f0e-83f8c97ed5f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531914406 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1531914406
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.370175734
Short name T1093
Test name
Test status
Simulation time 76279634 ps
CPU time 1.36 seconds
Started Jun 24 05:04:41 PM PDT 24
Finished Jun 24 05:04:44 PM PDT 24
Peak memory 206984 kb
Host smart-2e33c1b2-72de-4d4f-a7fc-30fe2ba7f01e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370175734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.370175734
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1164620595
Short name T1071
Test name
Test status
Simulation time 86020979 ps
CPU time 0.73 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:42 PM PDT 24
Peak memory 203652 kb
Host smart-90f27277-236c-445c-a5cd-d33b1af96a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164620595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1164620595
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.923201049
Short name T1038
Test name
Test status
Simulation time 255375916 ps
CPU time 2.94 seconds
Started Jun 24 05:04:49 PM PDT 24
Finished Jun 24 05:04:53 PM PDT 24
Peak memory 215356 kb
Host smart-9e4603cf-dc61-4d57-87d3-f96038e62cfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923201049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.923201049
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.356078026
Short name T1036
Test name
Test status
Simulation time 407860258 ps
CPU time 2.86 seconds
Started Jun 24 05:04:45 PM PDT 24
Finished Jun 24 05:04:49 PM PDT 24
Peak memory 215732 kb
Host smart-b5e4fdbf-e1cc-42a7-868f-ce573e2d5612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356078026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.356078026
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2917632479
Short name T1052
Test name
Test status
Simulation time 350468237 ps
CPU time 5.99 seconds
Started Jun 24 05:04:43 PM PDT 24
Finished Jun 24 05:04:50 PM PDT 24
Peak memory 216056 kb
Host smart-156bcc5b-b2aa-48f2-9a89-4f8e798b7f45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917632479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2917632479
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3658545261
Short name T993
Test name
Test status
Simulation time 28927482 ps
CPU time 1.63 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:54 PM PDT 24
Peak memory 215248 kb
Host smart-6d755aac-9328-4113-afa5-b3c89b90542f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658545261 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3658545261
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1808380815
Short name T118
Test name
Test status
Simulation time 130014899 ps
CPU time 2.4 seconds
Started Jun 24 05:04:52 PM PDT 24
Finished Jun 24 05:04:55 PM PDT 24
Peak memory 215508 kb
Host smart-93fdd26d-e0d1-48e6-9286-c7a93f9ddb88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808380815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1808380815
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.67533473
Short name T992
Test name
Test status
Simulation time 62014324 ps
CPU time 0.68 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:53 PM PDT 24
Peak memory 203540 kb
Host smart-6723d068-952b-44c7-98a0-6c06305f8fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67533473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.67533473
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1775476177
Short name T1054
Test name
Test status
Simulation time 713475683 ps
CPU time 3.96 seconds
Started Jun 24 05:04:50 PM PDT 24
Finished Jun 24 05:04:55 PM PDT 24
Peak memory 215248 kb
Host smart-35b47399-681c-4621-b540-ad468aa5fe8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775476177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1775476177
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3968491843
Short name T102
Test name
Test status
Simulation time 418720237 ps
CPU time 3.13 seconds
Started Jun 24 05:04:54 PM PDT 24
Finished Jun 24 05:04:58 PM PDT 24
Peak memory 215452 kb
Host smart-08221945-bd40-49ba-a272-b591d896202f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968491843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3968491843
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1668165842
Short name T1091
Test name
Test status
Simulation time 371475369 ps
CPU time 8.24 seconds
Started Jun 24 05:04:49 PM PDT 24
Finished Jun 24 05:04:58 PM PDT 24
Peak memory 215864 kb
Host smart-63fd33c6-abbd-49a3-beb7-d72e7a3e0b38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668165842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1668165842
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.627779225
Short name T1029
Test name
Test status
Simulation time 120042193 ps
CPU time 3.74 seconds
Started Jun 24 05:04:49 PM PDT 24
Finished Jun 24 05:04:54 PM PDT 24
Peak memory 216372 kb
Host smart-f2a9cb76-422c-45df-81cf-0b5f68929320
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627779225 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.627779225
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2517589999
Short name T113
Test name
Test status
Simulation time 217212049 ps
CPU time 2.76 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:55 PM PDT 24
Peak memory 215272 kb
Host smart-c849b99a-7255-4b85-989e-5473a3458f4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517589999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2517589999
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3063733855
Short name T999
Test name
Test status
Simulation time 29967281 ps
CPU time 0.73 seconds
Started Jun 24 05:04:50 PM PDT 24
Finished Jun 24 05:04:52 PM PDT 24
Peak memory 203952 kb
Host smart-75ac78f6-6427-4dc1-b885-ad98b2db41f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063733855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3063733855
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1151522248
Short name T136
Test name
Test status
Simulation time 117286692 ps
CPU time 1.69 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:54 PM PDT 24
Peak memory 215204 kb
Host smart-8ef100a8-cc59-42fe-bdeb-f2808d1620c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151522248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1151522248
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3570281010
Short name T103
Test name
Test status
Simulation time 123668653 ps
CPU time 1.89 seconds
Started Jun 24 05:04:50 PM PDT 24
Finished Jun 24 05:04:53 PM PDT 24
Peak memory 215492 kb
Host smart-58e6f0a7-a16d-4508-b96d-6d8740d823a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570281010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3570281010
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.840492458
Short name T1061
Test name
Test status
Simulation time 28316686 ps
CPU time 2.02 seconds
Started Jun 24 05:04:49 PM PDT 24
Finished Jun 24 05:04:53 PM PDT 24
Peak memory 216436 kb
Host smart-001f8fc2-97f2-4ac9-ab0e-78d9d802f822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840492458 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.840492458
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3234428159
Short name T995
Test name
Test status
Simulation time 36256922 ps
CPU time 1.3 seconds
Started Jun 24 05:04:49 PM PDT 24
Finished Jun 24 05:04:51 PM PDT 24
Peak memory 206952 kb
Host smart-ce7c9070-b90c-4f9f-9ae1-a61a40a75ea9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234428159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3234428159
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3559837882
Short name T1062
Test name
Test status
Simulation time 14988583 ps
CPU time 0.74 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:53 PM PDT 24
Peak memory 203704 kb
Host smart-afb1dfc3-6a4e-45ff-b4ad-21c316c0f90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559837882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3559837882
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1183903705
Short name T1049
Test name
Test status
Simulation time 397240747 ps
CPU time 4.31 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:57 PM PDT 24
Peak memory 215636 kb
Host smart-2ac60486-3fce-494b-a7bc-f62a82ba7d3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183903705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1183903705
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3651535197
Short name T94
Test name
Test status
Simulation time 205110550 ps
CPU time 2.75 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:55 PM PDT 24
Peak memory 215368 kb
Host smart-c6eb2918-e0d5-4bd9-a34f-5794dc227809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651535197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3651535197
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.484761207
Short name T145
Test name
Test status
Simulation time 5741430854 ps
CPU time 15.67 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:05:08 PM PDT 24
Peak memory 217452 kb
Host smart-ffc4e63a-a126-4681-9911-b0a9f853bc7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484761207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.484761207
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4143317176
Short name T1030
Test name
Test status
Simulation time 843663738 ps
CPU time 14.84 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:30 PM PDT 24
Peak memory 206916 kb
Host smart-f0275524-2cea-4dc0-ae9b-1655a808ecd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143317176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4143317176
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.971490210
Short name T977
Test name
Test status
Simulation time 371921404 ps
CPU time 12.55 seconds
Started Jun 24 05:04:15 PM PDT 24
Finished Jun 24 05:04:29 PM PDT 24
Peak memory 206976 kb
Host smart-cf057fc8-ce22-4122-9b47-d8318458006d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971490210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.971490210
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.903509255
Short name T82
Test name
Test status
Simulation time 141640973 ps
CPU time 1.23 seconds
Started Jun 24 05:04:15 PM PDT 24
Finished Jun 24 05:04:17 PM PDT 24
Peak memory 216256 kb
Host smart-9223294b-5d1e-4a17-87e5-98ddfd0e5708
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903509255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.903509255
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.530804502
Short name T107
Test name
Test status
Simulation time 142990369 ps
CPU time 2.62 seconds
Started Jun 24 05:04:12 PM PDT 24
Finished Jun 24 05:04:15 PM PDT 24
Peak memory 216556 kb
Host smart-4a252947-b7a8-41d2-86d4-9eb3d3eb47dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530804502 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.530804502
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3840985864
Short name T988
Test name
Test status
Simulation time 41330428 ps
CPU time 1.43 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:16 PM PDT 24
Peak memory 207008 kb
Host smart-f7971e3b-574a-410e-83b1-58d72de5a9e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840985864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
840985864
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3614471181
Short name T1077
Test name
Test status
Simulation time 14177959 ps
CPU time 0.69 seconds
Started Jun 24 05:04:06 PM PDT 24
Finished Jun 24 05:04:07 PM PDT 24
Peak memory 203536 kb
Host smart-72e28241-9ded-46b8-b9d8-651ac4c937e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614471181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
614471181
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4038607214
Short name T1083
Test name
Test status
Simulation time 290067699 ps
CPU time 2.41 seconds
Started Jun 24 05:04:24 PM PDT 24
Finished Jun 24 05:04:27 PM PDT 24
Peak memory 215260 kb
Host smart-77b98ff1-ae83-4de2-a304-58a9fcb0acea
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038607214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4038607214
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4221953556
Short name T1020
Test name
Test status
Simulation time 11043803 ps
CPU time 0.72 seconds
Started Jun 24 05:04:13 PM PDT 24
Finished Jun 24 05:04:15 PM PDT 24
Peak memory 203500 kb
Host smart-1f032522-b441-4fbf-98b1-250d5ce7e840
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221953556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4221953556
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.662608907
Short name T1032
Test name
Test status
Simulation time 58147684 ps
CPU time 3.8 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:25 PM PDT 24
Peak memory 215356 kb
Host smart-c095c4ec-d2a7-4b38-9374-4328b190dde1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662608907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.662608907
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2786076995
Short name T100
Test name
Test status
Simulation time 252343609 ps
CPU time 3.31 seconds
Started Jun 24 05:04:07 PM PDT 24
Finished Jun 24 05:04:12 PM PDT 24
Peak memory 216396 kb
Host smart-f849f459-7db3-4d19-8939-acedfed434df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786076995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
786076995
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.4036213027
Short name T1024
Test name
Test status
Simulation time 385329933 ps
CPU time 7.01 seconds
Started Jun 24 05:04:07 PM PDT 24
Finished Jun 24 05:04:16 PM PDT 24
Peak memory 215288 kb
Host smart-5a6fcedf-a736-4099-99b6-6466d440f9d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036213027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.4036213027
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.702274996
Short name T1034
Test name
Test status
Simulation time 17853957 ps
CPU time 0.73 seconds
Started Jun 24 05:04:50 PM PDT 24
Finished Jun 24 05:04:52 PM PDT 24
Peak memory 203676 kb
Host smart-f4ebcd06-9279-499e-9ed5-83fe4b0bd654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702274996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.702274996
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.458971170
Short name T984
Test name
Test status
Simulation time 18406355 ps
CPU time 0.82 seconds
Started Jun 24 05:04:54 PM PDT 24
Finished Jun 24 05:04:55 PM PDT 24
Peak memory 203536 kb
Host smart-ff43c564-9472-4c57-b822-33ebff521576
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458971170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.458971170
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1629121766
Short name T983
Test name
Test status
Simulation time 25699421 ps
CPU time 0.73 seconds
Started Jun 24 05:04:51 PM PDT 24
Finished Jun 24 05:04:53 PM PDT 24
Peak memory 203652 kb
Host smart-24a20a64-6fc6-4416-857c-948499f3c3d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629121766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1629121766
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3125976347
Short name T1005
Test name
Test status
Simulation time 10493365 ps
CPU time 0.73 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:00 PM PDT 24
Peak memory 203908 kb
Host smart-05bfac5a-4bd1-41a0-9ab0-f47def90d0fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125976347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3125976347
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1172416452
Short name T1043
Test name
Test status
Simulation time 58837960 ps
CPU time 0.76 seconds
Started Jun 24 05:04:59 PM PDT 24
Finished Jun 24 05:05:01 PM PDT 24
Peak memory 203932 kb
Host smart-eb0fdb39-7366-4df6-8a03-e7f11382c79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172416452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1172416452
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3015249653
Short name T1003
Test name
Test status
Simulation time 32129023 ps
CPU time 0.76 seconds
Started Jun 24 05:04:59 PM PDT 24
Finished Jun 24 05:05:01 PM PDT 24
Peak memory 203548 kb
Host smart-1fa74760-ef15-4252-b977-f196bb1d4520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015249653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3015249653
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1755870084
Short name T975
Test name
Test status
Simulation time 17176482 ps
CPU time 0.72 seconds
Started Jun 24 05:04:59 PM PDT 24
Finished Jun 24 05:05:01 PM PDT 24
Peak memory 203808 kb
Host smart-83a1db0b-ad4a-4d7d-97bb-504a78bae29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755870084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1755870084
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3933221562
Short name T1000
Test name
Test status
Simulation time 15519503 ps
CPU time 0.78 seconds
Started Jun 24 05:05:02 PM PDT 24
Finished Jun 24 05:05:04 PM PDT 24
Peak memory 203688 kb
Host smart-4a9a1b51-6501-4bab-9ea7-1a48fd770634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933221562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3933221562
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3308597029
Short name T1015
Test name
Test status
Simulation time 14257746 ps
CPU time 0.78 seconds
Started Jun 24 05:04:57 PM PDT 24
Finished Jun 24 05:04:59 PM PDT 24
Peak memory 203640 kb
Host smart-f997d7bc-40d5-4d8a-9da1-f04e6f02a25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308597029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3308597029
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2228482951
Short name T1007
Test name
Test status
Simulation time 13720085 ps
CPU time 0.76 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:00 PM PDT 24
Peak memory 203620 kb
Host smart-6abcb03d-236d-4ce5-ac9d-fc92ef2ab19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228482951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2228482951
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.43597131
Short name T115
Test name
Test status
Simulation time 660827829 ps
CPU time 15.88 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:31 PM PDT 24
Peak memory 207336 kb
Host smart-b4facf5e-bf11-4602-a92b-8e36d187d1f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43597131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
aliasing.43597131
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3661944666
Short name T1047
Test name
Test status
Simulation time 8659709594 ps
CPU time 24.62 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:46 PM PDT 24
Peak memory 215316 kb
Host smart-e6b3161b-97d9-45c7-a587-7ec3d7a9c181
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661944666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3661944666
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3034232676
Short name T1064
Test name
Test status
Simulation time 228831904 ps
CPU time 2.88 seconds
Started Jun 24 05:04:15 PM PDT 24
Finished Jun 24 05:04:19 PM PDT 24
Peak memory 216332 kb
Host smart-e21aaf57-b8f5-475b-9450-7e1d1912fb02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034232676 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3034232676
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1762456083
Short name T143
Test name
Test status
Simulation time 88216131 ps
CPU time 1.31 seconds
Started Jun 24 05:04:15 PM PDT 24
Finished Jun 24 05:04:18 PM PDT 24
Peak memory 215304 kb
Host smart-1f841bd5-5d4a-4fa2-9262-76ae9f67aa37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762456083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
762456083
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3564270560
Short name T1099
Test name
Test status
Simulation time 14748998 ps
CPU time 0.7 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:16 PM PDT 24
Peak memory 203940 kb
Host smart-ca87299b-2eee-434f-9aca-424b76a8a2ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564270560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
564270560
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3881942056
Short name T120
Test name
Test status
Simulation time 46572638 ps
CPU time 2.07 seconds
Started Jun 24 05:04:16 PM PDT 24
Finished Jun 24 05:04:19 PM PDT 24
Peak memory 215372 kb
Host smart-b22de10a-6692-4dd1-b5b8-d2b8ddb7c729
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881942056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3881942056
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.544508607
Short name T1100
Test name
Test status
Simulation time 36595363 ps
CPU time 0.66 seconds
Started Jun 24 05:04:15 PM PDT 24
Finished Jun 24 05:04:17 PM PDT 24
Peak memory 203504 kb
Host smart-e2504b01-26a5-41c2-ac7f-47d9279baeea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544508607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.544508607
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.878205964
Short name T135
Test name
Test status
Simulation time 210707298 ps
CPU time 4.58 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:20 PM PDT 24
Peak memory 215160 kb
Host smart-ba67ae98-7781-44c5-9800-c8be34937a53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878205964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.878205964
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.980571536
Short name T92
Test name
Test status
Simulation time 51268605 ps
CPU time 3.75 seconds
Started Jun 24 05:04:13 PM PDT 24
Finished Jun 24 05:04:18 PM PDT 24
Peak memory 215416 kb
Host smart-98a73ea8-690e-48f5-9712-6af9a0dde344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980571536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.980571536
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1589141534
Short name T95
Test name
Test status
Simulation time 1643607280 ps
CPU time 8.24 seconds
Started Jun 24 05:04:15 PM PDT 24
Finished Jun 24 05:04:25 PM PDT 24
Peak memory 215364 kb
Host smart-69bb2495-8b86-4807-875d-4703b1d0d48b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589141534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1589141534
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2572897993
Short name T976
Test name
Test status
Simulation time 13713531 ps
CPU time 0.73 seconds
Started Jun 24 05:04:56 PM PDT 24
Finished Jun 24 05:04:58 PM PDT 24
Peak memory 203604 kb
Host smart-9e9f516f-ed11-4583-bcb1-d774bcb74682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572897993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2572897993
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.4178924339
Short name T1063
Test name
Test status
Simulation time 43578201 ps
CPU time 0.7 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:00 PM PDT 24
Peak memory 203700 kb
Host smart-07e34bd2-7ddc-431a-9b2c-c9a0c1a07f5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178924339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
4178924339
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2155136804
Short name T1002
Test name
Test status
Simulation time 36484538 ps
CPU time 0.74 seconds
Started Jun 24 05:05:02 PM PDT 24
Finished Jun 24 05:05:03 PM PDT 24
Peak memory 203680 kb
Host smart-e91019db-b6e0-4d5f-90da-7f24d52ec412
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155136804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2155136804
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.276401807
Short name T1087
Test name
Test status
Simulation time 15892458 ps
CPU time 0.83 seconds
Started Jun 24 05:05:05 PM PDT 24
Finished Jun 24 05:05:07 PM PDT 24
Peak memory 203652 kb
Host smart-4c60dc3c-bcb4-40f3-918d-4c4c7ec1e548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276401807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.276401807
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2782118687
Short name T991
Test name
Test status
Simulation time 11979004 ps
CPU time 0.77 seconds
Started Jun 24 05:04:59 PM PDT 24
Finished Jun 24 05:05:01 PM PDT 24
Peak memory 203940 kb
Host smart-726b519f-b0e9-4d04-a650-fe5054c0e99f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782118687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2782118687
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4129724493
Short name T1012
Test name
Test status
Simulation time 41307137 ps
CPU time 0.75 seconds
Started Jun 24 05:05:02 PM PDT 24
Finished Jun 24 05:05:03 PM PDT 24
Peak memory 203680 kb
Host smart-5a2d2e64-6188-4036-af92-32dd8ec7db53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129724493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4129724493
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3541451038
Short name T979
Test name
Test status
Simulation time 13696482 ps
CPU time 0.75 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:00 PM PDT 24
Peak memory 203936 kb
Host smart-92383601-ac06-4cd7-8657-376993156c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541451038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3541451038
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.879581267
Short name T1072
Test name
Test status
Simulation time 32071178 ps
CPU time 0.7 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:00 PM PDT 24
Peak memory 203544 kb
Host smart-f3b1d90b-719c-44a8-8fcb-cf540f247a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879581267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.879581267
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1619292264
Short name T1068
Test name
Test status
Simulation time 51999867 ps
CPU time 0.73 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:00 PM PDT 24
Peak memory 203936 kb
Host smart-8dcc0324-0b1b-4ff4-a8a6-87de7e68476c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619292264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1619292264
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1771064505
Short name T1026
Test name
Test status
Simulation time 82617909 ps
CPU time 0.72 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:00 PM PDT 24
Peak memory 203688 kb
Host smart-a976f432-c8ca-4a45-b51c-8e71ba9b4440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771064505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1771064505
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2329391164
Short name T1089
Test name
Test status
Simulation time 1050548691 ps
CPU time 22.81 seconds
Started Jun 24 05:04:19 PM PDT 24
Finished Jun 24 05:04:43 PM PDT 24
Peak memory 215212 kb
Host smart-1d849bae-9737-489c-9348-b9ddfe9fe10e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329391164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2329391164
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.4020662720
Short name T1013
Test name
Test status
Simulation time 1043168799 ps
CPU time 32.45 seconds
Started Jun 24 05:04:22 PM PDT 24
Finished Jun 24 05:04:55 PM PDT 24
Peak memory 207040 kb
Host smart-a4a8b799-20de-469e-a1f7-1a719ea77639
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020662720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.4020662720
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3948520079
Short name T79
Test name
Test status
Simulation time 233697150 ps
CPU time 1.24 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:22 PM PDT 24
Peak memory 216260 kb
Host smart-e1c6c41a-0318-48b8-8155-bbf1551fd581
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948520079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3948520079
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.652295056
Short name T108
Test name
Test status
Simulation time 1485330408 ps
CPU time 3.53 seconds
Started Jun 24 05:04:23 PM PDT 24
Finished Jun 24 05:04:27 PM PDT 24
Peak memory 217168 kb
Host smart-57779ab2-464d-43b9-943e-47492f373656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652295056 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.652295056
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2592274786
Short name T121
Test name
Test status
Simulation time 21797083 ps
CPU time 1.4 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:23 PM PDT 24
Peak memory 215252 kb
Host smart-63d5eb4b-0188-4132-afab-5e50d3925f43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592274786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
592274786
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2669738947
Short name T996
Test name
Test status
Simulation time 23105107 ps
CPU time 0.74 seconds
Started Jun 24 05:04:15 PM PDT 24
Finished Jun 24 05:04:17 PM PDT 24
Peak memory 203932 kb
Host smart-722a583d-b36c-4acc-b889-c8d457691bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669738947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
669738947
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1517160372
Short name T117
Test name
Test status
Simulation time 33979901 ps
CPU time 1.28 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:23 PM PDT 24
Peak memory 215304 kb
Host smart-d89d59d8-eaaa-49d6-a240-edfede82fa5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517160372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1517160372
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2744978639
Short name T1035
Test name
Test status
Simulation time 30513690 ps
CPU time 0.64 seconds
Started Jun 24 05:04:19 PM PDT 24
Finished Jun 24 05:04:20 PM PDT 24
Peak memory 203536 kb
Host smart-8e72d1f7-54b6-49d1-904b-5718ae5f4b97
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744978639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2744978639
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3475261892
Short name T1070
Test name
Test status
Simulation time 357093255 ps
CPU time 3.18 seconds
Started Jun 24 05:04:21 PM PDT 24
Finished Jun 24 05:04:25 PM PDT 24
Peak memory 215356 kb
Host smart-cb69d947-baec-4546-b276-53128cc33fee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475261892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3475261892
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1654475739
Short name T99
Test name
Test status
Simulation time 375184589 ps
CPU time 4.75 seconds
Started Jun 24 05:04:13 PM PDT 24
Finished Jun 24 05:04:18 PM PDT 24
Peak memory 215328 kb
Host smart-043f234e-b196-4b92-ab74-e142e4009fdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654475739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
654475739
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3364978468
Short name T166
Test name
Test status
Simulation time 298496189 ps
CPU time 20.12 seconds
Started Jun 24 05:04:14 PM PDT 24
Finished Jun 24 05:04:35 PM PDT 24
Peak memory 215920 kb
Host smart-24fcb749-fab1-45b5-be0e-a3f05a3f4707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364978468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3364978468
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1596421569
Short name T1017
Test name
Test status
Simulation time 38224598 ps
CPU time 0.72 seconds
Started Jun 24 05:04:56 PM PDT 24
Finished Jun 24 05:04:58 PM PDT 24
Peak memory 203916 kb
Host smart-d8dd1929-9f01-42ed-a239-2bbaa92cf43d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596421569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1596421569
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3304667726
Short name T1022
Test name
Test status
Simulation time 18148203 ps
CPU time 0.68 seconds
Started Jun 24 05:04:55 PM PDT 24
Finished Jun 24 05:04:57 PM PDT 24
Peak memory 203480 kb
Host smart-67fbbbbe-08d8-4528-b932-91f41d2ca48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304667726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3304667726
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.626983170
Short name T990
Test name
Test status
Simulation time 20113126 ps
CPU time 0.77 seconds
Started Jun 24 05:04:57 PM PDT 24
Finished Jun 24 05:04:58 PM PDT 24
Peak memory 203636 kb
Host smart-494d74ef-8553-424e-914f-176185778df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626983170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.626983170
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.225213437
Short name T987
Test name
Test status
Simulation time 18768966 ps
CPU time 0.67 seconds
Started Jun 24 05:04:57 PM PDT 24
Finished Jun 24 05:04:59 PM PDT 24
Peak memory 203568 kb
Host smart-45757dcd-b545-445c-901b-4ff3b45012a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225213437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.225213437
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3234439599
Short name T1009
Test name
Test status
Simulation time 26652172 ps
CPU time 0.73 seconds
Started Jun 24 05:05:05 PM PDT 24
Finished Jun 24 05:05:07 PM PDT 24
Peak memory 203576 kb
Host smart-72399daf-059c-4571-b4dc-1647e918ada6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234439599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3234439599
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3612642936
Short name T982
Test name
Test status
Simulation time 43730182 ps
CPU time 0.7 seconds
Started Jun 24 05:04:57 PM PDT 24
Finished Jun 24 05:04:58 PM PDT 24
Peak memory 203892 kb
Host smart-2b24cf33-f84b-45cc-84d1-d41059138447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612642936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3612642936
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3680757648
Short name T1081
Test name
Test status
Simulation time 32966064 ps
CPU time 0.82 seconds
Started Jun 24 05:04:58 PM PDT 24
Finished Jun 24 05:05:01 PM PDT 24
Peak memory 203608 kb
Host smart-10757786-2b8b-445f-a988-744f6ca4fe78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680757648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3680757648
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1060263315
Short name T978
Test name
Test status
Simulation time 14636905 ps
CPU time 0.8 seconds
Started Jun 24 05:05:05 PM PDT 24
Finished Jun 24 05:05:07 PM PDT 24
Peak memory 203908 kb
Host smart-fd473104-e828-4725-8f21-9f09d6308fbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060263315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1060263315
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.683135737
Short name T1058
Test name
Test status
Simulation time 32092315 ps
CPU time 0.75 seconds
Started Jun 24 05:05:02 PM PDT 24
Finished Jun 24 05:05:03 PM PDT 24
Peak memory 203956 kb
Host smart-d215eef6-a5d0-4380-97fa-e84237fa6719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683135737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.683135737
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2476741691
Short name T1097
Test name
Test status
Simulation time 47167907 ps
CPU time 0.71 seconds
Started Jun 24 05:04:55 PM PDT 24
Finished Jun 24 05:04:57 PM PDT 24
Peak memory 203680 kb
Host smart-aefed54b-8641-4aad-bfeb-8ee94dee5c26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476741691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2476741691
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4211695551
Short name T1059
Test name
Test status
Simulation time 190554730 ps
CPU time 2.51 seconds
Started Jun 24 05:04:25 PM PDT 24
Finished Jun 24 05:04:28 PM PDT 24
Peak memory 216744 kb
Host smart-7afeda95-9efa-46b0-94fd-543e5b916496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211695551 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4211695551
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.707465936
Short name T1084
Test name
Test status
Simulation time 123680961 ps
CPU time 1.23 seconds
Started Jun 24 05:04:21 PM PDT 24
Finished Jun 24 05:04:23 PM PDT 24
Peak memory 215340 kb
Host smart-a94c06d8-b8d9-4608-a126-9208c15c8625
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707465936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.707465936
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1246508001
Short name T998
Test name
Test status
Simulation time 25301203 ps
CPU time 0.73 seconds
Started Jun 24 05:04:22 PM PDT 24
Finished Jun 24 05:04:23 PM PDT 24
Peak memory 203680 kb
Host smart-e198f157-8aed-4e5b-a426-c268cc01a50e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246508001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
246508001
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1899253629
Short name T1018
Test name
Test status
Simulation time 104034143 ps
CPU time 1.83 seconds
Started Jun 24 05:04:19 PM PDT 24
Finished Jun 24 05:04:22 PM PDT 24
Peak memory 215288 kb
Host smart-0d73ea4b-88d4-48f4-bb77-9a6c6b0486e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899253629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1899253629
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.24344477
Short name T165
Test name
Test status
Simulation time 431855444 ps
CPU time 6.49 seconds
Started Jun 24 05:04:22 PM PDT 24
Finished Jun 24 05:04:29 PM PDT 24
Peak memory 215672 kb
Host smart-6d60a367-7ef6-424c-933d-d3dd8af80555
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_t
l_intg_err.24344477
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2970968413
Short name T1079
Test name
Test status
Simulation time 251376363 ps
CPU time 2.79 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:44 PM PDT 24
Peak memory 216268 kb
Host smart-ebe9d0fe-0770-4904-977a-dd97d2bff3f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970968413 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2970968413
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2366223225
Short name T114
Test name
Test status
Simulation time 456343214 ps
CPU time 2.95 seconds
Started Jun 24 05:04:26 PM PDT 24
Finished Jun 24 05:04:30 PM PDT 24
Peak memory 215260 kb
Host smart-ffbe215e-ff21-4b4c-bf6e-d1979253962e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366223225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
366223225
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2217128023
Short name T1004
Test name
Test status
Simulation time 13066626 ps
CPU time 0.73 seconds
Started Jun 24 05:04:22 PM PDT 24
Finished Jun 24 05:04:23 PM PDT 24
Peak memory 203860 kb
Host smart-1f08f39b-c19a-4c38-a632-ad060812c807
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217128023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
217128023
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2768210719
Short name T989
Test name
Test status
Simulation time 208180233 ps
CPU time 4.09 seconds
Started Jun 24 05:04:26 PM PDT 24
Finished Jun 24 05:04:31 PM PDT 24
Peak memory 215280 kb
Host smart-3ce286cd-ac66-4001-85b1-3c8c59c59834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768210719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2768210719
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1767217576
Short name T164
Test name
Test status
Simulation time 737259016 ps
CPU time 13.7 seconds
Started Jun 24 05:04:20 PM PDT 24
Finished Jun 24 05:04:35 PM PDT 24
Peak memory 215300 kb
Host smart-84e580a6-d914-478e-b14a-1a4dd320f6f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767217576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1767217576
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.210910589
Short name T1014
Test name
Test status
Simulation time 147916158 ps
CPU time 1.63 seconds
Started Jun 24 05:04:26 PM PDT 24
Finished Jun 24 05:04:29 PM PDT 24
Peak memory 215352 kb
Host smart-a20ee526-f2ef-482e-b4de-1ca3ae2c9e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210910589 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.210910589
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.154013732
Short name T1076
Test name
Test status
Simulation time 74706992 ps
CPU time 1.28 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:42 PM PDT 24
Peak memory 215304 kb
Host smart-66d19256-54d8-4cb2-b5f2-c4c72f992b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154013732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.154013732
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.867011962
Short name T1082
Test name
Test status
Simulation time 35247645 ps
CPU time 0.69 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:41 PM PDT 24
Peak memory 203624 kb
Host smart-326d84fb-0bf6-47cb-bb4f-690b7d1a5fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867011962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.867011962
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3249170765
Short name T1073
Test name
Test status
Simulation time 139248895 ps
CPU time 3.01 seconds
Started Jun 24 05:04:27 PM PDT 24
Finished Jun 24 05:04:31 PM PDT 24
Peak memory 215304 kb
Host smart-d21098e0-13fc-4769-8e97-1708cfbb7212
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249170765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3249170765
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3134835310
Short name T1025
Test name
Test status
Simulation time 123202856 ps
CPU time 1.7 seconds
Started Jun 24 05:04:27 PM PDT 24
Finished Jun 24 05:04:30 PM PDT 24
Peak memory 215372 kb
Host smart-0b98a377-6e3b-4abb-9c37-3d75e1b754ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134835310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
134835310
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3208731283
Short name T97
Test name
Test status
Simulation time 416883835 ps
CPU time 7.1 seconds
Started Jun 24 05:04:26 PM PDT 24
Finished Jun 24 05:04:34 PM PDT 24
Peak memory 215288 kb
Host smart-275f5612-f8c4-4622-b8c9-e01105ec1ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208731283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3208731283
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2283269045
Short name T1037
Test name
Test status
Simulation time 102480755 ps
CPU time 2.59 seconds
Started Jun 24 05:04:26 PM PDT 24
Finished Jun 24 05:04:29 PM PDT 24
Peak memory 216676 kb
Host smart-b03dde7b-8383-402c-b269-c526fed5494c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283269045 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2283269045
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3305999307
Short name T1074
Test name
Test status
Simulation time 33668126 ps
CPU time 2.28 seconds
Started Jun 24 05:04:31 PM PDT 24
Finished Jun 24 05:04:34 PM PDT 24
Peak memory 215344 kb
Host smart-a510ca1c-6e7e-4be3-9b8c-7c8a03e37cbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305999307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
305999307
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.346432481
Short name T994
Test name
Test status
Simulation time 45102226 ps
CPU time 0.77 seconds
Started Jun 24 05:04:28 PM PDT 24
Finished Jun 24 05:04:29 PM PDT 24
Peak memory 203692 kb
Host smart-c37b8f7e-84a3-45e6-a1a0-3fb559474e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346432481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.346432481
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.388223666
Short name T1042
Test name
Test status
Simulation time 217205747 ps
CPU time 3.86 seconds
Started Jun 24 05:04:27 PM PDT 24
Finished Jun 24 05:04:32 PM PDT 24
Peak memory 215364 kb
Host smart-6f8b7355-8235-41c4-bfb0-855b56abe727
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388223666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.388223666
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.296688031
Short name T106
Test name
Test status
Simulation time 644392920 ps
CPU time 4.41 seconds
Started Jun 24 05:04:26 PM PDT 24
Finished Jun 24 05:04:31 PM PDT 24
Peak memory 215476 kb
Host smart-59ce917b-cba5-4657-b62b-e17011c659e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296688031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.296688031
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.69176088
Short name T109
Test name
Test status
Simulation time 303459842 ps
CPU time 8.56 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:49 PM PDT 24
Peak memory 215296 kb
Host smart-8dbdb9d8-e86e-424b-8f86-cc514b636f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69176088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_t
l_intg_err.69176088
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2999126433
Short name T1050
Test name
Test status
Simulation time 1653558878 ps
CPU time 3.37 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:44 PM PDT 24
Peak memory 217312 kb
Host smart-609fdb8b-fe9e-4ca3-9e5f-9a3332e77178
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999126433 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2999126433
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2978794648
Short name T1090
Test name
Test status
Simulation time 22620350 ps
CPU time 1.41 seconds
Started Jun 24 05:04:26 PM PDT 24
Finished Jun 24 05:04:29 PM PDT 24
Peak memory 215352 kb
Host smart-efe4dba5-aabf-47ae-abb1-99dc4606910e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978794648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
978794648
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3261500597
Short name T980
Test name
Test status
Simulation time 14117241 ps
CPU time 0.72 seconds
Started Jun 24 05:04:40 PM PDT 24
Finished Jun 24 05:04:41 PM PDT 24
Peak memory 203680 kb
Host smart-2bdc0afc-3a6b-4552-88f5-d93470638082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261500597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
261500597
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3072668888
Short name T1008
Test name
Test status
Simulation time 45599316 ps
CPU time 2.89 seconds
Started Jun 24 05:04:27 PM PDT 24
Finished Jun 24 05:04:31 PM PDT 24
Peak memory 215228 kb
Host smart-c3b1b707-e9ef-4bad-aa2d-25203ee979f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072668888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3072668888
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.801144927
Short name T1011
Test name
Test status
Simulation time 205022929 ps
CPU time 2.92 seconds
Started Jun 24 05:04:27 PM PDT 24
Finished Jun 24 05:04:31 PM PDT 24
Peak memory 215372 kb
Host smart-07e08b9a-8d16-40ef-a4af-53b94507d711
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801144927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.801144927
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3186549164
Short name T168
Test name
Test status
Simulation time 568125306 ps
CPU time 17.54 seconds
Started Jun 24 05:04:27 PM PDT 24
Finished Jun 24 05:04:46 PM PDT 24
Peak memory 215412 kb
Host smart-4e89837f-24c6-4951-bf4c-c6177d51b7cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186549164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3186549164
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1568916905
Short name T454
Test name
Test status
Simulation time 62027928 ps
CPU time 0.72 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:14 PM PDT 24
Peak memory 205616 kb
Host smart-216324df-b154-4b8a-adc8-ffb425009ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568916905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
568916905
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3477117397
Short name T729
Test name
Test status
Simulation time 183908745 ps
CPU time 2.38 seconds
Started Jun 24 05:10:11 PM PDT 24
Finished Jun 24 05:10:15 PM PDT 24
Peak memory 225508 kb
Host smart-7476d18f-7ab7-4323-b1a2-3039eed86aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477117397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3477117397
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1816758206
Short name T482
Test name
Test status
Simulation time 35987964 ps
CPU time 0.76 seconds
Started Jun 24 05:10:09 PM PDT 24
Finished Jun 24 05:10:11 PM PDT 24
Peak memory 206632 kb
Host smart-d8e3003f-14a9-4e47-ab7d-1461d3167546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816758206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1816758206
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2244189878
Short name T721
Test name
Test status
Simulation time 23354997427 ps
CPU time 121 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:12:15 PM PDT 24
Peak memory 256292 kb
Host smart-8899ef5b-c455-4d68-8a18-8ed44b136bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244189878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2244189878
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2326444906
Short name T61
Test name
Test status
Simulation time 83264296830 ps
CPU time 155.09 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:12:49 PM PDT 24
Peak memory 250212 kb
Host smart-956e700f-a529-4440-9683-8dcf63300268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326444906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2326444906
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2022070872
Short name T286
Test name
Test status
Simulation time 5103882808 ps
CPU time 17.39 seconds
Started Jun 24 05:10:13 PM PDT 24
Finished Jun 24 05:10:31 PM PDT 24
Peak memory 237432 kb
Host smart-7832e53e-0f8d-408b-b986-705cfaf693b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022070872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2022070872
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4068245871
Short name T486
Test name
Test status
Simulation time 375419550 ps
CPU time 6.79 seconds
Started Jun 24 05:10:09 PM PDT 24
Finished Jun 24 05:10:16 PM PDT 24
Peak memory 225492 kb
Host smart-e8e5f579-9a69-4583-a618-9f1cb567b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068245871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4068245871
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.907249948
Short name T523
Test name
Test status
Simulation time 784625642 ps
CPU time 16.87 seconds
Started Jun 24 05:10:11 PM PDT 24
Finished Jun 24 05:10:29 PM PDT 24
Peak memory 241864 kb
Host smart-46d6ca6e-ea29-4f71-aa58-9343ebbd6857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907249948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.907249948
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.148864268
Short name T243
Test name
Test status
Simulation time 155962324 ps
CPU time 2.76 seconds
Started Jun 24 05:10:09 PM PDT 24
Finished Jun 24 05:10:13 PM PDT 24
Peak memory 233680 kb
Host smart-082c70d1-76e2-4437-b1d5-74aad4809e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148864268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
148864268
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3228734553
Short name T960
Test name
Test status
Simulation time 3456125915 ps
CPU time 11.04 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:25 PM PDT 24
Peak memory 224400 kb
Host smart-94ac2fe2-2d2c-4bda-82ac-1a5103ed2bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228734553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3228734553
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3338089810
Short name T139
Test name
Test status
Simulation time 4558379280 ps
CPU time 11.76 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:25 PM PDT 24
Peak memory 222804 kb
Host smart-e0760cf3-ca84-4d70-b4b8-e3f8018abc69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3338089810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3338089810
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.32622891
Short name T73
Test name
Test status
Simulation time 34761210 ps
CPU time 0.94 seconds
Started Jun 24 05:10:11 PM PDT 24
Finished Jun 24 05:10:12 PM PDT 24
Peak memory 236340 kb
Host smart-38c1fbea-b730-4390-915c-1a5bd4909e54
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32622891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.32622891
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.604617316
Short name T824
Test name
Test status
Simulation time 58833340508 ps
CPU time 116.51 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:12:10 PM PDT 24
Peak memory 242480 kb
Host smart-d07bac36-85f6-44a0-bed9-845059d634f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604617316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.604617316
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2762561830
Short name T287
Test name
Test status
Simulation time 7718965104 ps
CPU time 26.98 seconds
Started Jun 24 05:10:13 PM PDT 24
Finished Jun 24 05:10:41 PM PDT 24
Peak memory 217364 kb
Host smart-4ad04adf-2cd7-4690-80c4-e56955e64ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762561830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2762561830
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1511922151
Short name T876
Test name
Test status
Simulation time 520652716 ps
CPU time 4.23 seconds
Started Jun 24 05:10:11 PM PDT 24
Finished Jun 24 05:10:16 PM PDT 24
Peak memory 217260 kb
Host smart-37b8c9e3-eadd-4161-a6c8-5fd60f8a6f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511922151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1511922151
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4241516359
Short name T351
Test name
Test status
Simulation time 147730829 ps
CPU time 1.32 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:14 PM PDT 24
Peak memory 217264 kb
Host smart-9f6b6821-8ddb-4f1d-a701-dbd3338213a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241516359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4241516359
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.908174068
Short name T527
Test name
Test status
Simulation time 95346372 ps
CPU time 0.8 seconds
Started Jun 24 05:10:14 PM PDT 24
Finished Jun 24 05:10:16 PM PDT 24
Peak memory 206864 kb
Host smart-bc735df2-2911-4905-84a2-16bfe2874053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908174068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.908174068
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3035419435
Short name T472
Test name
Test status
Simulation time 1034630732 ps
CPU time 10.27 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:24 PM PDT 24
Peak memory 241688 kb
Host smart-1d506309-24e8-4e9c-8ca6-383ffb28f1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035419435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3035419435
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3252579327
Short name T798
Test name
Test status
Simulation time 76456463 ps
CPU time 2.33 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:10:21 PM PDT 24
Peak memory 225496 kb
Host smart-bae64b1a-ee6a-4d3b-b421-03a728642638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252579327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3252579327
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.900659276
Short name T797
Test name
Test status
Simulation time 21382793 ps
CPU time 0.79 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:15 PM PDT 24
Peak memory 206680 kb
Host smart-0585972f-be09-4a71-b8ab-be51fa571698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900659276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.900659276
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.492980753
Short name T592
Test name
Test status
Simulation time 105867472072 ps
CPU time 213.43 seconds
Started Jun 24 05:10:18 PM PDT 24
Finished Jun 24 05:13:52 PM PDT 24
Peak memory 255548 kb
Host smart-9764ae8e-98a0-4d54-8dc8-298ac3193099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492980753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.492980753
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1422720817
Short name T695
Test name
Test status
Simulation time 16320929122 ps
CPU time 67.26 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:11:26 PM PDT 24
Peak memory 253060 kb
Host smart-defb12e6-748e-4b59-ab2a-bcae8bd04710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422720817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1422720817
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1715048880
Short name T720
Test name
Test status
Simulation time 17726347845 ps
CPU time 135.62 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:12:34 PM PDT 24
Peak memory 253368 kb
Host smart-43bf8a00-a77e-41a7-9f3b-e2419ba1169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715048880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1715048880
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2907536764
Short name T516
Test name
Test status
Simulation time 160239562 ps
CPU time 2.81 seconds
Started Jun 24 05:10:18 PM PDT 24
Finished Jun 24 05:10:22 PM PDT 24
Peak memory 225560 kb
Host smart-ee98bbc1-48ef-4a68-8a4e-aedb73e60c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907536764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2907536764
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4045941883
Short name T644
Test name
Test status
Simulation time 1042947493 ps
CPU time 4.8 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:10:23 PM PDT 24
Peak memory 225440 kb
Host smart-6ff80d09-6710-4ec8-ac16-642230902c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045941883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4045941883
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2056108246
Short name T344
Test name
Test status
Simulation time 231958919 ps
CPU time 4.4 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:10:20 PM PDT 24
Peak memory 233748 kb
Host smart-0bb32655-01bc-4824-b4da-f8a84db4f23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056108246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2056108246
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1304905610
Short name T743
Test name
Test status
Simulation time 33887069 ps
CPU time 1.08 seconds
Started Jun 24 05:10:10 PM PDT 24
Finished Jun 24 05:10:12 PM PDT 24
Peak memory 217616 kb
Host smart-d48b0734-69e0-4729-81c9-7d22ab888b9e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304905610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1304905610
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3152196240
Short name T70
Test name
Test status
Simulation time 896186332 ps
CPU time 3.25 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:10:20 PM PDT 24
Peak memory 225520 kb
Host smart-ed96bd82-8b36-4ddc-8cf8-f885dd8e0268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152196240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3152196240
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2963930347
Short name T419
Test name
Test status
Simulation time 26274231923 ps
CPU time 36.73 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:10:54 PM PDT 24
Peak memory 242024 kb
Host smart-9d4cbb0f-00d2-4731-bae3-58091af3f8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963930347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2963930347
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2472189971
Short name T748
Test name
Test status
Simulation time 632598869 ps
CPU time 8.57 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:10:24 PM PDT 24
Peak memory 223536 kb
Host smart-1c5fe49b-f269-42a9-a838-44c1bee9965a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2472189971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2472189971
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3843287317
Short name T76
Test name
Test status
Simulation time 35167918 ps
CPU time 0.9 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:10:20 PM PDT 24
Peak memory 236280 kb
Host smart-56711d12-7e6f-41ac-990b-bb8a11397f03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843287317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3843287317
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2160947462
Short name T658
Test name
Test status
Simulation time 1664967760 ps
CPU time 11.41 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:25 PM PDT 24
Peak memory 217516 kb
Host smart-1fbb83d1-1373-40fc-84a8-7afce8f5f716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160947462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2160947462
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1836308268
Short name T308
Test name
Test status
Simulation time 67820740 ps
CPU time 1.25 seconds
Started Jun 24 05:10:08 PM PDT 24
Finished Jun 24 05:10:10 PM PDT 24
Peak memory 209008 kb
Host smart-078a7236-be2b-4b50-b65a-3ea3f1531747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836308268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1836308268
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2520987564
Short name T879
Test name
Test status
Simulation time 20501346 ps
CPU time 0.66 seconds
Started Jun 24 05:10:12 PM PDT 24
Finished Jun 24 05:10:14 PM PDT 24
Peak memory 206388 kb
Host smart-1ea05015-6a21-4e95-bd2a-187cc2eda7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520987564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2520987564
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4094343084
Short name T389
Test name
Test status
Simulation time 6996972294 ps
CPU time 25.44 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 233864 kb
Host smart-dddfec0e-d832-4dd0-adfd-b5a632a2fc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094343084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4094343084
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2616342279
Short name T785
Test name
Test status
Simulation time 11280828 ps
CPU time 0.71 seconds
Started Jun 24 05:11:00 PM PDT 24
Finished Jun 24 05:11:02 PM PDT 24
Peak memory 205624 kb
Host smart-fc3c3235-ea64-4928-a416-63c2485ca5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616342279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2616342279
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1409104932
Short name T229
Test name
Test status
Simulation time 3364213868 ps
CPU time 11.42 seconds
Started Jun 24 05:10:58 PM PDT 24
Finished Jun 24 05:11:11 PM PDT 24
Peak memory 225604 kb
Host smart-c1ba1bca-e27c-4004-8a32-a20e553c6c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409104932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1409104932
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2329545394
Short name T471
Test name
Test status
Simulation time 13708304 ps
CPU time 0.79 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:10:57 PM PDT 24
Peak memory 207396 kb
Host smart-563b5559-66e1-4613-a755-4d9c12f32dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329545394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2329545394
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3838933023
Short name T239
Test name
Test status
Simulation time 6843417465 ps
CPU time 48.76 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 256792 kb
Host smart-d5dc8f54-a4b2-475e-ab45-b129983d02e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838933023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3838933023
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3370017284
Short name T517
Test name
Test status
Simulation time 2929157061 ps
CPU time 30.23 seconds
Started Jun 24 05:11:00 PM PDT 24
Finished Jun 24 05:11:32 PM PDT 24
Peak memory 240168 kb
Host smart-91feae0f-9e1d-490f-bbe6-e2b3e76874c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370017284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3370017284
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1956863925
Short name T896
Test name
Test status
Simulation time 112938586183 ps
CPU time 246.07 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:15:10 PM PDT 24
Peak memory 264984 kb
Host smart-70c57149-5c47-491a-946d-bc3be32019ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956863925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1956863925
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1927558940
Short name T837
Test name
Test status
Simulation time 374902163 ps
CPU time 6.89 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:11:11 PM PDT 24
Peak memory 249320 kb
Host smart-907bb0a9-275a-439b-b8ad-f59269780d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927558940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1927558940
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.460306730
Short name T367
Test name
Test status
Simulation time 721227867 ps
CPU time 4.38 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:11:01 PM PDT 24
Peak memory 233772 kb
Host smart-73a64a94-a005-41e7-9623-03e3631b1c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460306730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.460306730
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1321453699
Short name T220
Test name
Test status
Simulation time 2464325167 ps
CPU time 34.87 seconds
Started Jun 24 05:10:55 PM PDT 24
Finished Jun 24 05:11:33 PM PDT 24
Peak memory 241552 kb
Host smart-b0ef0371-7675-44b4-a7a1-11a8618e8597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321453699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1321453699
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1115537695
Short name T557
Test name
Test status
Simulation time 102765497 ps
CPU time 1.15 seconds
Started Jun 24 05:11:00 PM PDT 24
Finished Jun 24 05:11:02 PM PDT 24
Peak memory 217620 kb
Host smart-6c5e7cff-4c88-42ac-9180-5a5d5ef10889
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115537695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1115537695
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3563421109
Short name T665
Test name
Test status
Simulation time 6276585085 ps
CPU time 19.46 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:11:16 PM PDT 24
Peak memory 240844 kb
Host smart-9827649e-9545-446a-a5d1-7230c21695a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563421109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3563421109
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2751377344
Short name T252
Test name
Test status
Simulation time 1274175281 ps
CPU time 8.32 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:11:04 PM PDT 24
Peak memory 225404 kb
Host smart-7c54b60a-9c19-4335-ac58-0ec807298797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751377344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2751377344
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4069600411
Short name T384
Test name
Test status
Simulation time 249067550 ps
CPU time 4.33 seconds
Started Jun 24 05:11:01 PM PDT 24
Finished Jun 24 05:11:07 PM PDT 24
Peak memory 221192 kb
Host smart-875854e8-93fe-4749-9b66-a4e47f197fac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4069600411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4069600411
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.263369168
Short name T18
Test name
Test status
Simulation time 18220447440 ps
CPU time 186.89 seconds
Started Jun 24 05:11:04 PM PDT 24
Finished Jun 24 05:14:14 PM PDT 24
Peak memory 256376 kb
Host smart-19b0c72e-2c65-4f34-b5dd-b49d43f56103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263369168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.263369168
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.444012595
Short name T291
Test name
Test status
Simulation time 7264437861 ps
CPU time 42.92 seconds
Started Jun 24 05:10:57 PM PDT 24
Finished Jun 24 05:11:42 PM PDT 24
Peak memory 217316 kb
Host smart-56e30100-d627-4dae-806e-b7b9c1b82abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444012595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.444012595
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4261019695
Short name T686
Test name
Test status
Simulation time 1373183624 ps
CPU time 4.35 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:10:59 PM PDT 24
Peak memory 217324 kb
Host smart-3ac4c914-e156-4e10-bdae-381fc5e4adc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261019695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4261019695
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.997779286
Short name T304
Test name
Test status
Simulation time 210640682 ps
CPU time 7.4 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:11:04 PM PDT 24
Peak memory 217324 kb
Host smart-ba485bd5-a26d-4908-8280-b6a79a166a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997779286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.997779286
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2195345444
Short name T323
Test name
Test status
Simulation time 46996604 ps
CPU time 0.74 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:10:57 PM PDT 24
Peak memory 206868 kb
Host smart-ed7a70d7-ec94-4167-a894-343d47f6b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195345444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2195345444
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.924120843
Short name T674
Test name
Test status
Simulation time 60664997 ps
CPU time 2.27 seconds
Started Jun 24 05:10:55 PM PDT 24
Finished Jun 24 05:10:59 PM PDT 24
Peak memory 225508 kb
Host smart-7ad458e3-651e-478e-a9d4-d196071341f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924120843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.924120843
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1947610709
Short name T911
Test name
Test status
Simulation time 56966272 ps
CPU time 0.72 seconds
Started Jun 24 05:11:00 PM PDT 24
Finished Jun 24 05:11:03 PM PDT 24
Peak memory 205696 kb
Host smart-abb21a7d-8a5d-4191-bad2-3369ab4173d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947610709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1947610709
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3202177764
Short name T871
Test name
Test status
Simulation time 23362749176 ps
CPU time 17.32 seconds
Started Jun 24 05:11:03 PM PDT 24
Finished Jun 24 05:11:23 PM PDT 24
Peak memory 225664 kb
Host smart-c7629565-be1f-406d-a237-a4fc318cf77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202177764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3202177764
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3177457352
Short name T298
Test name
Test status
Simulation time 65054399 ps
CPU time 0.77 seconds
Started Jun 24 05:11:04 PM PDT 24
Finished Jun 24 05:11:07 PM PDT 24
Peak memory 206444 kb
Host smart-ba268931-8fce-44ee-ad2f-f24b532f9e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177457352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3177457352
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.391008032
Short name T935
Test name
Test status
Simulation time 22635279849 ps
CPU time 42.4 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:11:46 PM PDT 24
Peak memory 238584 kb
Host smart-0d9dc8c0-0760-4d8a-9837-64789aa1035c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391008032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.391008032
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1047825425
Short name T874
Test name
Test status
Simulation time 35709225740 ps
CPU time 277.9 seconds
Started Jun 24 05:11:04 PM PDT 24
Finished Jun 24 05:15:44 PM PDT 24
Peak memory 250672 kb
Host smart-45243659-514b-4afd-baee-9ecb2631ca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047825425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1047825425
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2298680166
Short name T926
Test name
Test status
Simulation time 15626627592 ps
CPU time 29.28 seconds
Started Jun 24 05:11:04 PM PDT 24
Finished Jun 24 05:11:35 PM PDT 24
Peak memory 233732 kb
Host smart-1c663b13-22b7-4614-b8a5-6bcac7245230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298680166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2298680166
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2691475055
Short name T216
Test name
Test status
Simulation time 1474790241 ps
CPU time 10.85 seconds
Started Jun 24 05:11:04 PM PDT 24
Finished Jun 24 05:11:17 PM PDT 24
Peak memory 233688 kb
Host smart-6fd5658a-ca3a-4d9a-806b-68e3999d8e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691475055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2691475055
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2381794492
Short name T909
Test name
Test status
Simulation time 228470320 ps
CPU time 1.09 seconds
Started Jun 24 05:11:03 PM PDT 24
Finished Jun 24 05:11:06 PM PDT 24
Peak memory 217608 kb
Host smart-d513b530-5fa1-45fe-bc3e-78753215b9c1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381794492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2381794492
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.411426213
Short name T394
Test name
Test status
Simulation time 2147852584 ps
CPU time 4.51 seconds
Started Jun 24 05:11:01 PM PDT 24
Finished Jun 24 05:11:07 PM PDT 24
Peak memory 225596 kb
Host smart-749665a0-fc37-4ec5-b923-38808ca23447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411426213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.411426213
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2344223998
Short name T707
Test name
Test status
Simulation time 2904511212 ps
CPU time 14.46 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:11:18 PM PDT 24
Peak memory 250076 kb
Host smart-63a253c2-bdb8-4727-970e-e34938fe1f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344223998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2344223998
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2389578612
Short name T504
Test name
Test status
Simulation time 1367707498 ps
CPU time 10.44 seconds
Started Jun 24 05:11:04 PM PDT 24
Finished Jun 24 05:11:17 PM PDT 24
Peak memory 219516 kb
Host smart-43ac76ff-b584-4a83-a46f-7c553b8760d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2389578612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2389578612
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.384849884
Short name T262
Test name
Test status
Simulation time 34139335192 ps
CPU time 117.53 seconds
Started Jun 24 05:11:03 PM PDT 24
Finished Jun 24 05:13:03 PM PDT 24
Peak memory 254376 kb
Host smart-cc66e1af-a167-4a10-ac9f-3e2e91c32298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384849884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.384849884
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2613273849
Short name T895
Test name
Test status
Simulation time 6290683610 ps
CPU time 27.71 seconds
Started Jun 24 05:11:00 PM PDT 24
Finished Jun 24 05:11:29 PM PDT 24
Peak memory 217420 kb
Host smart-a1a9ed0a-cb14-4182-8287-fb604baa2e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613273849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2613273849
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2641784713
Short name T949
Test name
Test status
Simulation time 537307623 ps
CPU time 2.16 seconds
Started Jun 24 05:11:01 PM PDT 24
Finished Jun 24 05:11:05 PM PDT 24
Peak memory 217344 kb
Host smart-e5f3a71a-f8a5-473f-bf69-cdadeddb71db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641784713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2641784713
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1505558328
Short name T590
Test name
Test status
Simulation time 40179050 ps
CPU time 0.79 seconds
Started Jun 24 05:11:00 PM PDT 24
Finished Jun 24 05:11:02 PM PDT 24
Peak memory 206856 kb
Host smart-76ea0202-3af2-4a3f-8e7a-d498484e99be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505558328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1505558328
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2895185403
Short name T646
Test name
Test status
Simulation time 28920733 ps
CPU time 0.78 seconds
Started Jun 24 05:11:01 PM PDT 24
Finished Jun 24 05:11:04 PM PDT 24
Peak memory 206528 kb
Host smart-5cb3b328-26e4-4ea6-aaeb-88513bb1ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895185403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2895185403
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3860463834
Short name T236
Test name
Test status
Simulation time 12218180798 ps
CPU time 11.51 seconds
Started Jun 24 05:11:03 PM PDT 24
Finished Jun 24 05:11:17 PM PDT 24
Peak memory 233724 kb
Host smart-9abafbc1-239d-4796-b545-7e0bd0d6d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860463834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3860463834
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4211868564
Short name T635
Test name
Test status
Simulation time 47325363 ps
CPU time 0.72 seconds
Started Jun 24 05:11:08 PM PDT 24
Finished Jun 24 05:11:10 PM PDT 24
Peak memory 205700 kb
Host smart-374f61b5-edf8-45cf-9101-16908c716513
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211868564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4211868564
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3613772429
Short name T541
Test name
Test status
Simulation time 184178636 ps
CPU time 3.23 seconds
Started Jun 24 05:11:11 PM PDT 24
Finished Jun 24 05:11:15 PM PDT 24
Peak memory 225556 kb
Host smart-d67a2f53-c9a7-415e-bf99-f52cfbd74553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613772429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3613772429
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4267476846
Short name T520
Test name
Test status
Simulation time 65058909 ps
CPU time 0.75 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:11:05 PM PDT 24
Peak memory 206804 kb
Host smart-11ee7764-b29b-41cc-aed8-43e84c208cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267476846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4267476846
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.646500807
Short name T276
Test name
Test status
Simulation time 60348479656 ps
CPU time 417.42 seconds
Started Jun 24 05:11:09 PM PDT 24
Finished Jun 24 05:18:09 PM PDT 24
Peak memory 262308 kb
Host smart-ab80f83c-efdd-4b0a-84e2-72a483e491c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646500807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.646500807
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2298985874
Short name T907
Test name
Test status
Simulation time 2010609186 ps
CPU time 25.25 seconds
Started Jun 24 05:11:10 PM PDT 24
Finished Jun 24 05:11:37 PM PDT 24
Peak memory 225608 kb
Host smart-0d74645e-812a-47a9-93fd-68f0116fa804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298985874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2298985874
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1210424055
Short name T910
Test name
Test status
Simulation time 220285375 ps
CPU time 2.92 seconds
Started Jun 24 05:11:09 PM PDT 24
Finished Jun 24 05:11:13 PM PDT 24
Peak memory 225492 kb
Host smart-c7e3add6-c3bb-4dfb-a992-cccdbc4e0726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210424055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1210424055
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.604844608
Short name T189
Test name
Test status
Simulation time 240292884 ps
CPU time 5.5 seconds
Started Jun 24 05:11:09 PM PDT 24
Finished Jun 24 05:11:16 PM PDT 24
Peak memory 233716 kb
Host smart-d33718fe-f79d-4f06-b57c-1fbf7e8dae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604844608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.604844608
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.315849378
Short name T540
Test name
Test status
Simulation time 19864479376 ps
CPU time 37.27 seconds
Started Jun 24 05:11:09 PM PDT 24
Finished Jun 24 05:11:48 PM PDT 24
Peak memory 233784 kb
Host smart-ac6eebb8-4029-4e9d-8a0c-00b797329f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315849378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.315849378
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.814338001
Short name T447
Test name
Test status
Simulation time 42531837 ps
CPU time 1.08 seconds
Started Jun 24 05:11:00 PM PDT 24
Finished Jun 24 05:11:02 PM PDT 24
Peak memory 218848 kb
Host smart-8b2a5892-13eb-45a5-827c-ebb0362b4ee3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814338001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.814338001
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.854960800
Short name T682
Test name
Test status
Simulation time 735548988 ps
CPU time 3.17 seconds
Started Jun 24 05:11:07 PM PDT 24
Finished Jun 24 05:11:12 PM PDT 24
Peak memory 233720 kb
Host smart-71cd475a-7b22-4b3f-80b3-51391de6c707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854960800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.854960800
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2234778389
Short name T846
Test name
Test status
Simulation time 54074261 ps
CPU time 2.53 seconds
Started Jun 24 05:11:08 PM PDT 24
Finished Jun 24 05:11:12 PM PDT 24
Peak memory 233672 kb
Host smart-4dc319d8-ee6b-43f0-a1f0-7dd750d653f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234778389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2234778389
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2309843806
Short name T882
Test name
Test status
Simulation time 283482150 ps
CPU time 4.95 seconds
Started Jun 24 05:11:09 PM PDT 24
Finished Jun 24 05:11:15 PM PDT 24
Peak memory 221200 kb
Host smart-a9a0d438-4ca1-40f7-bab3-53e61eb93a65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2309843806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2309843806
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.872791911
Short name T612
Test name
Test status
Simulation time 25852428019 ps
CPU time 35.72 seconds
Started Jun 24 05:11:10 PM PDT 24
Finished Jun 24 05:11:47 PM PDT 24
Peak memory 217428 kb
Host smart-b46f0500-7124-447c-9ddc-e8c1a29f4b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872791911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.872791911
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1721932464
Short name T848
Test name
Test status
Simulation time 179725489 ps
CPU time 0.7 seconds
Started Jun 24 05:11:02 PM PDT 24
Finished Jun 24 05:11:05 PM PDT 24
Peak memory 206580 kb
Host smart-377e46c8-fafc-4ecd-b8e0-81c221a543bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721932464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1721932464
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.538541439
Short name T585
Test name
Test status
Simulation time 21742951 ps
CPU time 0.69 seconds
Started Jun 24 05:11:07 PM PDT 24
Finished Jun 24 05:11:09 PM PDT 24
Peak memory 206444 kb
Host smart-def50827-4b84-4ac6-8fd7-92f890fe6367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538541439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.538541439
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1029057116
Short name T676
Test name
Test status
Simulation time 58098482 ps
CPU time 0.89 seconds
Started Jun 24 05:11:08 PM PDT 24
Finished Jun 24 05:11:10 PM PDT 24
Peak memory 206884 kb
Host smart-ce0812b6-11c5-42b5-8c8d-403a480f49ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029057116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1029057116
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2560768846
Short name T543
Test name
Test status
Simulation time 431602218 ps
CPU time 6.76 seconds
Started Jun 24 05:11:08 PM PDT 24
Finished Jun 24 05:11:16 PM PDT 24
Peak memory 233692 kb
Host smart-bc122966-d77d-449a-8bfb-4e16ea092274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560768846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2560768846
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.502925846
Short name T529
Test name
Test status
Simulation time 24071360 ps
CPU time 0.73 seconds
Started Jun 24 05:11:15 PM PDT 24
Finished Jun 24 05:11:17 PM PDT 24
Peak memory 206508 kb
Host smart-98d02afb-ad67-4410-8997-b8ad15341206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502925846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.502925846
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1606727441
Short name T936
Test name
Test status
Simulation time 638612705 ps
CPU time 4.13 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:11:21 PM PDT 24
Peak memory 233584 kb
Host smart-95343e60-f93e-4c8a-928b-fbb02450b993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606727441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1606727441
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4224932699
Short name T425
Test name
Test status
Simulation time 159213831 ps
CPU time 0.79 seconds
Started Jun 24 05:11:09 PM PDT 24
Finished Jun 24 05:11:11 PM PDT 24
Peak memory 207728 kb
Host smart-3d9e18c0-f921-46a6-bcda-97505800c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224932699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4224932699
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4097771521
Short name T919
Test name
Test status
Simulation time 51051226298 ps
CPU time 165.13 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:14:03 PM PDT 24
Peak memory 250280 kb
Host smart-99d8b894-db89-4958-b471-455552465a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097771521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4097771521
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3814621719
Short name T57
Test name
Test status
Simulation time 47580097562 ps
CPU time 35.06 seconds
Started Jun 24 05:11:17 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 225576 kb
Host smart-483f2e2b-f320-4060-85e6-10814e45f77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814621719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3814621719
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3252556354
Short name T402
Test name
Test status
Simulation time 4045654213 ps
CPU time 10.92 seconds
Started Jun 24 05:11:15 PM PDT 24
Finished Jun 24 05:11:27 PM PDT 24
Peak memory 225616 kb
Host smart-c683ae1b-3d6a-440e-a182-9826fe1756c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252556354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3252556354
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.817585988
Short name T64
Test name
Test status
Simulation time 712743427 ps
CPU time 14 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:11:32 PM PDT 24
Peak memory 233724 kb
Host smart-6676d14a-9d58-4511-a2a8-a6649404686e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817585988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.817585988
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1446165012
Short name T829
Test name
Test status
Simulation time 59303791 ps
CPU time 0.99 seconds
Started Jun 24 05:11:11 PM PDT 24
Finished Jun 24 05:11:13 PM PDT 24
Peak memory 217604 kb
Host smart-e57a1e59-8839-4aa2-bf92-befd6fb6cec8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446165012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1446165012
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1523626996
Short name T594
Test name
Test status
Simulation time 273533898 ps
CPU time 3.15 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:29 PM PDT 24
Peak memory 233716 kb
Host smart-bd17e6e1-7ab1-4c10-bc91-c680b45d84d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523626996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1523626996
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.172400097
Short name T934
Test name
Test status
Simulation time 6668065811 ps
CPU time 12.71 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:38 PM PDT 24
Peak memory 235196 kb
Host smart-48d0f0e4-fa91-407a-bc4b-8b1d692a4749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172400097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.172400097
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2568074231
Short name T550
Test name
Test status
Simulation time 129722691 ps
CPU time 0.96 seconds
Started Jun 24 05:11:15 PM PDT 24
Finished Jun 24 05:11:17 PM PDT 24
Peak memory 207708 kb
Host smart-1f1804e2-a0c0-404c-ad40-9d81f80f283b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568074231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2568074231
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.899066810
Short name T696
Test name
Test status
Simulation time 680770176 ps
CPU time 4.65 seconds
Started Jun 24 05:11:07 PM PDT 24
Finished Jun 24 05:11:13 PM PDT 24
Peak memory 217552 kb
Host smart-0cc8141d-0102-44c5-b6a0-4f7b1be70e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899066810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.899066810
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1456719117
Short name T444
Test name
Test status
Simulation time 928582776 ps
CPU time 2.89 seconds
Started Jun 24 05:11:12 PM PDT 24
Finished Jun 24 05:11:16 PM PDT 24
Peak memory 217088 kb
Host smart-e8aa16e5-c5df-41eb-8486-93451bacb06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456719117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1456719117
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.494053647
Short name T547
Test name
Test status
Simulation time 163459347 ps
CPU time 1.5 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:11:19 PM PDT 24
Peak memory 209108 kb
Host smart-fc72d055-6ad0-4677-b935-59f71c6ab5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494053647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.494053647
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3289989412
Short name T922
Test name
Test status
Simulation time 18336855 ps
CPU time 0.75 seconds
Started Jun 24 05:11:06 PM PDT 24
Finished Jun 24 05:11:09 PM PDT 24
Peak memory 206868 kb
Host smart-b149c751-b07f-48de-bdbd-dd4974dcc84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289989412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3289989412
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2037304861
Short name T963
Test name
Test status
Simulation time 2705573698 ps
CPU time 13.16 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:39 PM PDT 24
Peak memory 233876 kb
Host smart-fd92a581-7297-4cb3-ae94-c4c741359da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037304861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2037304861
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1575243851
Short name T409
Test name
Test status
Simulation time 40630337 ps
CPU time 0.71 seconds
Started Jun 24 05:11:22 PM PDT 24
Finished Jun 24 05:11:25 PM PDT 24
Peak memory 205684 kb
Host smart-ba293086-b911-4b1d-bb7f-d22a37c7ab87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575243851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1575243851
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.466421042
Short name T360
Test name
Test status
Simulation time 1165461585 ps
CPU time 5.91 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:32 PM PDT 24
Peak memory 225504 kb
Host smart-fa0b9428-d5cc-488a-bc42-03d707b09a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466421042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.466421042
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3830221516
Short name T672
Test name
Test status
Simulation time 61963951 ps
CPU time 0.83 seconds
Started Jun 24 05:11:17 PM PDT 24
Finished Jun 24 05:11:20 PM PDT 24
Peak memory 207816 kb
Host smart-e1e31f5f-7a6e-4dbb-a8eb-69f29f79fdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830221516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3830221516
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2935625906
Short name T126
Test name
Test status
Simulation time 151195076588 ps
CPU time 172.82 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:14:19 PM PDT 24
Peak memory 252264 kb
Host smart-ccb4c4f9-7ac6-4be7-8e4e-e304aac7b872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935625906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2935625906
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.260277816
Short name T267
Test name
Test status
Simulation time 24006048162 ps
CPU time 92.98 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:12:58 PM PDT 24
Peak memory 266412 kb
Host smart-b9718f5a-726a-401a-b898-e5e5fbff0d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260277816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.260277816
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2226549971
Short name T731
Test name
Test status
Simulation time 18304663932 ps
CPU time 215.17 seconds
Started Jun 24 05:11:23 PM PDT 24
Finished Jun 24 05:14:59 PM PDT 24
Peak memory 274552 kb
Host smart-9fd97ff1-3ca8-47e2-b092-0c2fa188096b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226549971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2226549971
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3278979153
Short name T953
Test name
Test status
Simulation time 2410768241 ps
CPU time 15.35 seconds
Started Jun 24 05:11:22 PM PDT 24
Finished Jun 24 05:11:38 PM PDT 24
Peak memory 239768 kb
Host smart-16c8472f-7dc9-4b43-8c1d-1c83c0df12f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278979153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3278979153
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.73195236
Short name T735
Test name
Test status
Simulation time 1292242013 ps
CPU time 8.14 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:34 PM PDT 24
Peak memory 233752 kb
Host smart-b867ff88-4e78-46cf-9039-316b80396921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73195236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.73195236
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1879157478
Short name T607
Test name
Test status
Simulation time 6174758251 ps
CPU time 5.58 seconds
Started Jun 24 05:11:17 PM PDT 24
Finished Jun 24 05:11:25 PM PDT 24
Peak memory 225600 kb
Host smart-b69167e9-6302-4cb6-844f-4a4f7c12988b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879157478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1879157478
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2522129894
Short name T421
Test name
Test status
Simulation time 15166679 ps
CPU time 0.98 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:11:18 PM PDT 24
Peak memory 218836 kb
Host smart-0282a083-1ebd-429a-aafe-edf36ad87014
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522129894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2522129894
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.10653533
Short name T814
Test name
Test status
Simulation time 311420419 ps
CPU time 3.97 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:11:21 PM PDT 24
Peak memory 225540 kb
Host smart-58d164cb-261a-4091-adde-45e84a1d67b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10653533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.10653533
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1828537283
Short name T127
Test name
Test status
Simulation time 1556805020 ps
CPU time 4.27 seconds
Started Jun 24 05:11:17 PM PDT 24
Finished Jun 24 05:11:23 PM PDT 24
Peak memory 225548 kb
Host smart-1cda41c8-0dcb-45e0-9d12-d394c6dd4edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828537283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1828537283
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2367599024
Short name T962
Test name
Test status
Simulation time 641425592 ps
CPU time 3.45 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:30 PM PDT 24
Peak memory 219788 kb
Host smart-6bd8ca5a-e522-4d6e-a823-cbe99f50e2c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2367599024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2367599024
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2513044888
Short name T303
Test name
Test status
Simulation time 726462839 ps
CPU time 3.04 seconds
Started Jun 24 05:11:18 PM PDT 24
Finished Jun 24 05:11:22 PM PDT 24
Peak memory 217300 kb
Host smart-afa65d7e-9f16-4be9-a59d-326d587e4798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513044888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2513044888
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3521588806
Short name T341
Test name
Test status
Simulation time 10967629 ps
CPU time 0.7 seconds
Started Jun 24 05:11:16 PM PDT 24
Finished Jun 24 05:11:18 PM PDT 24
Peak memory 206592 kb
Host smart-9354e0bf-c5b7-4304-b9d7-3644609f9c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521588806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3521588806
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3823194676
Short name T68
Test name
Test status
Simulation time 200227898 ps
CPU time 2.65 seconds
Started Jun 24 05:11:17 PM PDT 24
Finished Jun 24 05:11:21 PM PDT 24
Peak memory 217288 kb
Host smart-1be530bc-f2e8-48bd-9f1f-67cc7488b0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823194676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3823194676
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3401597550
Short name T427
Test name
Test status
Simulation time 400814492 ps
CPU time 0.91 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:26 PM PDT 24
Peak memory 206864 kb
Host smart-8b7b74ef-4d77-4f06-90e1-79069bc3ce9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401597550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3401597550
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1817185555
Short name T601
Test name
Test status
Simulation time 5526792394 ps
CPU time 6.72 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:33 PM PDT 24
Peak memory 233796 kb
Host smart-1e93f5b9-b0b2-43e5-8587-1b702c4fdea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817185555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1817185555
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2519374478
Short name T306
Test name
Test status
Simulation time 22004749 ps
CPU time 0.74 seconds
Started Jun 24 05:11:34 PM PDT 24
Finished Jun 24 05:11:36 PM PDT 24
Peak memory 206256 kb
Host smart-ea16d9a2-fe3b-498d-9233-0026528e1305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519374478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2519374478
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.697461328
Short name T589
Test name
Test status
Simulation time 2307451105 ps
CPU time 11.94 seconds
Started Jun 24 05:11:23 PM PDT 24
Finished Jun 24 05:11:37 PM PDT 24
Peak memory 233732 kb
Host smart-8200aafc-9ec1-446d-a177-47d7690d99eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697461328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.697461328
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1919062629
Short name T301
Test name
Test status
Simulation time 13673786 ps
CPU time 0.77 seconds
Started Jun 24 05:11:23 PM PDT 24
Finished Jun 24 05:11:25 PM PDT 24
Peak memory 207360 kb
Host smart-400be63b-7583-44a3-86aa-a773cf1eb48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919062629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1919062629
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2410502638
Short name T685
Test name
Test status
Simulation time 38392243 ps
CPU time 0.79 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:36 PM PDT 24
Peak memory 216720 kb
Host smart-741e9ee0-3d10-4a78-a527-232b14fc2386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410502638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2410502638
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2725599654
Short name T888
Test name
Test status
Simulation time 5976565583 ps
CPU time 49.18 seconds
Started Jun 24 05:11:30 PM PDT 24
Finished Jun 24 05:12:21 PM PDT 24
Peak memory 225656 kb
Host smart-bae2095e-5da9-4130-bb97-e8d87b60913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725599654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2725599654
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.999619581
Short name T652
Test name
Test status
Simulation time 2164061637 ps
CPU time 33.94 seconds
Started Jun 24 05:11:32 PM PDT 24
Finished Jun 24 05:12:08 PM PDT 24
Peak memory 225640 kb
Host smart-4cf96a1b-fea1-4959-870b-7bab798f0ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999619581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.999619581
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1329380097
Short name T86
Test name
Test status
Simulation time 20646285103 ps
CPU time 23.12 seconds
Started Jun 24 05:11:23 PM PDT 24
Finished Jun 24 05:11:48 PM PDT 24
Peak memory 233800 kb
Host smart-39320142-0770-42fc-9d41-97611c2c4881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329380097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1329380097
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.335720766
Short name T791
Test name
Test status
Simulation time 82319901 ps
CPU time 2.36 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:28 PM PDT 24
Peak memory 233484 kb
Host smart-5fe4cd34-59fb-4410-95b4-25f1febd1a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335720766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.335720766
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3301226660
Short name T739
Test name
Test status
Simulation time 17899288 ps
CPU time 1.06 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:27 PM PDT 24
Peak memory 217628 kb
Host smart-ce2fb2f5-3c8c-4db3-921d-4ff78aadc878
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301226660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3301226660
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3088773920
Short name T271
Test name
Test status
Simulation time 2879490721 ps
CPU time 6.55 seconds
Started Jun 24 05:11:23 PM PDT 24
Finished Jun 24 05:11:32 PM PDT 24
Peak memory 233840 kb
Host smart-c51352f0-7fd7-46bd-a362-d6e45d21a90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088773920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3088773920
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3326668043
Short name T751
Test name
Test status
Simulation time 1847596129 ps
CPU time 7.64 seconds
Started Jun 24 05:11:25 PM PDT 24
Finished Jun 24 05:11:35 PM PDT 24
Peak memory 243692 kb
Host smart-923470b4-f8c9-42a0-b4cd-07492f9a3a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326668043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3326668043
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1006385735
Short name T680
Test name
Test status
Simulation time 343706036 ps
CPU time 4 seconds
Started Jun 24 05:11:36 PM PDT 24
Finished Jun 24 05:11:41 PM PDT 24
Peak memory 223436 kb
Host smart-36cc2db1-1c13-478a-9cb0-cad18a417652
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1006385735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1006385735
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3499114001
Short name T148
Test name
Test status
Simulation time 18651345979 ps
CPU time 74.52 seconds
Started Jun 24 05:11:31 PM PDT 24
Finished Jun 24 05:12:48 PM PDT 24
Peak memory 251156 kb
Host smart-316b1b65-3c7c-4003-b7ea-7949f548dc54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499114001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3499114001
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2697301502
Short name T854
Test name
Test status
Simulation time 1494348976 ps
CPU time 23.07 seconds
Started Jun 24 05:11:23 PM PDT 24
Finished Jun 24 05:11:48 PM PDT 24
Peak memory 217472 kb
Host smart-db1bdc55-0565-46ff-a112-b466d82c4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697301502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2697301502
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1045933920
Short name T880
Test name
Test status
Simulation time 13043180 ps
CPU time 0.74 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:27 PM PDT 24
Peak memory 206592 kb
Host smart-919cfea0-380e-44e2-8ab7-f89c63554e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045933920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1045933920
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.722627412
Short name T451
Test name
Test status
Simulation time 14974543 ps
CPU time 0.69 seconds
Started Jun 24 05:11:24 PM PDT 24
Finished Jun 24 05:11:27 PM PDT 24
Peak memory 206524 kb
Host smart-8076fc44-000b-4e7f-8235-9602ec9ab119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722627412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.722627412
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2015681119
Short name T12
Test name
Test status
Simulation time 211054932 ps
CPU time 0.88 seconds
Started Jun 24 05:11:22 PM PDT 24
Finished Jun 24 05:11:23 PM PDT 24
Peak memory 207320 kb
Host smart-6c8bbffc-994b-4b90-83d6-04f955dec365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015681119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2015681119
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2128795727
Short name T849
Test name
Test status
Simulation time 106410735 ps
CPU time 3.14 seconds
Started Jun 24 05:11:22 PM PDT 24
Finished Jun 24 05:11:26 PM PDT 24
Peak memory 233768 kb
Host smart-bc40df03-ee2b-401a-9c00-a63d63522f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128795727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2128795727
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2365466721
Short name T887
Test name
Test status
Simulation time 13898962 ps
CPU time 0.72 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:36 PM PDT 24
Peak memory 206284 kb
Host smart-a87e25c1-8f6d-4319-a662-23d7cc8aadaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365466721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2365466721
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.885282360
Short name T225
Test name
Test status
Simulation time 96474086 ps
CPU time 2.81 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:38 PM PDT 24
Peak memory 233668 kb
Host smart-8670bbe7-ace8-4e86-a2a0-90a10f3e98f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885282360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.885282360
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.773375742
Short name T764
Test name
Test status
Simulation time 60672970 ps
CPU time 0.75 seconds
Started Jun 24 05:11:30 PM PDT 24
Finished Jun 24 05:11:32 PM PDT 24
Peak memory 207488 kb
Host smart-81b75960-b1ae-4c0a-a7ec-9536393b7fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773375742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.773375742
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1174789517
Short name T473
Test name
Test status
Simulation time 54220027766 ps
CPU time 96.03 seconds
Started Jun 24 05:11:31 PM PDT 24
Finished Jun 24 05:13:09 PM PDT 24
Peak memory 250248 kb
Host smart-146db260-166d-4f62-a8af-95d8a1ed4405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174789517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1174789517
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1493909276
Short name T811
Test name
Test status
Simulation time 5550484234 ps
CPU time 81.94 seconds
Started Jun 24 05:11:31 PM PDT 24
Finished Jun 24 05:12:54 PM PDT 24
Peak memory 256772 kb
Host smart-0649aa35-73ff-4471-a819-dbaf50da7d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493909276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1493909276
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1233467683
Short name T241
Test name
Test status
Simulation time 17921470197 ps
CPU time 63.98 seconds
Started Jun 24 05:11:32 PM PDT 24
Finished Jun 24 05:12:38 PM PDT 24
Peak memory 250732 kb
Host smart-73d30718-80e2-4c5f-815b-fb1510bb3043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233467683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1233467683
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1993074635
Short name T562
Test name
Test status
Simulation time 1238373810 ps
CPU time 10.64 seconds
Started Jun 24 05:11:34 PM PDT 24
Finished Jun 24 05:11:46 PM PDT 24
Peak memory 241960 kb
Host smart-3de65e1b-9b8c-4816-beb1-03a39b4b82c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993074635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1993074635
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.666258341
Short name T618
Test name
Test status
Simulation time 29358262 ps
CPU time 2.24 seconds
Started Jun 24 05:11:32 PM PDT 24
Finished Jun 24 05:11:36 PM PDT 24
Peak memory 225356 kb
Host smart-22fbea47-f0d2-4ae6-a3b6-e8e76c5c09be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666258341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.666258341
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3556181920
Short name T819
Test name
Test status
Simulation time 9456291632 ps
CPU time 45.21 seconds
Started Jun 24 05:11:31 PM PDT 24
Finished Jun 24 05:12:18 PM PDT 24
Peak memory 250172 kb
Host smart-5f73c07c-27fb-4cd9-b502-9b22e0422b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556181920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3556181920
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.331786235
Short name T336
Test name
Test status
Simulation time 26162448 ps
CPU time 1 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:36 PM PDT 24
Peak memory 218788 kb
Host smart-5387785e-4968-4af1-ae25-927c0a4a53c2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331786235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.331786235
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1276783896
Short name T621
Test name
Test status
Simulation time 90061370 ps
CPU time 2.35 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:37 PM PDT 24
Peak memory 225260 kb
Host smart-e067a019-f9db-4ece-9c3e-91a5adb01c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276783896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1276783896
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.984791684
Short name T493
Test name
Test status
Simulation time 96877202 ps
CPU time 2.12 seconds
Started Jun 24 05:11:30 PM PDT 24
Finished Jun 24 05:11:33 PM PDT 24
Peak memory 224176 kb
Host smart-3bfec848-d025-44ae-8a07-287816c2b7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984791684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.984791684
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1405981101
Short name T951
Test name
Test status
Simulation time 4858822593 ps
CPU time 14.85 seconds
Started Jun 24 05:11:31 PM PDT 24
Finished Jun 24 05:11:47 PM PDT 24
Peak memory 221804 kb
Host smart-da72eafa-55be-40ba-a3b0-0e8723767c00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1405981101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1405981101
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2766086932
Short name T939
Test name
Test status
Simulation time 15644413990 ps
CPU time 291.4 seconds
Started Jun 24 05:11:35 PM PDT 24
Finished Jun 24 05:16:28 PM PDT 24
Peak memory 282964 kb
Host smart-17161021-264a-4d5b-b763-7768bd9db913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766086932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2766086932
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2263103276
Short name T902
Test name
Test status
Simulation time 935076847 ps
CPU time 16.58 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:52 PM PDT 24
Peak memory 217580 kb
Host smart-b42be0a8-7301-4cdf-aa16-5cc479ffe590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263103276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2263103276
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2875522530
Short name T6
Test name
Test status
Simulation time 7820464199 ps
CPU time 8.55 seconds
Started Jun 24 05:11:33 PM PDT 24
Finished Jun 24 05:11:43 PM PDT 24
Peak memory 217480 kb
Host smart-684960e8-d8d4-4f0b-a664-56bc1fd86841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875522530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2875522530
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1171862435
Short name T570
Test name
Test status
Simulation time 154718989 ps
CPU time 1.26 seconds
Started Jun 24 05:11:30 PM PDT 24
Finished Jun 24 05:11:33 PM PDT 24
Peak memory 217036 kb
Host smart-ee017783-8832-481c-8c58-84257ac5c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171862435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1171862435
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3303582142
Short name T385
Test name
Test status
Simulation time 20271233 ps
CPU time 0.73 seconds
Started Jun 24 05:11:31 PM PDT 24
Finished Jun 24 05:11:33 PM PDT 24
Peak memory 206792 kb
Host smart-9a343316-4688-4c89-927c-b2f4b2d8a71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303582142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3303582142
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4087443883
Short name T633
Test name
Test status
Simulation time 7644477889 ps
CPU time 11.61 seconds
Started Jun 24 05:11:34 PM PDT 24
Finished Jun 24 05:11:47 PM PDT 24
Peak memory 225580 kb
Host smart-d89734fa-e0d0-4d82-a774-a49446911bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087443883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4087443883
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.120325784
Short name T494
Test name
Test status
Simulation time 18422171 ps
CPU time 0.7 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:42 PM PDT 24
Peak memory 206248 kb
Host smart-8f384837-99fa-4676-9458-cdad42402309
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120325784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.120325784
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2604122154
Short name T877
Test name
Test status
Simulation time 635860851 ps
CPU time 3.25 seconds
Started Jun 24 05:11:41 PM PDT 24
Finished Jun 24 05:11:46 PM PDT 24
Peak memory 233724 kb
Host smart-c16c761a-c4ae-44d4-91a8-153b998bd242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604122154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2604122154
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2527774621
Short name T873
Test name
Test status
Simulation time 18029949 ps
CPU time 0.77 seconds
Started Jun 24 05:11:31 PM PDT 24
Finished Jun 24 05:11:34 PM PDT 24
Peak memory 206628 kb
Host smart-59a9ee5b-f186-4cc9-9a00-05f5a266ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527774621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2527774621
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.623663590
Short name T955
Test name
Test status
Simulation time 79415009592 ps
CPU time 177.17 seconds
Started Jun 24 05:11:44 PM PDT 24
Finished Jun 24 05:14:42 PM PDT 24
Peak memory 266412 kb
Host smart-d4f1217d-96d8-47ad-828e-60591cca99c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623663590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.623663590
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2783760702
Short name T952
Test name
Test status
Simulation time 5538397438 ps
CPU time 28.77 seconds
Started Jun 24 05:11:41 PM PDT 24
Finished Jun 24 05:12:11 PM PDT 24
Peak memory 239616 kb
Host smart-a7e9714b-dafe-4ba8-8f78-efd2f4f51bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783760702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2783760702
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2122484183
Short name T342
Test name
Test status
Simulation time 346566396 ps
CPU time 5.56 seconds
Started Jun 24 05:11:41 PM PDT 24
Finished Jun 24 05:11:48 PM PDT 24
Peak memory 225568 kb
Host smart-bf6d4cd0-cd38-4bd9-9184-b36816b50621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122484183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2122484183
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3656230587
Short name T192
Test name
Test status
Simulation time 7024964329 ps
CPU time 42.57 seconds
Started Jun 24 05:11:45 PM PDT 24
Finished Jun 24 05:12:29 PM PDT 24
Peak memory 241772 kb
Host smart-dc21f169-f5f4-414c-937a-04eac98e4f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656230587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3656230587
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1944526600
Short name T299
Test name
Test status
Simulation time 15806324 ps
CPU time 1.03 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:42 PM PDT 24
Peak memory 217524 kb
Host smart-839b2ba0-eaa8-4154-ad8e-2bff61ac452b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944526600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1944526600
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3406764887
Short name T253
Test name
Test status
Simulation time 191257718 ps
CPU time 3.7 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:44 PM PDT 24
Peak memory 225552 kb
Host smart-1ef50b08-0098-44f4-8c7d-0b8ee775f277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406764887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3406764887
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2760595393
Short name T386
Test name
Test status
Simulation time 105484291 ps
CPU time 2.52 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:45 PM PDT 24
Peak memory 233464 kb
Host smart-d0b735c0-e7c8-488f-a409-c7a6f0a02462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760595393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2760595393
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.645707481
Short name T364
Test name
Test status
Simulation time 1171597745 ps
CPU time 4.67 seconds
Started Jun 24 05:11:36 PM PDT 24
Finished Jun 24 05:11:42 PM PDT 24
Peak memory 219912 kb
Host smart-79fc5e6d-624b-4671-b2c7-0f71dae89168
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=645707481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.645707481
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3523552088
Short name T538
Test name
Test status
Simulation time 49965533402 ps
CPU time 218.82 seconds
Started Jun 24 05:11:43 PM PDT 24
Finished Jun 24 05:15:23 PM PDT 24
Peak memory 251356 kb
Host smart-85739690-0b8f-4b1d-ba00-1c27bd3c3bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523552088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3523552088
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1027860190
Short name T331
Test name
Test status
Simulation time 3249095314 ps
CPU time 15.36 seconds
Started Jun 24 05:11:42 PM PDT 24
Finished Jun 24 05:11:59 PM PDT 24
Peak memory 217480 kb
Host smart-0798d89f-cfda-4028-8b0c-3600644b1c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027860190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1027860190
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.532703960
Short name T514
Test name
Test status
Simulation time 9247688730 ps
CPU time 24.62 seconds
Started Jun 24 05:11:43 PM PDT 24
Finished Jun 24 05:12:09 PM PDT 24
Peak memory 217440 kb
Host smart-85f4f314-234a-4a27-8f90-878d7989c909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532703960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.532703960
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.208541167
Short name T809
Test name
Test status
Simulation time 114159065 ps
CPU time 4.17 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:46 PM PDT 24
Peak memory 217348 kb
Host smart-b981eda2-3385-4c62-af29-26038426a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208541167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.208541167
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1442709410
Short name T591
Test name
Test status
Simulation time 21855603 ps
CPU time 0.79 seconds
Started Jun 24 05:11:43 PM PDT 24
Finished Jun 24 05:11:45 PM PDT 24
Peak memory 206876 kb
Host smart-da4e0d1e-8e98-4b5b-a55e-d759759d5789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442709410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1442709410
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1342007198
Short name T47
Test name
Test status
Simulation time 2496499854 ps
CPU time 14.28 seconds
Started Jun 24 05:11:41 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 241664 kb
Host smart-a176e8d9-50f5-4257-9bfb-63b520749666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342007198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1342007198
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3131735857
Short name T348
Test name
Test status
Simulation time 58081053 ps
CPU time 0.69 seconds
Started Jun 24 05:11:49 PM PDT 24
Finished Jun 24 05:11:52 PM PDT 24
Peak memory 205652 kb
Host smart-41279daa-a533-4481-94ac-980bd3d02e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131735857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3131735857
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2013117229
Short name T399
Test name
Test status
Simulation time 36287179 ps
CPU time 0.77 seconds
Started Jun 24 05:11:45 PM PDT 24
Finished Jun 24 05:11:47 PM PDT 24
Peak memory 207732 kb
Host smart-87690600-618d-43ee-a654-98bcef73051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013117229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2013117229
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1692745832
Short name T155
Test name
Test status
Simulation time 111921395629 ps
CPU time 73.34 seconds
Started Jun 24 05:11:50 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 250520 kb
Host smart-6b4a064e-df8b-454d-98ef-bf1219675a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692745832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1692745832
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1496464780
Short name T727
Test name
Test status
Simulation time 6889133652 ps
CPU time 23.82 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:12:14 PM PDT 24
Peak memory 218684 kb
Host smart-045d394e-590d-434e-b4a3-5b4f6bb7fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496464780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1496464780
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1451095912
Short name T211
Test name
Test status
Simulation time 110215922651 ps
CPU time 520.97 seconds
Started Jun 24 05:11:50 PM PDT 24
Finished Jun 24 05:20:33 PM PDT 24
Peak memory 254604 kb
Host smart-23b01122-c2b5-4276-a33e-67fa2218f2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451095912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1451095912
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.255599576
Short name T794
Test name
Test status
Simulation time 711999168 ps
CPU time 6.45 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:48 PM PDT 24
Peak memory 225496 kb
Host smart-ba758113-3170-4f6d-8189-850b5ca3dd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255599576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.255599576
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1692315601
Short name T221
Test name
Test status
Simulation time 235828270 ps
CPU time 2.82 seconds
Started Jun 24 05:11:43 PM PDT 24
Finished Jun 24 05:11:48 PM PDT 24
Peak memory 233684 kb
Host smart-d3c86e5e-0665-4ae2-aaf3-3dfce6948b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692315601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1692315601
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2088467645
Short name T188
Test name
Test status
Simulation time 17544354437 ps
CPU time 22.64 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:12:03 PM PDT 24
Peak memory 224232 kb
Host smart-3488e127-154e-4549-9f75-a262bb372711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088467645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2088467645
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3379855638
Short name T906
Test name
Test status
Simulation time 174436726 ps
CPU time 0.99 seconds
Started Jun 24 05:11:44 PM PDT 24
Finished Jun 24 05:11:47 PM PDT 24
Peak memory 218768 kb
Host smart-cc2cbd48-05d7-4148-829d-9b97a304b24c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379855638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3379855638
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.612994059
Short name T904
Test name
Test status
Simulation time 1149104929 ps
CPU time 2.85 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:45 PM PDT 24
Peak memory 233756 kb
Host smart-b4fb58cf-69b3-43df-9d71-16fe1f86dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612994059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.612994059
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2444811901
Short name T227
Test name
Test status
Simulation time 2243632962 ps
CPU time 3.53 seconds
Started Jun 24 05:11:39 PM PDT 24
Finished Jun 24 05:11:44 PM PDT 24
Peak memory 233844 kb
Host smart-03036b62-9f7b-4f28-acb4-86810841fa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444811901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2444811901
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2454809592
Short name T653
Test name
Test status
Simulation time 92217772 ps
CPU time 3.8 seconds
Started Jun 24 05:11:45 PM PDT 24
Finished Jun 24 05:11:50 PM PDT 24
Peak memory 223556 kb
Host smart-22253eb5-e8b5-4801-9b8d-a5c756011392
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2454809592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2454809592
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4214236074
Short name T153
Test name
Test status
Simulation time 138982305675 ps
CPU time 256.55 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:16:07 PM PDT 24
Peak memory 254692 kb
Host smart-2cdecf64-890b-44f1-b396-ead85f3a284e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214236074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4214236074
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3872327600
Short name T966
Test name
Test status
Simulation time 1623977007 ps
CPU time 15.74 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 217644 kb
Host smart-8be1afa5-8673-402d-a747-a43f9517b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872327600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3872327600
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3032935735
Short name T843
Test name
Test status
Simulation time 9019937856 ps
CPU time 8.55 seconds
Started Jun 24 05:11:45 PM PDT 24
Finished Jun 24 05:11:55 PM PDT 24
Peak memory 217300 kb
Host smart-48f88094-0406-4cba-a372-11e1db4903c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032935735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3032935735
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1532359366
Short name T415
Test name
Test status
Simulation time 1086592603 ps
CPU time 2.65 seconds
Started Jun 24 05:11:41 PM PDT 24
Finished Jun 24 05:11:46 PM PDT 24
Peak memory 217368 kb
Host smart-06b9029f-c91f-4b7e-9f38-4bdacfff8fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532359366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1532359366
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3947346243
Short name T28
Test name
Test status
Simulation time 159186321 ps
CPU time 0.83 seconds
Started Jun 24 05:11:40 PM PDT 24
Finished Jun 24 05:11:43 PM PDT 24
Peak memory 206888 kb
Host smart-a9a83002-7d0c-479c-b6ef-cbbda6eb4028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947346243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3947346243
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2001658558
Short name T865
Test name
Test status
Simulation time 849328572 ps
CPU time 6.58 seconds
Started Jun 24 05:11:41 PM PDT 24
Finished Jun 24 05:11:50 PM PDT 24
Peak memory 225488 kb
Host smart-73944c33-2a41-44ea-a975-05e7abe38850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001658558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2001658558
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2139345318
Short name T414
Test name
Test status
Simulation time 12100605 ps
CPU time 0.75 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:11:50 PM PDT 24
Peak memory 206156 kb
Host smart-ccd8b58e-2bbc-4759-9d6b-4dc02f71a1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139345318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2139345318
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3368301695
Short name T490
Test name
Test status
Simulation time 93523581 ps
CPU time 2.18 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 225116 kb
Host smart-c1c98845-f80a-49ae-a4fe-2e9654fbe1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368301695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3368301695
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.980305348
Short name T449
Test name
Test status
Simulation time 22868381 ps
CPU time 0.72 seconds
Started Jun 24 05:11:46 PM PDT 24
Finished Jun 24 05:11:49 PM PDT 24
Peak memory 206380 kb
Host smart-da8675f8-9f4c-4311-a100-d636931852c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980305348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.980305348
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1296026003
Short name T859
Test name
Test status
Simulation time 36107666276 ps
CPU time 112.11 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:13:42 PM PDT 24
Peak memory 252124 kb
Host smart-0b3ffb1c-95f8-4a00-93ae-3e7f0c75010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296026003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1296026003
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2532871567
Short name T197
Test name
Test status
Simulation time 5020473076 ps
CPU time 26.74 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:12:16 PM PDT 24
Peak memory 241792 kb
Host smart-f5edd509-817c-4fc8-994e-2b97fd6114f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532871567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2532871567
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.760771537
Short name T412
Test name
Test status
Simulation time 67984272111 ps
CPU time 191.36 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:15:02 PM PDT 24
Peak memory 256400 kb
Host smart-2786961b-a75b-4829-97a9-04e6cf5ddcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760771537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.760771537
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1573702918
Short name T625
Test name
Test status
Simulation time 1509791297 ps
CPU time 13.03 seconds
Started Jun 24 05:11:50 PM PDT 24
Finished Jun 24 05:12:05 PM PDT 24
Peak memory 233648 kb
Host smart-6aec50be-c175-4e3e-952c-d782fb31bf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573702918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1573702918
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1598049160
Short name T497
Test name
Test status
Simulation time 31939767 ps
CPU time 2.29 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 233512 kb
Host smart-9d9388e0-bac9-486a-947f-eae49de4fcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598049160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1598049160
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3813392354
Short name T722
Test name
Test status
Simulation time 2876910557 ps
CPU time 17.89 seconds
Started Jun 24 05:11:45 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 233808 kb
Host smart-60620250-d91c-4d92-bb3a-a8eca5f24cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813392354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3813392354
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3101064404
Short name T358
Test name
Test status
Simulation time 33372836 ps
CPU time 1.04 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:11:51 PM PDT 24
Peak memory 217588 kb
Host smart-b572cd4a-77d6-4715-a4e0-4eada335b066
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101064404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3101064404
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.381514402
Short name T683
Test name
Test status
Simulation time 6401334556 ps
CPU time 11.86 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:12:03 PM PDT 24
Peak memory 233860 kb
Host smart-79c4c0fe-e4b7-44a0-96e6-9f500269f832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381514402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.381514402
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3567270230
Short name T588
Test name
Test status
Simulation time 943739279 ps
CPU time 4.95 seconds
Started Jun 24 05:11:49 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 233724 kb
Host smart-4c4d6e50-6bfa-48aa-9553-8c1be5f97956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567270230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3567270230
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3078400556
Short name T11
Test name
Test status
Simulation time 2222357680 ps
CPU time 10.21 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:12:06 PM PDT 24
Peak memory 220452 kb
Host smart-af7017b5-ecc6-4af2-861e-ffeef08f8d39
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3078400556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3078400556
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3212007220
Short name T775
Test name
Test status
Simulation time 31014564882 ps
CPU time 327.73 seconds
Started Jun 24 05:11:50 PM PDT 24
Finished Jun 24 05:17:20 PM PDT 24
Peak memory 282224 kb
Host smart-dec5b551-8ec8-4c7b-bdd0-a408cab877dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212007220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3212007220
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.675788220
Short name T381
Test name
Test status
Simulation time 6573170742 ps
CPU time 33.37 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:12:29 PM PDT 24
Peak memory 217488 kb
Host smart-6d0e99fb-ffc0-48c7-b321-13ae02c80751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675788220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.675788220
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.898349995
Short name T772
Test name
Test status
Simulation time 22317047061 ps
CPU time 8.13 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 217504 kb
Host smart-ef480b64-2685-4475-ad07-a55921342ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898349995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.898349995
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2295914388
Short name T730
Test name
Test status
Simulation time 63600549 ps
CPU time 1.88 seconds
Started Jun 24 05:11:50 PM PDT 24
Finished Jun 24 05:11:54 PM PDT 24
Peak memory 217560 kb
Host smart-2adbdb24-70b8-422f-8ebd-61ac44da692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295914388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2295914388
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1288854734
Short name T710
Test name
Test status
Simulation time 48049410 ps
CPU time 0.83 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:11:50 PM PDT 24
Peak memory 206864 kb
Host smart-e3d638cf-c0c9-4340-9ee4-c60f4987c3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288854734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1288854734
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2941360043
Short name T787
Test name
Test status
Simulation time 36329939 ps
CPU time 2.5 seconds
Started Jun 24 05:11:49 PM PDT 24
Finished Jun 24 05:11:54 PM PDT 24
Peak memory 233416 kb
Host smart-46d98b07-1186-4885-ba3a-68b586a6124c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941360043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2941360043
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3993456216
Short name T506
Test name
Test status
Simulation time 18991841 ps
CPU time 0.73 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:10:18 PM PDT 24
Peak memory 206220 kb
Host smart-bde55530-ad44-480b-946a-f9638a3ab29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993456216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
993456216
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.345769128
Short name T87
Test name
Test status
Simulation time 2417342915 ps
CPU time 25.83 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 225692 kb
Host smart-a119902d-b001-4d14-bb6f-ef9d4d3dd3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345769128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.345769128
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.898192833
Short name T347
Test name
Test status
Simulation time 176711939 ps
CPU time 0.75 seconds
Started Jun 24 05:10:15 PM PDT 24
Finished Jun 24 05:10:17 PM PDT 24
Peak memory 206720 kb
Host smart-9af1683a-5f0f-4cfa-ac9f-48f280a40f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898192833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.898192833
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3122161277
Short name T460
Test name
Test status
Simulation time 1922788850 ps
CPU time 47.34 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:11:05 PM PDT 24
Peak memory 257148 kb
Host smart-be7fc942-b510-41fe-be6c-e5e48327bd7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122161277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3122161277
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2620003769
Short name T808
Test name
Test status
Simulation time 55335635331 ps
CPU time 448 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:17:45 PM PDT 24
Peak memory 257560 kb
Host smart-e1445031-336a-4205-a40e-28979fc395e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620003769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2620003769
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.518131817
Short name T946
Test name
Test status
Simulation time 1332324895 ps
CPU time 5.84 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:10:24 PM PDT 24
Peak memory 234332 kb
Host smart-764a7d5b-7638-4c84-8358-e126f331f276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518131817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
518131817
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1632121634
Short name T141
Test name
Test status
Simulation time 2357582818 ps
CPU time 37.17 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:10:54 PM PDT 24
Peak memory 239468 kb
Host smart-17ed8fe2-71e3-4d7e-bd01-7e8a3caf2d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632121634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1632121634
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1656791968
Short name T176
Test name
Test status
Simulation time 3112939380 ps
CPU time 17.87 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:10:36 PM PDT 24
Peak memory 233884 kb
Host smart-78c8243d-1f62-4ce0-a747-c198a07678c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656791968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1656791968
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3923270662
Short name T914
Test name
Test status
Simulation time 185795269 ps
CPU time 2.66 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:10:21 PM PDT 24
Peak memory 233744 kb
Host smart-aa7012c7-0a61-4f26-a016-3f8febacf773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923270662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3923270662
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1376899263
Short name T937
Test name
Test status
Simulation time 28671344 ps
CPU time 1.1 seconds
Started Jun 24 05:10:19 PM PDT 24
Finished Jun 24 05:10:21 PM PDT 24
Peak memory 218480 kb
Host smart-dd930082-d47b-4814-8e38-6a1f09b43f69
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376899263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1376899263
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2772575445
Short name T619
Test name
Test status
Simulation time 3888545820 ps
CPU time 11.54 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:10:30 PM PDT 24
Peak memory 225680 kb
Host smart-a5a48d12-5b54-4dd4-bda1-6f647ac415e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772575445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2772575445
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4217808256
Short name T8
Test name
Test status
Simulation time 31910348 ps
CPU time 2.49 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:10:21 PM PDT 24
Peak memory 233456 kb
Host smart-9c570666-6a80-4579-9c04-0efc2e25c5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217808256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4217808256
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3425471783
Short name T703
Test name
Test status
Simulation time 486335751 ps
CPU time 6.81 seconds
Started Jun 24 05:10:17 PM PDT 24
Finished Jun 24 05:10:25 PM PDT 24
Peak memory 221608 kb
Host smart-82d458f7-64ca-4191-8aa6-81507d6e2d94
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3425471783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3425471783
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2011507266
Short name T74
Test name
Test status
Simulation time 177570242 ps
CPU time 1.01 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:10:18 PM PDT 24
Peak memory 236376 kb
Host smart-62be7a5d-2e2d-41dd-a77b-a761e174cf17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011507266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2011507266
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3105991161
Short name T774
Test name
Test status
Simulation time 15415986315 ps
CPU time 41.04 seconds
Started Jun 24 05:10:16 PM PDT 24
Finished Jun 24 05:10:58 PM PDT 24
Peak memory 217484 kb
Host smart-89138291-e161-4b60-8341-7504ac220b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105991161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3105991161
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2840308562
Short name T820
Test name
Test status
Simulation time 189239026 ps
CPU time 1.92 seconds
Started Jun 24 05:10:19 PM PDT 24
Finished Jun 24 05:10:22 PM PDT 24
Peak memory 216760 kb
Host smart-7de63b05-6f4c-4b33-956f-55982e390302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840308562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2840308562
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1083701382
Short name T765
Test name
Test status
Simulation time 415689722 ps
CPU time 1.82 seconds
Started Jun 24 05:10:18 PM PDT 24
Finished Jun 24 05:10:21 PM PDT 24
Peak memory 209112 kb
Host smart-f226f34d-d6ee-460f-8009-349ee4df5941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083701382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1083701382
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.164798400
Short name T708
Test name
Test status
Simulation time 150666495 ps
CPU time 0.89 seconds
Started Jun 24 05:10:20 PM PDT 24
Finished Jun 24 05:10:22 PM PDT 24
Peak memory 206864 kb
Host smart-15d76eb6-fa22-4bda-ad81-9b7dae17623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164798400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.164798400
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.984697435
Short name T657
Test name
Test status
Simulation time 8652444856 ps
CPU time 8.68 seconds
Started Jun 24 05:10:14 PM PDT 24
Finished Jun 24 05:10:24 PM PDT 24
Peak memory 233832 kb
Host smart-2def80c9-d748-44ee-8a4b-5262cfe16807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984697435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.984697435
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1866798091
Short name T715
Test name
Test status
Simulation time 17164895 ps
CPU time 0.76 seconds
Started Jun 24 05:11:55 PM PDT 24
Finished Jun 24 05:11:58 PM PDT 24
Peak memory 206240 kb
Host smart-91b31d34-4741-42b4-b91c-a78704ee5d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866798091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1866798091
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3141307923
Short name T852
Test name
Test status
Simulation time 1068378710 ps
CPU time 5.96 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 233644 kb
Host smart-253cfb91-f5fe-4c89-8908-87035b63e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141307923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3141307923
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3316137202
Short name T365
Test name
Test status
Simulation time 125685139 ps
CPU time 0.79 seconds
Started Jun 24 05:11:50 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 208052 kb
Host smart-b2fcc449-6fc3-4fe9-8a40-912d38b748d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316137202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3316137202
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1591920980
Short name T851
Test name
Test status
Simulation time 97397789143 ps
CPU time 190.47 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:15:13 PM PDT 24
Peak memory 250440 kb
Host smart-ab613b49-6ee4-4705-97a5-2909f6aec9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591920980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1591920980
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3698804050
Short name T526
Test name
Test status
Simulation time 77798762 ps
CPU time 2.6 seconds
Started Jun 24 05:11:53 PM PDT 24
Finished Jun 24 05:11:56 PM PDT 24
Peak memory 233696 kb
Host smart-92f711ae-9ee0-4d97-b1f2-c206a52050fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698804050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3698804050
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3365528731
Short name T634
Test name
Test status
Simulation time 32535761 ps
CPU time 2.43 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 233772 kb
Host smart-0ac443f3-730f-4307-8b17-57b5245526a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365528731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3365528731
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3038448096
Short name T836
Test name
Test status
Simulation time 23138736361 ps
CPU time 82.77 seconds
Started Jun 24 05:11:52 PM PDT 24
Finished Jun 24 05:13:16 PM PDT 24
Peak memory 233812 kb
Host smart-0707f8a1-e946-4069-b30f-a06e9efdf7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038448096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3038448096
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.373166485
Short name T207
Test name
Test status
Simulation time 5832074746 ps
CPU time 16.67 seconds
Started Jun 24 05:11:46 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 225632 kb
Host smart-de07985c-7529-40aa-beff-370d5d118adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373166485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.373166485
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1623596156
Short name T214
Test name
Test status
Simulation time 752030606 ps
CPU time 4.4 seconds
Started Jun 24 05:11:47 PM PDT 24
Finished Jun 24 05:11:53 PM PDT 24
Peak memory 225444 kb
Host smart-0f7dbe0c-0d67-48a6-8bc1-824746891372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623596156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1623596156
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.905560062
Short name T354
Test name
Test status
Simulation time 843000103 ps
CPU time 5.02 seconds
Started Jun 24 05:11:52 PM PDT 24
Finished Jun 24 05:11:59 PM PDT 24
Peak memory 222728 kb
Host smart-6013d5ed-b95d-44b4-9b0a-514eabee4f20
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=905560062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.905560062
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1034153140
Short name T24
Test name
Test status
Simulation time 58683058 ps
CPU time 1.02 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:03 PM PDT 24
Peak memory 207908 kb
Host smart-74feefad-9893-4592-b0e8-42d520d87089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034153140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1034153140
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3076757039
Short name T833
Test name
Test status
Simulation time 4229739571 ps
CPU time 15.92 seconds
Started Jun 24 05:11:49 PM PDT 24
Finished Jun 24 05:12:08 PM PDT 24
Peak memory 217560 kb
Host smart-d30f461a-a4c3-4bf4-b937-babcece501ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076757039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3076757039
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.683900497
Short name T912
Test name
Test status
Simulation time 4259482097 ps
CPU time 11.64 seconds
Started Jun 24 05:11:51 PM PDT 24
Finished Jun 24 05:12:05 PM PDT 24
Peak memory 217680 kb
Host smart-192033fd-8c5f-44cf-be7a-1bbd0731406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683900497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.683900497
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1012129465
Short name T931
Test name
Test status
Simulation time 52663477 ps
CPU time 1.2 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:11:52 PM PDT 24
Peak memory 217204 kb
Host smart-39736aa3-dc3c-4408-b5b1-033fc61d2390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012129465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1012129465
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.820771204
Short name T943
Test name
Test status
Simulation time 112545085 ps
CPU time 1 seconds
Started Jun 24 05:11:46 PM PDT 24
Finished Jun 24 05:11:49 PM PDT 24
Peak memory 206784 kb
Host smart-04ca3bb9-3ff5-4426-b55b-68438fb23498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820771204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.820771204
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.918186519
Short name T256
Test name
Test status
Simulation time 10701759088 ps
CPU time 30.69 seconds
Started Jun 24 05:11:48 PM PDT 24
Finished Jun 24 05:12:21 PM PDT 24
Peak memory 233832 kb
Host smart-509daf8f-459b-4de3-bbed-67d08ee64795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918186519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.918186519
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3761082627
Short name T821
Test name
Test status
Simulation time 45051706 ps
CPU time 0.72 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 205644 kb
Host smart-3e2d9b27-36c4-4e9b-ad3b-e15dc3058acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761082627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3761082627
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4086637587
Short name T313
Test name
Test status
Simulation time 190845941 ps
CPU time 2.35 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:11:58 PM PDT 24
Peak memory 225448 kb
Host smart-110b52ce-97ff-46b0-8130-d74e10a26bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086637587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4086637587
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2066990226
Short name T159
Test name
Test status
Simulation time 13021932 ps
CPU time 0.79 seconds
Started Jun 24 05:11:56 PM PDT 24
Finished Jun 24 05:11:59 PM PDT 24
Peak memory 207480 kb
Host smart-5afcae98-e684-4262-b84b-88abd2af9b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066990226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2066990226
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.818296372
Short name T777
Test name
Test status
Simulation time 4130029765 ps
CPU time 28.17 seconds
Started Jun 24 05:11:55 PM PDT 24
Finished Jun 24 05:12:25 PM PDT 24
Peak memory 242060 kb
Host smart-3f6ad2a1-d5ca-4ad0-96eb-990b20461c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818296372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.818296372
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1567851649
Short name T641
Test name
Test status
Simulation time 48141034758 ps
CPU time 111.22 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:13:54 PM PDT 24
Peak memory 250564 kb
Host smart-0a216228-c33b-4970-8010-1fdeff06bb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567851649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1567851649
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4069157485
Short name T184
Test name
Test status
Simulation time 16412168690 ps
CPU time 74.4 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:13:10 PM PDT 24
Peak memory 257564 kb
Host smart-e61ae8f3-2cf1-473a-ab59-ab301176da94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069157485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4069157485
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3611970698
Short name T284
Test name
Test status
Simulation time 320965921 ps
CPU time 4.88 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:12:00 PM PDT 24
Peak memory 233780 kb
Host smart-27e8ed68-5736-44e1-9a42-b919ed3230c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611970698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3611970698
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2876072399
Short name T187
Test name
Test status
Simulation time 148716600 ps
CPU time 4.21 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:12:00 PM PDT 24
Peak memory 233744 kb
Host smart-b6ee2d70-18f9-4793-98ce-1ae4d95a1039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876072399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2876072399
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2813691618
Short name T50
Test name
Test status
Simulation time 6036523181 ps
CPU time 45.72 seconds
Started Jun 24 05:11:57 PM PDT 24
Finished Jun 24 05:12:44 PM PDT 24
Peak memory 241876 kb
Host smart-95d17d25-09e3-4483-8448-e7a423f0510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813691618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2813691618
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2350505308
Short name T244
Test name
Test status
Simulation time 231370831 ps
CPU time 2.81 seconds
Started Jun 24 05:11:53 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 225508 kb
Host smart-984ce55d-04ce-4014-919d-3564f570ad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350505308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2350505308
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1057312090
Short name T437
Test name
Test status
Simulation time 155080064 ps
CPU time 3.13 seconds
Started Jun 24 05:11:54 PM PDT 24
Finished Jun 24 05:11:58 PM PDT 24
Peak memory 225484 kb
Host smart-6675f35a-26b2-4005-9ebc-47106f42e921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057312090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1057312090
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3827489706
Short name T539
Test name
Test status
Simulation time 2861860761 ps
CPU time 7.51 seconds
Started Jun 24 05:11:56 PM PDT 24
Finished Jun 24 05:12:05 PM PDT 24
Peak memory 220284 kb
Host smart-9337d503-301d-4b31-8acd-25f901c32e82
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3827489706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3827489706
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.130198980
Short name T781
Test name
Test status
Simulation time 1868688375 ps
CPU time 17.29 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:20 PM PDT 24
Peak memory 217356 kb
Host smart-f9db92da-06f0-429e-9bc4-bb144e23acc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130198980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.130198980
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.957592075
Short name T416
Test name
Test status
Simulation time 14267938860 ps
CPU time 4.84 seconds
Started Jun 24 05:11:51 PM PDT 24
Finished Jun 24 05:11:58 PM PDT 24
Peak memory 217452 kb
Host smart-30022b18-b0fe-4032-ad59-6bd9252d617b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957592075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.957592075
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3581697690
Short name T872
Test name
Test status
Simulation time 169735677 ps
CPU time 1.14 seconds
Started Jun 24 05:11:51 PM PDT 24
Finished Jun 24 05:11:54 PM PDT 24
Peak memory 209152 kb
Host smart-8fadea17-3c8b-4a73-8c35-902af185d9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581697690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3581697690
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.159553134
Short name T913
Test name
Test status
Simulation time 55811773 ps
CPU time 0.79 seconds
Started Jun 24 05:11:55 PM PDT 24
Finished Jun 24 05:11:57 PM PDT 24
Peak memory 206824 kb
Host smart-d5f3a41b-f59e-4ad5-a222-713f44046643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159553134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.159553134
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2791055708
Short name T945
Test name
Test status
Simulation time 6467718546 ps
CPU time 10.51 seconds
Started Jun 24 05:11:56 PM PDT 24
Finished Jun 24 05:12:08 PM PDT 24
Peak memory 225672 kb
Host smart-76135d13-1f02-4d32-ac02-cfdc57fa48a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791055708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2791055708
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.834209047
Short name T392
Test name
Test status
Simulation time 20486866 ps
CPU time 0.74 seconds
Started Jun 24 05:12:00 PM PDT 24
Finished Jun 24 05:12:02 PM PDT 24
Peak memory 205744 kb
Host smart-1073ef06-f016-4ffa-84a7-9a87965f1d27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834209047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.834209047
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3888023816
Short name T52
Test name
Test status
Simulation time 1034756120 ps
CPU time 8.91 seconds
Started Jun 24 05:12:00 PM PDT 24
Finished Jun 24 05:12:11 PM PDT 24
Peak memory 225472 kb
Host smart-06933e89-c2cf-4011-b122-1901943ea763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888023816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3888023816
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3086947713
Short name T561
Test name
Test status
Simulation time 15407220 ps
CPU time 0.77 seconds
Started Jun 24 05:11:53 PM PDT 24
Finished Jun 24 05:11:55 PM PDT 24
Peak memory 207476 kb
Host smart-9be71ce4-932b-4a85-9c46-8f68f097ed63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086947713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3086947713
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3322553386
Short name T932
Test name
Test status
Simulation time 22609596 ps
CPU time 0.77 seconds
Started Jun 24 05:12:02 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 217056 kb
Host smart-981c2732-d0f3-4556-9ec1-e51d3b4acdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322553386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3322553386
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1447648063
Short name T759
Test name
Test status
Simulation time 41740258436 ps
CPU time 375.63 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:18:17 PM PDT 24
Peak memory 267420 kb
Host smart-df21f402-9912-4571-9cfc-95d07400afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447648063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1447648063
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2911282512
Short name T508
Test name
Test status
Simulation time 17679083937 ps
CPU time 163.68 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:14:47 PM PDT 24
Peak memory 242028 kb
Host smart-dc6c31e4-59ae-48ae-b8b1-0131de630769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911282512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2911282512
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1534594434
Short name T780
Test name
Test status
Simulation time 3578838415 ps
CPU time 15.39 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:18 PM PDT 24
Peak memory 239100 kb
Host smart-455f8bf3-8611-42b5-bb8e-8dbbdba26208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534594434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1534594434
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2809547382
Short name T222
Test name
Test status
Simulation time 1798580881 ps
CPU time 9.39 seconds
Started Jun 24 05:12:00 PM PDT 24
Finished Jun 24 05:12:10 PM PDT 24
Peak memory 233752 kb
Host smart-ebafb8ec-859d-46dc-89de-dc670ac0775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809547382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2809547382
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3854584772
Short name T786
Test name
Test status
Simulation time 369475400 ps
CPU time 12.14 seconds
Started Jun 24 05:12:02 PM PDT 24
Finished Jun 24 05:12:16 PM PDT 24
Peak memory 241760 kb
Host smart-ebb8fe22-ea9d-4ed8-bad8-a23a556fb475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854584772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3854584772
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3173335583
Short name T242
Test name
Test status
Simulation time 14702458949 ps
CPU time 12.97 seconds
Started Jun 24 05:12:02 PM PDT 24
Finished Jun 24 05:12:16 PM PDT 24
Peak memory 225668 kb
Host smart-1cebf8cc-06c9-4338-ac93-1c124ed19171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173335583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3173335583
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4076750829
Short name T391
Test name
Test status
Simulation time 2217354461 ps
CPU time 6.4 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:09 PM PDT 24
Peak memory 225524 kb
Host smart-35d1fcde-fa86-4c76-9327-147aa6ed9472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076750829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4076750829
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.315947883
Short name T462
Test name
Test status
Simulation time 1449545751 ps
CPU time 11.66 seconds
Started Jun 24 05:12:00 PM PDT 24
Finished Jun 24 05:12:13 PM PDT 24
Peak memory 224056 kb
Host smart-bd627761-944f-4abe-97e3-0271e324b0b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315947883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.315947883
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3561700054
Short name T150
Test name
Test status
Simulation time 432459027 ps
CPU time 1.25 seconds
Started Jun 24 05:12:00 PM PDT 24
Finished Jun 24 05:12:03 PM PDT 24
Peak memory 208080 kb
Host smart-ae1393b8-6265-4d82-97c5-ed0a310bbbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561700054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3561700054
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1347007923
Short name T420
Test name
Test status
Simulation time 689791005 ps
CPU time 10.03 seconds
Started Jun 24 05:11:53 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 217408 kb
Host smart-4b4710db-f1d8-4a41-a0ec-23f3b61d476b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347007923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1347007923
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1538398714
Short name T890
Test name
Test status
Simulation time 2550150199 ps
CPU time 7.23 seconds
Started Jun 24 05:11:57 PM PDT 24
Finished Jun 24 05:12:05 PM PDT 24
Peak memory 217432 kb
Host smart-67baa02a-75ae-45ee-9f09-2e775b12c544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538398714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1538398714
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.441865245
Short name T567
Test name
Test status
Simulation time 57725505 ps
CPU time 1.82 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 217304 kb
Host smart-f64d2cf3-61d2-4b6a-a22c-47ab588c23ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441865245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.441865245
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2334743486
Short name T889
Test name
Test status
Simulation time 217613909 ps
CPU time 1.06 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:03 PM PDT 24
Peak memory 207404 kb
Host smart-cc5bfdef-1134-434d-83a9-69f66fdf5739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334743486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2334743486
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4097047339
Short name T713
Test name
Test status
Simulation time 1456790661 ps
CPU time 9.72 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:13 PM PDT 24
Peak memory 225488 kb
Host smart-fff2936a-51fb-48a7-8bed-7f6e2a73f98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097047339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4097047339
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2388814786
Short name T938
Test name
Test status
Simulation time 13927318 ps
CPU time 0.71 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:11 PM PDT 24
Peak memory 206280 kb
Host smart-25e8c53e-0d82-4c95-9633-1a21cb10b55e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388814786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2388814786
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.129624195
Short name T732
Test name
Test status
Simulation time 1353827356 ps
CPU time 3.25 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:13 PM PDT 24
Peak memory 225532 kb
Host smart-459105f8-429b-4c4d-83d1-2acf8b4ad27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129624195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.129624195
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.46119260
Short name T714
Test name
Test status
Simulation time 96402182 ps
CPU time 0.8 seconds
Started Jun 24 05:12:01 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 207452 kb
Host smart-655aa494-7966-45c3-8275-ebafd66e7375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46119260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.46119260
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1790775194
Short name T78
Test name
Test status
Simulation time 11992197880 ps
CPU time 79.07 seconds
Started Jun 24 05:12:08 PM PDT 24
Finished Jun 24 05:13:27 PM PDT 24
Peak memory 250204 kb
Host smart-ac7428e1-1d67-4be2-835a-f39894f77e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790775194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1790775194
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.821763790
Short name T832
Test name
Test status
Simulation time 571196723 ps
CPU time 9.65 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:20 PM PDT 24
Peak memory 232564 kb
Host smart-a2edc713-cad0-4b06-be9d-2dbda0ac027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821763790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.821763790
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4294965501
Short name T600
Test name
Test status
Simulation time 482180754 ps
CPU time 6.22 seconds
Started Jun 24 05:12:12 PM PDT 24
Finished Jun 24 05:12:18 PM PDT 24
Peak memory 225500 kb
Host smart-ff9183c9-5fe5-41e7-85eb-62a75e6db347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294965501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4294965501
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4044347617
Short name T863
Test name
Test status
Simulation time 476108972 ps
CPU time 8.69 seconds
Started Jun 24 05:12:10 PM PDT 24
Finished Jun 24 05:12:19 PM PDT 24
Peak memory 238868 kb
Host smart-8206c338-5611-449e-9a88-b6ce86134500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044347617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4044347617
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.92113097
Short name T479
Test name
Test status
Simulation time 110081580 ps
CPU time 2.09 seconds
Started Jun 24 05:12:10 PM PDT 24
Finished Jun 24 05:12:13 PM PDT 24
Peak memory 223892 kb
Host smart-bf877180-e3e0-48e9-a787-c50a92d4593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92113097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.92113097
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3500873134
Short name T684
Test name
Test status
Simulation time 1264934195 ps
CPU time 4 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:14 PM PDT 24
Peak memory 233720 kb
Host smart-599b8eb8-1db5-4b12-b890-ad260b7a1a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500873134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3500873134
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4153234228
Short name T553
Test name
Test status
Simulation time 730386952 ps
CPU time 5.58 seconds
Started Jun 24 05:12:10 PM PDT 24
Finished Jun 24 05:12:17 PM PDT 24
Peak memory 220284 kb
Host smart-2b030ddd-6669-45af-89ff-bbc5d3ad7da4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4153234228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4153234228
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3123245214
Short name T974
Test name
Test status
Simulation time 12979616871 ps
CPU time 123.46 seconds
Started Jun 24 05:12:08 PM PDT 24
Finished Jun 24 05:14:13 PM PDT 24
Peak memory 250372 kb
Host smart-e376bd34-dbad-4eae-9a4f-18f2031ab742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123245214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3123245214
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.186827869
Short name T750
Test name
Test status
Simulation time 10273193562 ps
CPU time 28.44 seconds
Started Jun 24 05:12:08 PM PDT 24
Finished Jun 24 05:12:37 PM PDT 24
Peak memory 217780 kb
Host smart-9c1650e2-2dfd-4771-a172-63772782555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186827869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.186827869
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3286861233
Short name T361
Test name
Test status
Simulation time 15161806756 ps
CPU time 11.13 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:21 PM PDT 24
Peak memory 217500 kb
Host smart-e67f0d7a-8844-4b04-bece-4cbdddfd3feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286861233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3286861233
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1816220137
Short name T338
Test name
Test status
Simulation time 288427652 ps
CPU time 3.54 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:13 PM PDT 24
Peak memory 217304 kb
Host smart-351044e6-da74-4f31-9306-aba42b3bf074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816220137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1816220137
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3525161640
Short name T475
Test name
Test status
Simulation time 106902333 ps
CPU time 0.78 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:11 PM PDT 24
Peak memory 206844 kb
Host smart-1bdd1446-c964-4942-9af2-31b42c735dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525161640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3525161640
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1630726927
Short name T891
Test name
Test status
Simulation time 1012210480 ps
CPU time 6.47 seconds
Started Jun 24 05:12:12 PM PDT 24
Finished Jun 24 05:12:19 PM PDT 24
Peak memory 225464 kb
Host smart-b5f3e5b1-bf29-42e5-ab17-529331abe53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630726927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1630726927
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3630031022
Short name T776
Test name
Test status
Simulation time 40993050 ps
CPU time 0.73 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:12:21 PM PDT 24
Peak memory 206492 kb
Host smart-14abd6e7-0e54-4b8f-95c6-6e31014f8b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630031022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3630031022
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2417295874
Short name T862
Test name
Test status
Simulation time 291508582 ps
CPU time 3.14 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:12:23 PM PDT 24
Peak memory 233752 kb
Host smart-783c1ce4-305f-40cc-a51f-45cd591ddfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417295874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2417295874
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.145313670
Short name T484
Test name
Test status
Simulation time 20162919 ps
CPU time 0.77 seconds
Started Jun 24 05:12:15 PM PDT 24
Finished Jun 24 05:12:17 PM PDT 24
Peak memory 207804 kb
Host smart-19cafe85-cb5d-4470-81ba-0bc9ea4c7fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145313670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.145313670
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3586313797
Short name T258
Test name
Test status
Simulation time 94207452752 ps
CPU time 169.14 seconds
Started Jun 24 05:12:19 PM PDT 24
Finished Jun 24 05:15:10 PM PDT 24
Peak memory 250276 kb
Host smart-90b58ca6-e4f4-46d4-add8-f6a6ae4f1b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586313797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3586313797
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3652073678
Short name T822
Test name
Test status
Simulation time 173760354597 ps
CPU time 147.64 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:14:47 PM PDT 24
Peak memory 250140 kb
Host smart-128d8a83-81e8-4647-915d-b8202a10198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652073678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3652073678
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.372934036
Short name T281
Test name
Test status
Simulation time 150300305 ps
CPU time 6.29 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:12:26 PM PDT 24
Peak memory 241920 kb
Host smart-0197d10f-2d07-4391-b03e-13d7fc9c348e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372934036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.372934036
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2343945841
Short name T158
Test name
Test status
Simulation time 180335801 ps
CPU time 2.23 seconds
Started Jun 24 05:12:20 PM PDT 24
Finished Jun 24 05:12:24 PM PDT 24
Peak memory 224188 kb
Host smart-3188c033-809d-44a8-aff3-42fcc7d68226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343945841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2343945841
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2820782432
Short name T670
Test name
Test status
Simulation time 2515187553 ps
CPU time 7.8 seconds
Started Jun 24 05:12:19 PM PDT 24
Finished Jun 24 05:12:29 PM PDT 24
Peak memory 225588 kb
Host smart-f362fdc2-7621-42e5-a523-20a0f94b0cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820782432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2820782432
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.539620035
Short name T465
Test name
Test status
Simulation time 2707691485 ps
CPU time 9.12 seconds
Started Jun 24 05:12:08 PM PDT 24
Finished Jun 24 05:12:18 PM PDT 24
Peak memory 225524 kb
Host smart-1c370c71-6c84-4da7-af6a-ea8cd2e97283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539620035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.539620035
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.350762500
Short name T864
Test name
Test status
Simulation time 2237031666 ps
CPU time 3.86 seconds
Started Jun 24 05:12:08 PM PDT 24
Finished Jun 24 05:12:13 PM PDT 24
Peak memory 225668 kb
Host smart-6a4772ea-0802-4472-af14-3230c348149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350762500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.350762500
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.871108895
Short name T584
Test name
Test status
Simulation time 1558258899 ps
CPU time 3.87 seconds
Started Jun 24 05:12:22 PM PDT 24
Finished Jun 24 05:12:26 PM PDT 24
Peak memory 220548 kb
Host smart-e6b3a7d3-d57b-440c-9576-a0e4e207d285
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=871108895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.871108895
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1658361214
Short name T917
Test name
Test status
Simulation time 60239046723 ps
CPU time 451.24 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:19:51 PM PDT 24
Peak memory 255004 kb
Host smart-4662e0ea-cf24-44df-9a7d-e4ddca6330de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658361214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1658361214
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3596275376
Short name T771
Test name
Test status
Simulation time 4039683903 ps
CPU time 18.53 seconds
Started Jun 24 05:12:10 PM PDT 24
Finished Jun 24 05:12:30 PM PDT 24
Peak memory 217420 kb
Host smart-47b60aac-e41d-487e-9117-dc94c5249763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596275376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3596275376
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4063463289
Short name T343
Test name
Test status
Simulation time 1133073002 ps
CPU time 6.56 seconds
Started Jun 24 05:12:09 PM PDT 24
Finished Jun 24 05:12:16 PM PDT 24
Peak memory 217272 kb
Host smart-b3bab65c-3218-45e9-801b-c62217148313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063463289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4063463289
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2234251656
Short name T326
Test name
Test status
Simulation time 54394274 ps
CPU time 0.95 seconds
Started Jun 24 05:12:11 PM PDT 24
Finished Jun 24 05:12:12 PM PDT 24
Peak memory 207968 kb
Host smart-ae8585bb-62f6-4c80-9f10-715f1c2741dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234251656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2234251656
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4214377236
Short name T712
Test name
Test status
Simulation time 127186102 ps
CPU time 1.03 seconds
Started Jun 24 05:12:14 PM PDT 24
Finished Jun 24 05:12:16 PM PDT 24
Peak memory 206856 kb
Host smart-57e068c8-68ba-4b57-8640-cbc9e74b1bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214377236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4214377236
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.455011196
Short name T157
Test name
Test status
Simulation time 2500206814 ps
CPU time 5.42 seconds
Started Jun 24 05:12:22 PM PDT 24
Finished Jun 24 05:12:28 PM PDT 24
Peak memory 233868 kb
Host smart-608053d1-1020-4932-a8e9-5bc483a81dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455011196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.455011196
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.304435118
Short name T616
Test name
Test status
Simulation time 33116842 ps
CPU time 0.72 seconds
Started Jun 24 05:12:16 PM PDT 24
Finished Jun 24 05:12:17 PM PDT 24
Peak memory 205588 kb
Host smart-35bed502-2fec-44a3-8674-f0ff16b7ab51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304435118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.304435118
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1532551976
Short name T515
Test name
Test status
Simulation time 455252955 ps
CPU time 6.28 seconds
Started Jun 24 05:12:19 PM PDT 24
Finished Jun 24 05:12:27 PM PDT 24
Peak memory 225540 kb
Host smart-2b58ab4a-5856-4230-b168-9a4716be72e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532551976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1532551976
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4030936552
Short name T31
Test name
Test status
Simulation time 46872618 ps
CPU time 0.79 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:12:21 PM PDT 24
Peak memory 206448 kb
Host smart-75652623-d82f-48ac-bdf9-a6ba6b95d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030936552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4030936552
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3840693621
Short name T803
Test name
Test status
Simulation time 492896774 ps
CPU time 10.73 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:12:31 PM PDT 24
Peak memory 246376 kb
Host smart-4427f54e-5a57-4477-a651-09c569c11603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840693621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3840693621
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3787123806
Short name T574
Test name
Test status
Simulation time 9153808213 ps
CPU time 59.48 seconds
Started Jun 24 05:12:20 PM PDT 24
Finished Jun 24 05:13:21 PM PDT 24
Peak memory 265772 kb
Host smart-02cf430c-8504-4a3c-adf6-2b515d024c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787123806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3787123806
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3916521386
Short name T580
Test name
Test status
Simulation time 1596205667 ps
CPU time 4.44 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:12:24 PM PDT 24
Peak memory 225528 kb
Host smart-d0e3cc1b-b754-4281-9908-cf3d5b3e4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916521386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3916521386
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3652562862
Short name T664
Test name
Test status
Simulation time 5989626707 ps
CPU time 11.7 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:12:30 PM PDT 24
Peak memory 225612 kb
Host smart-f494a05f-368d-45c1-a8e5-491786781cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652562862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3652562862
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2507920597
Short name T793
Test name
Test status
Simulation time 60810487 ps
CPU time 2.25 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:12:22 PM PDT 24
Peak memory 225484 kb
Host smart-4066093b-9ae3-4c2f-b020-81ca61f4cafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507920597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2507920597
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1177987543
Short name T868
Test name
Test status
Simulation time 114974057 ps
CPU time 2.37 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:12:22 PM PDT 24
Peak memory 233472 kb
Host smart-13a0d6fc-9ff8-4734-bd1e-ae408550a179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177987543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1177987543
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3943852115
Short name T789
Test name
Test status
Simulation time 2806863738 ps
CPU time 12.3 seconds
Started Jun 24 05:12:21 PM PDT 24
Finished Jun 24 05:12:34 PM PDT 24
Peak memory 241884 kb
Host smart-6b6c9661-fbe6-40f6-9fe6-fd4b547c4efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943852115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3943852115
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2518273188
Short name T423
Test name
Test status
Simulation time 1602723754 ps
CPU time 5.75 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:12:25 PM PDT 24
Peak memory 224184 kb
Host smart-756497ff-601e-47cf-9111-1d7be00fec61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2518273188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2518273188
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2705038717
Short name T199
Test name
Test status
Simulation time 9118259083 ps
CPU time 135.14 seconds
Started Jun 24 05:12:18 PM PDT 24
Finished Jun 24 05:14:35 PM PDT 24
Peak memory 266704 kb
Host smart-c103979e-1e6f-493c-add2-921149f9cb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705038717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2705038717
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.387781006
Short name T831
Test name
Test status
Simulation time 1695125421 ps
CPU time 3.09 seconds
Started Jun 24 05:12:20 PM PDT 24
Finished Jun 24 05:12:24 PM PDT 24
Peak memory 217388 kb
Host smart-5cab3c06-7eb6-4b72-996f-99edd2cc9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387781006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.387781006
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1193386069
Short name T334
Test name
Test status
Simulation time 1631668562 ps
CPU time 6.76 seconds
Started Jun 24 05:12:16 PM PDT 24
Finished Jun 24 05:12:24 PM PDT 24
Peak memory 217292 kb
Host smart-78f20770-8e03-44e8-a4f8-975d8777f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193386069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1193386069
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4189919956
Short name T622
Test name
Test status
Simulation time 17020401 ps
CPU time 0.94 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:12:20 PM PDT 24
Peak memory 207900 kb
Host smart-50c941fc-facc-465a-ad03-2cee5e150a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189919956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4189919956
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2540611376
Short name T369
Test name
Test status
Simulation time 148148902 ps
CPU time 0.81 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:12:18 PM PDT 24
Peak memory 206868 kb
Host smart-98fd311e-3ab9-4f9b-94c6-dd4511eba9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540611376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2540611376
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1067195628
Short name T825
Test name
Test status
Simulation time 39665489502 ps
CPU time 30.82 seconds
Started Jun 24 05:12:17 PM PDT 24
Finished Jun 24 05:12:50 PM PDT 24
Peak memory 233772 kb
Host smart-f13b1722-f6e2-48d3-aa3e-7cd04809bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067195628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1067195628
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2301345934
Short name T489
Test name
Test status
Simulation time 15713387 ps
CPU time 0.73 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:28 PM PDT 24
Peak memory 205716 kb
Host smart-0b6b929f-d9ad-4464-92f4-0852ed7826c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301345934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2301345934
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3617983388
Short name T856
Test name
Test status
Simulation time 171624301 ps
CPU time 3.68 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:31 PM PDT 24
Peak memory 233644 kb
Host smart-6968ea83-ab2b-4bb1-b4c6-b74a3eb59beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617983388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3617983388
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.758699353
Short name T558
Test name
Test status
Simulation time 15407555 ps
CPU time 0.75 seconds
Started Jun 24 05:12:16 PM PDT 24
Finished Jun 24 05:12:18 PM PDT 24
Peak memory 206400 kb
Host smart-87378fc9-06c1-4a60-a871-3e47b3e02967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758699353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.758699353
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3585505486
Short name T371
Test name
Test status
Simulation time 227110399 ps
CPU time 5.55 seconds
Started Jun 24 05:12:23 PM PDT 24
Finished Jun 24 05:12:30 PM PDT 24
Peak memory 236612 kb
Host smart-e240f528-a1c5-4314-98ba-15dc5076ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585505486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3585505486
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.704551571
Short name T753
Test name
Test status
Simulation time 29543184844 ps
CPU time 95.94 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:14:03 PM PDT 24
Peak memory 250312 kb
Host smart-698f6b0b-27e9-4a2f-b727-36fc9bfd5a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704551571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.704551571
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3489987226
Short name T55
Test name
Test status
Simulation time 3827398542 ps
CPU time 22.83 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:50 PM PDT 24
Peak memory 220436 kb
Host smart-f403ad2e-edd7-44b4-9981-f12c8a3dee75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489987226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3489987226
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3509896498
Short name T636
Test name
Test status
Simulation time 272189696 ps
CPU time 3.39 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:29 PM PDT 24
Peak memory 233764 kb
Host smart-e89190eb-199b-4525-8b11-8d48decdddd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509896498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3509896498
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.442686706
Short name T469
Test name
Test status
Simulation time 25319967349 ps
CPU time 23.57 seconds
Started Jun 24 05:12:23 PM PDT 24
Finished Jun 24 05:12:47 PM PDT 24
Peak memory 225704 kb
Host smart-1969bfba-ba6e-434b-983c-11b3ed171b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442686706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.442686706
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3540597494
Short name T855
Test name
Test status
Simulation time 3647351476 ps
CPU time 9.05 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:36 PM PDT 24
Peak memory 233864 kb
Host smart-3a3989d9-bbac-4d71-88c1-7f20eaa974b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540597494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3540597494
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.13190375
Short name T268
Test name
Test status
Simulation time 3628071565 ps
CPU time 4.49 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:32 PM PDT 24
Peak memory 233764 kb
Host smart-ad3512a2-bcdb-4fd8-bd17-9d1196845b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13190375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.13190375
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4209728399
Short name T49
Test name
Test status
Simulation time 3417973484 ps
CPU time 14.08 seconds
Started Jun 24 05:12:27 PM PDT 24
Finished Jun 24 05:12:42 PM PDT 24
Peak memory 225552 kb
Host smart-7c111fe9-1815-44e0-ae18-737b48dab7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209728399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4209728399
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.773719014
Short name T758
Test name
Test status
Simulation time 113763604 ps
CPU time 4.01 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:31 PM PDT 24
Peak memory 223560 kb
Host smart-82df4cb0-73ce-429a-951d-af265a71c120
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=773719014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.773719014
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3547743822
Short name T629
Test name
Test status
Simulation time 17221354030 ps
CPU time 28.63 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:56 PM PDT 24
Peak memory 217432 kb
Host smart-6e414ac2-8044-4154-9c6c-a38f2fd8f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547743822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3547743822
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4181110201
Short name T376
Test name
Test status
Simulation time 1789930348 ps
CPU time 5.76 seconds
Started Jun 24 05:12:24 PM PDT 24
Finished Jun 24 05:12:31 PM PDT 24
Peak memory 217248 kb
Host smart-a9c2dc53-a821-447b-96c7-913973b39063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181110201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4181110201
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2204169400
Short name T768
Test name
Test status
Simulation time 466811688 ps
CPU time 1.85 seconds
Started Jun 24 05:12:23 PM PDT 24
Finished Jun 24 05:12:26 PM PDT 24
Peak memory 217368 kb
Host smart-a41edf57-be53-4160-8c6d-854c901c4ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204169400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2204169400
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1145697589
Short name T405
Test name
Test status
Simulation time 78252025 ps
CPU time 0.84 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:27 PM PDT 24
Peak memory 206876 kb
Host smart-8d90dbc5-ff75-4183-a302-32dda06f59a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145697589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1145697589
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4038590277
Short name T169
Test name
Test status
Simulation time 10789470040 ps
CPU time 29.56 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:57 PM PDT 24
Peak memory 241324 kb
Host smart-9f3ff18a-9f11-434d-a95c-24fbfc8f15f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038590277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4038590277
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2125796246
Short name T702
Test name
Test status
Simulation time 13799686 ps
CPU time 0.72 seconds
Started Jun 24 05:12:34 PM PDT 24
Finished Jun 24 05:12:36 PM PDT 24
Peak memory 205616 kb
Host smart-907a7633-5e63-44a8-b118-90f5c7d391dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125796246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2125796246
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3027855114
Short name T89
Test name
Test status
Simulation time 118812592 ps
CPU time 3.96 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:31 PM PDT 24
Peak memory 233724 kb
Host smart-1afd248d-9be2-4015-86d7-4d428b57a851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027855114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3027855114
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1122958644
Short name T627
Test name
Test status
Simulation time 16943955 ps
CPU time 0.75 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:28 PM PDT 24
Peak memory 206788 kb
Host smart-8c54fcf7-2b70-4b72-b5b3-09d020417ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122958644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1122958644
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3399507600
Short name T866
Test name
Test status
Simulation time 1241471833 ps
CPU time 31.27 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 255260 kb
Host smart-4f902e2c-11c6-4904-8a4a-28a047950692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399507600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3399507600
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4152973830
Short name T223
Test name
Test status
Simulation time 14378216638 ps
CPU time 137.16 seconds
Started Jun 24 05:12:30 PM PDT 24
Finished Jun 24 05:14:48 PM PDT 24
Peak memory 225948 kb
Host smart-768e8b2e-c9a6-40a5-b34e-4e5b33c62222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152973830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4152973830
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2121663568
Short name T382
Test name
Test status
Simulation time 2156987115 ps
CPU time 18.71 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:45 PM PDT 24
Peak memory 233764 kb
Host smart-a61a53fb-8aef-4e89-89b9-90a4e1b6beb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121663568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2121663568
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.173605988
Short name T62
Test name
Test status
Simulation time 7781406035 ps
CPU time 5.81 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:32 PM PDT 24
Peak memory 225612 kb
Host smart-68016b1d-4e51-4f1e-9368-df791faa7c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173605988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.173605988
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2061721420
Short name T799
Test name
Test status
Simulation time 113408091 ps
CPU time 2.1 seconds
Started Jun 24 05:12:28 PM PDT 24
Finished Jun 24 05:12:31 PM PDT 24
Peak memory 233444 kb
Host smart-345588b9-8c55-4606-983f-816241cc099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061721420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2061721420
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3453218343
Short name T755
Test name
Test status
Simulation time 92168237 ps
CPU time 2.15 seconds
Started Jun 24 05:12:28 PM PDT 24
Finished Jun 24 05:12:31 PM PDT 24
Peak memory 224788 kb
Host smart-19ed663f-fb5f-4eaf-8b28-7fb9bcbc5982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453218343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3453218343
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2353478282
Short name T238
Test name
Test status
Simulation time 440908163 ps
CPU time 6.54 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:33 PM PDT 24
Peak memory 233696 kb
Host smart-e4511695-df40-4f44-9d8b-05bb5a121822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353478282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2353478282
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1058877531
Short name T406
Test name
Test status
Simulation time 2079736634 ps
CPU time 8.9 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:42 PM PDT 24
Peak memory 220416 kb
Host smart-0909279a-8450-4484-b749-eb8d106cc949
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1058877531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1058877531
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3579459918
Short name T149
Test name
Test status
Simulation time 81255492 ps
CPU time 0.96 seconds
Started Jun 24 05:12:31 PM PDT 24
Finished Jun 24 05:12:33 PM PDT 24
Peak memory 207740 kb
Host smart-6a5376e4-4576-4f29-ab2f-a5bdf25fb7e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579459918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3579459918
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1000287924
Short name T292
Test name
Test status
Simulation time 583730250 ps
CPU time 6.45 seconds
Started Jun 24 05:12:24 PM PDT 24
Finished Jun 24 05:12:32 PM PDT 24
Peak memory 217360 kb
Host smart-67cdf83a-0b52-4ac6-84a5-89a8e27a2188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000287924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1000287924
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1299705914
Short name T671
Test name
Test status
Simulation time 1422711446 ps
CPU time 3.09 seconds
Started Jun 24 05:12:24 PM PDT 24
Finished Jun 24 05:12:28 PM PDT 24
Peak memory 217236 kb
Host smart-456f253f-8bb0-467d-a7d6-c11b928d3c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299705914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1299705914
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3738525215
Short name T499
Test name
Test status
Simulation time 73233127 ps
CPU time 0.95 seconds
Started Jun 24 05:12:23 PM PDT 24
Finished Jun 24 05:12:25 PM PDT 24
Peak memory 207584 kb
Host smart-d07bcf04-cbf1-4fb6-a119-080aed1da71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738525215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3738525215
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1828862046
Short name T706
Test name
Test status
Simulation time 59433361 ps
CPU time 0.82 seconds
Started Jun 24 05:12:26 PM PDT 24
Finished Jun 24 05:12:28 PM PDT 24
Peak memory 206876 kb
Host smart-03e6dfe6-c037-49e4-9af6-aaeb3d77aa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828862046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1828862046
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4294548486
Short name T564
Test name
Test status
Simulation time 5422855698 ps
CPU time 8.33 seconds
Started Jun 24 05:12:25 PM PDT 24
Finished Jun 24 05:12:34 PM PDT 24
Peak memory 235096 kb
Host smart-8f64243d-2a4c-41c0-82c3-62e9bf2bbb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294548486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4294548486
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2053309366
Short name T3
Test name
Test status
Simulation time 41670781 ps
CPU time 0.75 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:34 PM PDT 24
Peak memory 206292 kb
Host smart-ddd7433d-b104-4f04-be00-a3d3710a748b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053309366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2053309366
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3690961924
Short name T736
Test name
Test status
Simulation time 40554052 ps
CPU time 2.49 seconds
Started Jun 24 05:12:36 PM PDT 24
Finished Jun 24 05:12:39 PM PDT 24
Peak memory 233636 kb
Host smart-4aaab047-f27f-45b9-9062-7b36cc0656ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690961924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3690961924
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.240408429
Short name T944
Test name
Test status
Simulation time 53316096 ps
CPU time 0.78 seconds
Started Jun 24 05:12:31 PM PDT 24
Finished Jun 24 05:12:32 PM PDT 24
Peak memory 207476 kb
Host smart-4743df25-ed30-4059-81d0-b9d1b47b25e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240408429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.240408429
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2874459523
Short name T711
Test name
Test status
Simulation time 21697100191 ps
CPU time 67.81 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:13:41 PM PDT 24
Peak memory 254324 kb
Host smart-f3ebf906-fa4b-4747-b7c5-90a16973d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874459523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2874459523
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3358764432
Short name T867
Test name
Test status
Simulation time 36428845426 ps
CPU time 159.32 seconds
Started Jun 24 05:12:33 PM PDT 24
Finished Jun 24 05:15:14 PM PDT 24
Peak memory 255496 kb
Host smart-f2bb6401-e401-4b05-b253-9d1efef4ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358764432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3358764432
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1366097798
Short name T278
Test name
Test status
Simulation time 4386762897 ps
CPU time 29.21 seconds
Started Jun 24 05:12:34 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 233832 kb
Host smart-7c6354c8-a6a2-4b06-b399-524edc181146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366097798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1366097798
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2903880495
Short name T834
Test name
Test status
Simulation time 1032711602 ps
CPU time 7.23 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:41 PM PDT 24
Peak memory 233656 kb
Host smart-fa709122-620b-4dae-88c6-fb11153a7d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903880495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2903880495
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1941998191
Short name T218
Test name
Test status
Simulation time 28845351292 ps
CPU time 53.75 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:13:27 PM PDT 24
Peak memory 233876 kb
Host smart-c6f9663e-8a58-4937-b038-c6eb385cd786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941998191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1941998191
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3964086751
Short name T51
Test name
Test status
Simulation time 5600790281 ps
CPU time 5.47 seconds
Started Jun 24 05:12:34 PM PDT 24
Finished Jun 24 05:12:40 PM PDT 24
Peak memory 225476 kb
Host smart-44b8a1f8-e69e-42eb-ba11-b9a66bfdc0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964086751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3964086751
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.330923339
Short name T2
Test name
Test status
Simulation time 4706491218 ps
CPU time 6.41 seconds
Started Jun 24 05:12:34 PM PDT 24
Finished Jun 24 05:12:41 PM PDT 24
Peak memory 225848 kb
Host smart-3b6f2650-4112-4fcd-83d7-d53098cc835d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330923339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.330923339
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1028185736
Short name T897
Test name
Test status
Simulation time 1792945672 ps
CPU time 7.18 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:40 PM PDT 24
Peak memory 221124 kb
Host smart-d7476270-d97d-420c-8f21-b38eaee802c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1028185736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1028185736
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2469271298
Short name T551
Test name
Test status
Simulation time 22077892161 ps
CPU time 226.77 seconds
Started Jun 24 05:12:33 PM PDT 24
Finished Jun 24 05:16:21 PM PDT 24
Peak memory 256800 kb
Host smart-90b2f77d-df7d-4eb2-8281-c8e0b4d6fa51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469271298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2469271298
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3925453910
Short name T818
Test name
Test status
Simulation time 1909800733 ps
CPU time 12.4 seconds
Started Jun 24 05:12:31 PM PDT 24
Finished Jun 24 05:12:45 PM PDT 24
Peak memory 217384 kb
Host smart-d56fff01-418a-4004-b02f-538bd5cca4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925453910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3925453910
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2873623496
Short name T335
Test name
Test status
Simulation time 1775819104 ps
CPU time 3.05 seconds
Started Jun 24 05:12:34 PM PDT 24
Finished Jun 24 05:12:38 PM PDT 24
Peak memory 217260 kb
Host smart-d48941f7-6aec-4f81-97ce-61d91ab33a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873623496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2873623496
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2876848270
Short name T32
Test name
Test status
Simulation time 45515417 ps
CPU time 0.86 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:34 PM PDT 24
Peak memory 207972 kb
Host smart-d76a0a73-7759-427b-b03f-a0b482735bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876848270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2876848270
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1317344248
Short name T728
Test name
Test status
Simulation time 44254576 ps
CPU time 0.75 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:34 PM PDT 24
Peak memory 206752 kb
Host smart-00eb9c3c-f7fd-4555-b623-7704140eb2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317344248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1317344248
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1636473603
Short name T257
Test name
Test status
Simulation time 1062856213 ps
CPU time 6.14 seconds
Started Jun 24 05:12:35 PM PDT 24
Finished Jun 24 05:12:42 PM PDT 24
Peak memory 233684 kb
Host smart-7dacc7ed-4418-4842-9935-b00b37560406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636473603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1636473603
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.844584318
Short name T757
Test name
Test status
Simulation time 32705508 ps
CPU time 0.71 seconds
Started Jun 24 05:12:41 PM PDT 24
Finished Jun 24 05:12:42 PM PDT 24
Peak memory 205688 kb
Host smart-107d3a1f-794f-4b7d-b888-8567d215c399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844584318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.844584318
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1923812193
Short name T234
Test name
Test status
Simulation time 288495723 ps
CPU time 5.46 seconds
Started Jun 24 05:12:39 PM PDT 24
Finished Jun 24 05:12:46 PM PDT 24
Peak memory 225492 kb
Host smart-7b365340-ebe7-4a4a-982b-6c902725b978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923812193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1923812193
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3178867164
Short name T578
Test name
Test status
Simulation time 37608065 ps
CPU time 0.78 seconds
Started Jun 24 05:12:31 PM PDT 24
Finished Jun 24 05:12:32 PM PDT 24
Peak memory 206452 kb
Host smart-a520c0dd-5cc4-4a5a-89f1-d01d3697dd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178867164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3178867164
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.843947149
Short name T248
Test name
Test status
Simulation time 116887386247 ps
CPU time 254.24 seconds
Started Jun 24 05:12:39 PM PDT 24
Finished Jun 24 05:16:54 PM PDT 24
Peak memory 257788 kb
Host smart-97a24f4f-a795-4716-b2ed-f3a751d4e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843947149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.843947149
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1003607600
Short name T432
Test name
Test status
Simulation time 907913102 ps
CPU time 8.71 seconds
Started Jun 24 05:12:39 PM PDT 24
Finished Jun 24 05:12:49 PM PDT 24
Peak memory 220304 kb
Host smart-8fdf63fe-ce6c-47fe-ab1b-350f29aff061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003607600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1003607600
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3221077944
Short name T273
Test name
Test status
Simulation time 76058185690 ps
CPU time 154.29 seconds
Started Jun 24 05:12:39 PM PDT 24
Finished Jun 24 05:15:14 PM PDT 24
Peak memory 258256 kb
Host smart-87c4a497-ff79-430d-b4c7-faf0b68b1e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221077944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3221077944
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3791835507
Short name T9
Test name
Test status
Simulation time 4268283188 ps
CPU time 10.93 seconds
Started Jun 24 05:12:33 PM PDT 24
Finished Jun 24 05:12:45 PM PDT 24
Peak memory 234132 kb
Host smart-133c35f6-7edd-43a5-b69b-2a49dbed19d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791835507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3791835507
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2582384073
Short name T586
Test name
Test status
Simulation time 1664233348 ps
CPU time 8.52 seconds
Started Jun 24 05:12:31 PM PDT 24
Finished Jun 24 05:12:40 PM PDT 24
Peak memory 233688 kb
Host smart-b6bc49b1-9c74-4569-a085-f7b8d2ac1776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582384073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2582384073
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.523462433
Short name T536
Test name
Test status
Simulation time 779240340 ps
CPU time 6.24 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:39 PM PDT 24
Peak memory 225484 kb
Host smart-31eaebba-e7a5-495e-a67d-056f4a70ef1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523462433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.523462433
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4142898248
Short name T452
Test name
Test status
Simulation time 219392578 ps
CPU time 1.97 seconds
Started Jun 24 05:12:35 PM PDT 24
Finished Jun 24 05:12:38 PM PDT 24
Peak memory 224036 kb
Host smart-29077c3b-47fe-430e-bb9a-d0e47b58d395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142898248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4142898248
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.124296714
Short name T477
Test name
Test status
Simulation time 1771676825 ps
CPU time 4.71 seconds
Started Jun 24 05:12:40 PM PDT 24
Finished Jun 24 05:12:46 PM PDT 24
Peak memory 222868 kb
Host smart-bb617fe2-f7e1-4459-9113-7e2341b928ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=124296714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.124296714
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1640993544
Short name T151
Test name
Test status
Simulation time 61948893 ps
CPU time 1.17 seconds
Started Jun 24 05:12:40 PM PDT 24
Finished Jun 24 05:12:42 PM PDT 24
Peak memory 208856 kb
Host smart-4201a173-4459-4b33-8c0c-c403f5652db2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640993544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1640993544
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1723480635
Short name T289
Test name
Test status
Simulation time 2526788574 ps
CPU time 25.86 seconds
Started Jun 24 05:12:33 PM PDT 24
Finished Jun 24 05:13:00 PM PDT 24
Peak memory 217332 kb
Host smart-a9e62242-ef2e-4027-84fe-3d0e24eb7040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723480635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1723480635
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3451550070
Short name T673
Test name
Test status
Simulation time 5605308333 ps
CPU time 3.48 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:37 PM PDT 24
Peak memory 208672 kb
Host smart-18658a59-4a88-4bc8-9938-c4adf01640e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451550070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3451550070
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2622103322
Short name T651
Test name
Test status
Simulation time 44055447 ps
CPU time 1.08 seconds
Started Jun 24 05:12:32 PM PDT 24
Finished Jun 24 05:12:34 PM PDT 24
Peak memory 208892 kb
Host smart-9d409608-40fa-4ede-8d95-6ca4c1bd1193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622103322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2622103322
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2965191808
Short name T502
Test name
Test status
Simulation time 210099714 ps
CPU time 0.87 seconds
Started Jun 24 05:12:36 PM PDT 24
Finished Jun 24 05:12:37 PM PDT 24
Peak memory 206780 kb
Host smart-65a8ba67-49e3-4f9f-b9ef-f409e2a2fe84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965191808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2965191808
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1641971872
Short name T688
Test name
Test status
Simulation time 9769385301 ps
CPU time 21.35 seconds
Started Jun 24 05:12:38 PM PDT 24
Finished Jun 24 05:13:00 PM PDT 24
Peak memory 250252 kb
Host smart-705e5414-6025-41a8-bb1a-da6cfff8c4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641971872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1641971872
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.729548817
Short name T899
Test name
Test status
Simulation time 19834846 ps
CPU time 0.69 seconds
Started Jun 24 05:10:29 PM PDT 24
Finished Jun 24 05:10:31 PM PDT 24
Peak memory 206288 kb
Host smart-d935c53a-4c20-465e-ac25-5825ed967c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729548817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.729548817
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3213082949
Short name T647
Test name
Test status
Simulation time 1403856009 ps
CPU time 4.91 seconds
Started Jun 24 05:10:27 PM PDT 24
Finished Jun 24 05:10:33 PM PDT 24
Peak memory 225480 kb
Host smart-d5c36829-525e-45ae-b2d1-07d5ed33a148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213082949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3213082949
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.790290621
Short name T400
Test name
Test status
Simulation time 72773378 ps
CPU time 0.77 seconds
Started Jun 24 05:10:21 PM PDT 24
Finished Jun 24 05:10:23 PM PDT 24
Peak memory 206444 kb
Host smart-7581d6d2-9cec-4a6f-b3b8-4e3af3153c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790290621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.790290621
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2656602147
Short name T240
Test name
Test status
Simulation time 37415599690 ps
CPU time 273.76 seconds
Started Jun 24 05:10:29 PM PDT 24
Finished Jun 24 05:15:04 PM PDT 24
Peak memory 256440 kb
Host smart-fe92c84a-a400-472b-95ff-654c790a370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656602147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2656602147
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.600306060
Short name T60
Test name
Test status
Simulation time 25769438683 ps
CPU time 58.5 seconds
Started Jun 24 05:10:28 PM PDT 24
Finished Jun 24 05:11:28 PM PDT 24
Peak memory 250316 kb
Host smart-bf5ae0d0-5fdd-4fa5-8f8d-0fe82a5c602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600306060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.600306060
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.160621272
Short name T632
Test name
Test status
Simulation time 2560621550 ps
CPU time 36.87 seconds
Started Jun 24 05:10:29 PM PDT 24
Finished Jun 24 05:11:07 PM PDT 24
Peak memory 218328 kb
Host smart-77b5b097-4061-4338-930d-3d995da08175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160621272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
160621272
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3596021744
Short name T443
Test name
Test status
Simulation time 191913638 ps
CPU time 3.9 seconds
Started Jun 24 05:10:29 PM PDT 24
Finished Jun 24 05:10:34 PM PDT 24
Peak memory 234784 kb
Host smart-1f32fedc-8cd6-4c33-af65-5e6965cdd831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596021744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3596021744
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1963128397
Short name T893
Test name
Test status
Simulation time 240088238 ps
CPU time 5.4 seconds
Started Jun 24 05:10:21 PM PDT 24
Finished Jun 24 05:10:27 PM PDT 24
Peak memory 233768 kb
Host smart-2d298719-0cc9-420d-aebc-f06444a88a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963128397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1963128397
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3269972606
Short name T16
Test name
Test status
Simulation time 2149910407 ps
CPU time 5.88 seconds
Started Jun 24 05:10:21 PM PDT 24
Finished Jun 24 05:10:28 PM PDT 24
Peak memory 225520 kb
Host smart-3b688262-78cd-4a77-b4b8-205fcdce11f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269972606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3269972606
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.382457217
Short name T626
Test name
Test status
Simulation time 25758432 ps
CPU time 1.04 seconds
Started Jun 24 05:10:21 PM PDT 24
Finished Jun 24 05:10:23 PM PDT 24
Peak memory 217528 kb
Host smart-5668b344-f224-48e9-a8da-53adc300a2c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382457217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.382457217
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3193434915
Short name T918
Test name
Test status
Simulation time 6498957673 ps
CPU time 17.81 seconds
Started Jun 24 05:10:23 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 241464 kb
Host smart-cf40e23d-0ba4-47a6-a809-39a9955135a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193434915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3193434915
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1310616066
Short name T200
Test name
Test status
Simulation time 753636432 ps
CPU time 3.56 seconds
Started Jun 24 05:10:21 PM PDT 24
Finished Jun 24 05:10:25 PM PDT 24
Peak memory 225424 kb
Host smart-c42bc13b-431e-4933-9814-ed6e029ba3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310616066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1310616066
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1027848033
Short name T125
Test name
Test status
Simulation time 1003666509 ps
CPU time 9.16 seconds
Started Jun 24 05:10:26 PM PDT 24
Finished Jun 24 05:10:36 PM PDT 24
Peak memory 223500 kb
Host smart-7b390ec9-4a06-4acf-8ca0-ae15f9988e41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1027848033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1027848033
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3833191855
Short name T453
Test name
Test status
Simulation time 84379426 ps
CPU time 1.05 seconds
Started Jun 24 05:10:28 PM PDT 24
Finished Jun 24 05:10:30 PM PDT 24
Peak memory 207864 kb
Host smart-c8f59732-ca0a-4cf4-b890-da8cd27e7e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833191855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3833191855
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3716654962
Short name T628
Test name
Test status
Simulation time 5740335652 ps
CPU time 27.59 seconds
Started Jun 24 05:10:22 PM PDT 24
Finished Jun 24 05:10:50 PM PDT 24
Peak memory 217696 kb
Host smart-2493c944-f680-4619-be1a-bb00073e6dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716654962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3716654962
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1014610862
Short name T560
Test name
Test status
Simulation time 18278870568 ps
CPU time 11.72 seconds
Started Jun 24 05:10:19 PM PDT 24
Finished Jun 24 05:10:31 PM PDT 24
Peak memory 217424 kb
Host smart-a8dc0a9b-ff43-4e9f-8cfb-201cd2eb0b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014610862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1014610862
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3375460809
Short name T630
Test name
Test status
Simulation time 154668132 ps
CPU time 1.01 seconds
Started Jun 24 05:10:22 PM PDT 24
Finished Jun 24 05:10:24 PM PDT 24
Peak memory 208908 kb
Host smart-b2e1dada-b12a-4a74-960a-fe1b0facbbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375460809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3375460809
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3068516472
Short name T512
Test name
Test status
Simulation time 17566849 ps
CPU time 0.77 seconds
Started Jun 24 05:10:21 PM PDT 24
Finished Jun 24 05:10:23 PM PDT 24
Peak memory 206780 kb
Host smart-6d6d2217-b7d5-4fc2-b745-06369bc4a1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068516472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3068516472
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2931829309
Short name T500
Test name
Test status
Simulation time 2972348144 ps
CPU time 9.05 seconds
Started Jun 24 05:10:23 PM PDT 24
Finished Jun 24 05:10:32 PM PDT 24
Peak memory 233888 kb
Host smart-a81b49d3-d8bd-4f57-9c54-e551f70ac312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931829309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2931829309
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3568050478
Short name T861
Test name
Test status
Simulation time 45315496 ps
CPU time 0.78 seconds
Started Jun 24 05:12:51 PM PDT 24
Finished Jun 24 05:12:53 PM PDT 24
Peak memory 206240 kb
Host smart-1d85932e-7365-4130-b7fe-8e27162e2f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568050478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3568050478
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4099745797
Short name T485
Test name
Test status
Simulation time 733016889 ps
CPU time 3.7 seconds
Started Jun 24 05:12:39 PM PDT 24
Finished Jun 24 05:12:43 PM PDT 24
Peak memory 225436 kb
Host smart-a4590dbf-e171-4a11-b051-c71cf5cbce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099745797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4099745797
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.224815066
Short name T840
Test name
Test status
Simulation time 94597547 ps
CPU time 0.84 seconds
Started Jun 24 05:12:42 PM PDT 24
Finished Jun 24 05:12:43 PM PDT 24
Peak memory 207828 kb
Host smart-65cc0288-9b70-42ba-9382-83076a23a368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224815066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.224815066
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1170304975
Short name T54
Test name
Test status
Simulation time 9008850332 ps
CPU time 78.27 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:14:08 PM PDT 24
Peak memory 241980 kb
Host smart-2949b9c7-296d-43b0-b84c-2197330658bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170304975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1170304975
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1371672153
Short name T659
Test name
Test status
Simulation time 9015969068 ps
CPU time 67.46 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:13:58 PM PDT 24
Peak memory 256072 kb
Host smart-07f0dea5-9b15-4bcf-8d8b-1859c8a6b249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371672153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1371672153
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1342894362
Short name T521
Test name
Test status
Simulation time 215848200 ps
CPU time 3.79 seconds
Started Jun 24 05:12:37 PM PDT 24
Finished Jun 24 05:12:42 PM PDT 24
Peak memory 225420 kb
Host smart-3c5b07f3-faed-451c-95d2-d2044bcb6a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342894362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1342894362
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3858692753
Short name T322
Test name
Test status
Simulation time 369903544 ps
CPU time 7.6 seconds
Started Jun 24 05:12:38 PM PDT 24
Finished Jun 24 05:12:47 PM PDT 24
Peak memory 225572 kb
Host smart-17d3d5d0-b1ce-4cfd-a0c1-9aed4c802f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858692753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3858692753
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1351453554
Short name T196
Test name
Test status
Simulation time 7270648557 ps
CPU time 23.72 seconds
Started Jun 24 05:12:41 PM PDT 24
Finished Jun 24 05:13:05 PM PDT 24
Peak memory 233848 kb
Host smart-53597b2a-1a9b-44db-8050-563434511b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351453554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1351453554
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1968723326
Short name T923
Test name
Test status
Simulation time 231353179 ps
CPU time 3.76 seconds
Started Jun 24 05:12:41 PM PDT 24
Finished Jun 24 05:12:46 PM PDT 24
Peak memory 225440 kb
Host smart-ed15c653-d649-4b95-913c-12f6a2847684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968723326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1968723326
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3503042812
Short name T124
Test name
Test status
Simulation time 3226626597 ps
CPU time 17.98 seconds
Started Jun 24 05:12:39 PM PDT 24
Finished Jun 24 05:12:58 PM PDT 24
Peak memory 222660 kb
Host smart-83c0ce04-b0d6-4adf-86b3-4821d0bfd26d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3503042812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3503042812
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3619323659
Short name T154
Test name
Test status
Simulation time 3845141272 ps
CPU time 59.92 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:13:50 PM PDT 24
Peak memory 250324 kb
Host smart-1b0c58e1-b69b-4827-baf8-bc8c99694c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619323659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3619323659
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3344747276
Short name T950
Test name
Test status
Simulation time 2460086717 ps
CPU time 12.99 seconds
Started Jun 24 05:12:40 PM PDT 24
Finished Jun 24 05:12:54 PM PDT 24
Peak memory 217476 kb
Host smart-530e6aeb-adff-4862-9530-73aaa6e968c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344747276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3344747276
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.662094913
Short name T324
Test name
Test status
Simulation time 394640871 ps
CPU time 1.62 seconds
Started Jun 24 05:12:38 PM PDT 24
Finished Jun 24 05:12:41 PM PDT 24
Peak memory 208784 kb
Host smart-987ef243-1ccd-4cf9-b4a0-6a45a12ee532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662094913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.662094913
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1685316411
Short name T67
Test name
Test status
Simulation time 82127031 ps
CPU time 1.23 seconds
Started Jun 24 05:12:40 PM PDT 24
Finished Jun 24 05:12:42 PM PDT 24
Peak memory 217256 kb
Host smart-5962258e-b6b9-456a-a03b-5a36c44f6a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685316411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1685316411
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.503171672
Short name T595
Test name
Test status
Simulation time 85447863 ps
CPU time 0.77 seconds
Started Jun 24 05:12:38 PM PDT 24
Finished Jun 24 05:12:40 PM PDT 24
Peak memory 206868 kb
Host smart-de29d158-2bc6-4e49-829f-0d5ba7aac2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503171672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.503171672
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3777440023
Short name T537
Test name
Test status
Simulation time 6572656785 ps
CPU time 12.9 seconds
Started Jun 24 05:12:39 PM PDT 24
Finished Jun 24 05:12:53 PM PDT 24
Peak memory 240516 kb
Host smart-332b2644-f26a-4090-bb0e-a23e5e5f4475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777440023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3777440023
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.820049802
Short name T434
Test name
Test status
Simulation time 50533423 ps
CPU time 0.72 seconds
Started Jun 24 05:12:47 PM PDT 24
Finished Jun 24 05:12:49 PM PDT 24
Peak memory 205588 kb
Host smart-bb78d218-a2b5-4f98-8900-e37d7b06320a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820049802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.820049802
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1858769300
Short name T519
Test name
Test status
Simulation time 405587240 ps
CPU time 5.45 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:12:55 PM PDT 24
Peak memory 225448 kb
Host smart-ff339b79-9195-415a-82fb-71cdcba382b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858769300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1858769300
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2564813057
Short name T310
Test name
Test status
Simulation time 55446627 ps
CPU time 0.76 seconds
Started Jun 24 05:12:46 PM PDT 24
Finished Jun 24 05:12:48 PM PDT 24
Peak memory 208040 kb
Host smart-7011b32c-3643-4fd2-8fb8-673a5232ec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564813057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2564813057
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2117422031
Short name T816
Test name
Test status
Simulation time 2298620268 ps
CPU time 27.12 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:13:17 PM PDT 24
Peak memory 225668 kb
Host smart-6104b261-01a2-4c24-915d-cefa13adf1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117422031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2117422031
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.861684896
Short name T274
Test name
Test status
Simulation time 35362057832 ps
CPU time 76.11 seconds
Started Jun 24 05:12:47 PM PDT 24
Finished Jun 24 05:14:04 PM PDT 24
Peak memory 263184 kb
Host smart-05a904b9-3181-4cf6-b9bf-3f3582fa4a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861684896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.861684896
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3706091355
Short name T395
Test name
Test status
Simulation time 40278290215 ps
CPU time 246.43 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:16:57 PM PDT 24
Peak memory 250236 kb
Host smart-d2830063-8a12-4cc5-bebf-fb0ab8c06781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706091355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3706091355
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4161641936
Short name T640
Test name
Test status
Simulation time 15348447241 ps
CPU time 10.87 seconds
Started Jun 24 05:12:49 PM PDT 24
Finished Jun 24 05:13:02 PM PDT 24
Peak memory 233944 kb
Host smart-4c47e1dd-e15b-4503-a26f-3d108409db9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161641936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4161641936
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.287389334
Short name T807
Test name
Test status
Simulation time 1627558001 ps
CPU time 10.49 seconds
Started Jun 24 05:12:47 PM PDT 24
Finished Jun 24 05:12:59 PM PDT 24
Peak memory 233744 kb
Host smart-44f80df8-283d-4e38-901d-3f9b53a52d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287389334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.287389334
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.173425017
Short name T940
Test name
Test status
Simulation time 5634550213 ps
CPU time 59.28 seconds
Started Jun 24 05:12:46 PM PDT 24
Finished Jun 24 05:13:46 PM PDT 24
Peak memory 239720 kb
Host smart-8aaaca83-3482-40ab-9dae-dc5d9aa0e304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173425017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.173425017
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.419811660
Short name T246
Test name
Test status
Simulation time 80482877 ps
CPU time 2.14 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:12:52 PM PDT 24
Peak memory 225472 kb
Host smart-2690e04d-76d2-4ed9-ad97-0f87614c7d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419811660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.419811660
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3722971247
Short name T513
Test name
Test status
Simulation time 892189350 ps
CPU time 3.73 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:12:54 PM PDT 24
Peak memory 233756 kb
Host smart-fb47257e-ee2c-4d2f-a809-cb6f803ce629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722971247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3722971247
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2301068609
Short name T744
Test name
Test status
Simulation time 3833923039 ps
CPU time 13.16 seconds
Started Jun 24 05:12:47 PM PDT 24
Finished Jun 24 05:13:02 PM PDT 24
Peak memory 220264 kb
Host smart-5cfe360e-f6eb-442d-988c-e18e42fc3dbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2301068609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2301068609
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2189612226
Short name T445
Test name
Test status
Simulation time 132976045 ps
CPU time 0.91 seconds
Started Jun 24 05:12:46 PM PDT 24
Finished Jun 24 05:12:48 PM PDT 24
Peak memory 207448 kb
Host smart-241ecbc1-4910-4952-875c-ee0f7e35dc7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189612226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2189612226
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2418834466
Short name T933
Test name
Test status
Simulation time 9078816219 ps
CPU time 25.98 seconds
Started Jun 24 05:12:47 PM PDT 24
Finished Jun 24 05:13:15 PM PDT 24
Peak memory 217444 kb
Host smart-f66b8361-4318-4fbf-a511-5d3df65b81b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418834466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2418834466
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1337884617
Short name T719
Test name
Test status
Simulation time 1564650459 ps
CPU time 5.12 seconds
Started Jun 24 05:12:49 PM PDT 24
Finished Jun 24 05:12:56 PM PDT 24
Peak memory 217508 kb
Host smart-96f079b6-0c90-4dad-acc7-c81798683f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337884617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1337884617
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2477841255
Short name T436
Test name
Test status
Simulation time 28805713 ps
CPU time 1.02 seconds
Started Jun 24 05:12:49 PM PDT 24
Finished Jun 24 05:12:52 PM PDT 24
Peak memory 207952 kb
Host smart-ea10c494-f10f-4f84-a522-f4ea17cb7163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477841255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2477841255
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1506001365
Short name T296
Test name
Test status
Simulation time 22262696 ps
CPU time 0.78 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:12:51 PM PDT 24
Peak memory 206876 kb
Host smart-434d2a43-5d06-4986-bfa4-417b80f60dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506001365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1506001365
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.957042896
Short name T598
Test name
Test status
Simulation time 1206537365 ps
CPU time 9.18 seconds
Started Jun 24 05:12:47 PM PDT 24
Finished Jun 24 05:12:57 PM PDT 24
Peak memory 233704 kb
Host smart-96566af0-10ea-4f3a-8d01-b3163556e0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957042896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.957042896
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4008211765
Short name T71
Test name
Test status
Simulation time 37108165 ps
CPU time 0.76 seconds
Started Jun 24 05:12:57 PM PDT 24
Finished Jun 24 05:13:00 PM PDT 24
Peak memory 205700 kb
Host smart-f52bcfa5-13e1-471f-839c-f1f8fea6f97c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008211765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4008211765
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.744779927
Short name T930
Test name
Test status
Simulation time 2179124375 ps
CPU time 8.57 seconds
Started Jun 24 05:12:57 PM PDT 24
Finished Jun 24 05:13:08 PM PDT 24
Peak memory 225660 kb
Host smart-e1428381-092c-4a48-a88d-f1a9d6865ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744779927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.744779927
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2046788085
Short name T599
Test name
Test status
Simulation time 44444363 ps
CPU time 0.78 seconds
Started Jun 24 05:12:47 PM PDT 24
Finished Jun 24 05:12:48 PM PDT 24
Peak memory 207488 kb
Host smart-2ca2885c-9ced-47b6-ac30-7986d3dc78dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046788085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2046788085
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3941777738
Short name T177
Test name
Test status
Simulation time 208319809029 ps
CPU time 124.57 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:15:03 PM PDT 24
Peak memory 252816 kb
Host smart-99675ddd-a9bf-4b78-8077-31064b482966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941777738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3941777738
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.787789937
Short name T193
Test name
Test status
Simulation time 138046511491 ps
CPU time 337.96 seconds
Started Jun 24 05:12:57 PM PDT 24
Finished Jun 24 05:18:37 PM PDT 24
Peak memory 266428 kb
Host smart-2bf38686-9930-40a8-ac99-7f12cecd7c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787789937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.787789937
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.4159038097
Short name T58
Test name
Test status
Simulation time 9050507424 ps
CPU time 95.77 seconds
Started Jun 24 05:12:58 PM PDT 24
Finished Jun 24 05:14:35 PM PDT 24
Peak memory 250516 kb
Host smart-8b79e4e3-d925-4a0c-be81-8667dc244095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159038097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.4159038097
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.203582264
Short name T762
Test name
Test status
Simulation time 153671350 ps
CPU time 5.44 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:13:03 PM PDT 24
Peak memory 225568 kb
Host smart-cc9a7534-8049-4483-9c11-cd169222f62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203582264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.203582264
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2165856984
Short name T624
Test name
Test status
Simulation time 144071293 ps
CPU time 3.24 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:13:01 PM PDT 24
Peak memory 233700 kb
Host smart-06d8d386-190d-4f70-9b20-1af49b9a21cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165856984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2165856984
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2467677154
Short name T503
Test name
Test status
Simulation time 1391379518 ps
CPU time 8.6 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 233700 kb
Host smart-2e6c1cb7-ed1e-4f1d-81a0-d0ceddd0b2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467677154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2467677154
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.453344019
Short name T38
Test name
Test status
Simulation time 1140292792 ps
CPU time 2.76 seconds
Started Jun 24 05:12:58 PM PDT 24
Finished Jun 24 05:13:02 PM PDT 24
Peak memory 225460 kb
Host smart-3efbf327-1c17-46f9-ad58-cb5f159d05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453344019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.453344019
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4190383737
Short name T839
Test name
Test status
Simulation time 7579696699 ps
CPU time 7.2 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 225668 kb
Host smart-77c5cddd-6a05-433d-86c6-c00c60becdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190383737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4190383737
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4101296546
Short name T965
Test name
Test status
Simulation time 1659255376 ps
CPU time 18.28 seconds
Started Jun 24 05:12:54 PM PDT 24
Finished Jun 24 05:13:14 PM PDT 24
Peak memory 220304 kb
Host smart-e66c4676-d75e-4ddc-9d46-acb91b6d563e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4101296546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4101296546
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3539319435
Short name T905
Test name
Test status
Simulation time 1270915035 ps
CPU time 13.36 seconds
Started Jun 24 05:12:49 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 217356 kb
Host smart-daa28435-8679-44a6-9c21-39acf558ce82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539319435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3539319435
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2261009504
Short name T568
Test name
Test status
Simulation time 1236460265 ps
CPU time 7.48 seconds
Started Jun 24 05:12:49 PM PDT 24
Finished Jun 24 05:12:58 PM PDT 24
Peak memory 217328 kb
Host smart-e893c1c0-3517-45b7-af5a-de41152758b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261009504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2261009504
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2869157447
Short name T321
Test name
Test status
Simulation time 33515235 ps
CPU time 1.37 seconds
Started Jun 24 05:12:49 PM PDT 24
Finished Jun 24 05:12:52 PM PDT 24
Peak memory 217296 kb
Host smart-55f2ec66-c68e-49d2-8c17-700514db10a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869157447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2869157447
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3498737857
Short name T439
Test name
Test status
Simulation time 29407522 ps
CPU time 0.84 seconds
Started Jun 24 05:12:48 PM PDT 24
Finished Jun 24 05:12:51 PM PDT 24
Peak memory 206860 kb
Host smart-08051c5e-cacd-49b1-b947-9e66b5844163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498737857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3498737857
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1652757736
Short name T947
Test name
Test status
Simulation time 11865134187 ps
CPU time 11.73 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:13:08 PM PDT 24
Peak memory 233764 kb
Host smart-060354f1-aceb-4e06-9dd8-a3cba3ae4a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652757736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1652757736
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1204188897
Short name T372
Test name
Test status
Simulation time 14232027 ps
CPU time 0.74 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:12:59 PM PDT 24
Peak memory 206256 kb
Host smart-4673b459-943f-4c7e-acba-88c70b1f4c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204188897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1204188897
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1334890862
Short name T14
Test name
Test status
Simulation time 515966075 ps
CPU time 2.9 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:13:00 PM PDT 24
Peak memory 225492 kb
Host smart-f6fd6ddc-761f-477e-bfe0-af641bb924a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334890862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1334890862
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4278317803
Short name T968
Test name
Test status
Simulation time 16521866 ps
CPU time 0.77 seconds
Started Jun 24 05:13:01 PM PDT 24
Finished Jun 24 05:13:02 PM PDT 24
Peak memory 206492 kb
Host smart-e1c04a34-0878-4439-8c41-dee5a00df35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278317803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4278317803
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3139606502
Short name T620
Test name
Test status
Simulation time 20243245608 ps
CPU time 108.96 seconds
Started Jun 24 05:12:57 PM PDT 24
Finished Jun 24 05:14:48 PM PDT 24
Peak memory 254960 kb
Host smart-14aaaee0-88df-4300-9f4e-064eb7a0441f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139606502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3139606502
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2322744200
Short name T525
Test name
Test status
Simulation time 14350680259 ps
CPU time 110.47 seconds
Started Jun 24 05:12:59 PM PDT 24
Finished Jun 24 05:14:50 PM PDT 24
Peak memory 250236 kb
Host smart-cdf2e53f-e136-4722-83a7-ee8a05b9aa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322744200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2322744200
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3942155020
Short name T264
Test name
Test status
Simulation time 172916473426 ps
CPU time 440.31 seconds
Started Jun 24 05:12:57 PM PDT 24
Finished Jun 24 05:20:20 PM PDT 24
Peak memory 274728 kb
Host smart-f1000cc7-98ae-48ac-b60e-e4f76df8984f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942155020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3942155020
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2894252647
Short name T860
Test name
Test status
Simulation time 208803906 ps
CPU time 6.54 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 225540 kb
Host smart-6449446b-7e84-4831-97be-6299fcdbf679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894252647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2894252647
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.131723415
Short name T956
Test name
Test status
Simulation time 1148229383 ps
CPU time 8.21 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:13:05 PM PDT 24
Peak memory 225548 kb
Host smart-9b9b72a9-6c8f-45e4-b660-9095ec013327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131723415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.131723415
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1211107240
Short name T528
Test name
Test status
Simulation time 3342106088 ps
CPU time 36.75 seconds
Started Jun 24 05:12:58 PM PDT 24
Finished Jun 24 05:13:36 PM PDT 24
Peak memory 241396 kb
Host smart-8fe78731-b19d-4c2f-b62c-f32f8f036461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211107240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1211107240
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.4044406336
Short name T411
Test name
Test status
Simulation time 58049130 ps
CPU time 2.33 seconds
Started Jun 24 05:13:01 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 233524 kb
Host smart-4ebe8826-bd44-4bfb-a772-23808f2ea7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044406336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.4044406336
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3566940773
Short name T182
Test name
Test status
Simulation time 860652717 ps
CPU time 6.9 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 233540 kb
Host smart-343a6374-a901-43d3-9d18-c0af31505c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566940773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3566940773
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1627868444
Short name T806
Test name
Test status
Simulation time 1330917278 ps
CPU time 9.32 seconds
Started Jun 24 05:13:01 PM PDT 24
Finished Jun 24 05:13:11 PM PDT 24
Peak memory 224072 kb
Host smart-e2635786-4df3-4f1c-9b66-cf57a789ec55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1627868444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1627868444
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3268446642
Short name T160
Test name
Test status
Simulation time 276275851 ps
CPU time 1.16 seconds
Started Jun 24 05:13:01 PM PDT 24
Finished Jun 24 05:13:03 PM PDT 24
Peak memory 208220 kb
Host smart-717f5ed3-7123-48c0-9670-45dc54d83d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268446642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3268446642
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.653963309
Short name T488
Test name
Test status
Simulation time 1221181157 ps
CPU time 6.86 seconds
Started Jun 24 05:12:59 PM PDT 24
Finished Jun 24 05:13:07 PM PDT 24
Peak memory 217280 kb
Host smart-1055a96b-5dc5-472c-9e7d-d02954cccdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653963309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.653963309
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2740491236
Short name T740
Test name
Test status
Simulation time 3328647229 ps
CPU time 10.78 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:13:08 PM PDT 24
Peak memory 217464 kb
Host smart-487da584-9ba8-4653-a6f8-35b4c3821df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740491236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2740491236
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.918768741
Short name T307
Test name
Test status
Simulation time 34129700 ps
CPU time 0.92 seconds
Started Jun 24 05:13:01 PM PDT 24
Finished Jun 24 05:13:02 PM PDT 24
Peak memory 208016 kb
Host smart-faffaffd-07e2-46af-91c9-db55540bc3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918768741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.918768741
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3888199499
Short name T320
Test name
Test status
Simulation time 107336133 ps
CPU time 0.87 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:12:59 PM PDT 24
Peak memory 206864 kb
Host smart-191b4245-6046-47ad-949e-2784f7daff47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888199499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3888199499
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.658017062
Short name T886
Test name
Test status
Simulation time 6923525971 ps
CPU time 4.28 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:13:02 PM PDT 24
Peak memory 233824 kb
Host smart-336abda2-8cca-457f-a8e7-94bad9acfba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658017062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.658017062
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2297638049
Short name T694
Test name
Test status
Simulation time 23648230 ps
CPU time 0.72 seconds
Started Jun 24 05:13:10 PM PDT 24
Finished Jun 24 05:13:11 PM PDT 24
Peak memory 206248 kb
Host smart-04d91be2-0ddc-4493-8127-d6b17c4b7381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297638049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2297638049
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1115891962
Short name T763
Test name
Test status
Simulation time 436305288 ps
CPU time 6.96 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:13:11 PM PDT 24
Peak memory 225548 kb
Host smart-29e4137c-a975-4967-88d4-cd8ba123e51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115891962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1115891962
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2040467155
Short name T690
Test name
Test status
Simulation time 20412870 ps
CPU time 0.84 seconds
Started Jun 24 05:12:55 PM PDT 24
Finished Jun 24 05:12:58 PM PDT 24
Peak memory 207816 kb
Host smart-ec54010b-6836-4e3e-bda1-fadf23c51ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040467155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2040467155
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3258344054
Short name T883
Test name
Test status
Simulation time 38762769 ps
CPU time 0.77 seconds
Started Jun 24 05:13:04 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 216812 kb
Host smart-95a2fdf6-5dfb-442c-9d99-270302783370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258344054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3258344054
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1190120850
Short name T501
Test name
Test status
Simulation time 11863269166 ps
CPU time 123.37 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:15:07 PM PDT 24
Peak memory 242092 kb
Host smart-bae2f3a7-504b-4f34-9e6a-30964e944f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190120850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1190120850
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3445929413
Short name T190
Test name
Test status
Simulation time 10945882806 ps
CPU time 84.23 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:14:28 PM PDT 24
Peak memory 258180 kb
Host smart-636f13f1-6183-4f91-8e78-6e332b53ac1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445929413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3445929413
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.739402629
Short name T767
Test name
Test status
Simulation time 231745455 ps
CPU time 3.11 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:08 PM PDT 24
Peak memory 225492 kb
Host smart-8dfe9cb5-cd23-4a1b-acd1-9f023ce5b168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739402629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.739402629
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3551654168
Short name T333
Test name
Test status
Simulation time 177776188 ps
CPU time 3.02 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 225424 kb
Host smart-c4cdf09e-3ac6-4214-a945-61131a803a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551654168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3551654168
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1698115205
Short name T804
Test name
Test status
Simulation time 4915830012 ps
CPU time 40.73 seconds
Started Jun 24 05:13:04 PM PDT 24
Finished Jun 24 05:13:46 PM PDT 24
Peak memory 250496 kb
Host smart-56a26974-606f-4cab-abe1-39ffa570d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698115205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1698115205
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.69342320
Short name T25
Test name
Test status
Simulation time 21849814428 ps
CPU time 18.42 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:23 PM PDT 24
Peak memory 233840 kb
Host smart-7aa78471-a5ce-466e-a601-cf6b5e4b0c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69342320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.69342320
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3698791052
Short name T667
Test name
Test status
Simulation time 1506650861 ps
CPU time 6.93 seconds
Started Jun 24 05:13:08 PM PDT 24
Finished Jun 24 05:13:15 PM PDT 24
Peak memory 241912 kb
Host smart-0e7ea4f6-5dd3-4493-8118-9ccab509ba46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698791052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3698791052
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.963736229
Short name T337
Test name
Test status
Simulation time 5213553025 ps
CPU time 13.91 seconds
Started Jun 24 05:13:08 PM PDT 24
Finished Jun 24 05:13:23 PM PDT 24
Peak memory 220096 kb
Host smart-41fc5c57-9f8b-4f1f-ae1a-4eff11881c41
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=963736229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.963736229
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.4123427111
Short name T491
Test name
Test status
Simulation time 662506752 ps
CPU time 1.07 seconds
Started Jun 24 05:13:01 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 207832 kb
Host smart-291df05f-935f-4077-8fef-1006337ce64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123427111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.4123427111
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.37997569
Short name T869
Test name
Test status
Simulation time 1153922096 ps
CPU time 6.19 seconds
Started Jun 24 05:12:54 PM PDT 24
Finished Jun 24 05:13:02 PM PDT 24
Peak memory 217372 kb
Host smart-0a068c67-4591-4fa5-a188-fe779eeb7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37997569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.37997569
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1580650289
Short name T604
Test name
Test status
Simulation time 1856686307 ps
CPU time 7.79 seconds
Started Jun 24 05:12:56 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 217320 kb
Host smart-e8272bc8-3ad5-41e2-bf67-399d379b9d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580650289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1580650289
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2942226899
Short name T330
Test name
Test status
Simulation time 174199650 ps
CPU time 1.13 seconds
Started Jun 24 05:13:04 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 217116 kb
Host smart-f886fa30-d836-4f30-ad53-2b89b0d07d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942226899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2942226899
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4168402307
Short name T782
Test name
Test status
Simulation time 27724267 ps
CPU time 0.73 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 206888 kb
Host smart-ad2a4eb3-36ac-469d-bed2-cf831a51c111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168402307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4168402307
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2485726959
Short name T5
Test name
Test status
Simulation time 5569177020 ps
CPU time 11.73 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:13:15 PM PDT 24
Peak memory 241936 kb
Host smart-420fc3b2-caa1-44b2-a53c-51401d63805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485726959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2485726959
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1975520338
Short name T969
Test name
Test status
Simulation time 15808925 ps
CPU time 0.77 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:13 PM PDT 24
Peak memory 205692 kb
Host smart-daf8e4f2-a152-4602-b035-c7c708889861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975520338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1975520338
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.814246815
Short name T487
Test name
Test status
Simulation time 41052168 ps
CPU time 2.73 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:16 PM PDT 24
Peak memory 233668 kb
Host smart-07f0e70d-56c1-4bca-944d-690d6a3e5622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814246815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.814246815
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.662537915
Short name T311
Test name
Test status
Simulation time 47129792 ps
CPU time 0.78 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:05 PM PDT 24
Peak memory 207468 kb
Host smart-38d058c9-100f-4aaa-8c89-dee2c183e6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662537915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.662537915
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1336056646
Short name T426
Test name
Test status
Simulation time 3156722563 ps
CPU time 57.11 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:14:11 PM PDT 24
Peak memory 254504 kb
Host smart-3f162d05-5ed3-4e7a-a5a4-18686c04526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336056646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1336056646
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1398598449
Short name T40
Test name
Test status
Simulation time 72153148069 ps
CPU time 229.35 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:17:02 PM PDT 24
Peak memory 257028 kb
Host smart-ee3cd2d2-087e-4fe9-ab8d-5ef0fd1652b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398598449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1398598449
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.582700925
Short name T967
Test name
Test status
Simulation time 7535647933 ps
CPU time 85.91 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:14:40 PM PDT 24
Peak memory 255384 kb
Host smart-965cdb8f-bc1f-4c4a-af27-501b20ec5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582700925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.582700925
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3636963537
Short name T279
Test name
Test status
Simulation time 1033857447 ps
CPU time 8.49 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:13:22 PM PDT 24
Peak memory 233400 kb
Host smart-e760c2cc-b49b-409e-b294-a804c5951c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636963537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3636963537
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4032807652
Short name T233
Test name
Test status
Simulation time 8592609492 ps
CPU time 18.19 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:23 PM PDT 24
Peak memory 233884 kb
Host smart-f3456708-447a-41e1-9c11-62cf64d64cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032807652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4032807652
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3448717579
Short name T194
Test name
Test status
Simulation time 1091555283 ps
CPU time 13.29 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:17 PM PDT 24
Peak memory 251868 kb
Host smart-9d78a515-adc5-4996-ac12-9d850037c885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448717579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3448717579
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2321465644
Short name T603
Test name
Test status
Simulation time 151901341 ps
CPU time 2.49 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:07 PM PDT 24
Peak memory 233756 kb
Host smart-1d05b12f-443a-4f3e-9173-ecf0f50bf180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321465644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2321465644
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2684154192
Short name T156
Test name
Test status
Simulation time 8972345876 ps
CPU time 9.38 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:14 PM PDT 24
Peak memory 225620 kb
Host smart-bcaa439f-d9d3-41fa-9f08-1a6e0057f0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684154192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2684154192
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.66826759
Short name T549
Test name
Test status
Simulation time 664865542 ps
CPU time 5.46 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:18 PM PDT 24
Peak memory 220440 kb
Host smart-34ec178d-8db6-4a88-8f6c-767e2b2941f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=66826759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direc
t.66826759
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3387219991
Short name T431
Test name
Test status
Simulation time 8362600262 ps
CPU time 15.54 seconds
Started Jun 24 05:13:01 PM PDT 24
Finished Jun 24 05:13:18 PM PDT 24
Peak memory 217484 kb
Host smart-76a46abf-f5e4-4ffd-81f4-9d4614b1f57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387219991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3387219991
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3888397596
Short name T559
Test name
Test status
Simulation time 7797306819 ps
CPU time 14.18 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:13:17 PM PDT 24
Peak memory 217492 kb
Host smart-ae7ba6d7-7fc3-48fc-9113-f1e9aa42a73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888397596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3888397596
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2402361910
Short name T424
Test name
Test status
Simulation time 84089310 ps
CPU time 1.84 seconds
Started Jun 24 05:13:03 PM PDT 24
Finished Jun 24 05:13:06 PM PDT 24
Peak memory 217272 kb
Host smart-a1d913c4-175f-4917-9f1f-837735f358bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402361910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2402361910
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1396916279
Short name T417
Test name
Test status
Simulation time 22394061 ps
CPU time 0.87 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:13:04 PM PDT 24
Peak memory 206884 kb
Host smart-7559a2b7-9c30-423d-b633-52f0b8657a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396916279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1396916279
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.736303256
Short name T294
Test name
Test status
Simulation time 4964479831 ps
CPU time 8.9 seconds
Started Jun 24 05:13:02 PM PDT 24
Finished Jun 24 05:13:13 PM PDT 24
Peak memory 233744 kb
Host smart-b9fd50bd-ff9a-4a2b-83ae-df975d398889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736303256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.736303256
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2126292289
Short name T921
Test name
Test status
Simulation time 35003076 ps
CPU time 0.68 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:13:14 PM PDT 24
Peak memory 206156 kb
Host smart-b39985eb-b35c-4b07-b752-a074205bf179
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126292289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2126292289
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2648207161
Short name T617
Test name
Test status
Simulation time 3733948508 ps
CPU time 19 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:13:33 PM PDT 24
Peak memory 233848 kb
Host smart-edd65261-6815-4165-9944-3b7e82f35956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648207161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2648207161
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1514167757
Short name T718
Test name
Test status
Simulation time 17656882 ps
CPU time 0.81 seconds
Started Jun 24 05:13:21 PM PDT 24
Finished Jun 24 05:13:22 PM PDT 24
Peak memory 207756 kb
Host smart-40c07025-cf2b-4fab-8182-04af33465b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514167757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1514167757
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2534734697
Short name T191
Test name
Test status
Simulation time 510304155 ps
CPU time 11.65 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:13:25 PM PDT 24
Peak memory 233688 kb
Host smart-1d50dacb-d3e2-4e79-b5dd-ecc3383d3008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534734697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2534734697
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3148768418
Short name T422
Test name
Test status
Simulation time 12885909727 ps
CPU time 70.5 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:14:24 PM PDT 24
Peak memory 250232 kb
Host smart-d08775ed-5478-49e8-b70f-021deaece208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148768418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3148768418
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2275123138
Short name T175
Test name
Test status
Simulation time 85322222745 ps
CPU time 439.88 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:20:34 PM PDT 24
Peak memory 253724 kb
Host smart-b317132e-1a61-4afb-a701-9e998c8f3cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275123138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2275123138
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3352031260
Short name T691
Test name
Test status
Simulation time 9989304027 ps
CPU time 30.61 seconds
Started Jun 24 05:13:13 PM PDT 24
Finished Jun 24 05:13:45 PM PDT 24
Peak memory 225608 kb
Host smart-325332af-c23a-4eb8-8279-770841e0ff6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352031260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3352031260
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2992862172
Short name T770
Test name
Test status
Simulation time 8063965902 ps
CPU time 16.09 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:13:29 PM PDT 24
Peak memory 225612 kb
Host smart-d2c1f129-ef28-4f21-94cb-a360664b8e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992862172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2992862172
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1355362060
Short name T249
Test name
Test status
Simulation time 32182937149 ps
CPU time 39.82 seconds
Started Jun 24 05:13:10 PM PDT 24
Finished Jun 24 05:13:51 PM PDT 24
Peak memory 233792 kb
Host smart-e3d414bc-a816-4bde-a208-31aada90dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355362060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1355362060
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3861969337
Short name T266
Test name
Test status
Simulation time 1662032072 ps
CPU time 6.06 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:19 PM PDT 24
Peak memory 233748 kb
Host smart-604afdd9-1989-438f-ac9f-332578a487b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861969337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3861969337
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2965123864
Short name T830
Test name
Test status
Simulation time 3757637246 ps
CPU time 13.25 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:26 PM PDT 24
Peak memory 241808 kb
Host smart-824f4125-fe27-4cff-ab49-a31c76c65a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965123864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2965123864
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3591988797
Short name T810
Test name
Test status
Simulation time 639370324 ps
CPU time 4.88 seconds
Started Jun 24 05:13:10 PM PDT 24
Finished Jun 24 05:13:16 PM PDT 24
Peak memory 222244 kb
Host smart-8de8aac6-e5cd-4db1-b7c3-ac462c4bbbb6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3591988797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3591988797
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3986517401
Short name T749
Test name
Test status
Simulation time 46428595622 ps
CPU time 464.59 seconds
Started Jun 24 05:13:10 PM PDT 24
Finished Jun 24 05:20:56 PM PDT 24
Peak memory 266452 kb
Host smart-dd46b87a-6c1e-4675-92fc-e30c24f26750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986517401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3986517401
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1836338667
Short name T314
Test name
Test status
Simulation time 37860879 ps
CPU time 0.73 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:12 PM PDT 24
Peak memory 206596 kb
Host smart-d8e44b31-0e16-4488-8e0e-3abc79cae55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836338667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1836338667
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3124760268
Short name T474
Test name
Test status
Simulation time 1062919955 ps
CPU time 3.75 seconds
Started Jun 24 05:13:10 PM PDT 24
Finished Jun 24 05:13:14 PM PDT 24
Peak memory 216976 kb
Host smart-a69a5163-c9d4-4f6b-b89d-0e5c16ddaf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124760268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3124760268
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1338721217
Short name T675
Test name
Test status
Simulation time 178570621 ps
CPU time 2.21 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:13:16 PM PDT 24
Peak memory 217360 kb
Host smart-c810550b-2073-431f-a3c3-5356a9cff31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338721217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1338721217
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.57792580
Short name T397
Test name
Test status
Simulation time 136221620 ps
CPU time 0.81 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:14 PM PDT 24
Peak memory 206860 kb
Host smart-d8b7e8de-64f5-431e-8fe8-0462611bc9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57792580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.57792580
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1677593828
Short name T881
Test name
Test status
Simulation time 1836647917 ps
CPU time 11.4 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:23 PM PDT 24
Peak memory 250068 kb
Host smart-e5f62750-ffe8-48ab-aaa5-890681e5efeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677593828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1677593828
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1060059816
Short name T440
Test name
Test status
Simulation time 56879704 ps
CPU time 0.7 seconds
Started Jun 24 05:13:19 PM PDT 24
Finished Jun 24 05:13:20 PM PDT 24
Peak memory 206604 kb
Host smart-7cb28fc7-3a83-46e3-b52b-80e05fa7473a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060059816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1060059816
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1598959860
Short name T226
Test name
Test status
Simulation time 5243202382 ps
CPU time 14.79 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:41 PM PDT 24
Peak memory 233844 kb
Host smart-81168447-b0cb-4dc5-adf2-653ecba17575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598959860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1598959860
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4219805715
Short name T373
Test name
Test status
Simulation time 12640235 ps
CPU time 0.77 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:14 PM PDT 24
Peak memory 206436 kb
Host smart-9676066e-cf2e-46b7-b938-ab546bf94ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219805715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4219805715
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3757605278
Short name T245
Test name
Test status
Simulation time 24462345102 ps
CPU time 93.58 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:14:59 PM PDT 24
Peak memory 254780 kb
Host smart-fec8c3a9-4262-4b7d-8c16-092c914484fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757605278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3757605278
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.974183116
Short name T180
Test name
Test status
Simulation time 90744556767 ps
CPU time 210.62 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:16:57 PM PDT 24
Peak memory 270956 kb
Host smart-96d958ad-0a97-4151-b1f1-80319c21d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974183116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.974183116
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4104998122
Short name T137
Test name
Test status
Simulation time 440915894 ps
CPU time 9.51 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:36 PM PDT 24
Peak memory 241288 kb
Host smart-bd001ab7-4a26-43a5-b38e-ffde3941f948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104998122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4104998122
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3503688503
Short name T546
Test name
Test status
Simulation time 39273625 ps
CPU time 2.54 seconds
Started Jun 24 05:13:20 PM PDT 24
Finished Jun 24 05:13:23 PM PDT 24
Peak memory 233744 kb
Host smart-0aee1753-fd7a-4722-af11-8cc9bf9b986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503688503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3503688503
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.814452199
Short name T903
Test name
Test status
Simulation time 541997937 ps
CPU time 5.6 seconds
Started Jun 24 05:13:26 PM PDT 24
Finished Jun 24 05:13:33 PM PDT 24
Peak memory 225488 kb
Host smart-538ca7de-a993-4c5d-9630-1d2453a5ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814452199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.814452199
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1632582443
Short name T662
Test name
Test status
Simulation time 4429070629 ps
CPU time 16.99 seconds
Started Jun 24 05:13:26 PM PDT 24
Finished Jun 24 05:13:45 PM PDT 24
Peak memory 233764 kb
Host smart-5d53c2f2-a33d-491c-96c0-8c91bfc13c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632582443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1632582443
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1768854777
Short name T26
Test name
Test status
Simulation time 2778595009 ps
CPU time 5.82 seconds
Started Jun 24 05:13:23 PM PDT 24
Finished Jun 24 05:13:30 PM PDT 24
Peak memory 225584 kb
Host smart-846abe97-4ca7-430f-ad66-e865bc6cfa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768854777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1768854777
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2147370856
Short name T964
Test name
Test status
Simulation time 380305205 ps
CPU time 4.79 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:13:30 PM PDT 24
Peak memory 223928 kb
Host smart-7c713770-c5a6-4922-b32b-d272eb6cde5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2147370856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2147370856
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1302895628
Short name T357
Test name
Test status
Simulation time 864101362 ps
CPU time 9.63 seconds
Started Jun 24 05:13:12 PM PDT 24
Finished Jun 24 05:13:23 PM PDT 24
Peak memory 217280 kb
Host smart-2eb46c56-0eb4-461e-8b47-51d027fc81c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302895628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1302895628
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2996935170
Short name T790
Test name
Test status
Simulation time 5387673804 ps
CPU time 16.07 seconds
Started Jun 24 05:13:11 PM PDT 24
Finished Jun 24 05:13:28 PM PDT 24
Peak memory 217476 kb
Host smart-6001b236-158e-4a9a-b89a-794b34d4ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996935170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2996935170
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.158726267
Short name T925
Test name
Test status
Simulation time 200635308 ps
CPU time 2.36 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:13:27 PM PDT 24
Peak memory 217300 kb
Host smart-09f2f97f-1eb2-43c1-a9f9-f54257b080df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158726267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.158726267
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2273257137
Short name T83
Test name
Test status
Simulation time 189003108 ps
CPU time 0.84 seconds
Started Jun 24 05:13:19 PM PDT 24
Finished Jun 24 05:13:21 PM PDT 24
Peak memory 206764 kb
Host smart-8ed0f44a-1008-4b69-a652-1e1d6d29d4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273257137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2273257137
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2461672793
Short name T430
Test name
Test status
Simulation time 15730380903 ps
CPU time 17.88 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:44 PM PDT 24
Peak memory 241856 kb
Host smart-57fdad1c-f3d2-4cb2-8302-ebe2e77509ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461672793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2461672793
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2128514511
Short name T316
Test name
Test status
Simulation time 13947182 ps
CPU time 0.71 seconds
Started Jun 24 05:13:27 PM PDT 24
Finished Jun 24 05:13:29 PM PDT 24
Peak memory 206256 kb
Host smart-d384e784-41e2-4a8e-b970-d8779433e894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128514511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2128514511
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1887568317
Short name T88
Test name
Test status
Simulation time 8318473308 ps
CPU time 18.49 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:45 PM PDT 24
Peak memory 225844 kb
Host smart-c05de673-44e4-488c-8f31-0b97aa8dfac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887568317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1887568317
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1077326301
Short name T548
Test name
Test status
Simulation time 14801591 ps
CPU time 0.8 seconds
Started Jun 24 05:13:18 PM PDT 24
Finished Jun 24 05:13:19 PM PDT 24
Peak memory 207756 kb
Host smart-132f8756-242b-4f17-a433-dce551ea8b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077326301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1077326301
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.838599604
Short name T309
Test name
Test status
Simulation time 8017750638 ps
CPU time 19.51 seconds
Started Jun 24 05:13:26 PM PDT 24
Finished Jun 24 05:13:46 PM PDT 24
Peak memory 241024 kb
Host smart-2d5e4f90-2ec7-4830-9363-7ba485dd4af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838599604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.838599604
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.923825586
Short name T183
Test name
Test status
Simulation time 15955505716 ps
CPU time 50.02 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:14:17 PM PDT 24
Peak memory 252800 kb
Host smart-5f1bd9e3-a15e-4c66-9ecc-e98488ab3d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923825586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.923825586
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.85205060
Short name T433
Test name
Test status
Simulation time 13661146018 ps
CPU time 65.94 seconds
Started Jun 24 05:13:18 PM PDT 24
Finished Jun 24 05:14:24 PM PDT 24
Peak memory 250316 kb
Host smart-8c592efe-a106-4b30-aa93-0c077e459bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85205060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.85205060
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3282925715
Short name T700
Test name
Test status
Simulation time 919080175 ps
CPU time 9.78 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:36 PM PDT 24
Peak memory 233644 kb
Host smart-4cc453c1-e216-4312-a8ee-4ff0f4e2f659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282925715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3282925715
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1063728386
Short name T858
Test name
Test status
Simulation time 3100162292 ps
CPU time 18.32 seconds
Started Jun 24 05:13:19 PM PDT 24
Finished Jun 24 05:13:38 PM PDT 24
Peak memory 233884 kb
Host smart-e2e9087f-db26-48e3-bed0-40784ba491f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063728386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1063728386
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3683239873
Short name T593
Test name
Test status
Simulation time 1465539245 ps
CPU time 12.45 seconds
Started Jun 24 05:13:17 PM PDT 24
Finished Jun 24 05:13:30 PM PDT 24
Peak memory 233736 kb
Host smart-4591510c-7a6e-43de-ba81-7c7fe4945655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683239873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3683239873
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2416162582
Short name T556
Test name
Test status
Simulation time 1017805606 ps
CPU time 5.27 seconds
Started Jun 24 05:13:17 PM PDT 24
Finished Jun 24 05:13:23 PM PDT 24
Peak memory 233756 kb
Host smart-73c86e8c-7e39-46ca-861f-abc72118a304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416162582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2416162582
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2829703873
Short name T826
Test name
Test status
Simulation time 143390000 ps
CPU time 2.4 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:29 PM PDT 24
Peak memory 224116 kb
Host smart-e5fdbb4d-af29-4ef5-bb31-1edb1c8f3ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829703873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2829703873
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2621406175
Short name T318
Test name
Test status
Simulation time 6078751395 ps
CPU time 16.44 seconds
Started Jun 24 05:13:17 PM PDT 24
Finished Jun 24 05:13:34 PM PDT 24
Peak memory 224172 kb
Host smart-c0f5876d-4f3e-4f24-8976-8f9e60bae2b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2621406175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2621406175
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2058733092
Short name T656
Test name
Test status
Simulation time 90783856 ps
CPU time 0.71 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:27 PM PDT 24
Peak memory 206596 kb
Host smart-8878a268-ac66-4076-a1de-a5cd93d13eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058733092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2058733092
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1870696538
Short name T847
Test name
Test status
Simulation time 1447665997 ps
CPU time 1.39 seconds
Started Jun 24 05:13:23 PM PDT 24
Finished Jun 24 05:13:25 PM PDT 24
Peak memory 208764 kb
Host smart-4bfb48f8-14fb-4d7e-ba13-1602840c42b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870696538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1870696538
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4168173697
Short name T380
Test name
Test status
Simulation time 167374021 ps
CPU time 1.13 seconds
Started Jun 24 05:13:19 PM PDT 24
Finished Jun 24 05:13:21 PM PDT 24
Peak memory 208772 kb
Host smart-dfce06cb-70d8-45af-b5bd-fdf2e1fcbcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168173697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4168173697
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.248084716
Short name T483
Test name
Test status
Simulation time 216356433 ps
CPU time 0.87 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:28 PM PDT 24
Peak memory 206780 kb
Host smart-f3a4275d-884e-4b9c-a3fc-1dd7faf961dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248084716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.248084716
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3145205808
Short name T448
Test name
Test status
Simulation time 1489909380 ps
CPU time 8.68 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:35 PM PDT 24
Peak memory 233732 kb
Host smart-733b4f6d-f47f-439d-80a0-e17aeeac0ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145205808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3145205808
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2113187832
Short name T442
Test name
Test status
Simulation time 13510171 ps
CPU time 0.71 seconds
Started Jun 24 05:13:22 PM PDT 24
Finished Jun 24 05:13:24 PM PDT 24
Peak memory 205940 kb
Host smart-294647f2-eba6-4fa0-a81e-743f152f0c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113187832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2113187832
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3086085215
Short name T605
Test name
Test status
Simulation time 664102718 ps
CPU time 3.69 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:30 PM PDT 24
Peak memory 225560 kb
Host smart-9d8a3581-e763-46ad-985b-5c906ade81cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086085215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3086085215
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1276764749
Short name T325
Test name
Test status
Simulation time 14476377 ps
CPU time 0.81 seconds
Started Jun 24 05:13:28 PM PDT 24
Finished Jun 24 05:13:30 PM PDT 24
Peak memory 207504 kb
Host smart-02215d02-f1fa-4b2c-9006-f3642e2fc6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276764749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1276764749
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1517094441
Short name T277
Test name
Test status
Simulation time 16234501151 ps
CPU time 131.79 seconds
Started Jun 24 05:13:27 PM PDT 24
Finished Jun 24 05:15:40 PM PDT 24
Peak memory 251164 kb
Host smart-dd4e93a9-ff84-4d48-bd64-4ea55bcf3b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517094441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1517094441
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2420755028
Short name T645
Test name
Test status
Simulation time 2308844080 ps
CPU time 33.07 seconds
Started Jun 24 05:13:28 PM PDT 24
Finished Jun 24 05:14:01 PM PDT 24
Peak memory 249720 kb
Host smart-a6c576fb-b755-4cf3-b618-d7c859760943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420755028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2420755028
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.913722476
Short name T202
Test name
Test status
Simulation time 2575041653 ps
CPU time 49.57 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:14:16 PM PDT 24
Peak memory 250288 kb
Host smart-396f41fb-bdd9-4acf-9a19-a452616f44fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913722476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.913722476
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1174980154
Short name T609
Test name
Test status
Simulation time 675656225 ps
CPU time 4.2 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:31 PM PDT 24
Peak memory 236408 kb
Host smart-38866862-70bb-4a53-b7aa-d396ec59344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174980154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1174980154
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2938330258
Short name T677
Test name
Test status
Simulation time 99644288 ps
CPU time 3.17 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:29 PM PDT 24
Peak memory 233632 kb
Host smart-d2d07cb6-dcf3-4e97-9cf3-55d08bff30d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938330258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2938330258
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1138306951
Short name T716
Test name
Test status
Simulation time 33310500481 ps
CPU time 64.62 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:14:29 PM PDT 24
Peak memory 241964 kb
Host smart-fc12c0b7-587f-4147-87eb-9e3d10252a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138306951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1138306951
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.571462203
Short name T581
Test name
Test status
Simulation time 3071432730 ps
CPU time 9.36 seconds
Started Jun 24 05:13:26 PM PDT 24
Finished Jun 24 05:13:37 PM PDT 24
Peak memory 233792 kb
Host smart-10f1be40-b0d7-4c33-92a3-939651c061f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571462203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.571462203
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2198568448
Short name T374
Test name
Test status
Simulation time 245860989 ps
CPU time 3.63 seconds
Started Jun 24 05:13:27 PM PDT 24
Finished Jun 24 05:13:32 PM PDT 24
Peak memory 225436 kb
Host smart-01e72d27-915f-4df2-969c-2b7a333fb674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198568448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2198568448
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3106939164
Short name T761
Test name
Test status
Simulation time 299052220 ps
CPU time 5.79 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:13:31 PM PDT 24
Peak memory 221744 kb
Host smart-6fd981c9-1128-46a7-b3bb-b9f685506686
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106939164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3106939164
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1850805336
Short name T924
Test name
Test status
Simulation time 109352828573 ps
CPU time 501.66 seconds
Started Jun 24 05:13:26 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 256892 kb
Host smart-a19c311e-a34b-4568-9731-612cd3694373
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850805336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1850805336
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2828489827
Short name T328
Test name
Test status
Simulation time 8233955011 ps
CPU time 40.11 seconds
Started Jun 24 05:13:26 PM PDT 24
Finished Jun 24 05:14:08 PM PDT 24
Peak memory 221320 kb
Host smart-5496b940-da10-4fac-a695-b59f5ab5ba00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828489827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2828489827
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4044403893
Short name T583
Test name
Test status
Simulation time 1137429837 ps
CPU time 3.55 seconds
Started Jun 24 05:13:25 PM PDT 24
Finished Jun 24 05:13:30 PM PDT 24
Peak memory 217172 kb
Host smart-04251481-bbd7-4743-892e-f4ef4ae537f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044403893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4044403893
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4126967377
Short name T973
Test name
Test status
Simulation time 410723772 ps
CPU time 2.32 seconds
Started Jun 24 05:13:28 PM PDT 24
Finished Jun 24 05:13:31 PM PDT 24
Peak memory 217464 kb
Host smart-15f83827-eb83-4c60-8796-fe53e0f47846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126967377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4126967377
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1315637419
Short name T511
Test name
Test status
Simulation time 30271393 ps
CPU time 0.82 seconds
Started Jun 24 05:13:28 PM PDT 24
Finished Jun 24 05:13:30 PM PDT 24
Peak memory 206864 kb
Host smart-5be4638b-4f08-4b5e-93ef-aeabe797f9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315637419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1315637419
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1656528494
Short name T929
Test name
Test status
Simulation time 2880763415 ps
CPU time 7.38 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:13:32 PM PDT 24
Peak memory 225672 kb
Host smart-b22d2b0f-d43a-4a7c-9fe5-47a8c48ecfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656528494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1656528494
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1494320989
Short name T577
Test name
Test status
Simulation time 21607360 ps
CPU time 0.74 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:37 PM PDT 24
Peak memory 206252 kb
Host smart-4160480f-b2d3-42ed-b8f3-c0e1c50cbdc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494320989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
494320989
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2503215897
Short name T510
Test name
Test status
Simulation time 2946657748 ps
CPU time 5.74 seconds
Started Jun 24 05:10:35 PM PDT 24
Finished Jun 24 05:10:43 PM PDT 24
Peak memory 225648 kb
Host smart-664be272-5439-4abb-892e-d7143bbd8594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503215897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2503215897
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3180802822
Short name T370
Test name
Test status
Simulation time 19384912 ps
CPU time 0.84 seconds
Started Jun 24 05:10:27 PM PDT 24
Finished Jun 24 05:10:29 PM PDT 24
Peak memory 207480 kb
Host smart-a302bdd6-969c-4ccb-83e4-4c3b12337798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180802822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3180802822
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4178631868
Short name T555
Test name
Test status
Simulation time 12293749 ps
CPU time 0.83 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:37 PM PDT 24
Peak memory 216820 kb
Host smart-4a826897-c1af-421a-b1ba-0f07578dcba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178631868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4178631868
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.619076055
Short name T495
Test name
Test status
Simulation time 2886272303 ps
CPU time 15.7 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:52 PM PDT 24
Peak memory 220528 kb
Host smart-0fc6d1bb-248f-43cf-ac5b-b7720e5aa576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619076055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.619076055
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3409157688
Short name T206
Test name
Test status
Simulation time 78755454896 ps
CPU time 319.79 seconds
Started Jun 24 05:10:32 PM PDT 24
Finished Jun 24 05:15:53 PM PDT 24
Peak memory 254416 kb
Host smart-8381578c-7820-402e-a471-264e1128a44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409157688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3409157688
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2688351169
Short name T572
Test name
Test status
Simulation time 505598087 ps
CPU time 2.86 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:39 PM PDT 24
Peak memory 225548 kb
Host smart-3e8fa5c5-a708-4f50-baf3-a674597a39aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688351169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2688351169
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3574252113
Short name T545
Test name
Test status
Simulation time 1609753603 ps
CPU time 7.2 seconds
Started Jun 24 05:10:32 PM PDT 24
Finished Jun 24 05:10:39 PM PDT 24
Peak memory 225568 kb
Host smart-f98374d2-4034-47c4-940e-6280d2208b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574252113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3574252113
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4252463971
Short name T302
Test name
Test status
Simulation time 976652287 ps
CPU time 11.84 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:10:47 PM PDT 24
Peak memory 225456 kb
Host smart-c2b016ce-3ef6-4332-a125-434df323a327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252463971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4252463971
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3836303534
Short name T44
Test name
Test status
Simulation time 88014018 ps
CPU time 1.11 seconds
Started Jun 24 05:10:26 PM PDT 24
Finished Jun 24 05:10:28 PM PDT 24
Peak memory 217848 kb
Host smart-95963164-d77b-44e3-b202-a23f5836af87
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836303534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3836303534
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2647413154
Short name T582
Test name
Test status
Simulation time 942538274 ps
CPU time 3.76 seconds
Started Jun 24 05:10:37 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 225548 kb
Host smart-418826f3-a09d-4031-8299-e7212147e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647413154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2647413154
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.88273684
Short name T203
Test name
Test status
Simulation time 593585036 ps
CPU time 8.81 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:10:45 PM PDT 24
Peak memory 225572 kb
Host smart-0f0d29e4-9f9f-4ffd-9555-a81eafe5e126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88273684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.88273684
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2344049140
Short name T563
Test name
Test status
Simulation time 710482834 ps
CPU time 3.48 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:39 PM PDT 24
Peak memory 223624 kb
Host smart-d6d7382f-b87d-45e8-9e18-4c8775a33581
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2344049140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2344049140
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.740652243
Short name T75
Test name
Test status
Simulation time 169332001 ps
CPU time 1.09 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:38 PM PDT 24
Peak memory 236620 kb
Host smart-70f7ea28-e788-4733-8bae-50969125b9d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740652243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.740652243
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3695696905
Short name T161
Test name
Test status
Simulation time 8453295156 ps
CPU time 11.81 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:48 PM PDT 24
Peak memory 225632 kb
Host smart-b310df38-f6f5-43d7-975b-de626b7b0be4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695696905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3695696905
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.4039700421
Short name T290
Test name
Test status
Simulation time 1067504240 ps
CPU time 5.63 seconds
Started Jun 24 05:10:28 PM PDT 24
Finished Jun 24 05:10:34 PM PDT 24
Peak memory 217344 kb
Host smart-d752fdb1-b4df-4592-9a2c-4ba74a472a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039700421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.4039700421
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.730306640
Short name T305
Test name
Test status
Simulation time 13938410809 ps
CPU time 10.95 seconds
Started Jun 24 05:10:29 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 217448 kb
Host smart-61b86b68-75e9-4f0b-9e8a-a53a224a1832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730306640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.730306640
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3469935184
Short name T362
Test name
Test status
Simulation time 996649405 ps
CPU time 2.36 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:38 PM PDT 24
Peak memory 217300 kb
Host smart-8259fc92-65fc-4a13-8f0e-8436297da03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469935184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3469935184
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2474403547
Short name T610
Test name
Test status
Simulation time 18370115 ps
CPU time 0.75 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:38 PM PDT 24
Peak memory 206780 kb
Host smart-e7f39505-beab-4504-9480-1c8a3261fc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474403547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2474403547
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2499675200
Short name T390
Test name
Test status
Simulation time 2134849009 ps
CPU time 4.69 seconds
Started Jun 24 05:10:35 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 225484 kb
Host smart-3999dc17-7b6e-4e88-912c-939617579b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499675200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2499675200
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2889659943
Short name T481
Test name
Test status
Simulation time 42665184 ps
CPU time 0.71 seconds
Started Jun 24 05:13:33 PM PDT 24
Finished Jun 24 05:13:35 PM PDT 24
Peak memory 206544 kb
Host smart-5f8b8db9-a856-4119-b25c-f126e7e1f2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889659943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2889659943
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2915137912
Short name T813
Test name
Test status
Simulation time 254466928 ps
CPU time 4.18 seconds
Started Jun 24 05:13:34 PM PDT 24
Finished Jun 24 05:13:40 PM PDT 24
Peak memory 233604 kb
Host smart-a4a4857c-d762-4ceb-acdb-0b695a5d7f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915137912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2915137912
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3109722248
Short name T704
Test name
Test status
Simulation time 12911161 ps
CPU time 0.75 seconds
Started Jun 24 05:13:24 PM PDT 24
Finished Jun 24 05:13:25 PM PDT 24
Peak memory 207452 kb
Host smart-9dc5e1f6-c364-435a-a8b1-f6bc3e56990b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109722248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3109722248
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1000765140
Short name T828
Test name
Test status
Simulation time 2764109845 ps
CPU time 32.4 seconds
Started Jun 24 05:13:34 PM PDT 24
Finished Jun 24 05:14:07 PM PDT 24
Peak memory 251280 kb
Host smart-1aad4e84-729f-4826-8a14-e13c5d084e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000765140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1000765140
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3481076575
Short name T186
Test name
Test status
Simulation time 3377495301 ps
CPU time 55.39 seconds
Started Jun 24 05:13:35 PM PDT 24
Finished Jun 24 05:14:31 PM PDT 24
Peak memory 256668 kb
Host smart-2dc6d073-5347-4e54-b4c6-170e07fb841d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481076575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3481076575
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.606879273
Short name T648
Test name
Test status
Simulation time 3452066238 ps
CPU time 14.73 seconds
Started Jun 24 05:13:35 PM PDT 24
Finished Jun 24 05:13:51 PM PDT 24
Peak memory 236256 kb
Host smart-4ea1c19f-a35b-41dd-920c-df32b8b17442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606879273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.606879273
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1060897478
Short name T900
Test name
Test status
Simulation time 401097514 ps
CPU time 5.52 seconds
Started Jun 24 05:13:34 PM PDT 24
Finished Jun 24 05:13:41 PM PDT 24
Peak memory 233676 kb
Host smart-bc9be9bf-986d-43c4-9bde-47c1065b72f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060897478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1060897478
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.980531095
Short name T681
Test name
Test status
Simulation time 14118360543 ps
CPU time 35.7 seconds
Started Jun 24 05:13:31 PM PDT 24
Finished Jun 24 05:14:08 PM PDT 24
Peak memory 225624 kb
Host smart-6af8ad19-0fe3-499a-bebb-c9c47e403f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980531095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.980531095
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.266577647
Short name T532
Test name
Test status
Simulation time 883652275 ps
CPU time 4.99 seconds
Started Jun 24 05:13:33 PM PDT 24
Finished Jun 24 05:13:39 PM PDT 24
Peak memory 233744 kb
Host smart-0a0887c2-582f-46cc-861d-8ed3ac6edb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266577647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.266577647
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2661722584
Short name T823
Test name
Test status
Simulation time 6433347871 ps
CPU time 9.43 seconds
Started Jun 24 05:13:35 PM PDT 24
Finished Jun 24 05:13:45 PM PDT 24
Peak memory 233876 kb
Host smart-15e5c0d2-4c97-4b2e-893e-90383433336d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661722584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2661722584
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3326439721
Short name T892
Test name
Test status
Simulation time 1352369059 ps
CPU time 5 seconds
Started Jun 24 05:13:35 PM PDT 24
Finished Jun 24 05:13:41 PM PDT 24
Peak memory 223388 kb
Host smart-d047f45a-e566-4760-935f-f954f2bf0b4e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3326439721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3326439721
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1623855565
Short name T779
Test name
Test status
Simulation time 45558769 ps
CPU time 0.94 seconds
Started Jun 24 05:13:34 PM PDT 24
Finished Jun 24 05:13:37 PM PDT 24
Peak memory 206884 kb
Host smart-1c704b87-a158-48bf-88ad-99ee32f5bddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623855565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1623855565
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.430266608
Short name T927
Test name
Test status
Simulation time 1204718907 ps
CPU time 18.68 seconds
Started Jun 24 05:13:27 PM PDT 24
Finished Jun 24 05:13:47 PM PDT 24
Peak memory 217632 kb
Host smart-69e2d524-f876-4146-95d7-8da493d90737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430266608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.430266608
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1962194264
Short name T524
Test name
Test status
Simulation time 2621065528 ps
CPU time 9.79 seconds
Started Jun 24 05:13:23 PM PDT 24
Finished Jun 24 05:13:33 PM PDT 24
Peak memory 217488 kb
Host smart-2eec99de-be03-486e-9081-0c360d1ec04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962194264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1962194264
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1316742608
Short name T388
Test name
Test status
Simulation time 114277193 ps
CPU time 1.79 seconds
Started Jun 24 05:13:26 PM PDT 24
Finished Jun 24 05:13:29 PM PDT 24
Peak memory 217360 kb
Host smart-0e44d8bd-330b-49e2-80c1-749f84e4ce97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316742608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1316742608
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1350752295
Short name T300
Test name
Test status
Simulation time 304938095 ps
CPU time 0.8 seconds
Started Jun 24 05:13:27 PM PDT 24
Finished Jun 24 05:13:29 PM PDT 24
Peak memory 207044 kb
Host smart-c5a08a7a-5733-40d3-a24c-b59ee658a392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350752295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1350752295
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2746975320
Short name T747
Test name
Test status
Simulation time 430093467 ps
CPU time 2.78 seconds
Started Jun 24 05:13:34 PM PDT 24
Finished Jun 24 05:13:38 PM PDT 24
Peak memory 225516 kb
Host smart-a6e7774a-28aa-4ef5-a16f-98b74507e6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746975320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2746975320
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3875605596
Short name T769
Test name
Test status
Simulation time 14983977 ps
CPU time 0.71 seconds
Started Jun 24 05:13:44 PM PDT 24
Finished Jun 24 05:13:46 PM PDT 24
Peak memory 206600 kb
Host smart-97c04354-cdd9-4786-ba87-12dc968bd35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875605596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3875605596
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4074600565
Short name T530
Test name
Test status
Simulation time 2103584586 ps
CPU time 18.83 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:14:07 PM PDT 24
Peak memory 225548 kb
Host smart-a8206f5a-0bcb-4f01-bca1-a6d9a847eefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074600565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4074600565
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.748579244
Short name T756
Test name
Test status
Simulation time 26757124 ps
CPU time 0.77 seconds
Started Jun 24 05:13:32 PM PDT 24
Finished Jun 24 05:13:33 PM PDT 24
Peak memory 207468 kb
Host smart-b7ade38c-fd40-4914-8b4f-bd1c0887d38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748579244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.748579244
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3501833749
Short name T228
Test name
Test status
Simulation time 64779736809 ps
CPU time 473.29 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:21:44 PM PDT 24
Peak memory 263464 kb
Host smart-f8840a59-63d6-4ffa-b30d-1f53a9f1db24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501833749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3501833749
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1372974205
Short name T130
Test name
Test status
Simulation time 37795096120 ps
CPU time 389.64 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:20:19 PM PDT 24
Peak memory 253556 kb
Host smart-5ace1084-b20f-4870-b609-24b9ba74b958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372974205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1372974205
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2252375685
Short name T265
Test name
Test status
Simulation time 38574314331 ps
CPU time 388.32 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:20:18 PM PDT 24
Peak memory 258500 kb
Host smart-c92d1fba-6011-4c4e-85f8-36114ce9bc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252375685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2252375685
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3926091702
Short name T446
Test name
Test status
Simulation time 573684889 ps
CPU time 5.14 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:13:56 PM PDT 24
Peak memory 233644 kb
Host smart-9cb78dbf-ff91-41f8-960a-313a0885d0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926091702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3926091702
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.691134063
Short name T410
Test name
Test status
Simulation time 5182122273 ps
CPU time 18.31 seconds
Started Jun 24 05:13:46 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 233900 kb
Host smart-8166f6f7-114e-4b8a-a9b0-3798685c3726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691134063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.691134063
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3021186105
Short name T230
Test name
Test status
Simulation time 9109477160 ps
CPU time 22.82 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:14:12 PM PDT 24
Peak memory 233788 kb
Host smart-8434cbdb-4aca-4de8-b645-acbcb4c82057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021186105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3021186105
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4227192857
Short name T717
Test name
Test status
Simulation time 1163623065 ps
CPU time 2.18 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:13:51 PM PDT 24
Peak memory 223988 kb
Host smart-f94ee837-0f5a-425b-bd7b-59c26e5b737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227192857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4227192857
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.994288634
Short name T575
Test name
Test status
Simulation time 406332774 ps
CPU time 4.4 seconds
Started Jun 24 05:13:51 PM PDT 24
Finished Jun 24 05:13:59 PM PDT 24
Peak memory 225560 kb
Host smart-82cde74b-0b71-4ae8-80f3-3d7f1046fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994288634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.994288634
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4220250978
Short name T140
Test name
Test status
Simulation time 5895731464 ps
CPU time 13.49 seconds
Started Jun 24 05:13:49 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 224112 kb
Host smart-535ea8c5-5875-4dea-97de-dd384ded5c05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4220250978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4220250978
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2675110977
Short name T569
Test name
Test status
Simulation time 6061058390 ps
CPU time 26.32 seconds
Started Jun 24 05:13:34 PM PDT 24
Finished Jun 24 05:14:01 PM PDT 24
Peak memory 219004 kb
Host smart-3bd7a1ed-eea4-47fc-8eb9-b5a62c7081cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675110977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2675110977
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3493269918
Short name T352
Test name
Test status
Simulation time 40527528083 ps
CPU time 12.62 seconds
Started Jun 24 05:13:35 PM PDT 24
Finished Jun 24 05:13:49 PM PDT 24
Peak memory 217488 kb
Host smart-d3860f70-fba8-4470-8955-15e95714ad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493269918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3493269918
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4156553101
Short name T387
Test name
Test status
Simulation time 83849230 ps
CPU time 4.49 seconds
Started Jun 24 05:13:34 PM PDT 24
Finished Jun 24 05:13:39 PM PDT 24
Peak memory 217164 kb
Host smart-8e019390-b8b2-4120-8aad-b9fc3ba43324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156553101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4156553101
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2231276739
Short name T401
Test name
Test status
Simulation time 67467325 ps
CPU time 0.73 seconds
Started Jun 24 05:13:35 PM PDT 24
Finished Jun 24 05:13:37 PM PDT 24
Peak memory 206876 kb
Host smart-e9812f60-5ad9-4fe0-af24-76faedd60823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231276739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2231276739
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.943514860
Short name T435
Test name
Test status
Simulation time 1846730160 ps
CPU time 4.67 seconds
Started Jun 24 05:13:51 PM PDT 24
Finished Jun 24 05:13:59 PM PDT 24
Peak memory 233768 kb
Host smart-da0184f2-eab2-46b5-9f31-7defe4fe3991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943514860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.943514860
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3545502849
Short name T69
Test name
Test status
Simulation time 15131534 ps
CPU time 0.77 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:13:49 PM PDT 24
Peak memory 206168 kb
Host smart-1b4b769f-d0c3-4df0-a3d1-007feb3a7936
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545502849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3545502849
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.812977196
Short name T428
Test name
Test status
Simulation time 480234698 ps
CPU time 4.3 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:13:54 PM PDT 24
Peak memory 233752 kb
Host smart-5234cec4-c69e-4e03-8782-ccccc9f2620f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812977196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.812977196
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3736274648
Short name T466
Test name
Test status
Simulation time 15546619 ps
CPU time 0.77 seconds
Started Jun 24 05:13:46 PM PDT 24
Finished Jun 24 05:13:48 PM PDT 24
Peak memory 206448 kb
Host smart-c660cb89-4287-48ef-8136-da89f54d3b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736274648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3736274648
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.654816809
Short name T660
Test name
Test status
Simulation time 23776652635 ps
CPU time 77.05 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:15:07 PM PDT 24
Peak memory 258524 kb
Host smart-76900fe1-8fe5-441c-ba93-23af8894ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654816809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.654816809
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.189883739
Short name T259
Test name
Test status
Simulation time 30383763941 ps
CPU time 72.63 seconds
Started Jun 24 05:13:46 PM PDT 24
Finished Jun 24 05:15:00 PM PDT 24
Peak memory 242052 kb
Host smart-0c1cb916-9160-4b57-bb68-9f22b109bdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189883739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.189883739
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.162630335
Short name T689
Test name
Test status
Simulation time 18527787646 ps
CPU time 75.91 seconds
Started Jun 24 05:13:46 PM PDT 24
Finished Jun 24 05:15:03 PM PDT 24
Peak memory 254316 kb
Host smart-148aea78-cf12-42c1-886d-5278daba7d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162630335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.162630335
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.656083284
Short name T850
Test name
Test status
Simulation time 844964990 ps
CPU time 6.26 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:13:57 PM PDT 24
Peak memory 234872 kb
Host smart-a0e85edb-cd5f-43a1-b732-f2110601c47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656083284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.656083284
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.717209350
Short name T752
Test name
Test status
Simulation time 2061224859 ps
CPU time 3.58 seconds
Started Jun 24 05:13:46 PM PDT 24
Finished Jun 24 05:13:50 PM PDT 24
Peak memory 225424 kb
Host smart-888ef98d-c73f-4ecc-bc68-1de1f1cbf8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717209350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.717209350
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4275098700
Short name T463
Test name
Test status
Simulation time 30931595 ps
CPU time 1.98 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:13:51 PM PDT 24
Peak memory 224172 kb
Host smart-ac6d1ff5-564a-43ec-9fa7-bef19bb1be7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275098700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4275098700
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1620588683
Short name T678
Test name
Test status
Simulation time 1365625835 ps
CPU time 5.94 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:13:56 PM PDT 24
Peak memory 233696 kb
Host smart-81c42a36-5506-4708-8264-27642ab410b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620588683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1620588683
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.373267420
Short name T838
Test name
Test status
Simulation time 3053550951 ps
CPU time 11.11 seconds
Started Jun 24 05:13:49 PM PDT 24
Finished Jun 24 05:14:03 PM PDT 24
Peak memory 233764 kb
Host smart-58decda3-8c63-40dd-8074-99cb84b11ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373267420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.373267420
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2201423316
Short name T375
Test name
Test status
Simulation time 208578040 ps
CPU time 4 seconds
Started Jun 24 05:13:44 PM PDT 24
Finished Jun 24 05:13:49 PM PDT 24
Peak memory 224024 kb
Host smart-b5a02f53-cf1a-44ae-b702-de8830b2ca37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2201423316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2201423316
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1069729872
Short name T579
Test name
Test status
Simulation time 32015052708 ps
CPU time 60.31 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:14:50 PM PDT 24
Peak memory 250324 kb
Host smart-a2c3be9b-e6d3-4c0a-8504-fe90c3db7d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069729872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1069729872
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2017740056
Short name T766
Test name
Test status
Simulation time 7270453154 ps
CPU time 38.43 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:14:27 PM PDT 24
Peak memory 217416 kb
Host smart-bf615baf-fb2d-4f2e-83ae-aebd6526b60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017740056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2017740056
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1572264128
Short name T597
Test name
Test status
Simulation time 1319579695 ps
CPU time 3.94 seconds
Started Jun 24 05:13:45 PM PDT 24
Finished Jun 24 05:13:50 PM PDT 24
Peak memory 217312 kb
Host smart-f75abc75-2b10-4382-ae14-82543614de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572264128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1572264128
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3930488883
Short name T480
Test name
Test status
Simulation time 21335117 ps
CPU time 0.93 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:13:52 PM PDT 24
Peak memory 208056 kb
Host smart-d2bef05d-10fe-443d-bb6c-4ca997b9739a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930488883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3930488883
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2782953444
Short name T65
Test name
Test status
Simulation time 90256934 ps
CPU time 1.02 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:13:52 PM PDT 24
Peak memory 206876 kb
Host smart-7075406f-375b-4d34-8e93-a989d32dfcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782953444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2782953444
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1884992548
Short name T668
Test name
Test status
Simulation time 25920723489 ps
CPU time 10.89 seconds
Started Jun 24 05:13:44 PM PDT 24
Finished Jun 24 05:13:56 PM PDT 24
Peak memory 233852 kb
Host smart-572495b4-e8bc-429d-bb1f-75baee92d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884992548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1884992548
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2371105426
Short name T841
Test name
Test status
Simulation time 28345099 ps
CPU time 0.75 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:14:00 PM PDT 24
Peak memory 205700 kb
Host smart-ca1acec7-c13a-4a15-9345-f15291f16065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371105426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2371105426
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2646145345
Short name T232
Test name
Test status
Simulation time 60011755 ps
CPU time 2.14 seconds
Started Jun 24 05:13:57 PM PDT 24
Finished Jun 24 05:14:01 PM PDT 24
Peak memory 225520 kb
Host smart-c5edeefe-7477-487c-8c73-d2f9bfb46d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646145345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2646145345
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1219659254
Short name T812
Test name
Test status
Simulation time 14126189 ps
CPU time 0.81 seconds
Started Jun 24 05:13:47 PM PDT 24
Finished Jun 24 05:13:50 PM PDT 24
Peak memory 207800 kb
Host smart-82d49b61-6751-4d18-bc10-2a2833a77569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219659254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1219659254
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2633413814
Short name T693
Test name
Test status
Simulation time 4573456225 ps
CPU time 32.91 seconds
Started Jun 24 05:13:53 PM PDT 24
Finished Jun 24 05:14:28 PM PDT 24
Peak memory 242068 kb
Host smart-8778226d-74ec-4804-9fb0-946c9b3057ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633413814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2633413814
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3803032085
Short name T614
Test name
Test status
Simulation time 6025754541 ps
CPU time 89.18 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:15:30 PM PDT 24
Peak memory 261764 kb
Host smart-4730b5d5-8551-4aa2-a0d3-98e9b343755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803032085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3803032085
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1989825953
Short name T637
Test name
Test status
Simulation time 36495573173 ps
CPU time 309.26 seconds
Started Jun 24 05:13:54 PM PDT 24
Finished Jun 24 05:19:05 PM PDT 24
Peak memory 250200 kb
Host smart-8883e6eb-d046-45dd-a9af-3a48c28e3e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989825953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1989825953
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.849843513
Short name T518
Test name
Test status
Simulation time 3136628550 ps
CPU time 24.35 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:14:25 PM PDT 24
Peak memory 244048 kb
Host smart-2bec4cad-8719-4be8-82c2-fb5b4bccec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849843513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.849843513
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3564499205
Short name T908
Test name
Test status
Simulation time 466250765 ps
CPU time 2.52 seconds
Started Jun 24 05:13:54 PM PDT 24
Finished Jun 24 05:13:58 PM PDT 24
Peak memory 227620 kb
Host smart-0f247548-2dcb-4079-a04a-0a369422b968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564499205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3564499205
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.20985529
Short name T534
Test name
Test status
Simulation time 5134674130 ps
CPU time 48.04 seconds
Started Jun 24 05:13:57 PM PDT 24
Finished Jun 24 05:14:47 PM PDT 24
Peak memory 232732 kb
Host smart-9d4010d9-4a5e-4687-a284-1adb0234780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20985529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.20985529
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2378397368
Short name T573
Test name
Test status
Simulation time 633297761 ps
CPU time 3.96 seconds
Started Jun 24 05:13:59 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 225552 kb
Host smart-c787d2f3-c3f3-4283-bd9b-de63c309f918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378397368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2378397368
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1583852455
Short name T215
Test name
Test status
Simulation time 859964377 ps
CPU time 4.44 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 241344 kb
Host smart-442f5fe9-a458-4b17-8439-5a7fe6d7f822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583852455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1583852455
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1626527381
Short name T606
Test name
Test status
Simulation time 142249292 ps
CPU time 4 seconds
Started Jun 24 05:14:00 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 224064 kb
Host smart-b1ed36c7-7624-492e-be6b-a7526afc2df2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1626527381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1626527381
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2214641620
Short name T272
Test name
Test status
Simulation time 60189070456 ps
CPU time 581.37 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:23:40 PM PDT 24
Peak memory 269968 kb
Host smart-ec8b900a-4003-44bc-a57b-0ff08210df67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214641620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2214641620
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2586375249
Short name T531
Test name
Test status
Simulation time 17689609615 ps
CPU time 12.08 seconds
Started Jun 24 05:13:46 PM PDT 24
Finished Jun 24 05:13:59 PM PDT 24
Peak memory 217756 kb
Host smart-ba0002aa-c30d-4764-8b1c-859e746b6ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586375249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2586375249
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3260995635
Short name T383
Test name
Test status
Simulation time 983530899 ps
CPU time 6.16 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:13:57 PM PDT 24
Peak memory 217368 kb
Host smart-fd330b8d-c785-4cd6-bc9d-f8cb6028f844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260995635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3260995635
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1299086229
Short name T642
Test name
Test status
Simulation time 359112433 ps
CPU time 1.05 seconds
Started Jun 24 05:13:49 PM PDT 24
Finished Jun 24 05:13:53 PM PDT 24
Peak memory 208692 kb
Host smart-82e728a6-039f-4072-bc26-078a31af1f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299086229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1299086229
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4112591659
Short name T63
Test name
Test status
Simulation time 32094485 ps
CPU time 0.73 seconds
Started Jun 24 05:13:48 PM PDT 24
Finished Jun 24 05:13:52 PM PDT 24
Peak memory 206848 kb
Host smart-e6d3d6e6-af56-493f-aa6a-2bef28c6c97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112591659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4112591659
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.984079939
Short name T35
Test name
Test status
Simulation time 1060728749 ps
CPU time 3.76 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:14:04 PM PDT 24
Peak memory 225536 kb
Host smart-37e00f98-a241-4ae5-bd24-69382fe358b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984079939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.984079939
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1952342504
Short name T650
Test name
Test status
Simulation time 27218294 ps
CPU time 0.74 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:14:00 PM PDT 24
Peak memory 206240 kb
Host smart-5a5d9cea-6681-4574-8893-79ff21271daf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952342504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1952342504
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2454582098
Short name T507
Test name
Test status
Simulation time 2355075014 ps
CPU time 16.84 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:14:15 PM PDT 24
Peak memory 233840 kb
Host smart-46823ca1-d486-49b2-aa9a-dcc5baae8d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454582098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2454582098
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3991736945
Short name T492
Test name
Test status
Simulation time 71249974 ps
CPU time 0.79 seconds
Started Jun 24 05:13:57 PM PDT 24
Finished Jun 24 05:14:00 PM PDT 24
Peak memory 207420 kb
Host smart-71fc1b2e-781d-403f-b124-b3d477519eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991736945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3991736945
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1407487027
Short name T269
Test name
Test status
Simulation time 71004035491 ps
CPU time 471.73 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:21:49 PM PDT 24
Peak memory 258448 kb
Host smart-37331689-36b2-4d17-865f-5f6d1a1acb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407487027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1407487027
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.213877744
Short name T916
Test name
Test status
Simulation time 2010482694 ps
CPU time 21.74 seconds
Started Jun 24 05:14:00 PM PDT 24
Finished Jun 24 05:14:23 PM PDT 24
Peak memory 222972 kb
Host smart-d9d6910e-07f8-40e5-b9a3-f011574f654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213877744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.213877744
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1898062052
Short name T661
Test name
Test status
Simulation time 17482553922 ps
CPU time 78.54 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:15:16 PM PDT 24
Peak memory 239632 kb
Host smart-a25dfa98-95b0-451d-a1db-06aa498e8193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898062052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1898062052
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2857969850
Short name T209
Test name
Test status
Simulation time 315852331 ps
CPU time 6.64 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 250136 kb
Host smart-02695bc1-4a73-40aa-ae15-df7c7e53bc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857969850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2857969850
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1619747453
Short name T701
Test name
Test status
Simulation time 830786806 ps
CPU time 6.57 seconds
Started Jun 24 05:13:57 PM PDT 24
Finished Jun 24 05:14:06 PM PDT 24
Peak memory 225504 kb
Host smart-051e128d-6bb4-4e0b-bf5d-69799be37f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619747453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1619747453
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2759965451
Short name T726
Test name
Test status
Simulation time 1054453960 ps
CPU time 16.48 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:14:14 PM PDT 24
Peak memory 225488 kb
Host smart-ac821bec-69ec-4ed2-880d-2b6bfccf2a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759965451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2759965451
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3183136117
Short name T663
Test name
Test status
Simulation time 239419190 ps
CPU time 2.84 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:14:02 PM PDT 24
Peak memory 225500 kb
Host smart-901d2acc-288e-4c00-bc56-4b78c9398a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183136117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3183136117
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4138671410
Short name T498
Test name
Test status
Simulation time 38141674635 ps
CPU time 28.28 seconds
Started Jun 24 05:14:01 PM PDT 24
Finished Jun 24 05:14:30 PM PDT 24
Peak memory 233884 kb
Host smart-d8c801e4-4831-40ef-8181-8bf5abab49b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138671410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4138671410
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.809596397
Short name T413
Test name
Test status
Simulation time 280861433 ps
CPU time 5.33 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:14:02 PM PDT 24
Peak memory 222928 kb
Host smart-9da306ce-b7b4-48ef-b6a0-015d50a06a28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809596397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.809596397
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.92240254
Short name T961
Test name
Test status
Simulation time 43690143102 ps
CPU time 239.5 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:18:00 PM PDT 24
Peak memory 258524 kb
Host smart-5a7e7ca2-98ff-4abf-b393-36176c9237a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92240254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress
_all.92240254
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3526527411
Short name T857
Test name
Test status
Simulation time 2887327764 ps
CPU time 31.71 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:14:32 PM PDT 24
Peak memory 221796 kb
Host smart-fdc9c1e7-a793-4770-8e4e-0fd6e07635f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526527411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3526527411
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1941510463
Short name T359
Test name
Test status
Simulation time 831756663 ps
CPU time 3.42 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:14:01 PM PDT 24
Peak memory 217296 kb
Host smart-ae1f9333-f8cd-43d2-9f8a-bf44ce4eb533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941510463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1941510463
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3379495293
Short name T317
Test name
Test status
Simulation time 75246839 ps
CPU time 3.44 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:14:04 PM PDT 24
Peak memory 217480 kb
Host smart-4c7ed0ff-cc26-47e7-bd2c-e120ef1065d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379495293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3379495293
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4048092367
Short name T77
Test name
Test status
Simulation time 11246117 ps
CPU time 0.7 seconds
Started Jun 24 05:13:54 PM PDT 24
Finished Jun 24 05:13:56 PM PDT 24
Peak memory 206528 kb
Host smart-08f8c6ce-0009-4fa0-830d-7c2297c6ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048092367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4048092367
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3892140439
Short name T801
Test name
Test status
Simulation time 295518781 ps
CPU time 6.16 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 240676 kb
Host smart-c039feb3-e3f0-4785-beee-dd66e3d20833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892140439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3892140439
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2988395454
Short name T552
Test name
Test status
Simulation time 25946685 ps
CPU time 0.73 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:07 PM PDT 24
Peak memory 206260 kb
Host smart-870f7541-edc2-4196-8e3c-26ec81a2757c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988395454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2988395454
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3810435944
Short name T608
Test name
Test status
Simulation time 639446849 ps
CPU time 7.43 seconds
Started Jun 24 05:14:03 PM PDT 24
Finished Jun 24 05:14:12 PM PDT 24
Peak memory 233728 kb
Host smart-160d2a3c-67bd-4140-9422-a0a010be3e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810435944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3810435944
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3843601605
Short name T329
Test name
Test status
Simulation time 43492662 ps
CPU time 0.78 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:13:57 PM PDT 24
Peak memory 207404 kb
Host smart-44a47fbf-9ec7-4bfc-a6d9-8f1c952049f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843601605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3843601605
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3074777706
Short name T778
Test name
Test status
Simulation time 5566956616 ps
CPU time 33.56 seconds
Started Jun 24 05:14:00 PM PDT 24
Finished Jun 24 05:14:35 PM PDT 24
Peak memory 252264 kb
Host smart-1d606a08-0642-474a-8165-f5fa8c93e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074777706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3074777706
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.1693524619
Short name T827
Test name
Test status
Simulation time 237507760962 ps
CPU time 275.34 seconds
Started Jun 24 05:14:06 PM PDT 24
Finished Jun 24 05:18:42 PM PDT 24
Peak memory 265636 kb
Host smart-3f58441e-175f-498c-892f-8cf2921cecb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693524619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.1693524619
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1112917009
Short name T110
Test name
Test status
Simulation time 5338492609 ps
CPU time 44.59 seconds
Started Jun 24 05:14:03 PM PDT 24
Finished Jun 24 05:14:49 PM PDT 24
Peak memory 252780 kb
Host smart-a9395fd2-0e57-41e7-902a-94fbc8ace31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112917009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1112917009
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3048199938
Short name T844
Test name
Test status
Simulation time 851128746 ps
CPU time 5.76 seconds
Started Jun 24 05:13:58 PM PDT 24
Finished Jun 24 05:14:06 PM PDT 24
Peak memory 233772 kb
Host smart-628b8412-74ab-4cc3-a6ff-6b5fc173982d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048199938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3048199938
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2317952046
Short name T251
Test name
Test status
Simulation time 1067125200 ps
CPU time 9.61 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:14:08 PM PDT 24
Peak memory 233600 kb
Host smart-00885bf6-4a45-432d-8fdc-ad67d402b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317952046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2317952046
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2088719484
Short name T623
Test name
Test status
Simulation time 852551549 ps
CPU time 4.04 seconds
Started Jun 24 05:14:01 PM PDT 24
Finished Jun 24 05:14:06 PM PDT 24
Peak memory 225420 kb
Host smart-e210d65d-bff6-4326-809e-3433bb294d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088719484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2088719484
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1073839729
Short name T210
Test name
Test status
Simulation time 291749361 ps
CPU time 5.63 seconds
Started Jun 24 05:13:59 PM PDT 24
Finished Jun 24 05:14:07 PM PDT 24
Peak memory 233704 kb
Host smart-2fdde5a4-16f6-401e-91a6-b2713cd6c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073839729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1073839729
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3163768492
Short name T356
Test name
Test status
Simulation time 685396803 ps
CPU time 5.55 seconds
Started Jun 24 05:14:05 PM PDT 24
Finished Jun 24 05:14:12 PM PDT 24
Peak memory 221560 kb
Host smart-4909adb7-915e-40c8-ae30-363fb9c1f4b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163768492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3163768492
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4126160219
Short name T760
Test name
Test status
Simulation time 37712406 ps
CPU time 1.01 seconds
Started Jun 24 05:14:05 PM PDT 24
Finished Jun 24 05:14:07 PM PDT 24
Peak memory 208160 kb
Host smart-cb5b28e4-19de-43e6-b1de-89e90264bc27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126160219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4126160219
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3002031142
Short name T346
Test name
Test status
Simulation time 1720999108 ps
CPU time 24.63 seconds
Started Jun 24 05:13:59 PM PDT 24
Finished Jun 24 05:14:26 PM PDT 24
Peak memory 217380 kb
Host smart-a898d865-a979-418a-8340-a749526ae6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002031142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3002031142
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3774003349
Short name T745
Test name
Test status
Simulation time 13365007301 ps
CPU time 17 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:14:16 PM PDT 24
Peak memory 217744 kb
Host smart-35f56130-b8a1-49b8-965d-83855b5b144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774003349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3774003349
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3066571868
Short name T835
Test name
Test status
Simulation time 546661647 ps
CPU time 1.43 seconds
Started Jun 24 05:13:56 PM PDT 24
Finished Jun 24 05:14:01 PM PDT 24
Peak memory 217596 kb
Host smart-3ae63e53-746b-4647-a37d-767b88726c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066571868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3066571868
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3275276061
Short name T461
Test name
Test status
Simulation time 88632153 ps
CPU time 0.83 seconds
Started Jun 24 05:13:55 PM PDT 24
Finished Jun 24 05:13:58 PM PDT 24
Peak memory 206856 kb
Host smart-383636bc-1e4b-4fb4-9df3-6ec24fdd1747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275276061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3275276061
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3653561774
Short name T213
Test name
Test status
Simulation time 190845656 ps
CPU time 2.96 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:08 PM PDT 24
Peak memory 225508 kb
Host smart-4dd57846-e820-45fe-9535-65eaf534a79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653561774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3653561774
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3620151917
Short name T746
Test name
Test status
Simulation time 34276484 ps
CPU time 0.69 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:12 PM PDT 24
Peak memory 206200 kb
Host smart-59607e84-5c78-4d22-a1b6-9082d2990435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620151917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3620151917
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3357859545
Short name T800
Test name
Test status
Simulation time 1197406127 ps
CPU time 3.75 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:10 PM PDT 24
Peak memory 233716 kb
Host smart-a8f75c68-1af3-4412-8de0-14c87a2a2d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357859545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3357859545
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1606569188
Short name T458
Test name
Test status
Simulation time 151587616 ps
CPU time 0.82 seconds
Started Jun 24 05:14:05 PM PDT 24
Finished Jun 24 05:14:07 PM PDT 24
Peak memory 207812 kb
Host smart-444ce14d-d9dc-4852-9974-87cca078f871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606569188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1606569188
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1529397922
Short name T181
Test name
Test status
Simulation time 565625304749 ps
CPU time 338.83 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:19:44 PM PDT 24
Peak memory 266540 kb
Host smart-4f11d2ce-5222-42b8-89a2-0153dd5c3a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529397922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1529397922
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1007848550
Short name T842
Test name
Test status
Simulation time 46191677592 ps
CPU time 87.3 seconds
Started Jun 24 05:14:02 PM PDT 24
Finished Jun 24 05:15:31 PM PDT 24
Peak memory 239996 kb
Host smart-a54a831f-6443-4d98-8197-c441b801d611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007848550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1007848550
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.485342261
Short name T174
Test name
Test status
Simulation time 49669602864 ps
CPU time 135.68 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:16:35 PM PDT 24
Peak memory 253848 kb
Host smart-ba67e54c-7681-44c1-98f3-f976ec54d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485342261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.485342261
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3460370119
Short name T48
Test name
Test status
Simulation time 2064522991 ps
CPU time 13.21 seconds
Started Jun 24 05:14:02 PM PDT 24
Finished Jun 24 05:14:16 PM PDT 24
Peak memory 241936 kb
Host smart-7a8e08b4-371b-404e-a677-d3af1bde5ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460370119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3460370119
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1470241108
Short name T655
Test name
Test status
Simulation time 4608960339 ps
CPU time 13.9 seconds
Started Jun 24 05:14:05 PM PDT 24
Finished Jun 24 05:14:20 PM PDT 24
Peak memory 225644 kb
Host smart-ea01cdeb-bbfc-4b4a-b731-d5a9b8335c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470241108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1470241108
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2915905078
Short name T27
Test name
Test status
Simulation time 8580222048 ps
CPU time 74.13 seconds
Started Jun 24 05:14:03 PM PDT 24
Finished Jun 24 05:15:19 PM PDT 24
Peak memory 241600 kb
Host smart-263e226d-92d3-4788-a3f6-77b332ed3240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915905078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2915905078
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.681631628
Short name T928
Test name
Test status
Simulation time 1313572804 ps
CPU time 9.21 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:15 PM PDT 24
Peak memory 225548 kb
Host smart-ae13fb8b-6a7e-43d5-b243-e5b0ade61274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681631628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.681631628
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.643149104
Short name T312
Test name
Test status
Simulation time 525639564 ps
CPU time 3.46 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:09 PM PDT 24
Peak memory 233752 kb
Host smart-a3c3805b-7792-4a9d-9958-21b2da34a8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643149104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.643149104
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1021953124
Short name T542
Test name
Test status
Simulation time 2892642502 ps
CPU time 5.94 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:11 PM PDT 24
Peak memory 219984 kb
Host smart-54bd62a3-bef6-48c8-a941-394ab6a4d5d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1021953124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1021953124
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.244032267
Short name T131
Test name
Test status
Simulation time 14380223518 ps
CPU time 182.41 seconds
Started Jun 24 05:14:13 PM PDT 24
Finished Jun 24 05:17:17 PM PDT 24
Peak memory 255036 kb
Host smart-158b9eb3-7168-4e6f-ad7e-b202ed07c61c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244032267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.244032267
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2541253138
Short name T805
Test name
Test status
Simulation time 1925383026 ps
CPU time 12.77 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:19 PM PDT 24
Peak memory 217368 kb
Host smart-10868314-77e6-4704-82a6-3d410f8ba35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541253138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2541253138
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2620360212
Short name T639
Test name
Test status
Simulation time 56882251125 ps
CPU time 14.65 seconds
Started Jun 24 05:14:03 PM PDT 24
Finished Jun 24 05:14:18 PM PDT 24
Peak memory 217328 kb
Host smart-603ad6c8-fbe2-4f0f-931d-dd4461cd48c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620360212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2620360212
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.858403535
Short name T792
Test name
Test status
Simulation time 414875924 ps
CPU time 2.09 seconds
Started Jun 24 05:14:03 PM PDT 24
Finished Jun 24 05:14:06 PM PDT 24
Peak memory 217232 kb
Host smart-947260a5-4471-4bd0-ad64-e731f80f591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858403535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.858403535
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1688230498
Short name T467
Test name
Test status
Simulation time 165210438 ps
CPU time 0.81 seconds
Started Jun 24 05:14:04 PM PDT 24
Finished Jun 24 05:14:06 PM PDT 24
Peak memory 206876 kb
Host smart-583e4968-88e4-4ab0-a900-1af61f7cb4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688230498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1688230498
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.37829998
Short name T368
Test name
Test status
Simulation time 56510795 ps
CPU time 2.4 seconds
Started Jun 24 05:14:02 PM PDT 24
Finished Jun 24 05:14:05 PM PDT 24
Peak memory 233656 kb
Host smart-af2f02c5-1a6d-4b22-a3cb-b0dc9ebec9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37829998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.37829998
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1899698552
Short name T363
Test name
Test status
Simulation time 14143762 ps
CPU time 0.74 seconds
Started Jun 24 05:14:10 PM PDT 24
Finished Jun 24 05:14:12 PM PDT 24
Peak memory 205620 kb
Host smart-7225baef-23dc-488f-847f-625a90107a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899698552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1899698552
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3335011809
Short name T429
Test name
Test status
Simulation time 2220097751 ps
CPU time 8.15 seconds
Started Jun 24 05:14:15 PM PDT 24
Finished Jun 24 05:14:24 PM PDT 24
Peak memory 233848 kb
Host smart-f6d8e981-c55a-470b-a5cb-d2e63aab595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335011809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3335011809
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.129292032
Short name T942
Test name
Test status
Simulation time 32585762 ps
CPU time 0.78 seconds
Started Jun 24 05:14:13 PM PDT 24
Finished Jun 24 05:14:15 PM PDT 24
Peak memory 207472 kb
Host smart-527db5d4-7ab3-4018-b5bb-d85f5144805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129292032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.129292032
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2601284482
Short name T464
Test name
Test status
Simulation time 62289743884 ps
CPU time 78.97 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:15:32 PM PDT 24
Peak memory 257384 kb
Host smart-facf8f74-0e24-44f7-9bff-f0ffab35e95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601284482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2601284482
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4205423899
Short name T649
Test name
Test status
Simulation time 5720784963 ps
CPU time 38.03 seconds
Started Jun 24 05:14:10 PM PDT 24
Finished Jun 24 05:14:48 PM PDT 24
Peak memory 225568 kb
Host smart-167e9277-bb15-41b6-af97-dfcbfd5cc43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205423899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4205423899
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2964083700
Short name T133
Test name
Test status
Simulation time 70820582053 ps
CPU time 281.8 seconds
Started Jun 24 05:14:15 PM PDT 24
Finished Jun 24 05:18:58 PM PDT 24
Peak memory 253844 kb
Host smart-5614b88c-2fc8-4154-a358-dce9da16c7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964083700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2964083700
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3082120571
Short name T283
Test name
Test status
Simulation time 250515548 ps
CPU time 9.49 seconds
Started Jun 24 05:14:19 PM PDT 24
Finished Jun 24 05:14:30 PM PDT 24
Peak memory 233280 kb
Host smart-5361fa51-bdb9-4294-b88b-133246f94208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082120571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3082120571
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3515152532
Short name T205
Test name
Test status
Simulation time 697370897 ps
CPU time 8.38 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:21 PM PDT 24
Peak memory 225500 kb
Host smart-96ead9c7-99ba-4948-bdf9-37d55cbd6b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515152532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3515152532
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3724697131
Short name T737
Test name
Test status
Simulation time 5710923557 ps
CPU time 21.66 seconds
Started Jun 24 05:14:10 PM PDT 24
Finished Jun 24 05:14:33 PM PDT 24
Peak memory 241580 kb
Host smart-be932086-83a8-40b6-8bf2-f73d79aa7800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724697131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3724697131
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1653978142
Short name T698
Test name
Test status
Simulation time 5343586168 ps
CPU time 7.34 seconds
Started Jun 24 05:14:12 PM PDT 24
Finished Jun 24 05:14:21 PM PDT 24
Peak memory 234044 kb
Host smart-54874910-1fcb-44c1-8103-e5e535f2480c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653978142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1653978142
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.361480349
Short name T725
Test name
Test status
Simulation time 10697171802 ps
CPU time 30.06 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:42 PM PDT 24
Peak memory 240304 kb
Host smart-483a2d10-4c03-42bf-ac31-88c9f822c70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361480349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.361480349
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.223100633
Short name T724
Test name
Test status
Simulation time 746527132 ps
CPU time 4.34 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:23 PM PDT 24
Peak memory 221252 kb
Host smart-7583ce52-b9d1-4671-a4ff-16a6df62528d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=223100633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.223100633
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.86902908
Short name T132
Test name
Test status
Simulation time 395418324914 ps
CPU time 1044.41 seconds
Started Jun 24 05:14:10 PM PDT 24
Finished Jun 24 05:31:36 PM PDT 24
Peak memory 274172 kb
Host smart-18b11d44-3a42-4528-8280-bec95292d24b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86902908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress
_all.86902908
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2775922401
Short name T350
Test name
Test status
Simulation time 10443975241 ps
CPU time 26.03 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:45 PM PDT 24
Peak memory 217536 kb
Host smart-c43e7e48-f550-48f3-ae3d-504ebfcbbdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775922401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2775922401
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2645704528
Short name T742
Test name
Test status
Simulation time 883769702 ps
CPU time 1.7 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:14 PM PDT 24
Peak memory 208836 kb
Host smart-c2592397-84a2-4113-ad08-a9d0576f6df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645704528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2645704528
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.43781254
Short name T631
Test name
Test status
Simulation time 371030648 ps
CPU time 1.26 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:14 PM PDT 24
Peak memory 208904 kb
Host smart-86311584-6f3d-4556-8716-e085aea87002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43781254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.43781254
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.410194549
Short name T84
Test name
Test status
Simulation time 85903290 ps
CPU time 0.79 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:14 PM PDT 24
Peak memory 206748 kb
Host smart-fbde0bf8-586f-4b62-a9f4-fdf1bd600b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410194549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.410194549
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3730928472
Short name T802
Test name
Test status
Simulation time 76800242 ps
CPU time 2.23 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:15 PM PDT 24
Peak memory 225212 kb
Host smart-e223f2aa-0190-415b-a3df-1c817bc52eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730928472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3730928472
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.445505867
Short name T478
Test name
Test status
Simulation time 32929574 ps
CPU time 0.7 seconds
Started Jun 24 05:14:19 PM PDT 24
Finished Jun 24 05:14:21 PM PDT 24
Peak memory 206496 kb
Host smart-5e649732-41f2-4021-b319-2270cf568fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445505867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.445505867
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1297493047
Short name T170
Test name
Test status
Simulation time 1158612925 ps
CPU time 3.06 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:15 PM PDT 24
Peak memory 225484 kb
Host smart-b32ebf96-266a-4d7a-be92-a05f8e081bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297493047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1297493047
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.568368849
Short name T533
Test name
Test status
Simulation time 89153145 ps
CPU time 0.74 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:19 PM PDT 24
Peak memory 206448 kb
Host smart-6a33dd9f-0b14-451e-af7e-ba1c1326eaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568368849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.568368849
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2197602314
Short name T476
Test name
Test status
Simulation time 40144687227 ps
CPU time 165.05 seconds
Started Jun 24 05:14:21 PM PDT 24
Finished Jun 24 05:17:08 PM PDT 24
Peak memory 253504 kb
Host smart-abca2e56-0e65-4181-b4af-a248c9fda524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197602314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2197602314
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.845628564
Short name T571
Test name
Test status
Simulation time 62105862176 ps
CPU time 150.03 seconds
Started Jun 24 05:14:26 PM PDT 24
Finished Jun 24 05:16:56 PM PDT 24
Peak memory 258492 kb
Host smart-7c8366ac-6abb-4e74-91b0-1c517e6545ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845628564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.845628564
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1810803121
Short name T134
Test name
Test status
Simulation time 9755318691 ps
CPU time 55.22 seconds
Started Jun 24 05:14:19 PM PDT 24
Finished Jun 24 05:15:15 PM PDT 24
Peak memory 241500 kb
Host smart-08303874-1387-4c30-82c0-14bbec943579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810803121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1810803121
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2625789914
Short name T784
Test name
Test status
Simulation time 51268600 ps
CPU time 2.92 seconds
Started Jun 24 05:14:13 PM PDT 24
Finished Jun 24 05:14:17 PM PDT 24
Peak memory 233944 kb
Host smart-e5b80185-cbea-4f48-b430-e0449b849218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625789914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2625789914
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.963386584
Short name T554
Test name
Test status
Simulation time 4092046188 ps
CPU time 8.38 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:21 PM PDT 24
Peak memory 225628 kb
Host smart-51c3c815-0cd3-496f-b786-dacde2d28160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963386584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.963386584
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2940753145
Short name T509
Test name
Test status
Simulation time 4555116278 ps
CPU time 14.99 seconds
Started Jun 24 05:14:12 PM PDT 24
Finished Jun 24 05:14:28 PM PDT 24
Peak memory 225608 kb
Host smart-f4da9bae-eb54-490e-ad9a-5053725d9655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940753145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2940753145
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2661821421
Short name T576
Test name
Test status
Simulation time 501114698 ps
CPU time 3.24 seconds
Started Jun 24 05:14:12 PM PDT 24
Finished Jun 24 05:14:16 PM PDT 24
Peak memory 233744 kb
Host smart-de12445e-127e-41f4-ada2-52a332fc688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661821421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2661821421
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.810063980
Short name T733
Test name
Test status
Simulation time 28300425319 ps
CPU time 22.04 seconds
Started Jun 24 05:14:13 PM PDT 24
Finished Jun 24 05:14:36 PM PDT 24
Peak memory 233828 kb
Host smart-f117f370-1924-4395-83e8-6229dfea7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810063980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.810063980
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4197515208
Short name T142
Test name
Test status
Simulation time 1153495956 ps
CPU time 9.63 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:29 PM PDT 24
Peak memory 222460 kb
Host smart-c17cf6ac-3d80-437f-a475-550c8e4392f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4197515208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4197515208
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1875451106
Short name T33
Test name
Test status
Simulation time 254957219 ps
CPU time 0.84 seconds
Started Jun 24 05:14:20 PM PDT 24
Finished Jun 24 05:14:23 PM PDT 24
Peak memory 206448 kb
Host smart-37d444b5-8ca6-4b38-a1f6-82cee47cdcb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875451106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1875451106
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.65137177
Short name T565
Test name
Test status
Simulation time 1064318704 ps
CPU time 7.6 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:20 PM PDT 24
Peak memory 217584 kb
Host smart-1b126a71-30c0-40b6-a71c-f4612387b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65137177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.65137177
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1275196080
Short name T901
Test name
Test status
Simulation time 3561221134 ps
CPU time 2.22 seconds
Started Jun 24 05:14:19 PM PDT 24
Finished Jun 24 05:14:22 PM PDT 24
Peak memory 208644 kb
Host smart-577c83ac-1b55-4464-a7e1-29f472dfe1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275196080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1275196080
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3049452414
Short name T875
Test name
Test status
Simulation time 116326345 ps
CPU time 0.91 seconds
Started Jun 24 05:14:11 PM PDT 24
Finished Jun 24 05:14:13 PM PDT 24
Peak memory 207488 kb
Host smart-e6647b2c-a937-4112-a809-3e8f07c942bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049452414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3049452414
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1913211406
Short name T340
Test name
Test status
Simulation time 196642288 ps
CPU time 0.85 seconds
Started Jun 24 05:14:12 PM PDT 24
Finished Jun 24 05:14:14 PM PDT 24
Peak memory 206900 kb
Host smart-c11ac52f-89a9-4acb-a816-4078b3acb290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913211406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1913211406
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3795711769
Short name T408
Test name
Test status
Simulation time 1101769968 ps
CPU time 6.36 seconds
Started Jun 24 05:14:10 PM PDT 24
Finished Jun 24 05:14:17 PM PDT 24
Peak memory 249988 kb
Host smart-714ccce5-fd33-4184-ad70-eb2ec5f9013b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795711769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3795711769
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3239440688
Short name T957
Test name
Test status
Simulation time 11456568 ps
CPU time 0.73 seconds
Started Jun 24 05:14:28 PM PDT 24
Finished Jun 24 05:14:30 PM PDT 24
Peak memory 206260 kb
Host smart-ba0d3b8b-5dd5-4a5e-b7ce-2730b91decc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239440688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3239440688
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2443967665
Short name T544
Test name
Test status
Simulation time 6597503960 ps
CPU time 17.42 seconds
Started Jun 24 05:14:20 PM PDT 24
Finished Jun 24 05:14:39 PM PDT 24
Peak memory 233780 kb
Host smart-28824751-91c1-4dc3-8d4b-dbf47ef65958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443967665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2443967665
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4259925772
Short name T611
Test name
Test status
Simulation time 14132542 ps
CPU time 0.73 seconds
Started Jun 24 05:14:20 PM PDT 24
Finished Jun 24 05:14:22 PM PDT 24
Peak memory 206448 kb
Host smart-f40bbbd1-857d-4a56-8a7f-b82c1e5eb72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259925772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4259925772
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.122943564
Short name T260
Test name
Test status
Simulation time 2207637240 ps
CPU time 22.29 seconds
Started Jun 24 05:14:29 PM PDT 24
Finished Jun 24 05:14:53 PM PDT 24
Peak memory 252440 kb
Host smart-7344308d-6750-43d9-b2b2-2b5ddb4959ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122943564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.122943564
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1121222560
Short name T643
Test name
Test status
Simulation time 32427865191 ps
CPU time 62.59 seconds
Started Jun 24 05:14:26 PM PDT 24
Finished Jun 24 05:15:29 PM PDT 24
Peak memory 241084 kb
Host smart-472c814e-8dca-4e11-8ef6-3c7c8e849f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121222560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1121222560
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.958510904
Short name T884
Test name
Test status
Simulation time 11219754587 ps
CPU time 160.79 seconds
Started Jun 24 05:14:27 PM PDT 24
Finished Jun 24 05:17:08 PM PDT 24
Peak memory 253264 kb
Host smart-8a93095d-b67c-4f42-92f6-7a95952e361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958510904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.958510904
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.873348680
Short name T355
Test name
Test status
Simulation time 143605447 ps
CPU time 3.45 seconds
Started Jun 24 05:14:20 PM PDT 24
Finished Jun 24 05:14:25 PM PDT 24
Peak memory 225504 kb
Host smart-e34b39b1-25c0-4765-8cb8-8b994a07bb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873348680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.873348680
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3573020058
Short name T705
Test name
Test status
Simulation time 188300837 ps
CPU time 2.2 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:20 PM PDT 24
Peak memory 224916 kb
Host smart-6bdc4a41-3ac7-4168-a256-c7545d86acdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573020058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3573020058
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3989576093
Short name T293
Test name
Test status
Simulation time 30987473 ps
CPU time 2.54 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:21 PM PDT 24
Peak memory 233748 kb
Host smart-62d340e9-ff80-478f-a516-e85b2aa663a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989576093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3989576093
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.631809365
Short name T247
Test name
Test status
Simulation time 1399997866 ps
CPU time 10 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:29 PM PDT 24
Peak memory 241900 kb
Host smart-73cc91c3-12ce-4e95-88c1-f6d198a3410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631809365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.631809365
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3262066510
Short name T596
Test name
Test status
Simulation time 186726170 ps
CPU time 1.95 seconds
Started Jun 24 05:14:21 PM PDT 24
Finished Jun 24 05:14:24 PM PDT 24
Peak memory 224104 kb
Host smart-72804b44-fde3-4267-bd91-bc33ac301c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262066510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3262066510
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2909590512
Short name T438
Test name
Test status
Simulation time 496359862 ps
CPU time 3.9 seconds
Started Jun 24 05:14:20 PM PDT 24
Finished Jun 24 05:14:25 PM PDT 24
Peak memory 223476 kb
Host smart-9f653137-f9de-45ad-bcf5-5d2b66c500e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2909590512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2909590512
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1203906930
Short name T204
Test name
Test status
Simulation time 1696038308 ps
CPU time 26.85 seconds
Started Jun 24 05:14:29 PM PDT 24
Finished Jun 24 05:14:57 PM PDT 24
Peak memory 242008 kb
Host smart-76a42ee4-4b69-429b-afc1-cb214e14f106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203906930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1203906930
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2956232513
Short name T393
Test name
Test status
Simulation time 6037910642 ps
CPU time 33.18 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:52 PM PDT 24
Peak memory 217472 kb
Host smart-18a99d89-293b-4702-9a6d-3746f1ef4942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956232513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2956232513
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3261069415
Short name T85
Test name
Test status
Simulation time 5392165135 ps
CPU time 8.88 seconds
Started Jun 24 05:14:20 PM PDT 24
Finished Jun 24 05:14:31 PM PDT 24
Peak memory 217500 kb
Host smart-f128fc59-eeb7-41db-82be-69b6e68cd7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261069415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3261069415
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1968316330
Short name T853
Test name
Test status
Simulation time 1583033580 ps
CPU time 6.46 seconds
Started Jun 24 05:14:19 PM PDT 24
Finished Jun 24 05:14:26 PM PDT 24
Peak memory 217248 kb
Host smart-abaf2ca2-effb-42a5-8dd3-f76870961e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968316330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1968316330
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2639836638
Short name T378
Test name
Test status
Simulation time 14308237 ps
CPU time 0.74 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:20 PM PDT 24
Peak memory 206764 kb
Host smart-65e23a82-2394-4fe2-8a4a-2a5ade86f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639836638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2639836638
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1136444877
Short name T255
Test name
Test status
Simulation time 11563350151 ps
CPU time 9.58 seconds
Started Jun 24 05:14:18 PM PDT 24
Finished Jun 24 05:14:29 PM PDT 24
Peak memory 225664 kb
Host smart-d6866876-7baf-4e57-b960-1f1312de545a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136444877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1136444877
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1011514525
Short name T10
Test name
Test status
Simulation time 16004438 ps
CPU time 0.74 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:10:35 PM PDT 24
Peak memory 206200 kb
Host smart-b14c893c-8665-461b-ab5a-0303a39e06d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011514525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
011514525
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.4218605865
Short name T815
Test name
Test status
Simulation time 32093405 ps
CPU time 2.24 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:39 PM PDT 24
Peak memory 225524 kb
Host smart-05af36e9-5e3e-43bd-8c86-6c522f47591e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218605865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.4218605865
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.654518913
Short name T353
Test name
Test status
Simulation time 30744328 ps
CPU time 0.78 seconds
Started Jun 24 05:10:36 PM PDT 24
Finished Jun 24 05:10:38 PM PDT 24
Peak memory 207984 kb
Host smart-ffa186ce-dc29-4dac-84e1-55d75b601cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654518913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.654518913
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.4053091291
Short name T741
Test name
Test status
Simulation time 5055011197 ps
CPU time 51.68 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:11:27 PM PDT 24
Peak memory 256008 kb
Host smart-ff6c98f2-4807-46d0-9c21-9af8ca082b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053091291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.4053091291
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3198678938
Short name T254
Test name
Test status
Simulation time 1807361462 ps
CPU time 32.17 seconds
Started Jun 24 05:10:35 PM PDT 24
Finished Jun 24 05:11:09 PM PDT 24
Peak memory 225456 kb
Host smart-3d50b34a-1f61-416c-ad78-b61855bbe165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198678938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3198678938
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3689715253
Short name T263
Test name
Test status
Simulation time 48110943817 ps
CPU time 215.16 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:14:11 PM PDT 24
Peak memory 266312 kb
Host smart-e9b26db8-681b-4f69-9c3b-27590d318135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689715253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3689715253
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2145452710
Short name T699
Test name
Test status
Simulation time 3721428653 ps
CPU time 31.57 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:11:06 PM PDT 24
Peak memory 225536 kb
Host smart-684d925b-8af5-40a8-a320-59090c37f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145452710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2145452710
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4052838334
Short name T237
Test name
Test status
Simulation time 832281409 ps
CPU time 6.42 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 233740 kb
Host smart-e680a68e-508b-4632-ad91-15d1f1368620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052838334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4052838334
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2585639614
Short name T231
Test name
Test status
Simulation time 39061097832 ps
CPU time 158.55 seconds
Started Jun 24 05:10:36 PM PDT 24
Finished Jun 24 05:13:16 PM PDT 24
Peak memory 250440 kb
Host smart-def9c49e-0821-4d06-a83d-daf7371ae987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585639614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2585639614
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.4145663304
Short name T45
Test name
Test status
Simulation time 15802508 ps
CPU time 1.04 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:10:35 PM PDT 24
Peak memory 218832 kb
Host smart-ff3e5583-9245-4991-990d-13bc17f7ca43
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145663304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.4145663304
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2223422949
Short name T948
Test name
Test status
Simulation time 48369072687 ps
CPU time 32.34 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:11:07 PM PDT 24
Peak memory 241376 kb
Host smart-ff3e1525-2aab-4803-bf23-030e31a9003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223422949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2223422949
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3452402829
Short name T773
Test name
Test status
Simulation time 5342703365 ps
CPU time 6.99 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:43 PM PDT 24
Peak memory 233812 kb
Host smart-880ee7ba-6b92-41c3-bde4-68f1bb4510cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452402829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3452402829
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1450828052
Short name T457
Test name
Test status
Simulation time 91085572 ps
CPU time 4.26 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:10:39 PM PDT 24
Peak memory 223348 kb
Host smart-2ddc200a-bdaf-424a-9002-63b57baf521c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1450828052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1450828052
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2755251327
Short name T959
Test name
Test status
Simulation time 13065764389 ps
CPU time 53.15 seconds
Started Jun 24 05:10:37 PM PDT 24
Finished Jun 24 05:11:31 PM PDT 24
Peak memory 225748 kb
Host smart-7535b8d4-e8f4-42c5-aff4-8d939a4f6215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755251327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2755251327
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.550815008
Short name T615
Test name
Test status
Simulation time 4271393821 ps
CPU time 14.19 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:50 PM PDT 24
Peak memory 217812 kb
Host smart-3d90ae31-2b8c-485b-8ab3-8785dfef6658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550815008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.550815008
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1721236379
Short name T783
Test name
Test status
Simulation time 7507932869 ps
CPU time 18.61 seconds
Started Jun 24 05:10:33 PM PDT 24
Finished Jun 24 05:10:53 PM PDT 24
Peak memory 217500 kb
Host smart-5361906a-5674-4c2c-9b44-9ffe7a6f4a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721236379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1721236379
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3220280700
Short name T898
Test name
Test status
Simulation time 17754903 ps
CPU time 0.71 seconds
Started Jun 24 05:10:36 PM PDT 24
Finished Jun 24 05:10:38 PM PDT 24
Peak memory 206888 kb
Host smart-4ec46074-7d07-4392-a7a2-c661815eedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220280700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3220280700
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2267503256
Short name T404
Test name
Test status
Simulation time 131688749 ps
CPU time 0.8 seconds
Started Jun 24 05:10:32 PM PDT 24
Finished Jun 24 05:10:34 PM PDT 24
Peak memory 206864 kb
Host smart-9528b42d-2f5c-495c-b282-3f23ab8ae4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267503256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2267503256
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4293010289
Short name T224
Test name
Test status
Simulation time 736560428 ps
CPU time 5.63 seconds
Started Jun 24 05:10:34 PM PDT 24
Finished Jun 24 05:10:42 PM PDT 24
Peak memory 233720 kb
Host smart-99978064-a092-4e53-b4bf-31e2be476a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293010289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4293010289
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1563999677
Short name T297
Test name
Test status
Simulation time 14175832 ps
CPU time 0.74 seconds
Started Jun 24 05:10:40 PM PDT 24
Finished Jun 24 05:10:43 PM PDT 24
Peak memory 206244 kb
Host smart-4e4fd9ee-2629-4a25-ae14-d32844aaae98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563999677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
563999677
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1418933256
Short name T958
Test name
Test status
Simulation time 883449667 ps
CPU time 12.85 seconds
Started Jun 24 05:10:40 PM PDT 24
Finished Jun 24 05:10:54 PM PDT 24
Peak memory 225384 kb
Host smart-633ae971-7e9f-49a1-befa-025597bfb038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418933256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1418933256
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3568719750
Short name T345
Test name
Test status
Simulation time 17878504 ps
CPU time 0.81 seconds
Started Jun 24 05:10:42 PM PDT 24
Finished Jun 24 05:10:44 PM PDT 24
Peak memory 207712 kb
Host smart-ed071e69-e09b-40c2-a6d9-8da16504c4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568719750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3568719750
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1450150471
Short name T339
Test name
Test status
Simulation time 26067759987 ps
CPU time 65.06 seconds
Started Jun 24 05:10:41 PM PDT 24
Finished Jun 24 05:11:48 PM PDT 24
Peak memory 250572 kb
Host smart-bebff80f-809c-4d5f-bade-8a09da3c9c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450150471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1450150471
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3430912322
Short name T29
Test name
Test status
Simulation time 5259221529 ps
CPU time 86.23 seconds
Started Jun 24 05:10:40 PM PDT 24
Finished Jun 24 05:12:08 PM PDT 24
Peak memory 258168 kb
Host smart-d310fd92-ecf9-4fab-ba7e-10676a532c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430912322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3430912322
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3774878743
Short name T450
Test name
Test status
Simulation time 12366613384 ps
CPU time 54.58 seconds
Started Jun 24 05:10:40 PM PDT 24
Finished Jun 24 05:11:36 PM PDT 24
Peak memory 240696 kb
Host smart-658b226c-1638-4e08-833c-2b20515f065f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774878743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3774878743
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.457960083
Short name T379
Test name
Test status
Simulation time 1924853413 ps
CPU time 4.15 seconds
Started Jun 24 05:10:41 PM PDT 24
Finished Jun 24 05:10:46 PM PDT 24
Peak memory 225508 kb
Host smart-e96a9f41-d8dc-4eff-b3d0-a4e6cbf12b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457960083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.457960083
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1282215676
Short name T941
Test name
Test status
Simulation time 15096133418 ps
CPU time 23.23 seconds
Started Jun 24 05:10:43 PM PDT 24
Finished Jun 24 05:11:07 PM PDT 24
Peak memory 225536 kb
Host smart-021761bd-98ac-40ec-8caf-4c6d1e170859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282215676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1282215676
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2403358485
Short name T295
Test name
Test status
Simulation time 73271100 ps
CPU time 2.3 seconds
Started Jun 24 05:10:40 PM PDT 24
Finished Jun 24 05:10:44 PM PDT 24
Peak memory 225468 kb
Host smart-cbd1124a-9911-4633-8a36-5fca0aaafba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403358485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2403358485
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3283854704
Short name T709
Test name
Test status
Simulation time 59839906 ps
CPU time 1.04 seconds
Started Jun 24 05:10:43 PM PDT 24
Finished Jun 24 05:10:45 PM PDT 24
Peak memory 217604 kb
Host smart-3f6ab3dc-42be-480a-b3ef-cd49b642699f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283854704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3283854704
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.308776762
Short name T53
Test name
Test status
Simulation time 2523676483 ps
CPU time 10.89 seconds
Started Jun 24 05:10:42 PM PDT 24
Finished Jun 24 05:10:55 PM PDT 24
Peak memory 225564 kb
Host smart-57d0c8d6-1dde-4013-a854-1f98e0dca143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308776762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
308776762
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.492052767
Short name T613
Test name
Test status
Simulation time 60948153 ps
CPU time 2.49 seconds
Started Jun 24 05:10:40 PM PDT 24
Finished Jun 24 05:10:43 PM PDT 24
Peak memory 234004 kb
Host smart-ae942ed0-36d9-49a6-a7b2-179d32de1185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492052767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.492052767
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4152778696
Short name T36
Test name
Test status
Simulation time 1321162971 ps
CPU time 14.45 seconds
Started Jun 24 05:10:41 PM PDT 24
Finished Jun 24 05:10:57 PM PDT 24
Peak memory 224040 kb
Host smart-81d8c072-b601-4aec-baf5-a8883001fd71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152778696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4152778696
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2639971415
Short name T152
Test name
Test status
Simulation time 111067410 ps
CPU time 1.04 seconds
Started Jun 24 05:10:39 PM PDT 24
Finished Jun 24 05:10:41 PM PDT 24
Peak memory 208040 kb
Host smart-42b382a2-d5a6-405f-8f1e-d661dde18f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639971415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2639971415
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1581232128
Short name T638
Test name
Test status
Simulation time 3567372595 ps
CPU time 22.67 seconds
Started Jun 24 05:10:42 PM PDT 24
Finished Jun 24 05:11:06 PM PDT 24
Peak memory 217420 kb
Host smart-479c95f6-1b54-4646-a4c7-4d688ed998a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581232128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1581232128
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3043416693
Short name T795
Test name
Test status
Simulation time 2676619991 ps
CPU time 5.51 seconds
Started Jun 24 05:10:41 PM PDT 24
Finished Jun 24 05:10:48 PM PDT 24
Peak memory 217464 kb
Host smart-835ec13d-542c-4a5f-9481-b77a84955d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043416693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3043416693
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3606696141
Short name T30
Test name
Test status
Simulation time 44526235 ps
CPU time 1.39 seconds
Started Jun 24 05:10:39 PM PDT 24
Finished Jun 24 05:10:41 PM PDT 24
Peak memory 209084 kb
Host smart-792ef409-e170-48be-af99-99693a1794f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606696141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3606696141
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2906555140
Short name T315
Test name
Test status
Simulation time 65850597 ps
CPU time 0.86 seconds
Started Jun 24 05:10:41 PM PDT 24
Finished Jun 24 05:10:44 PM PDT 24
Peak memory 207004 kb
Host smart-5cacf852-f02f-4758-bf45-ae9280892ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906555140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2906555140
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2740544830
Short name T219
Test name
Test status
Simulation time 39720319195 ps
CPU time 13.66 seconds
Started Jun 24 05:10:41 PM PDT 24
Finished Jun 24 05:10:56 PM PDT 24
Peak memory 225624 kb
Host smart-be8c051e-ed9b-45d1-9e8d-23391c06880e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740544830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2740544830
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3663045348
Short name T496
Test name
Test status
Simulation time 32935102 ps
CPU time 0.69 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:10:51 PM PDT 24
Peak memory 206232 kb
Host smart-6dcbe9c6-742b-483d-b7c1-6ccf58acbe0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663045348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
663045348
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4083205676
Short name T654
Test name
Test status
Simulation time 36465677 ps
CPU time 2.58 seconds
Started Jun 24 05:10:52 PM PDT 24
Finished Jun 24 05:10:55 PM PDT 24
Peak memory 233728 kb
Host smart-0f2ead6e-b37c-41d7-abd9-fda4783fab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083205676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4083205676
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.679380017
Short name T327
Test name
Test status
Simulation time 55319637 ps
CPU time 0.75 seconds
Started Jun 24 05:10:50 PM PDT 24
Finished Jun 24 05:10:52 PM PDT 24
Peak memory 206784 kb
Host smart-8e34d8fb-4cdd-498c-9fd6-01b235c6fa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679380017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.679380017
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3888708611
Short name T459
Test name
Test status
Simulation time 108925722271 ps
CPU time 171.97 seconds
Started Jun 24 05:10:48 PM PDT 24
Finished Jun 24 05:13:42 PM PDT 24
Peak memory 252300 kb
Host smart-52ef5378-59dd-48b1-b3a5-5b5e35b72c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888708611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3888708611
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3523784758
Short name T171
Test name
Test status
Simulation time 52121974764 ps
CPU time 174.39 seconds
Started Jun 24 05:10:47 PM PDT 24
Finished Jun 24 05:13:44 PM PDT 24
Peak memory 274760 kb
Host smart-cb3de41f-19f1-4265-b0d0-e2f231e6daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523784758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3523784758
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1148082235
Short name T972
Test name
Test status
Simulation time 4451742561 ps
CPU time 36.09 seconds
Started Jun 24 05:10:46 PM PDT 24
Finished Jun 24 05:11:25 PM PDT 24
Peak memory 242088 kb
Host smart-55cbd126-ba30-499e-9221-f9ed3eb523b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148082235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1148082235
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.850759628
Short name T212
Test name
Test status
Simulation time 5550481484 ps
CPU time 12.98 seconds
Started Jun 24 05:10:47 PM PDT 24
Finished Jun 24 05:11:02 PM PDT 24
Peak memory 233872 kb
Host smart-812239a7-ccea-4b33-9357-36d41211032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850759628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.850759628
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.369763038
Short name T470
Test name
Test status
Simulation time 138031148 ps
CPU time 2.21 seconds
Started Jun 24 05:10:46 PM PDT 24
Finished Jun 24 05:10:50 PM PDT 24
Peak memory 219432 kb
Host smart-301bd6a8-4d8c-4bd2-bde6-68bd26879ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369763038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.369763038
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3244922171
Short name T468
Test name
Test status
Simulation time 53876965 ps
CPU time 1.02 seconds
Started Jun 24 05:10:48 PM PDT 24
Finished Jun 24 05:10:50 PM PDT 24
Peak memory 217524 kb
Host smart-bac94d33-f5c0-4902-8f41-145d03a85bff
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244922171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3244922171
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.532749226
Short name T954
Test name
Test status
Simulation time 31774737 ps
CPU time 2.57 seconds
Started Jun 24 05:10:48 PM PDT 24
Finished Jun 24 05:10:53 PM PDT 24
Peak memory 233464 kb
Host smart-20040786-d252-4223-b29b-3671a6bc3c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532749226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
532749226
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.336356762
Short name T185
Test name
Test status
Simulation time 54158701119 ps
CPU time 31.29 seconds
Started Jun 24 05:10:52 PM PDT 24
Finished Jun 24 05:11:24 PM PDT 24
Peak memory 233792 kb
Host smart-cffc31c6-cf5e-4de8-b229-09be38949c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336356762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.336356762
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4000430817
Short name T817
Test name
Test status
Simulation time 360173172 ps
CPU time 6.93 seconds
Started Jun 24 05:10:48 PM PDT 24
Finished Jun 24 05:10:57 PM PDT 24
Peak memory 222112 kb
Host smart-1d6e62c1-8eb2-4668-bb41-fb862976aee3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4000430817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4000430817
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2251146928
Short name T920
Test name
Test status
Simulation time 114077541900 ps
CPU time 352.6 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:16:43 PM PDT 24
Peak memory 274896 kb
Host smart-fd738915-956e-4dd0-9674-5e92003f2e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251146928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2251146928
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2190951917
Short name T723
Test name
Test status
Simulation time 6716454533 ps
CPU time 36.72 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:11:27 PM PDT 24
Peak memory 217480 kb
Host smart-f64c8ce9-3fae-423d-8ad1-35f130641c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190951917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2190951917
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.925213157
Short name T687
Test name
Test status
Simulation time 1059148362 ps
CPU time 2.25 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:10:53 PM PDT 24
Peak memory 208876 kb
Host smart-e87b6b9b-8a85-457a-922b-e1687b4e7dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925213157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.925213157
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4284630041
Short name T894
Test name
Test status
Simulation time 35646551 ps
CPU time 0.94 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:10:51 PM PDT 24
Peak memory 207908 kb
Host smart-1e235279-3e0b-4218-a3b4-a3f4d7ec1984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284630041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4284630041
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1313715480
Short name T418
Test name
Test status
Simulation time 181178921 ps
CPU time 0.92 seconds
Started Jun 24 05:10:48 PM PDT 24
Finished Jun 24 05:10:51 PM PDT 24
Peak memory 206872 kb
Host smart-6093b96f-3fd4-4af8-b906-68dcf03008f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313715480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1313715480
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3293707011
Short name T788
Test name
Test status
Simulation time 35506381 ps
CPU time 2.24 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:10:53 PM PDT 24
Peak memory 224896 kb
Host smart-2afa4618-9a28-447c-a627-90c9b97b6412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293707011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3293707011
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3751040967
Short name T796
Test name
Test status
Simulation time 28069084 ps
CPU time 0.73 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:10:55 PM PDT 24
Peak memory 206268 kb
Host smart-e0f084f3-1067-4802-acaf-31b3fc57891b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751040967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
751040967
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1353596502
Short name T398
Test name
Test status
Simulation time 71300638 ps
CPU time 2.83 seconds
Started Jun 24 05:10:47 PM PDT 24
Finished Jun 24 05:10:52 PM PDT 24
Peak memory 233668 kb
Host smart-892b1789-8ddd-4f8c-b6b5-83e2193b7b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353596502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1353596502
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3511110554
Short name T396
Test name
Test status
Simulation time 200987055 ps
CPU time 0.77 seconds
Started Jun 24 05:10:50 PM PDT 24
Finished Jun 24 05:10:52 PM PDT 24
Peak memory 207648 kb
Host smart-3cf63917-ac49-4f3b-a1ab-6d467aa26460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511110554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3511110554
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.401042512
Short name T275
Test name
Test status
Simulation time 19018013825 ps
CPU time 172.86 seconds
Started Jun 24 05:10:50 PM PDT 24
Finished Jun 24 05:13:44 PM PDT 24
Peak memory 251832 kb
Host smart-a1474ce5-8429-452e-be4e-4372111323e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401042512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.401042512
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3162930633
Short name T208
Test name
Test status
Simulation time 14131351402 ps
CPU time 68.78 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:12:04 PM PDT 24
Peak memory 255788 kb
Host smart-9180d8cf-27ab-4ebc-92c3-a9e6d0b055f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162930633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3162930633
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3324105726
Short name T870
Test name
Test status
Simulation time 202395145237 ps
CPU time 399.16 seconds
Started Jun 24 05:10:48 PM PDT 24
Finished Jun 24 05:17:29 PM PDT 24
Peak memory 267088 kb
Host smart-d9c854a7-f804-4b85-94b4-9c49b5806c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324105726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3324105726
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1936833471
Short name T282
Test name
Test status
Simulation time 509349115 ps
CPU time 7.57 seconds
Started Jun 24 05:10:48 PM PDT 24
Finished Jun 24 05:10:58 PM PDT 24
Peak memory 233608 kb
Host smart-11cfe6e9-3bc4-4f7a-b8ad-4f52c2dd63af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936833471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1936833471
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.285715442
Short name T456
Test name
Test status
Simulation time 8805404373 ps
CPU time 6.47 seconds
Started Jun 24 05:10:52 PM PDT 24
Finished Jun 24 05:11:00 PM PDT 24
Peak memory 233852 kb
Host smart-8e83e7c7-d0ac-4421-9ef0-fcb6c8b74450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285715442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.285715442
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3747103603
Short name T4
Test name
Test status
Simulation time 6411122580 ps
CPU time 23.87 seconds
Started Jun 24 05:10:47 PM PDT 24
Finished Jun 24 05:11:13 PM PDT 24
Peak memory 233852 kb
Host smart-eea5c816-7d62-451d-ba01-680e969f5b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747103603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3747103603
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.325860541
Short name T679
Test name
Test status
Simulation time 117860100 ps
CPU time 1.09 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:10:52 PM PDT 24
Peak memory 217520 kb
Host smart-7fa22144-91f5-4f65-b565-d13e2bf2fa44
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325860541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.325860541
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1095192925
Short name T441
Test name
Test status
Simulation time 8057565021 ps
CPU time 24.71 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:11:20 PM PDT 24
Peak memory 241308 kb
Host smart-e7afdb1a-abfd-48a6-a6c3-d218905239dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095192925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1095192925
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.161654521
Short name T970
Test name
Test status
Simulation time 8411406826 ps
CPU time 13.43 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:11:04 PM PDT 24
Peak memory 233856 kb
Host smart-f489ee20-0983-4391-a376-6811cbf27e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161654521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.161654521
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.297987331
Short name T697
Test name
Test status
Simulation time 210987396 ps
CPU time 4.62 seconds
Started Jun 24 05:10:52 PM PDT 24
Finished Jun 24 05:10:58 PM PDT 24
Peak memory 219880 kb
Host smart-5e748d73-9c1b-4a5f-b296-baef1992bacd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=297987331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.297987331
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1047683166
Short name T42
Test name
Test status
Simulation time 19050489496 ps
CPU time 231.03 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:14:41 PM PDT 24
Peak memory 258336 kb
Host smart-f20a4c54-94d7-437b-a177-31c7e705a7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047683166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1047683166
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2144400255
Short name T738
Test name
Test status
Simulation time 1196986156 ps
CPU time 6.99 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:11:02 PM PDT 24
Peak memory 217268 kb
Host smart-4429c340-0855-4137-a40c-f244da6ca7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144400255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2144400255
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2759345683
Short name T971
Test name
Test status
Simulation time 10455207774 ps
CPU time 16.76 seconds
Started Jun 24 05:10:47 PM PDT 24
Finished Jun 24 05:11:05 PM PDT 24
Peak memory 217504 kb
Host smart-fc124bdd-e454-447c-ace3-667876abce60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759345683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2759345683
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2015871618
Short name T349
Test name
Test status
Simulation time 120690109 ps
CPU time 1.83 seconds
Started Jun 24 05:10:49 PM PDT 24
Finished Jun 24 05:10:52 PM PDT 24
Peak memory 217356 kb
Host smart-6aca3261-5046-466e-ab78-c5ee502aefee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015871618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2015871618
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3767450471
Short name T366
Test name
Test status
Simulation time 37784228 ps
CPU time 0.73 seconds
Started Jun 24 05:10:46 PM PDT 24
Finished Jun 24 05:10:49 PM PDT 24
Peak memory 206788 kb
Host smart-de80e95a-7857-4ea8-a903-878610013b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767450471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3767450471
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.11853391
Short name T734
Test name
Test status
Simulation time 9225921726 ps
CPU time 4.41 seconds
Started Jun 24 05:10:50 PM PDT 24
Finished Jun 24 05:10:56 PM PDT 24
Peak memory 225584 kb
Host smart-01b3ce92-817a-4007-867d-802c5771812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11853391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.11853391
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3981161325
Short name T377
Test name
Test status
Simulation time 36846505 ps
CPU time 0.7 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:10:56 PM PDT 24
Peak memory 206244 kb
Host smart-21a8ea2e-d09e-4236-8963-8db8d7efd220
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981161325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
981161325
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1923530580
Short name T535
Test name
Test status
Simulation time 114862863 ps
CPU time 2.5 seconds
Started Jun 24 05:10:57 PM PDT 24
Finished Jun 24 05:11:01 PM PDT 24
Peak memory 233744 kb
Host smart-e886a6cd-8cae-4aff-bbcc-6c590e04c7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923530580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1923530580
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3581628532
Short name T754
Test name
Test status
Simulation time 226968270 ps
CPU time 0.8 seconds
Started Jun 24 05:10:55 PM PDT 24
Finished Jun 24 05:10:58 PM PDT 24
Peak memory 207464 kb
Host smart-266e748c-0a3c-43c8-b3cb-88fc2bdb7aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581628532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3581628532
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.334649473
Short name T878
Test name
Test status
Simulation time 28274609352 ps
CPU time 46.54 seconds
Started Jun 24 05:10:56 PM PDT 24
Finished Jun 24 05:11:45 PM PDT 24
Peak memory 238580 kb
Host smart-2de983ce-6b15-4a29-abc1-552d99959999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334649473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.334649473
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3703793852
Short name T56
Test name
Test status
Simulation time 48108482952 ps
CPU time 117.72 seconds
Started Jun 24 05:10:52 PM PDT 24
Finished Jun 24 05:12:51 PM PDT 24
Peak memory 250568 kb
Host smart-2ed25b4b-db4d-47c8-af6e-70304f9246a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703793852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3703793852
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2020637491
Short name T522
Test name
Test status
Simulation time 26889941425 ps
CPU time 297.38 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:15:52 PM PDT 24
Peak memory 263024 kb
Host smart-10ecd3e3-4827-4f70-8a39-a906e2041114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020637491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2020637491
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4269477129
Short name T455
Test name
Test status
Simulation time 2959225676 ps
CPU time 14.02 seconds
Started Jun 24 05:10:55 PM PDT 24
Finished Jun 24 05:11:12 PM PDT 24
Peak memory 238896 kb
Host smart-df3bfdfc-1712-415c-8729-5dc079536c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269477129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4269477129
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4150226079
Short name T37
Test name
Test status
Simulation time 453104607 ps
CPU time 4.7 seconds
Started Jun 24 05:10:57 PM PDT 24
Finished Jun 24 05:11:04 PM PDT 24
Peak memory 233764 kb
Host smart-5728eee5-485c-481e-b715-dbc7d703cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150226079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4150226079
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4061319815
Short name T915
Test name
Test status
Simulation time 38130382299 ps
CPU time 64.38 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:11:59 PM PDT 24
Peak memory 241800 kb
Host smart-3062228b-271d-4b3c-9532-08b13a06e841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061319815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4061319815
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4011685019
Short name T319
Test name
Test status
Simulation time 31779293 ps
CPU time 1.09 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:10:56 PM PDT 24
Peak memory 217584 kb
Host smart-a0e0bc4c-dabc-42b1-a8b7-c3a4e838b0a8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011685019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4011685019
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3368117632
Short name T885
Test name
Test status
Simulation time 18034102354 ps
CPU time 11.68 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:11:06 PM PDT 24
Peak memory 233788 kb
Host smart-1513d257-c6c0-400d-8b09-4c11a7142bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368117632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3368117632
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.353969830
Short name T587
Test name
Test status
Simulation time 1931548296 ps
CPU time 5.22 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:11:02 PM PDT 24
Peak memory 225544 kb
Host smart-dad1ecd4-0c45-45a1-ade6-ed3c64381a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353969830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.353969830
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1995531905
Short name T692
Test name
Test status
Simulation time 760441808 ps
CPU time 7.79 seconds
Started Jun 24 05:10:56 PM PDT 24
Finished Jun 24 05:11:06 PM PDT 24
Peak memory 219732 kb
Host smart-5c10cfde-853c-4f4a-a76d-7838a0de0763
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1995531905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1995531905
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2027470771
Short name T669
Test name
Test status
Simulation time 83715048 ps
CPU time 0.98 seconds
Started Jun 24 05:10:55 PM PDT 24
Finished Jun 24 05:10:59 PM PDT 24
Peak memory 207496 kb
Host smart-5b9e3c87-201a-44f2-afad-95117bd170ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027470771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2027470771
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.765303880
Short name T288
Test name
Test status
Simulation time 36092874587 ps
CPU time 44.92 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:11:41 PM PDT 24
Peak memory 217600 kb
Host smart-bdd9f8af-a815-4dfc-b02e-b5215d7f7099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765303880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.765303880
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.487152300
Short name T666
Test name
Test status
Simulation time 3190387630 ps
CPU time 2.3 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:10:59 PM PDT 24
Peak memory 209048 kb
Host smart-8e71cb63-7cc4-4789-9e4b-b2174f351302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487152300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.487152300
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.433699918
Short name T845
Test name
Test status
Simulation time 46126903 ps
CPU time 0.78 seconds
Started Jun 24 05:10:54 PM PDT 24
Finished Jun 24 05:10:57 PM PDT 24
Peak memory 206840 kb
Host smart-b77ae730-666b-4c8e-a4b8-e073a6d8bbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433699918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.433699918
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1758019733
Short name T407
Test name
Test status
Simulation time 510110409 ps
CPU time 0.9 seconds
Started Jun 24 05:10:55 PM PDT 24
Finished Jun 24 05:10:58 PM PDT 24
Peak memory 206780 kb
Host smart-2785f17a-9c10-426e-8a9a-dc68270f7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758019733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1758019733
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3152307776
Short name T235
Test name
Test status
Simulation time 27193709772 ps
CPU time 22.27 seconds
Started Jun 24 05:10:53 PM PDT 24
Finished Jun 24 05:11:16 PM PDT 24
Peak memory 230240 kb
Host smart-a3f2c52f-cf4a-45ec-a8a0-6249d85c3c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152307776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3152307776
Directory /workspace/9.spi_device_upload/latest
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