Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3814129	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4068766

1

T1

1

T2

17272

T3

898

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4514188	1			T1	1		T2	11289		T3	4
values[0x0]	1686016	1			T1	1		T2	5767		T3	428
values[0x1]	1682691	1			T2	5684		T3	468		T4	390

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2697273	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5185622

1

T1

1

T2

18383

T3

899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32169	1			T2	100		T4	4		T7	1
valid_sources[0x01]	26806	1			T2	102		T4	1		T11	4
valid_sources[0x02]	31780	1			T2	89		T11	7		T12	4
valid_sources[0x03]	28686	1			T2	91		T4	9		T11	5
valid_sources[0x04]	32064	1			T2	81		T11	4		T12	4
valid_sources[0x05]	33545	1			T2	96		T4	2		T7	845
valid_sources[0x06]	28571	1			T2	100		T4	3		T11	5
valid_sources[0x07]	28862	1			T2	83		T4	4		T11	4
valid_sources[0x08]	29221	1			T2	78		T3	451		T4	1
valid_sources[0x09]	29772	1			T2	86		T4	6		T11	3
valid_sources[0x0a]	27814	1			T2	75		T4	6		T11	2
valid_sources[0x0b]	29996	1			T2	100		T10	147		T11	8
valid_sources[0x0c]	28286	1			T2	88		T4	8		T11	4
valid_sources[0x0d]	30065	1			T2	76		T4	8		T11	6
valid_sources[0x0e]	29859	1			T2	88		T4	5		T11	6
valid_sources[0x0f]	27624	1			T2	109		T11	2		T12	1
valid_sources[0x10]	31099	1			T2	101		T4	1		T11	6
valid_sources[0x11]	26963	1			T2	82		T4	12		T11	4
valid_sources[0x12]	30242	1			T2	93		T4	5		T11	4
valid_sources[0x13]	28901	1			T2	94		T4	6		T11	5
valid_sources[0x14]	73598	1			T2	90		T4	18		T11	4
valid_sources[0x15]	47199	1			T2	89		T4	3		T11	4
valid_sources[0x16]	26286	1			T2	87		T4	11		T7	1
valid_sources[0x17]	31383	1			T2	94		T4	7		T11	7
valid_sources[0x18]	33242	1			T2	98		T4	5		T5	61
valid_sources[0x19]	33698	1			T2	78		T4	16		T11	2
valid_sources[0x1a]	28520	1			T2	75		T4	8		T11	1
valid_sources[0x1b]	29156	1			T2	79		T7	1		T11	3
valid_sources[0x1c]	31983	1			T2	94		T4	2		T11	5
valid_sources[0x1d]	31473	1			T2	87		T4	1		T11	8
valid_sources[0x1e]	28709	1			T2	87		T4	6		T7	416
valid_sources[0x1f]	29777	1			T2	90		T4	13		T11	9
valid_sources[0x20]	28703	1			T2	101		T4	7		T11	6
valid_sources[0x21]	39229	1			T2	82		T4	5		T11	2
valid_sources[0x22]	30036	1			T2	91		T4	3		T11	6
valid_sources[0x23]	29595	1			T2	88		T4	3		T7	1
valid_sources[0x24]	29970	1			T2	87		T4	9		T7	1
valid_sources[0x25]	30125	1			T2	99		T4	5		T11	7
valid_sources[0x26]	30688	1			T2	74		T11	12		T12	7
valid_sources[0x27]	31394	1			T2	94		T4	4		T11	9
valid_sources[0x28]	30268	1			T2	96		T4	1		T11	5
valid_sources[0x29]	29903	1			T2	84		T4	5		T11	2
valid_sources[0x2a]	30063	1			T2	88		T4	1		T7	453
valid_sources[0x2b]	29523	1			T2	90		T4	11		T11	2
valid_sources[0x2c]	28199	1			T2	94		T4	1		T11	10
valid_sources[0x2d]	34858	1			T2	90		T4	13		T7	1
valid_sources[0x2e]	34053	1			T2	79		T4	1		T11	4
valid_sources[0x2f]	30182	1			T2	74		T4	5		T11	2
valid_sources[0x30]	27500	1			T2	87		T4	2		T7	880
valid_sources[0x31]	28920	1			T2	86		T4	12		T11	5
valid_sources[0x32]	29221	1			T2	92		T4	4		T11	2
valid_sources[0x33]	32828	1			T2	87		T4	6		T11	2
valid_sources[0x34]	27995	1			T2	88		T4	5		T11	4
valid_sources[0x35]	36299	1			T2	79		T4	4		T10	145
valid_sources[0x36]	26758	1			T2	83		T4	3		T11	6
valid_sources[0x37]	29586	1			T2	81		T4	13		T11	4
valid_sources[0x38]	30333	1			T2	76		T4	12		T10	1
valid_sources[0x39]	27929	1			T2	84		T4	1		T7	373
valid_sources[0x3a]	27035	1			T2	90		T4	4		T11	4
valid_sources[0x3b]	30257	1			T2	100		T4	3		T11	9
valid_sources[0x3c]	32267	1			T2	84		T4	9		T6	20
valid_sources[0x3d]	41217	1			T2	72		T4	2		T7	2
valid_sources[0x3e]	30697	1			T2	86		T11	3		T12	4
valid_sources[0x3f]	27752	1			T2	94		T4	10		T9	2
valid_sources[0x40]	30847	1			T2	97		T4	1		T10	82
valid_sources[0x41]	31728	1			T2	94		T4	6		T11	5
valid_sources[0x42]	29230	1			T2	92		T4	7		T11	6
valid_sources[0x43]	28929	1			T2	82		T4	3		T7	1
valid_sources[0x44]	29218	1			T2	93		T4	4		T11	5
valid_sources[0x45]	31278	1			T2	82		T4	7		T10	76
valid_sources[0x46]	32930	1			T2	88		T4	8		T11	3
valid_sources[0x47]	25850	1			T2	90		T4	3		T11	6
valid_sources[0x48]	30272	1			T2	83		T4	8		T11	5
valid_sources[0x49]	29343	1			T2	97		T4	6		T10	127
valid_sources[0x4a]	34350	1			T2	78		T4	4		T11	3
valid_sources[0x4b]	28900	1			T2	85		T4	3		T11	3
valid_sources[0x4c]	31443	1			T2	83		T4	10		T11	4
valid_sources[0x4d]	29558	1			T2	98		T4	19		T7	1
valid_sources[0x4e]	30093	1			T2	98		T7	182		T9	1
valid_sources[0x4f]	27842	1			T2	86		T4	1		T10	30
valid_sources[0x50]	28836	1			T2	78		T4	5		T7	1
valid_sources[0x51]	27802	1			T2	90		T4	4		T11	8
valid_sources[0x52]	28586	1			T2	88		T4	8		T11	7
valid_sources[0x53]	28568	1			T2	97		T4	3		T9	1
valid_sources[0x54]	30326	1			T2	101		T4	3		T10	79
valid_sources[0x55]	27846	1			T2	85		T4	7		T11	4
valid_sources[0x56]	32327	1			T2	86		T4	7		T7	1
valid_sources[0x57]	25457	1			T2	87		T4	16		T11	5
valid_sources[0x58]	31087	1			T2	94		T4	4		T7	1
valid_sources[0x59]	29071	1			T2	92		T4	12		T7	225
valid_sources[0x5a]	27611	1			T2	82		T4	7		T11	1
valid_sources[0x5b]	29469	1			T2	119		T4	4		T9	1
valid_sources[0x5c]	27845	1			T2	67		T4	3		T7	1
valid_sources[0x5d]	32510	1			T2	88		T4	9		T11	3
valid_sources[0x5e]	28546	1			T2	87		T4	9		T11	5
valid_sources[0x5f]	30669	1			T2	100		T4	5		T11	5
valid_sources[0x60]	30129	1			T2	84		T4	5		T11	2
valid_sources[0x61]	34075	1			T2	101		T4	3		T7	1
valid_sources[0x62]	28003	1			T2	94		T4	3		T11	3
valid_sources[0x63]	36866	1			T2	81		T4	8		T11	5
valid_sources[0x64]	28290	1			T2	88		T4	3		T11	3
valid_sources[0x65]	28554	1			T2	97		T4	10		T11	3
valid_sources[0x66]	34673	1			T2	101		T4	4		T11	3
valid_sources[0x67]	31906	1			T2	79		T4	15		T11	1
valid_sources[0x68]	30675	1			T2	87		T4	3		T10	25
valid_sources[0x69]	34164	1			T2	81		T4	7		T11	4
valid_sources[0x6a]	34174	1			T2	88		T4	4		T11	5
valid_sources[0x6b]	27919	1			T2	102		T4	3		T10	38
valid_sources[0x6c]	30744	1			T2	97		T4	4		T10	93
valid_sources[0x6d]	27288	1			T2	96		T4	7		T11	11
valid_sources[0x6e]	29115	1			T2	89		T4	5		T9	1
valid_sources[0x6f]	29245	1			T2	82		T11	4		T13	95
valid_sources[0x70]	33163	1			T2	88		T4	3		T9	1
valid_sources[0x71]	27792	1			T2	82		T4	4		T10	32
valid_sources[0x72]	35577	1			T2	96		T4	6		T11	2
valid_sources[0x73]	28130	1			T2	92		T4	5		T11	5
valid_sources[0x74]	27697	1			T2	108		T4	5		T8	1
valid_sources[0x75]	30843	1			T2	82		T4	3		T11	5
valid_sources[0x76]	28826	1			T2	95		T4	1		T7	1
valid_sources[0x77]	28609	1			T2	100		T4	7		T7	1436
valid_sources[0x78]	33303	1			T2	78		T4	2		T7	1
valid_sources[0x79]	29868	1			T2	85		T4	12		T11	1
valid_sources[0x7a]	30789	1			T2	91		T4	10		T8	1
valid_sources[0x7b]	31027	1			T2	79		T11	10		T12	6
valid_sources[0x7c]	32151	1			T2	81		T4	13		T11	2
valid_sources[0x7d]	30925	1			T2	93		T4	10		T7	1
valid_sources[0x7e]	66260	1			T2	93		T4	5		T10	86
valid_sources[0x7f]	29873	1			T2	84		T4	5		T9	1
valid_sources[0x80]	30164	1			T2	76		T4	2		T11	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1044800

1

T1

1

T2

5885

T3

3

values[0x0]

all_enables

biggest_size

1525622

1

T2

5754

T3

428

T4

311

values[0x1]

all_enables

biggest_size

1498344

1

T2

5633

T3

467

T4

309