Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3830332

1

T1

1

T2

5468

T3

2

full_word

4067675

1

T1

1

T2

17272

T3

898

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7897557	1			T1	2		T2	22740		T3	900
auto[TlIntgErrCmd]	159	1			T86	10		T87	9		T91	8
auto[TlIntgErrData]	162	1			T86	10		T87	6		T91	7
auto[TlIntgErrBoth]	129	1			T86	10		T87	5		T91	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4515318

1

T1

1

T2

11289

T3

4

auto[1]

3382689

1

T1

1

T2

11451

T3

896

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3470248	1			T2	5404		T3	1		T4	510
auto[TlIntgErrNone]	partial	auto[1]	359668	1			T1	1		T2	64		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	1044848	1			T1	1		T2	5885		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	3022793	1			T2	11387		T3	895		T4	620
auto[TlIntgErrCmd]	partial	auto[0]	74	1			T86	5		T87	4		T91	4
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T86	2		T87	5		T91	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T86	2		T92	1		T179	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T86	1		T180	1		T181	1
auto[TlIntgErrData]	partial	auto[0]	75	1			T86	7		T87	2		T91	2
auto[TlIntgErrData]	partial	auto[1]	74	1			T86	3		T87	3		T91	5
auto[TlIntgErrData]	full_word	auto[0]	6	1			T182	1		T180	1		T183	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T87	1		T92	1		T175	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T86	5		T87	3		T91	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T86	5		T87	2		T91	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T183	1		T181	1		T184	2
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T177	3		T185	1		T183	1