Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456361766	2511709	0	0
DepthKnown_A	456361766	456228381	0	0
RvalidKnown_A	456361766	456228381	0	0
WreadyKnown_A	456361766	456228381	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	2511709	0	0
T2	774961	17481	0	0
T3	630304	1663	0	0
T4	44177	0	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	7486	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1343	0	0
T11	0	832	0	0
T12	0	1663	0	0
T13	0	12484	0	0
T14	0	14970	0	0
T15	0	832	0	0
T16	0	1666	0	0
T25	933	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456361766	2767153	0	0
DepthKnown_A	456361766	456228381	0	0
RvalidKnown_A	456361766	456228381	0	0
WreadyKnown_A	456361766	456228381	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	2767153	0	0
T2	774961	18006	0	0
T3	630304	832	0	0
T4	44177	0	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5824	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	832	0	0
T12	0	832	0	0
T13	0	17826	0	0
T14	0	9984	0	0
T15	0	832	0	0
T16	0	835	0	0
T25	933	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456361766	175002	0	0
DepthKnown_A	456361766	456228381	0	0
RvalidKnown_A	456361766	456228381	0	0
WreadyKnown_A	456361766	456228381	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	175002	0	0
T2	774961	387	0	0
T3	630304	0	0	0
T4	44177	117	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	96	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	0	0	0
T13	0	1345	0	0
T14	0	1448	0	0
T15	0	551	0	0
T25	933	0	0	0
T30	0	18	0	0
T32	0	737	0	0
T33	0	23	0	0
T35	0	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456361766	397407	0	0
DepthKnown_A	456361766	456228381	0	0
RvalidKnown_A	456361766	456228381	0	0
WreadyKnown_A	456361766	456228381	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	397407	0	0
T2	774961	1315	0	0
T3	630304	0	0	0
T4	44177	501	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	96	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	0	0	0
T13	0	3933	0	0
T14	0	1448	0	0
T15	0	551	0	0
T25	933	0	0	0
T30	0	18	0	0
T32	0	2289	0	0
T33	0	89	0	0
T35	0	277	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456361766	6496416	0	0
DepthKnown_A	456361766	456228381	0	0
RvalidKnown_A	456361766	456228381	0	0
WreadyKnown_A	456361766	456228381	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	6496416	0	0
T1	654	2	0	0
T2	774961	11570	0	0
T3	630304	68	0	0
T4	44177	1407	0	0
T5	1457	61	0	0
T6	4867	20	0	0
T7	229016	3666	0	0
T8	704	9	0	0
T9	1219	17	0	0
T10	18359	612	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	456361766	13295075	0	0
DepthKnown_A	456361766	456228381	0	0
RvalidKnown_A	456361766	456228381	0	0
WreadyKnown_A	456361766	456228381	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	13295075	0	0
T1	654	10	0	0
T2	774961	33895	0	0
T3	630304	68	0	0
T4	44177	5865	0	0
T5	1457	254	0	0
T6	4867	93	0	0
T7	229016	3664	0	0
T8	704	9	0	0
T9	1219	90	0	0
T10	18359	609	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	456361766	456228381	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0