Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T13,T14
1	0	Covered	T4,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T13
1	0	Unreachable
1	1	Covered	T4,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T11
1	0	Covered	T2,T7,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Unreachable
1	1	Covered	T2,T7,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	714367443	582747048	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	714367443	3350770	0	0
GntImpliesValid_A	714367443	3350770	0	0
GrantKnown_A	714367443	582747048	0	0
IdxKnown_A	714367443	582747048	0	0
IndexIsCorrect_A	714367443	3350770	0	0
LockArbDecision_A	714367443	0	0	0
NoReadyValidNoGrant_A	714367443	0	0	0
ReadyAndValidImplyGrant_A	714367443	3350770	0	0
ReqAndReadyImplyGrant_A	714367443	3350770	0	0
ReqImpliesValid_A	714367443	3350770	0	0
ReqStaysHighUntilGranted0_M	714367443	0	0	0
RoundRobin_A	714367443	7	0	926
ValidKnown_A	714367443	582747048	0	0
gen_data_port_assertion.DataFlow_A	714367443	3350770	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	582747048	0	0
T1	654	561	0	0
T2	1737216	1734141	0	0
T3	756021	755296	0	0
T4	175401	108904	0	0
T5	1457	1399	0	0
T6	5731	5216	0	0
T7	870332	548259	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	71857	44410	0	0
T11	66576	33288	0	0
T12	137240	68134	0	0
T13	1690666	837160	0	0
T14	222602	1105148	0	0
T15	0	122686	0	0
T16	0	144	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	3350770	0	0
T2	1737216	17058	0	0
T3	756021	832	0	0
T4	175401	1416	0	0
T5	1457	0	0	0
T6	5731	0	0	0
T7	870332	6329	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	71857	1088	0	0
T11	66576	836	0	0
T12	137240	832	0	0
T13	1690666	22070	0	0
T14	222602	31362	0	0
T15	0	3589	0	0
T25	933	0	0	0
T27	62228	0	0	0
T30	2088	168	0	0
T32	0	7418	0	0
T33	0	98	0	0
T35	0	530	0	0
T44	0	2790	0	0
T47	0	9148	0	0
T48	0	11605	0	0
T52	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	3350770	0	0
T2	1737216	17058	0	0
T3	756021	832	0	0
T4	175401	1416	0	0
T5	1457	0	0	0
T6	5731	0	0	0
T7	870332	6329	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	71857	1088	0	0
T11	66576	836	0	0
T12	137240	832	0	0
T13	1690666	22070	0	0
T14	222602	31362	0	0
T15	0	3589	0	0
T25	933	0	0	0
T27	62228	0	0	0
T30	2088	168	0	0
T32	0	7418	0	0
T33	0	98	0	0
T35	0	530	0	0
T44	0	2790	0	0
T47	0	9148	0	0
T48	0	11605	0	0
T52	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	582747048	0	0
T1	654	561	0	0
T2	1737216	1734141	0	0
T3	756021	755296	0	0
T4	175401	108904	0	0
T5	1457	1399	0	0
T6	5731	5216	0	0
T7	870332	548259	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	71857	44410	0	0
T11	66576	33288	0	0
T12	137240	68134	0	0
T13	1690666	837160	0	0
T14	222602	1105148	0	0
T15	0	122686	0	0
T16	0	144	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	582747048	0	0
T1	654	561	0	0
T2	1737216	1734141	0	0
T3	756021	755296	0	0
T4	175401	108904	0	0
T5	1457	1399	0	0
T6	5731	5216	0	0
T7	870332	548259	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	71857	44410	0	0
T11	66576	33288	0	0
T12	137240	68134	0	0
T13	1690666	837160	0	0
T14	222602	1105148	0	0
T15	0	122686	0	0
T16	0	144	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	3350770	0	0
T2	1737216	17058	0	0
T3	756021	832	0	0
T4	175401	1416	0	0
T5	1457	0	0	0
T6	5731	0	0	0
T7	870332	6329	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	71857	1088	0	0
T11	66576	836	0	0
T12	137240	832	0	0
T13	1690666	22070	0	0
T14	222602	31362	0	0
T15	0	3589	0	0
T25	933	0	0	0
T27	62228	0	0	0
T30	2088	168	0	0
T32	0	7418	0	0
T33	0	98	0	0
T35	0	530	0	0
T44	0	2790	0	0
T47	0	9148	0	0
T48	0	11605	0	0
T52	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	3350770	0	0
T2	1737216	17058	0	0
T3	756021	832	0	0
T4	175401	1416	0	0
T5	1457	0	0	0
T6	5731	0	0	0
T7	870332	6329	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	71857	1088	0	0
T11	66576	836	0	0
T12	137240	832	0	0
T13	1690666	22070	0	0
T14	222602	31362	0	0
T15	0	3589	0	0
T25	933	0	0	0
T27	62228	0	0	0
T30	2088	168	0	0
T32	0	7418	0	0
T33	0	98	0	0
T35	0	530	0	0
T44	0	2790	0	0
T47	0	9148	0	0
T48	0	11605	0	0
T52	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	3350770	0	0
T2	1737216	17058	0	0
T3	756021	832	0	0
T4	175401	1416	0	0
T5	1457	0	0	0
T6	5731	0	0	0
T7	870332	6329	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	71857	1088	0	0
T11	66576	836	0	0
T12	137240	832	0	0
T13	1690666	22070	0	0
T14	222602	31362	0	0
T15	0	3589	0	0
T25	933	0	0	0
T27	62228	0	0	0
T30	2088	168	0	0
T32	0	7418	0	0
T33	0	98	0	0
T35	0	530	0	0
T44	0	2790	0	0
T47	0	9148	0	0
T48	0	11605	0	0
T52	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	3350770	0	0
T2	1737216	17058	0	0
T3	756021	832	0	0
T4	175401	1416	0	0
T5	1457	0	0	0
T6	5731	0	0	0
T7	870332	6329	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	71857	1088	0	0
T11	66576	836	0	0
T12	137240	832	0	0
T13	1690666	22070	0	0
T14	222602	31362	0	0
T15	0	3589	0	0
T25	933	0	0	0
T27	62228	0	0	0
T30	2088	168	0	0
T32	0	7418	0	0
T33	0	98	0	0
T35	0	530	0	0
T44	0	2790	0	0
T47	0	9148	0	0
T48	0	11605	0	0
T52	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	7	0	926
T13	170335	1	0	1
T14	556098	0	0	1
T15	253826	0	0	1
T16	4730	0	0	1
T26	1182	0	0	1
T27	317208	0	0	1
T28	983	0	0	1
T29	1280	0	0	1
T30	7197	0	0	1
T31	6358	0	0	1
T37	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	582747048	0	0
T1	654	561	0	0
T2	1737216	1734141	0	0
T3	756021	755296	0	0
T4	175401	108904	0	0
T5	1457	1399	0	0
T6	5731	5216	0	0
T7	870332	548259	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	71857	44410	0	0
T11	66576	33288	0	0
T12	137240	68134	0	0
T13	1690666	837160	0	0
T14	222602	1105148	0	0
T15	0	122686	0	0
T16	0	144	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	714367443	3350770	0	0
T2	1737216	17058	0	0
T3	756021	832	0	0
T4	175401	1416	0	0
T5	1457	0	0	0
T6	5731	0	0	0
T7	870332	6329	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	71857	1088	0	0
T11	66576	836	0	0
T12	137240	832	0	0
T13	1690666	22070	0	0
T14	222602	31362	0	0
T15	0	3589	0	0
T25	933	0	0	0
T27	62228	0	0	0
T30	2088	168	0	0
T32	0	7418	0	0
T33	0	98	0	0
T35	0	530	0	0
T44	0	2790	0	0
T47	0	9148	0	0
T48	0	11605	0	0
T52	0	118	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T13,T14
1	0	Covered	T4,T13,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T13
1	0	Unreachable
1	1	Covered	T4,T13,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T13,T14
0	0	1	Unreachable
0	0	0	Covered	T4,T6,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T13,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	130313696	26326168	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	130313696	612011	0	0
GntImpliesValid_A	130313696	612011	0	0
GrantKnown_A	130313696	26326168	0	0
IdxKnown_A	130313696	26326168	0	0
IndexIsCorrect_A	130313696	612011	0	0
LockArbDecision_A	130313696	0	0	0
NoReadyValidNoGrant_A	130313696	0	0	0
ReadyAndValidImplyGrant_A	130313696	612011	0	0
ReqAndReadyImplyGrant_A	130313696	612011	0	0
ReqImpliesValid_A	130313696	612011	0	0
ReqStaysHighUntilGranted0_M	130313696	0	0	0
RoundRobin_A	130313696	0	0	0
ValidKnown_A	130313696	26326168	0	0
gen_data_port_assertion.DataFlow_A	130313696	612011	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	26326168	0	0
T4	65612	64808	0	0
T6	432	432	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	152216	0	0
T14	111301	118416	0	0
T15	0	106488	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	612011	0	0
T4	65612	894	0	0
T6	432	0	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	5154	0	0
T14	111301	5209	0	0
T15	0	3588	0	0
T27	62228	0	0	0
T30	2088	112	0	0
T32	0	2418	0	0
T33	0	98	0	0
T44	0	2790	0	0
T48	0	5156	0	0
T52	0	118	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	612011	0	0
T4	65612	894	0	0
T6	432	0	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	5154	0	0
T14	111301	5209	0	0
T15	0	3588	0	0
T27	62228	0	0	0
T30	2088	112	0	0
T32	0	2418	0	0
T33	0	98	0	0
T44	0	2790	0	0
T48	0	5156	0	0
T52	0	118	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	26326168	0	0
T4	65612	64808	0	0
T6	432	432	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	152216	0	0
T14	111301	118416	0	0
T15	0	106488	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	26326168	0	0
T4	65612	64808	0	0
T6	432	432	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	152216	0	0
T14	111301	118416	0	0
T15	0	106488	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	612011	0	0
T4	65612	894	0	0
T6	432	0	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	5154	0	0
T14	111301	5209	0	0
T15	0	3588	0	0
T27	62228	0	0	0
T30	2088	112	0	0
T32	0	2418	0	0
T33	0	98	0	0
T44	0	2790	0	0
T48	0	5156	0	0
T52	0	118	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	612011	0	0
T4	65612	894	0	0
T6	432	0	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	5154	0	0
T14	111301	5209	0	0
T15	0	3588	0	0
T27	62228	0	0	0
T30	2088	112	0	0
T32	0	2418	0	0
T33	0	98	0	0
T44	0	2790	0	0
T48	0	5156	0	0
T52	0	118	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	612011	0	0
T4	65612	894	0	0
T6	432	0	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	5154	0	0
T14	111301	5209	0	0
T15	0	3588	0	0
T27	62228	0	0	0
T30	2088	112	0	0
T32	0	2418	0	0
T33	0	98	0	0
T44	0	2790	0	0
T48	0	5156	0	0
T52	0	118	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	612011	0	0
T4	65612	894	0	0
T6	432	0	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	5154	0	0
T14	111301	5209	0	0
T15	0	3588	0	0
T27	62228	0	0	0
T30	2088	112	0	0
T32	0	2418	0	0
T33	0	98	0	0
T44	0	2790	0	0
T48	0	5156	0	0
T52	0	118	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	26326168	0	0
T4	65612	64808	0	0
T6	432	432	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	152216	0	0
T14	111301	118416	0	0
T15	0	106488	0	0
T27	62228	57480	0	0
T30	2088	2088	0	0
T31	0	576	0	0
T32	0	56824	0	0
T33	0	1752	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	612011	0	0
T4	65612	894	0	0
T6	432	0	0	0
T7	320658	0	0	0
T10	26749	0	0	0
T11	33288	0	0	0
T12	68620	0	0	0
T13	845333	5154	0	0
T14	111301	5209	0	0
T15	0	3588	0	0
T27	62228	0	0	0
T30	2088	112	0	0
T32	0	2418	0	0
T33	0	98	0	0
T44	0	2790	0	0
T48	0	5156	0	0
T52	0	118	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T11

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T11
1	0	Covered	T2,T7,T11

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Unreachable
1	1	Covered	T2,T7,T11

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T7,T11
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	130313696	102765844	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	130313696	730471	0	0
GntImpliesValid_A	130313696	730471	0	0
GrantKnown_A	130313696	102765844	0	0
IdxKnown_A	130313696	102765844	0	0
IndexIsCorrect_A	130313696	730471	0	0
LockArbDecision_A	130313696	0	0	0
NoReadyValidNoGrant_A	130313696	0	0	0
ReadyAndValidImplyGrant_A	130313696	730471	0	0
ReqAndReadyImplyGrant_A	130313696	730471	0	0
ReqImpliesValid_A	130313696	730471	0	0
ReqStaysHighUntilGranted0_M	130313696	0	0	0
RoundRobin_A	130313696	0	0	0
ValidKnown_A	130313696	102765844	0	0
gen_data_port_assertion.DataFlow_A	130313696	730471	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	102765844	0	0
T2	962255	959187	0	0
T3	125717	125066	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	319248	0	0
T10	26749	26129	0	0
T11	33288	33288	0	0
T12	68620	68134	0	0
T13	845333	684944	0	0
T14	111301	986732	0	0
T15	0	16198	0	0
T16	0	144	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	730471	0	0
T2	962255	5824	0	0
T3	125717	0	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	398	0	0
T10	26749	0	0	0
T11	33288	2	0	0
T12	68620	0	0	0
T13	845333	4826	0	0
T14	111301	13025	0	0
T15	0	1	0	0
T32	0	5000	0	0
T35	0	530	0	0
T47	0	9148	0	0
T48	0	6449	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	730471	0	0
T2	962255	5824	0	0
T3	125717	0	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	398	0	0
T10	26749	0	0	0
T11	33288	2	0	0
T12	68620	0	0	0
T13	845333	4826	0	0
T14	111301	13025	0	0
T15	0	1	0	0
T32	0	5000	0	0
T35	0	530	0	0
T47	0	9148	0	0
T48	0	6449	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	102765844	0	0
T2	962255	959187	0	0
T3	125717	125066	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	319248	0	0
T10	26749	26129	0	0
T11	33288	33288	0	0
T12	68620	68134	0	0
T13	845333	684944	0	0
T14	111301	986732	0	0
T15	0	16198	0	0
T16	0	144	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	102765844	0	0
T2	962255	959187	0	0
T3	125717	125066	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	319248	0	0
T10	26749	26129	0	0
T11	33288	33288	0	0
T12	68620	68134	0	0
T13	845333	684944	0	0
T14	111301	986732	0	0
T15	0	16198	0	0
T16	0	144	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	730471	0	0
T2	962255	5824	0	0
T3	125717	0	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	398	0	0
T10	26749	0	0	0
T11	33288	2	0	0
T12	68620	0	0	0
T13	845333	4826	0	0
T14	111301	13025	0	0
T15	0	1	0	0
T32	0	5000	0	0
T35	0	530	0	0
T47	0	9148	0	0
T48	0	6449	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	730471	0	0
T2	962255	5824	0	0
T3	125717	0	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	398	0	0
T10	26749	0	0	0
T11	33288	2	0	0
T12	68620	0	0	0
T13	845333	4826	0	0
T14	111301	13025	0	0
T15	0	1	0	0
T32	0	5000	0	0
T35	0	530	0	0
T47	0	9148	0	0
T48	0	6449	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	730471	0	0
T2	962255	5824	0	0
T3	125717	0	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	398	0	0
T10	26749	0	0	0
T11	33288	2	0	0
T12	68620	0	0	0
T13	845333	4826	0	0
T14	111301	13025	0	0
T15	0	1	0	0
T32	0	5000	0	0
T35	0	530	0	0
T47	0	9148	0	0
T48	0	6449	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	730471	0	0
T2	962255	5824	0	0
T3	125717	0	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	398	0	0
T10	26749	0	0	0
T11	33288	2	0	0
T12	68620	0	0	0
T13	845333	4826	0	0
T14	111301	13025	0	0
T15	0	1	0	0
T32	0	5000	0	0
T35	0	530	0	0
T47	0	9148	0	0
T48	0	6449	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	102765844	0	0
T2	962255	959187	0	0
T3	125717	125066	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	319248	0	0
T10	26749	26129	0	0
T11	33288	33288	0	0
T12	68620	68134	0	0
T13	845333	684944	0	0
T14	111301	986732	0	0
T15	0	16198	0	0
T16	0	144	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130313696	730471	0	0
T2	962255	5824	0	0
T3	125717	0	0	0
T4	65612	0	0	0
T6	432	0	0	0
T7	320658	398	0	0
T10	26749	0	0	0
T11	33288	2	0	0
T12	68620	0	0	0
T13	845333	4826	0	0
T14	111301	13025	0	0
T15	0	1	0	0
T32	0	5000	0	0
T35	0	530	0	0
T47	0	9148	0	0
T48	0	6449	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T7

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453740051	453655036	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	453740051	2008288	0	0
GntImpliesValid_A	453740051	2008288	0	0
GrantKnown_A	453740051	453655036	0	0
IdxKnown_A	453740051	453655036	0	0
IndexIsCorrect_A	453740051	2008288	0	0
LockArbDecision_A	453740051	0	0	0
NoReadyValidNoGrant_A	453740051	0	0	0
ReadyAndValidImplyGrant_A	453740051	2008288	0	0
ReqAndReadyImplyGrant_A	453740051	2008288	0	0
ReqImpliesValid_A	453740051	2008288	0	0
ReqStaysHighUntilGranted0_M	453740051	0	0	0
RoundRobin_A	453740051	7	0	926
ValidKnown_A	453740051	453655036	0	0
gen_data_port_assertion.DataFlow_A	453740051	2008288	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	453655036	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	2008288	0	0
T2	774961	11234	0	0
T3	630304	832	0	0
T4	44177	522	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5931	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	12090	0	0
T14	0	13128	0	0
T25	933	0	0	0
T30	0	56	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	2008288	0	0
T2	774961	11234	0	0
T3	630304	832	0	0
T4	44177	522	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5931	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	12090	0	0
T14	0	13128	0	0
T25	933	0	0	0
T30	0	56	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	453655036	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	453655036	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	2008288	0	0
T2	774961	11234	0	0
T3	630304	832	0	0
T4	44177	522	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5931	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	12090	0	0
T14	0	13128	0	0
T25	933	0	0	0
T30	0	56	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	2008288	0	0
T2	774961	11234	0	0
T3	630304	832	0	0
T4	44177	522	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5931	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	12090	0	0
T14	0	13128	0	0
T25	933	0	0	0
T30	0	56	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	2008288	0	0
T2	774961	11234	0	0
T3	630304	832	0	0
T4	44177	522	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5931	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	12090	0	0
T14	0	13128	0	0
T25	933	0	0	0
T30	0	56	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	2008288	0	0
T2	774961	11234	0	0
T3	630304	832	0	0
T4	44177	522	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5931	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	12090	0	0
T14	0	13128	0	0
T25	933	0	0	0
T30	0	56	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	7	0	926
T13	170335	1	0	1
T14	556098	0	0	1
T15	253826	0	0	1
T16	4730	0	0	1
T26	1182	0	0	1
T27	317208	0	0	1
T28	983	0	0	1
T29	1280	0	0	1
T30	7197	0	0	1
T31	6358	0	0	1
T37	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	453655036	0	0
T1	654	561	0	0
T2	774961	774954	0	0
T3	630304	630230	0	0
T4	44177	44096	0	0
T5	1457	1399	0	0
T6	4867	4784	0	0
T7	229016	229011	0	0
T8	704	615	0	0
T9	1219	1154	0	0
T10	18359	18281	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453740051	2008288	0	0
T2	774961	11234	0	0
T3	630304	832	0	0
T4	44177	522	0	0
T5	1457	0	0	0
T6	4867	0	0	0
T7	229016	5931	0	0
T8	704	0	0	0
T9	1219	0	0	0
T10	18359	1088	0	0
T11	0	834	0	0
T12	0	832	0	0
T13	0	12090	0	0
T14	0	13128	0	0
T25	933	0	0	0
T30	0	56	0	0