Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3405 |
0 |
0 |
T86 |
81262 |
4 |
0 |
0 |
T87 |
20055 |
1 |
0 |
0 |
T88 |
9808 |
4 |
0 |
0 |
T89 |
7864 |
8 |
0 |
0 |
T90 |
5742 |
11 |
0 |
0 |
T93 |
5464 |
52 |
0 |
0 |
T94 |
2283 |
3 |
0 |
0 |
T103 |
4479 |
3 |
0 |
0 |
T110 |
2259 |
1 |
0 |
0 |
T114 |
4998 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2987 |
0 |
0 |
T88 |
9808 |
22 |
0 |
0 |
T118 |
157527 |
268 |
0 |
0 |
T120 |
3651 |
6 |
0 |
0 |
T123 |
7466 |
12 |
0 |
0 |
T126 |
12641 |
12 |
0 |
0 |
T137 |
12320 |
25 |
0 |
0 |
T142 |
13242 |
63 |
0 |
0 |
T143 |
20479 |
55 |
0 |
0 |
T144 |
13900 |
42 |
0 |
0 |
T145 |
11605 |
8 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2919 |
0 |
0 |
T88 |
9808 |
13 |
0 |
0 |
T118 |
157527 |
268 |
0 |
0 |
T120 |
3651 |
4 |
0 |
0 |
T122 |
4576 |
4 |
0 |
0 |
T123 |
7466 |
11 |
0 |
0 |
T137 |
12320 |
28 |
0 |
0 |
T142 |
13242 |
57 |
0 |
0 |
T143 |
20479 |
51 |
0 |
0 |
T144 |
13900 |
15 |
0 |
0 |
T145 |
11605 |
12 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3714 |
0 |
0 |
T88 |
9808 |
17 |
0 |
0 |
T115 |
3626 |
11 |
0 |
0 |
T118 |
157527 |
273 |
0 |
0 |
T122 |
4576 |
5 |
0 |
0 |
T123 |
7466 |
12 |
0 |
0 |
T137 |
12320 |
10 |
0 |
0 |
T142 |
13242 |
10 |
0 |
0 |
T143 |
20479 |
90 |
0 |
0 |
T144 |
13900 |
94 |
0 |
0 |
T145 |
11605 |
27 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
12917 |
0 |
0 |
T88 |
9808 |
152 |
0 |
0 |
T115 |
3626 |
2 |
0 |
0 |
T118 |
157527 |
247 |
0 |
0 |
T120 |
3651 |
1 |
0 |
0 |
T122 |
4576 |
118 |
0 |
0 |
T123 |
7466 |
90 |
0 |
0 |
T137 |
12320 |
5 |
0 |
0 |
T142 |
13242 |
20 |
0 |
0 |
T143 |
20479 |
45 |
0 |
0 |
T144 |
13900 |
14 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
12075 |
0 |
0 |
T88 |
9808 |
268 |
0 |
0 |
T115 |
3626 |
6 |
0 |
0 |
T118 |
157527 |
287 |
0 |
0 |
T122 |
4576 |
119 |
0 |
0 |
T123 |
7466 |
80 |
0 |
0 |
T137 |
12320 |
55 |
0 |
0 |
T142 |
13242 |
28 |
0 |
0 |
T143 |
20479 |
39 |
0 |
0 |
T144 |
13900 |
25 |
0 |
0 |
T145 |
11605 |
20 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
12300 |
0 |
0 |
T88 |
9808 |
98 |
0 |
0 |
T115 |
3626 |
71 |
0 |
0 |
T118 |
157527 |
291 |
0 |
0 |
T122 |
4576 |
126 |
0 |
0 |
T123 |
7466 |
100 |
0 |
0 |
T137 |
12320 |
59 |
0 |
0 |
T142 |
13242 |
18 |
0 |
0 |
T143 |
20479 |
91 |
0 |
0 |
T144 |
13900 |
62 |
0 |
0 |
T145 |
11605 |
22 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
12057 |
0 |
0 |
T88 |
9808 |
144 |
0 |
0 |
T115 |
3626 |
51 |
0 |
0 |
T118 |
157527 |
272 |
0 |
0 |
T120 |
3651 |
96 |
0 |
0 |
T122 |
4576 |
117 |
0 |
0 |
T123 |
7466 |
67 |
0 |
0 |
T137 |
12320 |
5 |
0 |
0 |
T142 |
13242 |
21 |
0 |
0 |
T143 |
20479 |
26 |
0 |
0 |
T144 |
13900 |
47 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
13267 |
0 |
0 |
T88 |
9808 |
132 |
0 |
0 |
T118 |
157527 |
307 |
0 |
0 |
T120 |
3651 |
111 |
0 |
0 |
T123 |
7466 |
141 |
0 |
0 |
T126 |
12641 |
137 |
0 |
0 |
T137 |
12320 |
16 |
0 |
0 |
T142 |
13242 |
40 |
0 |
0 |
T143 |
20479 |
51 |
0 |
0 |
T144 |
13900 |
33 |
0 |
0 |
T145 |
11605 |
27 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
12447 |
0 |
0 |
T88 |
9808 |
4 |
0 |
0 |
T118 |
157527 |
255 |
0 |
0 |
T120 |
3651 |
107 |
0 |
0 |
T122 |
4576 |
120 |
0 |
0 |
T123 |
7466 |
51 |
0 |
0 |
T137 |
12320 |
3 |
0 |
0 |
T142 |
13242 |
34 |
0 |
0 |
T143 |
20479 |
50 |
0 |
0 |
T144 |
13900 |
61 |
0 |
0 |
T145 |
11605 |
10 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
11333 |
0 |
0 |
T88 |
9808 |
138 |
0 |
0 |
T118 |
157527 |
293 |
0 |
0 |
T120 |
3651 |
94 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T123 |
7466 |
67 |
0 |
0 |
T137 |
12320 |
7 |
0 |
0 |
T142 |
13242 |
19 |
0 |
0 |
T143 |
20479 |
88 |
0 |
0 |
T144 |
13900 |
34 |
0 |
0 |
T145 |
11605 |
18 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
13264 |
0 |
0 |
T88 |
9808 |
117 |
0 |
0 |
T115 |
3626 |
9 |
0 |
0 |
T118 |
157527 |
311 |
0 |
0 |
T120 |
3651 |
1 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T123 |
7466 |
137 |
0 |
0 |
T137 |
12320 |
14 |
0 |
0 |
T142 |
13242 |
24 |
0 |
0 |
T143 |
20479 |
100 |
0 |
0 |
T144 |
13900 |
54 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6624 |
0 |
0 |
T88 |
9808 |
12 |
0 |
0 |
T115 |
3626 |
6 |
0 |
0 |
T118 |
157527 |
308 |
0 |
0 |
T120 |
3651 |
2 |
0 |
0 |
T122 |
4576 |
43 |
0 |
0 |
T123 |
7466 |
48 |
0 |
0 |
T137 |
12320 |
21 |
0 |
0 |
T142 |
13242 |
42 |
0 |
0 |
T143 |
20479 |
62 |
0 |
0 |
T144 |
13900 |
71 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6771 |
0 |
0 |
T88 |
9808 |
96 |
0 |
0 |
T115 |
3626 |
3 |
0 |
0 |
T118 |
157527 |
253 |
0 |
0 |
T120 |
3651 |
1 |
0 |
0 |
T122 |
4576 |
7 |
0 |
0 |
T123 |
7466 |
19 |
0 |
0 |
T137 |
12320 |
8 |
0 |
0 |
T142 |
13242 |
22 |
0 |
0 |
T143 |
20479 |
47 |
0 |
0 |
T144 |
13900 |
58 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6554 |
0 |
0 |
T88 |
9808 |
27 |
0 |
0 |
T115 |
3626 |
10 |
0 |
0 |
T118 |
157527 |
358 |
0 |
0 |
T120 |
3651 |
9 |
0 |
0 |
T122 |
4576 |
2 |
0 |
0 |
T123 |
7466 |
26 |
0 |
0 |
T137 |
12320 |
22 |
0 |
0 |
T142 |
13242 |
45 |
0 |
0 |
T143 |
20479 |
78 |
0 |
0 |
T144 |
13900 |
57 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6908 |
0 |
0 |
T88 |
9808 |
62 |
0 |
0 |
T115 |
3626 |
41 |
0 |
0 |
T118 |
157527 |
316 |
0 |
0 |
T120 |
3651 |
5 |
0 |
0 |
T122 |
4576 |
4 |
0 |
0 |
T123 |
7466 |
33 |
0 |
0 |
T137 |
12320 |
28 |
0 |
0 |
T142 |
13242 |
16 |
0 |
0 |
T143 |
20479 |
39 |
0 |
0 |
T144 |
13900 |
33 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6513 |
0 |
0 |
T88 |
9808 |
10 |
0 |
0 |
T115 |
3626 |
7 |
0 |
0 |
T118 |
157527 |
245 |
0 |
0 |
T120 |
3651 |
7 |
0 |
0 |
T122 |
4576 |
6 |
0 |
0 |
T123 |
7466 |
12 |
0 |
0 |
T137 |
12320 |
35 |
0 |
0 |
T142 |
13242 |
8 |
0 |
0 |
T143 |
20479 |
67 |
0 |
0 |
T144 |
13900 |
33 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6453 |
0 |
0 |
T88 |
9808 |
7 |
0 |
0 |
T115 |
3626 |
36 |
0 |
0 |
T118 |
157527 |
253 |
0 |
0 |
T120 |
3651 |
35 |
0 |
0 |
T122 |
4576 |
7 |
0 |
0 |
T123 |
7466 |
28 |
0 |
0 |
T137 |
12320 |
32 |
0 |
0 |
T142 |
13242 |
14 |
0 |
0 |
T143 |
20479 |
75 |
0 |
0 |
T144 |
13900 |
84 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6598 |
0 |
0 |
T88 |
9808 |
57 |
0 |
0 |
T115 |
3626 |
17 |
0 |
0 |
T118 |
157527 |
231 |
0 |
0 |
T120 |
3651 |
5 |
0 |
0 |
T122 |
4576 |
41 |
0 |
0 |
T123 |
7466 |
25 |
0 |
0 |
T137 |
12320 |
35 |
0 |
0 |
T142 |
13242 |
4 |
0 |
0 |
T143 |
20479 |
60 |
0 |
0 |
T144 |
13900 |
58 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6320 |
0 |
0 |
T88 |
9808 |
54 |
0 |
0 |
T118 |
157527 |
266 |
0 |
0 |
T120 |
3651 |
41 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T123 |
7466 |
23 |
0 |
0 |
T137 |
12320 |
9 |
0 |
0 |
T142 |
13242 |
22 |
0 |
0 |
T143 |
20479 |
90 |
0 |
0 |
T144 |
13900 |
21 |
0 |
0 |
T145 |
11605 |
20 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6535 |
0 |
0 |
T88 |
9808 |
114 |
0 |
0 |
T118 |
157527 |
285 |
0 |
0 |
T120 |
3651 |
8 |
0 |
0 |
T122 |
4576 |
2 |
0 |
0 |
T123 |
7466 |
20 |
0 |
0 |
T137 |
12320 |
12 |
0 |
0 |
T142 |
13242 |
23 |
0 |
0 |
T143 |
20479 |
59 |
0 |
0 |
T144 |
13900 |
72 |
0 |
0 |
T145 |
11605 |
2 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
7281 |
0 |
0 |
T88 |
9808 |
70 |
0 |
0 |
T115 |
3626 |
26 |
0 |
0 |
T118 |
157527 |
293 |
0 |
0 |
T120 |
3651 |
37 |
0 |
0 |
T122 |
4576 |
48 |
0 |
0 |
T137 |
12320 |
54 |
0 |
0 |
T142 |
13242 |
25 |
0 |
0 |
T143 |
20479 |
58 |
0 |
0 |
T144 |
13900 |
56 |
0 |
0 |
T145 |
11605 |
8 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6548 |
0 |
0 |
T88 |
9808 |
57 |
0 |
0 |
T115 |
3626 |
8 |
0 |
0 |
T118 |
157527 |
231 |
0 |
0 |
T120 |
3651 |
7 |
0 |
0 |
T122 |
4576 |
42 |
0 |
0 |
T123 |
7466 |
52 |
0 |
0 |
T137 |
12320 |
22 |
0 |
0 |
T142 |
13242 |
26 |
0 |
0 |
T143 |
20479 |
62 |
0 |
0 |
T144 |
13900 |
55 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6870 |
0 |
0 |
T88 |
9808 |
50 |
0 |
0 |
T118 |
157527 |
183 |
0 |
0 |
T120 |
3651 |
48 |
0 |
0 |
T122 |
4576 |
2 |
0 |
0 |
T123 |
7466 |
65 |
0 |
0 |
T137 |
12320 |
12 |
0 |
0 |
T142 |
13242 |
21 |
0 |
0 |
T143 |
20479 |
35 |
0 |
0 |
T144 |
13900 |
55 |
0 |
0 |
T145 |
11605 |
6 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
7119 |
0 |
0 |
T88 |
9808 |
46 |
0 |
0 |
T115 |
3626 |
25 |
0 |
0 |
T118 |
157527 |
303 |
0 |
0 |
T120 |
3651 |
29 |
0 |
0 |
T122 |
4576 |
47 |
0 |
0 |
T123 |
7466 |
35 |
0 |
0 |
T137 |
12320 |
34 |
0 |
0 |
T142 |
13242 |
63 |
0 |
0 |
T143 |
20479 |
17 |
0 |
0 |
T144 |
13900 |
38 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
7203 |
0 |
0 |
T88 |
9808 |
18 |
0 |
0 |
T115 |
3626 |
16 |
0 |
0 |
T118 |
157527 |
217 |
0 |
0 |
T120 |
3651 |
2 |
0 |
0 |
T122 |
4576 |
2 |
0 |
0 |
T123 |
7466 |
48 |
0 |
0 |
T137 |
12320 |
15 |
0 |
0 |
T142 |
13242 |
9 |
0 |
0 |
T143 |
20479 |
54 |
0 |
0 |
T144 |
13900 |
59 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6111 |
0 |
0 |
T88 |
9808 |
103 |
0 |
0 |
T118 |
157527 |
291 |
0 |
0 |
T120 |
3651 |
44 |
0 |
0 |
T122 |
4576 |
59 |
0 |
0 |
T123 |
7466 |
21 |
0 |
0 |
T137 |
12320 |
39 |
0 |
0 |
T142 |
13242 |
8 |
0 |
0 |
T143 |
20479 |
39 |
0 |
0 |
T144 |
13900 |
24 |
0 |
0 |
T145 |
11605 |
23 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6825 |
0 |
0 |
T88 |
9808 |
6 |
0 |
0 |
T115 |
3626 |
11 |
0 |
0 |
T118 |
157527 |
278 |
0 |
0 |
T120 |
3651 |
7 |
0 |
0 |
T122 |
4576 |
7 |
0 |
0 |
T123 |
7466 |
19 |
0 |
0 |
T137 |
12320 |
5 |
0 |
0 |
T142 |
13242 |
12 |
0 |
0 |
T143 |
20479 |
60 |
0 |
0 |
T144 |
13900 |
34 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6090 |
0 |
0 |
T88 |
9808 |
38 |
0 |
0 |
T115 |
3626 |
19 |
0 |
0 |
T118 |
157527 |
250 |
0 |
0 |
T120 |
3651 |
38 |
0 |
0 |
T122 |
4576 |
4 |
0 |
0 |
T123 |
7466 |
45 |
0 |
0 |
T137 |
12320 |
49 |
0 |
0 |
T142 |
13242 |
16 |
0 |
0 |
T143 |
20479 |
94 |
0 |
0 |
T144 |
13900 |
56 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6862 |
0 |
0 |
T88 |
9808 |
67 |
0 |
0 |
T115 |
3626 |
47 |
0 |
0 |
T118 |
157527 |
325 |
0 |
0 |
T122 |
4576 |
6 |
0 |
0 |
T126 |
12641 |
86 |
0 |
0 |
T137 |
12320 |
19 |
0 |
0 |
T142 |
13242 |
1 |
0 |
0 |
T143 |
20479 |
41 |
0 |
0 |
T144 |
13900 |
78 |
0 |
0 |
T145 |
11605 |
14 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6657 |
0 |
0 |
T88 |
9808 |
7 |
0 |
0 |
T115 |
3626 |
8 |
0 |
0 |
T118 |
157527 |
223 |
0 |
0 |
T120 |
3651 |
9 |
0 |
0 |
T122 |
4576 |
57 |
0 |
0 |
T123 |
7466 |
21 |
0 |
0 |
T137 |
12320 |
27 |
0 |
0 |
T142 |
13242 |
16 |
0 |
0 |
T143 |
20479 |
105 |
0 |
0 |
T144 |
13900 |
48 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6254 |
0 |
0 |
T88 |
9808 |
72 |
0 |
0 |
T115 |
3626 |
22 |
0 |
0 |
T118 |
157527 |
248 |
0 |
0 |
T120 |
3651 |
4 |
0 |
0 |
T122 |
4576 |
52 |
0 |
0 |
T123 |
7466 |
23 |
0 |
0 |
T137 |
12320 |
37 |
0 |
0 |
T142 |
13242 |
31 |
0 |
0 |
T143 |
20479 |
30 |
0 |
0 |
T144 |
13900 |
42 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
7378 |
0 |
0 |
T88 |
9808 |
41 |
0 |
0 |
T118 |
157527 |
288 |
0 |
0 |
T120 |
3651 |
45 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T123 |
7466 |
19 |
0 |
0 |
T137 |
12320 |
21 |
0 |
0 |
T142 |
13242 |
26 |
0 |
0 |
T143 |
20479 |
111 |
0 |
0 |
T144 |
13900 |
79 |
0 |
0 |
T145 |
11605 |
22 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
7150 |
0 |
0 |
T88 |
9808 |
7 |
0 |
0 |
T115 |
3626 |
32 |
0 |
0 |
T118 |
157527 |
236 |
0 |
0 |
T120 |
3651 |
1 |
0 |
0 |
T122 |
4576 |
2 |
0 |
0 |
T123 |
7466 |
51 |
0 |
0 |
T137 |
12320 |
14 |
0 |
0 |
T142 |
13242 |
12 |
0 |
0 |
T143 |
20479 |
83 |
0 |
0 |
T144 |
13900 |
68 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
6650 |
0 |
0 |
T88 |
9808 |
47 |
0 |
0 |
T115 |
3626 |
25 |
0 |
0 |
T118 |
157527 |
233 |
0 |
0 |
T120 |
3651 |
1 |
0 |
0 |
T122 |
4576 |
39 |
0 |
0 |
T123 |
7466 |
10 |
0 |
0 |
T137 |
12320 |
12 |
0 |
0 |
T142 |
13242 |
13 |
0 |
0 |
T143 |
20479 |
100 |
0 |
0 |
T144 |
13900 |
20 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
7056 |
0 |
0 |
T88 |
9808 |
152 |
0 |
0 |
T115 |
3626 |
17 |
0 |
0 |
T118 |
157527 |
249 |
0 |
0 |
T120 |
3651 |
9 |
0 |
0 |
T122 |
4576 |
49 |
0 |
0 |
T137 |
12320 |
34 |
0 |
0 |
T142 |
13242 |
47 |
0 |
0 |
T143 |
20479 |
97 |
0 |
0 |
T144 |
13900 |
73 |
0 |
0 |
T145 |
11605 |
15 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3254 |
0 |
0 |
T88 |
9808 |
6 |
0 |
0 |
T118 |
157527 |
294 |
0 |
0 |
T120 |
3651 |
9 |
0 |
0 |
T122 |
4576 |
6 |
0 |
0 |
T126 |
12641 |
21 |
0 |
0 |
T137 |
12320 |
8 |
0 |
0 |
T142 |
13242 |
29 |
0 |
0 |
T143 |
20479 |
84 |
0 |
0 |
T144 |
13900 |
32 |
0 |
0 |
T145 |
11605 |
23 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3106 |
0 |
0 |
T88 |
9808 |
21 |
0 |
0 |
T118 |
157527 |
188 |
0 |
0 |
T123 |
7466 |
5 |
0 |
0 |
T126 |
12641 |
15 |
0 |
0 |
T137 |
12320 |
29 |
0 |
0 |
T142 |
13242 |
73 |
0 |
0 |
T143 |
20479 |
96 |
0 |
0 |
T144 |
13900 |
16 |
0 |
0 |
T145 |
11605 |
2 |
0 |
0 |
T146 |
37116 |
181 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3499 |
0 |
0 |
T88 |
9808 |
24 |
0 |
0 |
T115 |
3626 |
2 |
0 |
0 |
T118 |
157527 |
290 |
0 |
0 |
T122 |
4576 |
4 |
0 |
0 |
T123 |
7466 |
7 |
0 |
0 |
T137 |
12320 |
30 |
0 |
0 |
T142 |
13242 |
22 |
0 |
0 |
T143 |
20479 |
85 |
0 |
0 |
T144 |
13900 |
67 |
0 |
0 |
T145 |
11605 |
17 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3360 |
0 |
0 |
T88 |
9808 |
13 |
0 |
0 |
T118 |
157527 |
318 |
0 |
0 |
T120 |
3651 |
3 |
0 |
0 |
T122 |
4576 |
8 |
0 |
0 |
T123 |
7466 |
2 |
0 |
0 |
T137 |
12320 |
25 |
0 |
0 |
T142 |
13242 |
42 |
0 |
0 |
T143 |
20479 |
67 |
0 |
0 |
T144 |
13900 |
78 |
0 |
0 |
T145 |
11605 |
21 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3860 |
0 |
0 |
T88 |
9808 |
25 |
0 |
0 |
T115 |
3626 |
2 |
0 |
0 |
T118 |
157527 |
246 |
0 |
0 |
T120 |
3651 |
20 |
0 |
0 |
T122 |
4576 |
27 |
0 |
0 |
T123 |
7466 |
2 |
0 |
0 |
T137 |
12320 |
14 |
0 |
0 |
T142 |
13242 |
57 |
0 |
0 |
T143 |
20479 |
105 |
0 |
0 |
T144 |
13900 |
51 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
5664 |
0 |
0 |
T20 |
3939 |
43 |
0 |
0 |
T115 |
0 |
16 |
0 |
0 |
T147 |
0 |
58 |
0 |
0 |
T148 |
0 |
10 |
0 |
0 |
T149 |
0 |
52 |
0 |
0 |
T150 |
0 |
29 |
0 |
0 |
T151 |
0 |
110 |
0 |
0 |
T152 |
0 |
30 |
0 |
0 |
T153 |
0 |
27 |
0 |
0 |
T154 |
0 |
5 |
0 |
0 |
T155 |
75858 |
0 |
0 |
0 |
T156 |
19725 |
0 |
0 |
0 |
T157 |
1269 |
0 |
0 |
0 |
T158 |
233090 |
0 |
0 |
0 |
T159 |
119812 |
0 |
0 |
0 |
T160 |
13459 |
0 |
0 |
0 |
T161 |
1398 |
0 |
0 |
0 |
T162 |
3114 |
0 |
0 |
0 |
T163 |
4794 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3268 |
0 |
0 |
T88 |
9808 |
15 |
0 |
0 |
T115 |
3626 |
1 |
0 |
0 |
T118 |
157527 |
289 |
0 |
0 |
T120 |
3651 |
5 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T123 |
7466 |
11 |
0 |
0 |
T137 |
12320 |
7 |
0 |
0 |
T142 |
13242 |
26 |
0 |
0 |
T143 |
20479 |
69 |
0 |
0 |
T144 |
13900 |
58 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3426 |
0 |
0 |
T88 |
9808 |
10 |
0 |
0 |
T115 |
3626 |
3 |
0 |
0 |
T118 |
157527 |
246 |
0 |
0 |
T120 |
3651 |
4 |
0 |
0 |
T122 |
4576 |
4 |
0 |
0 |
T123 |
7466 |
8 |
0 |
0 |
T137 |
12320 |
21 |
0 |
0 |
T142 |
13242 |
35 |
0 |
0 |
T143 |
20479 |
88 |
0 |
0 |
T144 |
13900 |
61 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2985 |
0 |
0 |
T88 |
9808 |
15 |
0 |
0 |
T118 |
157527 |
297 |
0 |
0 |
T120 |
3651 |
4 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T123 |
7466 |
9 |
0 |
0 |
T137 |
12320 |
13 |
0 |
0 |
T142 |
13242 |
17 |
0 |
0 |
T143 |
20479 |
50 |
0 |
0 |
T144 |
13900 |
55 |
0 |
0 |
T145 |
11605 |
34 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2958 |
0 |
0 |
T88 |
9808 |
4 |
0 |
0 |
T115 |
3626 |
7 |
0 |
0 |
T118 |
157527 |
287 |
0 |
0 |
T120 |
3651 |
8 |
0 |
0 |
T122 |
4576 |
2 |
0 |
0 |
T137 |
12320 |
23 |
0 |
0 |
T142 |
13242 |
39 |
0 |
0 |
T143 |
20479 |
56 |
0 |
0 |
T144 |
13900 |
57 |
0 |
0 |
T145 |
11605 |
48 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3099 |
0 |
0 |
T88 |
9808 |
11 |
0 |
0 |
T118 |
157527 |
276 |
0 |
0 |
T120 |
3651 |
2 |
0 |
0 |
T123 |
7466 |
14 |
0 |
0 |
T126 |
12641 |
14 |
0 |
0 |
T137 |
12320 |
43 |
0 |
0 |
T142 |
13242 |
42 |
0 |
0 |
T143 |
20479 |
57 |
0 |
0 |
T144 |
13900 |
53 |
0 |
0 |
T145 |
11605 |
16 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3025 |
0 |
0 |
T88 |
9808 |
17 |
0 |
0 |
T118 |
157527 |
228 |
0 |
0 |
T120 |
3651 |
4 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T126 |
12641 |
8 |
0 |
0 |
T137 |
12320 |
31 |
0 |
0 |
T142 |
13242 |
16 |
0 |
0 |
T143 |
20479 |
121 |
0 |
0 |
T144 |
13900 |
72 |
0 |
0 |
T145 |
11605 |
25 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3989 |
0 |
0 |
T88 |
9808 |
30 |
0 |
0 |
T118 |
157527 |
266 |
0 |
0 |
T120 |
3651 |
14 |
0 |
0 |
T123 |
7466 |
4 |
0 |
0 |
T126 |
12641 |
42 |
0 |
0 |
T137 |
12320 |
38 |
0 |
0 |
T142 |
13242 |
19 |
0 |
0 |
T143 |
20479 |
77 |
0 |
0 |
T144 |
13900 |
53 |
0 |
0 |
T145 |
11605 |
50 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2924 |
0 |
0 |
T88 |
9808 |
6 |
0 |
0 |
T118 |
157527 |
255 |
0 |
0 |
T120 |
3651 |
4 |
0 |
0 |
T122 |
4576 |
6 |
0 |
0 |
T126 |
12641 |
13 |
0 |
0 |
T137 |
12320 |
9 |
0 |
0 |
T142 |
13242 |
40 |
0 |
0 |
T143 |
20479 |
84 |
0 |
0 |
T144 |
13900 |
76 |
0 |
0 |
T145 |
11605 |
22 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
4179 |
0 |
0 |
T88 |
9808 |
34 |
0 |
0 |
T115 |
3626 |
6 |
0 |
0 |
T118 |
157527 |
269 |
0 |
0 |
T122 |
4576 |
12 |
0 |
0 |
T123 |
7466 |
27 |
0 |
0 |
T137 |
12320 |
15 |
0 |
0 |
T142 |
13242 |
30 |
0 |
0 |
T143 |
20479 |
91 |
0 |
0 |
T144 |
13900 |
55 |
0 |
0 |
T145 |
11605 |
20 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3312 |
0 |
0 |
T88 |
9808 |
10 |
0 |
0 |
T93 |
5464 |
4 |
0 |
0 |
T118 |
157527 |
324 |
0 |
0 |
T122 |
4576 |
15 |
0 |
0 |
T123 |
7466 |
10 |
0 |
0 |
T137 |
12320 |
39 |
0 |
0 |
T142 |
13242 |
11 |
0 |
0 |
T143 |
20479 |
59 |
0 |
0 |
T144 |
13900 |
33 |
0 |
0 |
T145 |
11605 |
18 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2846 |
0 |
0 |
T88 |
9808 |
18 |
0 |
0 |
T115 |
3626 |
6 |
0 |
0 |
T118 |
157527 |
306 |
0 |
0 |
T122 |
4576 |
9 |
0 |
0 |
T123 |
7466 |
3 |
0 |
0 |
T137 |
12320 |
15 |
0 |
0 |
T142 |
13242 |
8 |
0 |
0 |
T143 |
20479 |
6 |
0 |
0 |
T144 |
13900 |
19 |
0 |
0 |
T145 |
11605 |
24 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3010 |
0 |
0 |
T88 |
9808 |
8 |
0 |
0 |
T115 |
3626 |
4 |
0 |
0 |
T118 |
157527 |
275 |
0 |
0 |
T122 |
4576 |
5 |
0 |
0 |
T126 |
12641 |
5 |
0 |
0 |
T137 |
12320 |
26 |
0 |
0 |
T142 |
13242 |
28 |
0 |
0 |
T143 |
20479 |
52 |
0 |
0 |
T144 |
13900 |
49 |
0 |
0 |
T145 |
11605 |
7 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2870 |
0 |
0 |
T88 |
9808 |
4 |
0 |
0 |
T118 |
157527 |
304 |
0 |
0 |
T120 |
3651 |
4 |
0 |
0 |
T122 |
4576 |
10 |
0 |
0 |
T123 |
7466 |
7 |
0 |
0 |
T137 |
12320 |
28 |
0 |
0 |
T142 |
13242 |
4 |
0 |
0 |
T143 |
20479 |
57 |
0 |
0 |
T144 |
13900 |
22 |
0 |
0 |
T145 |
11605 |
16 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2872 |
0 |
0 |
T88 |
9808 |
12 |
0 |
0 |
T118 |
157527 |
283 |
0 |
0 |
T120 |
3651 |
2 |
0 |
0 |
T122 |
4576 |
3 |
0 |
0 |
T123 |
7466 |
9 |
0 |
0 |
T137 |
12320 |
41 |
0 |
0 |
T142 |
13242 |
25 |
0 |
0 |
T143 |
20479 |
41 |
0 |
0 |
T144 |
13900 |
12 |
0 |
0 |
T145 |
11605 |
14 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
2963 |
0 |
0 |
T88 |
9808 |
9 |
0 |
0 |
T115 |
3626 |
7 |
0 |
0 |
T118 |
157527 |
282 |
0 |
0 |
T120 |
3651 |
1 |
0 |
0 |
T122 |
4576 |
6 |
0 |
0 |
T123 |
7466 |
10 |
0 |
0 |
T137 |
12320 |
37 |
0 |
0 |
T142 |
13242 |
19 |
0 |
0 |
T143 |
20479 |
56 |
0 |
0 |
T144 |
13900 |
48 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
456361766 |
3032 |
0 |
0 |
T88 |
9808 |
12 |
0 |
0 |
T115 |
3626 |
2 |
0 |
0 |
T118 |
157527 |
323 |
0 |
0 |
T123 |
7466 |
15 |
0 |
0 |
T126 |
12641 |
7 |
0 |
0 |
T137 |
12320 |
22 |
0 |
0 |
T142 |
13242 |
4 |
0 |
0 |
T143 |
20479 |
68 |
0 |
0 |
T144 |
13900 |
67 |
0 |
0 |
T145 |
11605 |
46 |
0 |
0 |