Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.07 98.62 89.36 97.28 95.43 99.25


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1026 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2245641235 Jun 25 06:30:20 PM PDT 24 Jun 25 06:30:24 PM PDT 24 360157280 ps
T1027 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3017493118 Jun 25 06:30:58 PM PDT 24 Jun 25 06:31:02 PM PDT 24 40146689 ps
T128 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1064252443 Jun 25 06:30:15 PM PDT 24 Jun 25 06:30:55 PM PDT 24 4780407948 ps
T1028 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1365992526 Jun 25 06:30:44 PM PDT 24 Jun 25 06:30:46 PM PDT 24 25114163 ps
T102 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1913962756 Jun 25 06:30:21 PM PDT 24 Jun 25 06:30:26 PM PDT 24 80044568 ps
T1029 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3212588784 Jun 25 06:30:33 PM PDT 24 Jun 25 06:30:34 PM PDT 24 17363551 ps
T1030 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.15012848 Jun 25 06:30:17 PM PDT 24 Jun 25 06:30:19 PM PDT 24 11480516 ps
T1031 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3798147172 Jun 25 06:30:38 PM PDT 24 Jun 25 06:30:41 PM PDT 24 156238712 ps
T1032 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.484983776 Jun 25 06:30:44 PM PDT 24 Jun 25 06:30:46 PM PDT 24 11164153 ps
T1033 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.609354484 Jun 25 06:30:16 PM PDT 24 Jun 25 06:30:19 PM PDT 24 30694525 ps
T1034 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1185252458 Jun 25 06:30:10 PM PDT 24 Jun 25 06:30:15 PM PDT 24 444443387 ps
T1035 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.387213426 Jun 25 06:30:12 PM PDT 24 Jun 25 06:30:17 PM PDT 24 651351382 ps
T178 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1446616453 Jun 25 06:30:09 PM PDT 24 Jun 25 06:30:34 PM PDT 24 1057417038 ps
T1036 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3231397049 Jun 25 06:30:38 PM PDT 24 Jun 25 06:30:42 PM PDT 24 101178858 ps
T1037 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.970767901 Jun 25 06:30:28 PM PDT 24 Jun 25 06:30:30 PM PDT 24 90747358 ps
T1038 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4121757818 Jun 25 06:30:04 PM PDT 24 Jun 25 06:30:08 PM PDT 24 33046610 ps
T72 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1880933612 Jun 25 06:30:16 PM PDT 24 Jun 25 06:30:20 PM PDT 24 22463974 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3592565667 Jun 25 06:30:14 PM PDT 24 Jun 25 06:30:16 PM PDT 24 157895841 ps
T1040 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.989234165 Jun 25 06:30:37 PM PDT 24 Jun 25 06:30:43 PM PDT 24 179405475 ps
T99 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3318495759 Jun 25 06:30:22 PM PDT 24 Jun 25 06:30:26 PM PDT 24 41430056 ps
T1041 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3460834848 Jun 25 06:30:20 PM PDT 24 Jun 25 06:30:22 PM PDT 24 11239582 ps
T175 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1641641235 Jun 25 06:30:04 PM PDT 24 Jun 25 06:30:13 PM PDT 24 372509393 ps
T97 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.768245242 Jun 25 06:30:21 PM PDT 24 Jun 25 06:30:26 PM PDT 24 143130383 ps
T98 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4021142962 Jun 25 06:30:37 PM PDT 24 Jun 25 06:30:40 PM PDT 24 29559445 ps
T1042 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3888287617 Jun 25 06:30:36 PM PDT 24 Jun 25 06:30:41 PM PDT 24 147743058 ps
T1043 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1319260747 Jun 25 06:30:14 PM PDT 24 Jun 25 06:30:18 PM PDT 24 286158786 ps
T100 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2863209577 Jun 25 06:30:29 PM PDT 24 Jun 25 06:30:32 PM PDT 24 192372219 ps
T112 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.980251923 Jun 25 06:30:34 PM PDT 24 Jun 25 06:30:37 PM PDT 24 29481374 ps
T185 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1634607038 Jun 25 06:30:38 PM PDT 24 Jun 25 06:30:47 PM PDT 24 1437476250 ps
T1044 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2824483872 Jun 25 06:30:38 PM PDT 24 Jun 25 06:30:42 PM PDT 24 544058285 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1986127262 Jun 25 06:30:09 PM PDT 24 Jun 25 06:30:20 PM PDT 24 1866094834 ps
T180 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1128326420 Jun 25 06:30:15 PM PDT 24 Jun 25 06:30:33 PM PDT 24 12861841475 ps
T1046 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.901592702 Jun 25 06:30:44 PM PDT 24 Jun 25 06:30:46 PM PDT 24 14677618 ps
T1047 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1103281285 Jun 25 06:30:44 PM PDT 24 Jun 25 06:30:47 PM PDT 24 57226264 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3515240051 Jun 25 06:30:13 PM PDT 24 Jun 25 06:30:15 PM PDT 24 37702083 ps
T1049 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3852362071 Jun 25 06:30:46 PM PDT 24 Jun 25 06:30:48 PM PDT 24 31247744 ps
T183 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3313389689 Jun 25 06:30:38 PM PDT 24 Jun 25 06:30:57 PM PDT 24 299998466 ps
T1050 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1821867044 Jun 25 06:30:29 PM PDT 24 Jun 25 06:30:31 PM PDT 24 17273618 ps
T181 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1619102540 Jun 25 06:30:29 PM PDT 24 Jun 25 06:30:38 PM PDT 24 646982767 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3083875355 Jun 25 06:30:10 PM PDT 24 Jun 25 06:30:14 PM PDT 24 27333043 ps
T1052 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2584381850 Jun 25 06:30:14 PM PDT 24 Jun 25 06:30:34 PM PDT 24 558397866 ps
T1053 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4123962720 Jun 25 06:30:43 PM PDT 24 Jun 25 06:30:46 PM PDT 24 98929724 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1878857274 Jun 25 06:30:31 PM PDT 24 Jun 25 06:30:33 PM PDT 24 18587889 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1836637781 Jun 25 06:30:23 PM PDT 24 Jun 25 06:30:27 PM PDT 24 199499802 ps
T104 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3245321118 Jun 25 06:30:17 PM PDT 24 Jun 25 06:30:24 PM PDT 24 721831106 ps
T1056 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3947521789 Jun 25 06:31:01 PM PDT 24 Jun 25 06:31:04 PM PDT 24 49581505 ps
T73 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.303785035 Jun 25 06:30:09 PM PDT 24 Jun 25 06:30:12 PM PDT 24 152377532 ps
T1057 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3564921350 Jun 25 06:30:14 PM PDT 24 Jun 25 06:30:39 PM PDT 24 1074787749 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1603495614 Jun 25 06:30:08 PM PDT 24 Jun 25 06:30:23 PM PDT 24 566493036 ps
T1059 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2268319754 Jun 25 06:30:22 PM PDT 24 Jun 25 06:30:26 PM PDT 24 122944511 ps
T1060 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3740589978 Jun 25 06:30:22 PM PDT 24 Jun 25 06:30:25 PM PDT 24 120739167 ps
T1061 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2654421523 Jun 25 06:30:58 PM PDT 24 Jun 25 06:31:02 PM PDT 24 13774895 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3718508475 Jun 25 06:30:37 PM PDT 24 Jun 25 06:30:40 PM PDT 24 135448230 ps
T1063 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3568355498 Jun 25 06:30:34 PM PDT 24 Jun 25 06:30:37 PM PDT 24 78913020 ps
T184 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1218194041 Jun 25 06:30:27 PM PDT 24 Jun 25 06:30:47 PM PDT 24 302064691 ps
T174 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1689935197 Jun 25 06:30:05 PM PDT 24 Jun 25 06:30:09 PM PDT 24 110279004 ps
T1064 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2414890931 Jun 25 06:30:20 PM PDT 24 Jun 25 06:30:22 PM PDT 24 23089806 ps
T1065 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2535079334 Jun 25 06:30:37 PM PDT 24 Jun 25 06:30:40 PM PDT 24 43906213 ps
T105 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.998451404 Jun 25 06:30:19 PM PDT 24 Jun 25 06:30:26 PM PDT 24 768221251 ps
T1066 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2624053352 Jun 25 06:30:36 PM PDT 24 Jun 25 06:30:39 PM PDT 24 327385968 ps
T1067 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3172724218 Jun 25 06:30:44 PM PDT 24 Jun 25 06:30:47 PM PDT 24 14724387 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2552484758 Jun 25 06:30:14 PM PDT 24 Jun 25 06:30:18 PM PDT 24 142028957 ps
T1069 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2630877125 Jun 25 06:30:29 PM PDT 24 Jun 25 06:30:33 PM PDT 24 35068688 ps
T1070 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1442567756 Jun 25 06:30:31 PM PDT 24 Jun 25 06:30:36 PM PDT 24 181227095 ps
T1071 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2755760445 Jun 25 06:30:28 PM PDT 24 Jun 25 06:30:32 PM PDT 24 82251270 ps
T1072 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3954923303 Jun 25 06:30:28 PM PDT 24 Jun 25 06:30:32 PM PDT 24 108480935 ps
T1073 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3506977634 Jun 25 06:30:45 PM PDT 24 Jun 25 06:30:47 PM PDT 24 11271837 ps
T1074 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.711192254 Jun 25 06:30:13 PM PDT 24 Jun 25 06:30:17 PM PDT 24 101616457 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.981620237 Jun 25 06:30:15 PM PDT 24 Jun 25 06:30:32 PM PDT 24 219082149 ps
T1076 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1988881981 Jun 25 06:30:16 PM PDT 24 Jun 25 06:30:22 PM PDT 24 593138341 ps
T1077 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3517152416 Jun 25 06:30:46 PM PDT 24 Jun 25 06:30:48 PM PDT 24 57797689 ps
T1078 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2590885821 Jun 25 06:30:46 PM PDT 24 Jun 25 06:30:48 PM PDT 24 67450319 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.990255141 Jun 25 06:30:36 PM PDT 24 Jun 25 06:30:37 PM PDT 24 14982564 ps
T1080 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3605003540 Jun 25 06:30:15 PM PDT 24 Jun 25 06:30:18 PM PDT 24 232294587 ps
T176 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2748290276 Jun 25 06:30:34 PM PDT 24 Jun 25 06:30:48 PM PDT 24 403373888 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2865905727 Jun 25 06:30:15 PM PDT 24 Jun 25 06:30:34 PM PDT 24 1617819439 ps
T1082 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1502801593 Jun 25 06:30:10 PM PDT 24 Jun 25 06:30:50 PM PDT 24 2411760910 ps
T1083 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.445990858 Jun 25 06:30:29 PM PDT 24 Jun 25 06:30:34 PM PDT 24 404688388 ps
T1084 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2516505314 Jun 25 06:30:56 PM PDT 24 Jun 25 06:30:58 PM PDT 24 50138683 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2598512423 Jun 25 06:30:33 PM PDT 24 Jun 25 06:30:35 PM PDT 24 24514381 ps
T1086 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1742320009 Jun 25 06:30:57 PM PDT 24 Jun 25 06:31:01 PM PDT 24 13772176 ps
T1087 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.52221111 Jun 25 06:30:05 PM PDT 24 Jun 25 06:30:09 PM PDT 24 55023771 ps
T1088 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.532027131 Jun 25 06:30:28 PM PDT 24 Jun 25 06:30:30 PM PDT 24 318277395 ps
T107 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3925328916 Jun 25 06:30:10 PM PDT 24 Jun 25 06:30:16 PM PDT 24 344821156 ps
T1089 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3237568084 Jun 25 06:30:45 PM PDT 24 Jun 25 06:30:47 PM PDT 24 25215064 ps
T74 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2307048716 Jun 25 06:30:15 PM PDT 24 Jun 25 06:30:18 PM PDT 24 15909073 ps
T1090 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1296762518 Jun 25 06:30:44 PM PDT 24 Jun 25 06:30:46 PM PDT 24 15416005 ps
T1091 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.621241366 Jun 25 06:30:45 PM PDT 24 Jun 25 06:30:48 PM PDT 24 42378499 ps
T1092 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.112329166 Jun 25 06:30:36 PM PDT 24 Jun 25 06:30:38 PM PDT 24 227004632 ps
T179 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.788807757 Jun 25 06:30:31 PM PDT 24 Jun 25 06:30:55 PM PDT 24 10172242913 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2362752256 Jun 25 06:30:21 PM PDT 24 Jun 25 06:30:27 PM PDT 24 220829144 ps
T1094 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1121267807 Jun 25 06:30:17 PM PDT 24 Jun 25 06:30:21 PM PDT 24 257833214 ps
T1095 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.874769228 Jun 25 06:30:36 PM PDT 24 Jun 25 06:30:38 PM PDT 24 75414262 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2178203823 Jun 25 06:30:14 PM PDT 24 Jun 25 06:30:20 PM PDT 24 151485284 ps
T113 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4077117180 Jun 25 06:30:14 PM PDT 24 Jun 25 06:30:18 PM PDT 24 42207321 ps
T1097 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.568861939 Jun 25 06:30:37 PM PDT 24 Jun 25 06:30:42 PM PDT 24 109934835 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1719051584 Jun 25 06:30:27 PM PDT 24 Jun 25 06:30:36 PM PDT 24 1420674071 ps
T108 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.466771470 Jun 25 06:30:38 PM PDT 24 Jun 25 06:30:44 PM PDT 24 1616316064 ps
T1099 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3235398075 Jun 25 06:30:56 PM PDT 24 Jun 25 06:30:58 PM PDT 24 58765032 ps
T1100 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.313628681 Jun 25 06:30:43 PM PDT 24 Jun 25 06:30:45 PM PDT 24 57577294 ps
T1101 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1948300477 Jun 25 06:30:45 PM PDT 24 Jun 25 06:31:02 PM PDT 24 2155724226 ps

Test location /workspace/coverage/default/4.spi_device_flash_all.319473931
Short name T2
Test name
Test status
Simulation time 309984785611 ps
CPU time 529.85 seconds
Started Jun 25 06:46:13 PM PDT 24
Finished Jun 25 06:55:04 PM PDT 24
Peak memory 256060 kb
Host smart-0c91b7ca-2856-48b4-9c25-51348bd19d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319473931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.319473931
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2396671307
Short name T13
Test name
Test status
Simulation time 70973889453 ps
CPU time 230.55 seconds
Started Jun 25 06:50:57 PM PDT 24
Finished Jun 25 06:54:49 PM PDT 24
Peak memory 274276 kb
Host smart-45c74085-ff84-435e-b2d8-35127221ca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396671307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2396671307
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3365430426
Short name T24
Test name
Test status
Simulation time 127644523981 ps
CPU time 548.97 seconds
Started Jun 25 06:46:14 PM PDT 24
Finished Jun 25 06:55:24 PM PDT 24
Peak memory 273272 kb
Host smart-8b44e05f-2596-4f27-aec2-f5dfeb77a181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365430426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3365430426
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2713219495
Short name T88
Test name
Test status
Simulation time 467123131 ps
CPU time 2.87 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 217924 kb
Host smart-6202654b-1932-4218-b704-e4d4ed0c97d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713219495 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2713219495
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2538759281
Short name T22
Test name
Test status
Simulation time 55329064052 ps
CPU time 239.62 seconds
Started Jun 25 06:46:50 PM PDT 24
Finished Jun 25 06:50:51 PM PDT 24
Peak memory 282500 kb
Host smart-390f8aa3-0fee-492a-a6b4-0874407cc7cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538759281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2538759281
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.5156014
Short name T59
Test name
Test status
Simulation time 18121423 ps
CPU time 0.76 seconds
Started Jun 25 06:44:32 PM PDT 24
Finished Jun 25 06:44:34 PM PDT 24
Peak memory 216652 kb
Host smart-5f69cdf7-c07f-4229-9f0c-85577a5f73e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5156014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.5156014
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.215838349
Short name T14
Test name
Test status
Simulation time 205962248895 ps
CPU time 577.04 seconds
Started Jun 25 06:51:52 PM PDT 24
Finished Jun 25 07:01:30 PM PDT 24
Peak memory 273512 kb
Host smart-01e9fe08-bc47-4e87-bc38-3c9f30874ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215838349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.215838349
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3163659935
Short name T203
Test name
Test status
Simulation time 267533533273 ps
CPU time 674.54 seconds
Started Jun 25 06:49:29 PM PDT 24
Finished Jun 25 07:00:45 PM PDT 24
Peak memory 282576 kb
Host smart-86a9d7fc-6e60-4df2-93a5-2f86fd021627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163659935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3163659935
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.74233662
Short name T44
Test name
Test status
Simulation time 8884782347 ps
CPU time 125.85 seconds
Started Jun 25 06:46:14 PM PDT 24
Finished Jun 25 06:48:21 PM PDT 24
Peak memory 249704 kb
Host smart-c536260a-cc24-4f92-9571-85f9df6da0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74233662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.74233662
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2603260856
Short name T17
Test name
Test status
Simulation time 72295789 ps
CPU time 1.13 seconds
Started Jun 25 06:45:47 PM PDT 24
Finished Jun 25 06:45:49 PM PDT 24
Peak memory 235828 kb
Host smart-f1410d1b-3727-4632-ab0b-ce6796fe9c87
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603260856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2603260856
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3905415080
Short name T36
Test name
Test status
Simulation time 790902954883 ps
CPU time 708.46 seconds
Started Jun 25 06:51:29 PM PDT 24
Finished Jun 25 07:03:19 PM PDT 24
Peak memory 261168 kb
Host smart-76f561ab-9d00-452a-81bb-b686972872ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905415080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3905415080
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2476823788
Short name T45
Test name
Test status
Simulation time 13827794160 ps
CPU time 64.35 seconds
Started Jun 25 06:47:14 PM PDT 24
Finished Jun 25 06:48:19 PM PDT 24
Peak memory 254660 kb
Host smart-1004150b-6da9-499b-9152-710e5e545a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476823788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2476823788
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3736970433
Short name T167
Test name
Test status
Simulation time 57710242563 ps
CPU time 357.24 seconds
Started Jun 25 06:51:39 PM PDT 24
Finished Jun 25 06:57:37 PM PDT 24
Peak memory 262864 kb
Host smart-6b02b0d9-f72c-4fec-8abf-f8ff82981c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736970433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3736970433
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3491370642
Short name T86
Test name
Test status
Simulation time 3250564107 ps
CPU time 22.1 seconds
Started Jun 25 06:30:27 PM PDT 24
Finished Jun 25 06:30:50 PM PDT 24
Peak memory 216376 kb
Host smart-091a72fa-7d65-4f41-9acd-153644f2a071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491370642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3491370642
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1139843358
Short name T116
Test name
Test status
Simulation time 71168231 ps
CPU time 2.54 seconds
Started Jun 25 06:30:37 PM PDT 24
Finished Jun 25 06:30:41 PM PDT 24
Peak memory 215720 kb
Host smart-db504a2a-f2ca-42a4-8cd8-f037462d3ca8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139843358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1139843358
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3294990674
Short name T55
Test name
Test status
Simulation time 38382810786 ps
CPU time 510.02 seconds
Started Jun 25 06:47:45 PM PDT 24
Finished Jun 25 06:56:17 PM PDT 24
Peak memory 289648 kb
Host smart-3a53456d-a9f7-47c0-a50d-4ec582c09b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294990674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3294990674
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1224846190
Short name T194
Test name
Test status
Simulation time 85366880602 ps
CPU time 776.2 seconds
Started Jun 25 06:48:16 PM PDT 24
Finished Jun 25 07:01:14 PM PDT 24
Peak memory 282600 kb
Host smart-f3752150-3a15-498b-a14c-1880548f3d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224846190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1224846190
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1330329135
Short name T226
Test name
Test status
Simulation time 324102557591 ps
CPU time 781.77 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:59:44 PM PDT 24
Peak memory 266912 kb
Host smart-d92e9cb5-b6c9-4540-97c5-87c93ec235dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330329135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1330329135
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.61249980
Short name T96
Test name
Test status
Simulation time 67166976 ps
CPU time 4.38 seconds
Started Jun 25 06:30:05 PM PDT 24
Finished Jun 25 06:30:11 PM PDT 24
Peak memory 215848 kb
Host smart-93017e15-7873-478d-b5e4-74610216c5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61249980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.61249980
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2800378371
Short name T372
Test name
Test status
Simulation time 57460002 ps
CPU time 1.05 seconds
Started Jun 25 06:44:58 PM PDT 24
Finished Jun 25 06:45:00 PM PDT 24
Peak memory 217180 kb
Host smart-e1f7b8f7-0565-4502-98e5-b40d70b1b681
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800378371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2800378371
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1173873437
Short name T200
Test name
Test status
Simulation time 35652014576 ps
CPU time 479.51 seconds
Started Jun 25 06:44:53 PM PDT 24
Finished Jun 25 06:52:54 PM PDT 24
Peak memory 274204 kb
Host smart-7b862852-d8cc-4277-beda-e67dbf3bbdc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173873437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1173873437
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3656330701
Short name T255
Test name
Test status
Simulation time 178974544683 ps
CPU time 651.87 seconds
Started Jun 25 06:51:17 PM PDT 24
Finished Jun 25 07:02:10 PM PDT 24
Peak memory 256452 kb
Host smart-049f7e63-837c-427d-9360-fee00c87ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656330701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3656330701
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3748876826
Short name T197
Test name
Test status
Simulation time 164973712652 ps
CPU time 384.55 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:58:10 PM PDT 24
Peak memory 254392 kb
Host smart-fcad6299-c940-4c43-96a7-972e1a2910f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748876826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3748876826
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3889882066
Short name T150
Test name
Test status
Simulation time 77223278404 ps
CPU time 602.45 seconds
Started Jun 25 06:45:57 PM PDT 24
Finished Jun 25 06:56:00 PM PDT 24
Peak memory 264732 kb
Host smart-02c64cef-469f-4e6c-836b-a7561ea816ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889882066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3889882066
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2361017320
Short name T27
Test name
Test status
Simulation time 6344190912 ps
CPU time 11.52 seconds
Started Jun 25 06:48:32 PM PDT 24
Finished Jun 25 06:48:46 PM PDT 24
Peak memory 216868 kb
Host smart-521f7c6d-7662-4346-a7fb-c3449679ea9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361017320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2361017320
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.802851954
Short name T9
Test name
Test status
Simulation time 93891590 ps
CPU time 0.76 seconds
Started Jun 25 06:49:49 PM PDT 24
Finished Jun 25 06:49:52 PM PDT 24
Peak memory 205756 kb
Host smart-ea50af83-9fb1-40c3-ac24-4900864caa31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802851954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.802851954
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2347814081
Short name T844
Test name
Test status
Simulation time 331807556904 ps
CPU time 367.91 seconds
Started Jun 25 06:45:33 PM PDT 24
Finished Jun 25 06:51:42 PM PDT 24
Peak memory 261656 kb
Host smart-5f4bae7a-a93c-48bb-9cac-98d771c57e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347814081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2347814081
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1070558241
Short name T428
Test name
Test status
Simulation time 6229217138 ps
CPU time 175.34 seconds
Started Jun 25 06:47:16 PM PDT 24
Finished Jun 25 06:50:13 PM PDT 24
Peak memory 264436 kb
Host smart-6acf36a9-6301-4154-975e-5da984e5b9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070558241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1070558241
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3245321118
Short name T104
Test name
Test status
Simulation time 721831106 ps
CPU time 4.94 seconds
Started Jun 25 06:30:17 PM PDT 24
Finished Jun 25 06:30:24 PM PDT 24
Peak memory 216060 kb
Host smart-ebc9b545-0d39-44b8-9bd3-75003c8f1e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245321118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
245321118
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3313389689
Short name T183
Test name
Test status
Simulation time 299998466 ps
CPU time 17.21 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:57 PM PDT 24
Peak memory 216092 kb
Host smart-ce919479-6c24-49a5-9c8e-a3beb679e06f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313389689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3313389689
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2189525588
Short name T54
Test name
Test status
Simulation time 24606492498 ps
CPU time 226.68 seconds
Started Jun 25 06:52:59 PM PDT 24
Finished Jun 25 06:56:46 PM PDT 24
Peak memory 250756 kb
Host smart-5d0edddd-099b-4fbf-91c7-d26e978182f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189525588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2189525588
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1071164915
Short name T32
Test name
Test status
Simulation time 91330307200 ps
CPU time 373.04 seconds
Started Jun 25 06:48:13 PM PDT 24
Finished Jun 25 06:54:27 PM PDT 24
Peak memory 257420 kb
Host smart-40fe9024-a8ee-4cfc-aa5e-fdeb2db62e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071164915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1071164915
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3065632062
Short name T41
Test name
Test status
Simulation time 19575048236 ps
CPU time 201.22 seconds
Started Jun 25 06:52:58 PM PDT 24
Finished Jun 25 06:56:21 PM PDT 24
Peak memory 265028 kb
Host smart-63ffb72e-fd87-43b8-8f6e-43801dabae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065632062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3065632062
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1925404501
Short name T188
Test name
Test status
Simulation time 620746435 ps
CPU time 3.56 seconds
Started Jun 25 06:48:51 PM PDT 24
Finished Jun 25 06:48:56 PM PDT 24
Peak memory 224956 kb
Host smart-1235214d-d6a1-43ce-82eb-cacfcc8a30ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925404501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1925404501
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1641641235
Short name T175
Test name
Test status
Simulation time 372509393 ps
CPU time 7.44 seconds
Started Jun 25 06:30:04 PM PDT 24
Finished Jun 25 06:30:13 PM PDT 24
Peak memory 216400 kb
Host smart-f2f18efe-2a49-45e4-8389-ef4deb8952cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641641235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1641641235
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3802776401
Short name T817
Test name
Test status
Simulation time 315127033256 ps
CPU time 484.09 seconds
Started Jun 25 06:48:48 PM PDT 24
Finished Jun 25 06:56:54 PM PDT 24
Peak memory 267564 kb
Host smart-1f40ddbb-d06b-46bd-a584-ff947d2c5d3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802776401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3802776401
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.31927882
Short name T326
Test name
Test status
Simulation time 223902987 ps
CPU time 10.51 seconds
Started Jun 25 06:49:16 PM PDT 24
Finished Jun 25 06:49:27 PM PDT 24
Peak memory 249564 kb
Host smart-08416d4c-855d-48cb-9c6e-64354e415526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31927882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.31927882
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3188871978
Short name T214
Test name
Test status
Simulation time 263710830987 ps
CPU time 234.46 seconds
Started Jun 25 06:49:26 PM PDT 24
Finished Jun 25 06:53:22 PM PDT 24
Peak memory 256876 kb
Host smart-6ec0a9ad-85cc-4c51-884e-e5c7519991e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188871978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3188871978
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.718804306
Short name T637
Test name
Test status
Simulation time 18154058472 ps
CPU time 60.7 seconds
Started Jun 25 06:45:35 PM PDT 24
Finished Jun 25 06:46:36 PM PDT 24
Peak memory 241456 kb
Host smart-7dae547f-bec8-4c21-b9e6-302e5f495ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718804306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.718804306
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.828834149
Short name T133
Test name
Test status
Simulation time 225829820393 ps
CPU time 534.76 seconds
Started Jun 25 06:50:35 PM PDT 24
Finished Jun 25 06:59:32 PM PDT 24
Peak memory 269660 kb
Host smart-94070f72-e339-4a52-981d-c776d4ac0983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828834149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.828834149
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3925328916
Short name T107
Test name
Test status
Simulation time 344821156 ps
CPU time 3.98 seconds
Started Jun 25 06:30:10 PM PDT 24
Finished Jun 25 06:30:16 PM PDT 24
Peak memory 215920 kb
Host smart-e49cdb3f-266e-4911-99ff-5bcc89c5c344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925328916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
925328916
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1887033544
Short name T248
Test name
Test status
Simulation time 111939419589 ps
CPU time 36.64 seconds
Started Jun 25 06:45:09 PM PDT 24
Finished Jun 25 06:45:47 PM PDT 24
Peak memory 240900 kb
Host smart-14599edf-5f1f-4965-aef0-1342e7113c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887033544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1887033544
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3394244824
Short name T315
Test name
Test status
Simulation time 676433748176 ps
CPU time 387.62 seconds
Started Jun 25 06:47:39 PM PDT 24
Finished Jun 25 06:54:08 PM PDT 24
Peak memory 267116 kb
Host smart-75696a8c-dd85-4c0b-ae9b-44afe6d67dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394244824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3394244824
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1384953208
Short name T23
Test name
Test status
Simulation time 387087473808 ps
CPU time 713.11 seconds
Started Jun 25 06:48:14 PM PDT 24
Finished Jun 25 07:00:09 PM PDT 24
Peak memory 257756 kb
Host smart-3fb5bd70-b750-4d66-b387-f871e0176d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384953208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1384953208
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4245043894
Short name T308
Test name
Test status
Simulation time 2619087786 ps
CPU time 10.23 seconds
Started Jun 25 06:49:27 PM PDT 24
Finished Jun 25 06:49:39 PM PDT 24
Peak memory 233228 kb
Host smart-1f37422e-720f-4c37-af20-3e6d4052ffdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245043894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4245043894
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.927374197
Short name T232
Test name
Test status
Simulation time 100393403446 ps
CPU time 995.25 seconds
Started Jun 25 06:49:32 PM PDT 24
Finished Jun 25 07:06:09 PM PDT 24
Peak memory 273708 kb
Host smart-18e95e75-ac11-4c9c-8649-501ec3fbfa59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927374197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.927374197
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3075333196
Short name T75
Test name
Test status
Simulation time 2091949729 ps
CPU time 25.66 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:50:01 PM PDT 24
Peak memory 216948 kb
Host smart-c2a46c7b-9d74-47a5-ad5d-69b82473f166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075333196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3075333196
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1998076659
Short name T209
Test name
Test status
Simulation time 19683837873 ps
CPU time 89.45 seconds
Started Jun 25 06:52:46 PM PDT 24
Finished Jun 25 06:54:17 PM PDT 24
Peak memory 240644 kb
Host smart-0892665d-642b-4636-aa89-456f3b7c9bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998076659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1998076659
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3158156399
Short name T286
Test name
Test status
Simulation time 92224087 ps
CPU time 2.75 seconds
Started Jun 25 06:48:49 PM PDT 24
Finished Jun 25 06:48:54 PM PDT 24
Peak memory 224944 kb
Host smart-d8ef7b5d-c2cf-446b-85df-f970d7b3d913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158156399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3158156399
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2307048716
Short name T74
Test name
Test status
Simulation time 15909073 ps
CPU time 0.99 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:18 PM PDT 24
Peak memory 207252 kb
Host smart-81833fda-eb82-42bd-b001-1df95c5dcb5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307048716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2307048716
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1986127262
Short name T1045
Test name
Test status
Simulation time 1866094834 ps
CPU time 9.13 seconds
Started Jun 25 06:30:09 PM PDT 24
Finished Jun 25 06:30:20 PM PDT 24
Peak memory 215724 kb
Host smart-041d9220-15d9-4e3e-aada-ad238706b21e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986127262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1986127262
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3181618448
Short name T1023
Test name
Test status
Simulation time 2538321347 ps
CPU time 14.02 seconds
Started Jun 25 06:30:07 PM PDT 24
Finished Jun 25 06:30:22 PM PDT 24
Peak memory 207600 kb
Host smart-fbb3f979-e08d-464b-816d-b19a4ffc95bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181618448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3181618448
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3034083425
Short name T1024
Test name
Test status
Simulation time 52093944 ps
CPU time 0.99 seconds
Started Jun 25 06:30:08 PM PDT 24
Finished Jun 25 06:30:11 PM PDT 24
Peak memory 207256 kb
Host smart-ae65bb78-8034-4a22-bdbb-73dfabdb60cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034083425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3034083425
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1994023339
Short name T89
Test name
Test status
Simulation time 163843112 ps
CPU time 2.6 seconds
Started Jun 25 06:30:08 PM PDT 24
Finished Jun 25 06:30:12 PM PDT 24
Peak memory 216776 kb
Host smart-73739dc8-69fc-49e4-a8da-9872c6d70e3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994023339 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1994023339
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3083875355
Short name T1051
Test name
Test status
Simulation time 27333043 ps
CPU time 1.81 seconds
Started Jun 25 06:30:10 PM PDT 24
Finished Jun 25 06:30:14 PM PDT 24
Peak memory 207488 kb
Host smart-311322ef-c70c-48d1-99f5-62e897894c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083875355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
083875355
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1797408990
Short name T999
Test name
Test status
Simulation time 12602275 ps
CPU time 0.77 seconds
Started Jun 25 06:30:07 PM PDT 24
Finished Jun 25 06:30:09 PM PDT 24
Peak memory 204076 kb
Host smart-8095140c-1d42-46f8-b1da-ea2a9ba669e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797408990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
797408990
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4121757818
Short name T1038
Test name
Test status
Simulation time 33046610 ps
CPU time 1.82 seconds
Started Jun 25 06:30:04 PM PDT 24
Finished Jun 25 06:30:08 PM PDT 24
Peak memory 215788 kb
Host smart-c3c41ad4-a67a-4759-afeb-d5b7dfd1d449
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121757818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4121757818
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3409134771
Short name T995
Test name
Test status
Simulation time 74783064 ps
CPU time 0.67 seconds
Started Jun 25 06:30:08 PM PDT 24
Finished Jun 25 06:30:10 PM PDT 24
Peak memory 203932 kb
Host smart-dd05e3dc-79db-4e11-a601-dc226f5fb224
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409134771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3409134771
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.52221111
Short name T1087
Test name
Test status
Simulation time 55023771 ps
CPU time 2.81 seconds
Started Jun 25 06:30:05 PM PDT 24
Finished Jun 25 06:30:09 PM PDT 24
Peak memory 215788 kb
Host smart-663be7ca-1d73-436c-ae91-794847660bee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52221111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_same_csr_outstanding.52221111
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1689935197
Short name T174
Test name
Test status
Simulation time 110279004 ps
CPU time 2.23 seconds
Started Jun 25 06:30:05 PM PDT 24
Finished Jun 25 06:30:09 PM PDT 24
Peak memory 215884 kb
Host smart-e3efcd79-58a0-4df7-84d6-ea8df8582c99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689935197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
689935197
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1446616453
Short name T178
Test name
Test status
Simulation time 1057417038 ps
CPU time 23.99 seconds
Started Jun 25 06:30:09 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 223940 kb
Host smart-420da56a-d1f1-411c-b9e6-4916c6471797
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446616453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1446616453
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4167022663
Short name T1012
Test name
Test status
Simulation time 312657333 ps
CPU time 8.47 seconds
Started Jun 25 06:30:09 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 207520 kb
Host smart-1af0723c-b271-489e-81c3-167582579611
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167022663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4167022663
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1502801593
Short name T1082
Test name
Test status
Simulation time 2411760910 ps
CPU time 38.44 seconds
Started Jun 25 06:30:10 PM PDT 24
Finished Jun 25 06:30:50 PM PDT 24
Peak memory 207640 kb
Host smart-5ce62da7-a7de-4598-bf18-7c668c3df437
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502801593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1502801593
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.303785035
Short name T73
Test name
Test status
Simulation time 152377532 ps
CPU time 1.15 seconds
Started Jun 25 06:30:09 PM PDT 24
Finished Jun 25 06:30:12 PM PDT 24
Peak memory 207428 kb
Host smart-8c7faee2-42f2-4b33-93c4-f4aa13ea667a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303785035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.303785035
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1185252458
Short name T1034
Test name
Test status
Simulation time 444443387 ps
CPU time 2.85 seconds
Started Jun 25 06:30:10 PM PDT 24
Finished Jun 25 06:30:15 PM PDT 24
Peak memory 217432 kb
Host smart-75bbabe3-f9b0-42ec-8502-a47b8f54d892
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185252458 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1185252458
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1711033613
Short name T119
Test name
Test status
Simulation time 123560217 ps
CPU time 1.35 seconds
Started Jun 25 06:30:06 PM PDT 24
Finished Jun 25 06:30:09 PM PDT 24
Peak memory 207592 kb
Host smart-abfdb747-de16-458f-8f4e-290d947d2bf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711033613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
711033613
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3925800525
Short name T1011
Test name
Test status
Simulation time 17306428 ps
CPU time 0.76 seconds
Started Jun 25 06:30:10 PM PDT 24
Finished Jun 25 06:30:12 PM PDT 24
Peak memory 204336 kb
Host smart-d556d7e4-46f6-4f58-9b79-189d49f12253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925800525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
925800525
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4071531232
Short name T124
Test name
Test status
Simulation time 194795236 ps
CPU time 1.85 seconds
Started Jun 25 06:30:06 PM PDT 24
Finished Jun 25 06:30:09 PM PDT 24
Peak memory 215768 kb
Host smart-ad24865e-49e5-4034-9f96-35b36e14571b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071531232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4071531232
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.4078638642
Short name T1016
Test name
Test status
Simulation time 13334329 ps
CPU time 0.68 seconds
Started Jun 25 06:30:11 PM PDT 24
Finished Jun 25 06:30:13 PM PDT 24
Peak memory 204320 kb
Host smart-94f7c5c4-9573-410e-9ed4-68d800f5f89f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078638642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.4078638642
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1482685552
Short name T1010
Test name
Test status
Simulation time 170267784 ps
CPU time 4.22 seconds
Started Jun 25 06:30:10 PM PDT 24
Finished Jun 25 06:30:16 PM PDT 24
Peak memory 215684 kb
Host smart-fc6a28e0-cc14-4a43-9b0b-12b13d8bddca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482685552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1482685552
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3459067335
Short name T1019
Test name
Test status
Simulation time 118901456 ps
CPU time 2.84 seconds
Started Jun 25 06:30:22 PM PDT 24
Finished Jun 25 06:30:27 PM PDT 24
Peak memory 217316 kb
Host smart-dc4f715b-5b0f-48ff-8ab0-84ec78b5a097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459067335 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3459067335
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2597363045
Short name T120
Test name
Test status
Simulation time 146140608 ps
CPU time 1.28 seconds
Started Jun 25 06:30:21 PM PDT 24
Finished Jun 25 06:30:24 PM PDT 24
Peak memory 207488 kb
Host smart-4d1e8adf-2ce4-4d21-9171-32233c953d56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597363045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2597363045
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2414890931
Short name T1064
Test name
Test status
Simulation time 23089806 ps
CPU time 0.8 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:22 PM PDT 24
Peak memory 204076 kb
Host smart-e514985d-a3f2-4e3c-b5d1-06095aad8d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414890931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2414890931
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1024376902
Short name T1025
Test name
Test status
Simulation time 42642073 ps
CPU time 2.85 seconds
Started Jun 25 06:30:21 PM PDT 24
Finished Jun 25 06:30:25 PM PDT 24
Peak memory 215692 kb
Host smart-368dd358-6461-4457-8ec5-2fb45e5f1c23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024376902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1024376902
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1913962756
Short name T102
Test name
Test status
Simulation time 80044568 ps
CPU time 2.67 seconds
Started Jun 25 06:30:21 PM PDT 24
Finished Jun 25 06:30:26 PM PDT 24
Peak memory 216900 kb
Host smart-8c82cf90-a626-4e2c-89d6-fd6769fbf9a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913962756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1913962756
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2748290276
Short name T176
Test name
Test status
Simulation time 403373888 ps
CPU time 13.04 seconds
Started Jun 25 06:30:34 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 215732 kb
Host smart-5e18b41b-b5da-4659-aea5-88d66c9036db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748290276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2748290276
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4205330979
Short name T94
Test name
Test status
Simulation time 91399352 ps
CPU time 1.8 seconds
Started Jun 25 06:30:29 PM PDT 24
Finished Jun 25 06:30:32 PM PDT 24
Peak memory 216800 kb
Host smart-e2e8b48f-602b-45db-a1de-4d896e17bf28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205330979 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4205330979
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.445990858
Short name T1083
Test name
Test status
Simulation time 404688388 ps
CPU time 2.96 seconds
Started Jun 25 06:30:29 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 215816 kb
Host smart-b71643ef-c715-49a8-b927-ba2ccbcd5f67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445990858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.445990858
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1878857274
Short name T1054
Test name
Test status
Simulation time 18587889 ps
CPU time 0.71 seconds
Started Jun 25 06:30:31 PM PDT 24
Finished Jun 25 06:30:33 PM PDT 24
Peak memory 203996 kb
Host smart-90b31941-d3cd-409b-aebb-75f2eaf00d97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878857274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1878857274
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1305957864
Short name T137
Test name
Test status
Simulation time 155970550 ps
CPU time 3.09 seconds
Started Jun 25 06:30:29 PM PDT 24
Finished Jun 25 06:30:33 PM PDT 24
Peak memory 215760 kb
Host smart-78ca51ac-6028-46a7-bc26-8f173e085752
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305957864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1305957864
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3318495759
Short name T99
Test name
Test status
Simulation time 41430056 ps
CPU time 2.75 seconds
Started Jun 25 06:30:22 PM PDT 24
Finished Jun 25 06:30:26 PM PDT 24
Peak memory 215992 kb
Host smart-42d170fb-241f-4a10-bf63-d2abc0cc630e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318495759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3318495759
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.788807757
Short name T179
Test name
Test status
Simulation time 10172242913 ps
CPU time 23.41 seconds
Started Jun 25 06:30:31 PM PDT 24
Finished Jun 25 06:30:55 PM PDT 24
Peak memory 215804 kb
Host smart-9af077f6-f5a8-4eda-bb5a-232fae11dda5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788807757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.788807757
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.4262534033
Short name T103
Test name
Test status
Simulation time 186704824 ps
CPU time 3.31 seconds
Started Jun 25 06:30:28 PM PDT 24
Finished Jun 25 06:30:33 PM PDT 24
Peak memory 218648 kb
Host smart-82cf2ed9-efa8-40c6-899b-11fc7a083449
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262534033 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.4262534033
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4192419067
Short name T122
Test name
Test status
Simulation time 47701103 ps
CPU time 1.31 seconds
Started Jun 25 06:30:28 PM PDT 24
Finished Jun 25 06:30:30 PM PDT 24
Peak memory 207472 kb
Host smart-e66cb4e1-3611-488d-bdd1-799995c841e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192419067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4192419067
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.970767901
Short name T1037
Test name
Test status
Simulation time 90747358 ps
CPU time 0.72 seconds
Started Jun 25 06:30:28 PM PDT 24
Finished Jun 25 06:30:30 PM PDT 24
Peak memory 204336 kb
Host smart-9867494c-ed8d-46b4-b603-a7b68bd5af81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970767901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.970767901
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1442567756
Short name T1070
Test name
Test status
Simulation time 181227095 ps
CPU time 3.91 seconds
Started Jun 25 06:30:31 PM PDT 24
Finished Jun 25 06:30:36 PM PDT 24
Peak memory 207600 kb
Host smart-3531edd9-9162-4fb3-8d37-ed94c0ea952e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442567756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1442567756
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3031586772
Short name T106
Test name
Test status
Simulation time 405944260 ps
CPU time 2.85 seconds
Started Jun 25 06:30:30 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 215876 kb
Host smart-5bc17484-7ab0-4be1-9aaa-a39a7e20b793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031586772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3031586772
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1619102540
Short name T181
Test name
Test status
Simulation time 646982767 ps
CPU time 7.14 seconds
Started Jun 25 06:30:29 PM PDT 24
Finished Jun 25 06:30:38 PM PDT 24
Peak memory 215752 kb
Host smart-550c3f89-5537-4ef3-bcf7-018822b8da1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619102540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1619102540
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3850411633
Short name T1018
Test name
Test status
Simulation time 164795079 ps
CPU time 1.65 seconds
Started Jun 25 06:30:40 PM PDT 24
Finished Jun 25 06:30:43 PM PDT 24
Peak memory 215864 kb
Host smart-073e7d38-a2c5-4689-afd6-d592111fc48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850411633 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3850411633
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2630877125
Short name T1069
Test name
Test status
Simulation time 35068688 ps
CPU time 2.05 seconds
Started Jun 25 06:30:29 PM PDT 24
Finished Jun 25 06:30:33 PM PDT 24
Peak memory 220456 kb
Host smart-081c6746-537d-4778-9369-331660066120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630877125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2630877125
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1821867044
Short name T1050
Test name
Test status
Simulation time 17273618 ps
CPU time 0.81 seconds
Started Jun 25 06:30:29 PM PDT 24
Finished Jun 25 06:30:31 PM PDT 24
Peak memory 204040 kb
Host smart-dc2de0b4-1af0-4a31-9d36-5dee87c04095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821867044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1821867044
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3954923303
Short name T1072
Test name
Test status
Simulation time 108480935 ps
CPU time 2.86 seconds
Started Jun 25 06:30:28 PM PDT 24
Finished Jun 25 06:30:32 PM PDT 24
Peak memory 215668 kb
Host smart-36753bf4-7ff8-48ce-b441-73e0a6eaef04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954923303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3954923303
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4109330811
Short name T101
Test name
Test status
Simulation time 144309252 ps
CPU time 4.11 seconds
Started Jun 25 06:30:34 PM PDT 24
Finished Jun 25 06:30:39 PM PDT 24
Peak memory 215924 kb
Host smart-b9bd878d-c944-444e-94e5-44f088bc1907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109330811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4109330811
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1719051584
Short name T1098
Test name
Test status
Simulation time 1420674071 ps
CPU time 7.96 seconds
Started Jun 25 06:30:27 PM PDT 24
Finished Jun 25 06:30:36 PM PDT 24
Peak memory 216072 kb
Host smart-06c1b419-34d6-4467-bde0-0c394f5fcb7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719051584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1719051584
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.532027131
Short name T1088
Test name
Test status
Simulation time 318277395 ps
CPU time 1.76 seconds
Started Jun 25 06:30:28 PM PDT 24
Finished Jun 25 06:30:30 PM PDT 24
Peak memory 215972 kb
Host smart-3a8c28ea-3a14-427e-9fe5-2d5a390e5f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532027131 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.532027131
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.474463735
Short name T127
Test name
Test status
Simulation time 66231742 ps
CPU time 1.99 seconds
Started Jun 25 06:30:28 PM PDT 24
Finished Jun 25 06:30:31 PM PDT 24
Peak memory 207516 kb
Host smart-12ee435c-fb53-4457-b71b-f8334f84eb43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474463735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.474463735
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2258447059
Short name T1014
Test name
Test status
Simulation time 14056160 ps
CPU time 0.77 seconds
Started Jun 25 06:30:30 PM PDT 24
Finished Jun 25 06:30:32 PM PDT 24
Peak memory 204292 kb
Host smart-a0eb78d7-3365-429e-9fda-6ab3d2ea2faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258447059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2258447059
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3657040333
Short name T145
Test name
Test status
Simulation time 1657968394 ps
CPU time 2.83 seconds
Started Jun 25 06:30:31 PM PDT 24
Finished Jun 25 06:30:35 PM PDT 24
Peak memory 215732 kb
Host smart-43be2fe3-f8bb-4a5d-acd1-4dda8018277c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657040333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3657040333
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2863209577
Short name T100
Test name
Test status
Simulation time 192372219 ps
CPU time 1.86 seconds
Started Jun 25 06:30:29 PM PDT 24
Finished Jun 25 06:30:32 PM PDT 24
Peak memory 215892 kb
Host smart-2ebb1a86-39e1-4b45-9b4c-afb36beeeda2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863209577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2863209577
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3231397049
Short name T1036
Test name
Test status
Simulation time 101178858 ps
CPU time 2.07 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:42 PM PDT 24
Peak memory 216868 kb
Host smart-183d682e-1ae6-4b2f-be76-31bbdc2a16fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231397049 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3231397049
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2535079334
Short name T1065
Test name
Test status
Simulation time 43906213 ps
CPU time 0.69 seconds
Started Jun 25 06:30:37 PM PDT 24
Finished Jun 25 06:30:40 PM PDT 24
Peak memory 203972 kb
Host smart-6f3dce64-2067-4df8-9980-94f0e5b98a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535079334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2535079334
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3718508475
Short name T1062
Test name
Test status
Simulation time 135448230 ps
CPU time 1.81 seconds
Started Jun 25 06:30:37 PM PDT 24
Finished Jun 25 06:30:40 PM PDT 24
Peak memory 207512 kb
Host smart-3267894f-c36a-49d4-bb01-53d1d4642084
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718508475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3718508475
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2755760445
Short name T1071
Test name
Test status
Simulation time 82251270 ps
CPU time 2.39 seconds
Started Jun 25 06:30:28 PM PDT 24
Finished Jun 25 06:30:32 PM PDT 24
Peak memory 215872 kb
Host smart-b65050e4-b69a-48ed-a164-963faff316d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755760445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2755760445
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1218194041
Short name T184
Test name
Test status
Simulation time 302064691 ps
CPU time 18.99 seconds
Started Jun 25 06:30:27 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 215764 kb
Host smart-39626bc7-36d1-44cc-a723-dd50985b427e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218194041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1218194041
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1559229157
Short name T110
Test name
Test status
Simulation time 251101009 ps
CPU time 1.87 seconds
Started Jun 25 06:30:37 PM PDT 24
Finished Jun 25 06:30:40 PM PDT 24
Peak memory 216844 kb
Host smart-f7379c9c-0c01-4157-8794-aae5153a5fc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559229157 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1559229157
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.112329166
Short name T1092
Test name
Test status
Simulation time 227004632 ps
CPU time 1.9 seconds
Started Jun 25 06:30:36 PM PDT 24
Finished Jun 25 06:30:38 PM PDT 24
Peak memory 215736 kb
Host smart-fd86f7be-a906-4018-a3e9-75e91d227fb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112329166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.112329166
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1775736875
Short name T1022
Test name
Test status
Simulation time 24357517 ps
CPU time 0.73 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:41 PM PDT 24
Peak memory 204336 kb
Host smart-3f01eca5-26fd-4a36-8aaf-0caf7f1508f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775736875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1775736875
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.568861939
Short name T1097
Test name
Test status
Simulation time 109934835 ps
CPU time 3.02 seconds
Started Jun 25 06:30:37 PM PDT 24
Finished Jun 25 06:30:42 PM PDT 24
Peak memory 215636 kb
Host smart-bd5b57ea-bce5-4d47-9621-e210104408ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568861939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.568861939
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3798147172
Short name T1031
Test name
Test status
Simulation time 156238712 ps
CPU time 1.35 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:41 PM PDT 24
Peak memory 215884 kb
Host smart-b99adf5b-270f-47db-ad8a-68ecea046863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798147172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3798147172
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2526898372
Short name T177
Test name
Test status
Simulation time 3332673988 ps
CPU time 20.45 seconds
Started Jun 25 06:30:35 PM PDT 24
Finished Jun 25 06:30:57 PM PDT 24
Peak memory 215848 kb
Host smart-bbacbb4d-c9f3-43ce-9bc3-44b0cf8ad4ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526898372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2526898372
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.989234165
Short name T1040
Test name
Test status
Simulation time 179405475 ps
CPU time 4.33 seconds
Started Jun 25 06:30:37 PM PDT 24
Finished Jun 25 06:30:43 PM PDT 24
Peak memory 217336 kb
Host smart-c4186cdd-106c-4f61-ab03-48a7b40a5169
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989234165 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.989234165
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.529757851
Short name T121
Test name
Test status
Simulation time 183531684 ps
CPU time 2.71 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:43 PM PDT 24
Peak memory 220736 kb
Host smart-6abfcc4f-4030-431c-94f3-ac1c419946d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529757851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.529757851
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.874769228
Short name T1095
Test name
Test status
Simulation time 75414262 ps
CPU time 0.75 seconds
Started Jun 25 06:30:36 PM PDT 24
Finished Jun 25 06:30:38 PM PDT 24
Peak memory 204064 kb
Host smart-4f721823-8236-4e11-8723-33ca897d94a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874769228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.874769228
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3422428817
Short name T144
Test name
Test status
Simulation time 1544546676 ps
CPU time 3.16 seconds
Started Jun 25 06:30:36 PM PDT 24
Finished Jun 25 06:30:41 PM PDT 24
Peak memory 215788 kb
Host smart-a9afe1e5-07f0-4f8a-b779-d856827e6d0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422428817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3422428817
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.830149703
Short name T95
Test name
Test status
Simulation time 164394690 ps
CPU time 2.34 seconds
Started Jun 25 06:30:36 PM PDT 24
Finished Jun 25 06:30:39 PM PDT 24
Peak memory 215884 kb
Host smart-d8c4f7d9-7c9c-418d-be1f-8fc83fa5d38d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830149703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.830149703
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3888287617
Short name T1042
Test name
Test status
Simulation time 147743058 ps
CPU time 3.6 seconds
Started Jun 25 06:30:36 PM PDT 24
Finished Jun 25 06:30:41 PM PDT 24
Peak memory 217932 kb
Host smart-aa429f43-9126-437c-b1cc-f23c7d4e49dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888287617 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3888287617
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2624053352
Short name T1066
Test name
Test status
Simulation time 327385968 ps
CPU time 1.42 seconds
Started Jun 25 06:30:36 PM PDT 24
Finished Jun 25 06:30:39 PM PDT 24
Peak memory 207448 kb
Host smart-7f7dcf03-8fae-4d6e-9f93-f0212318a9e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624053352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2624053352
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.990255141
Short name T1079
Test name
Test status
Simulation time 14982564 ps
CPU time 0.74 seconds
Started Jun 25 06:30:36 PM PDT 24
Finished Jun 25 06:30:37 PM PDT 24
Peak memory 204284 kb
Host smart-0fd475dd-df91-4a4f-8f3c-24a20dd2ca70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990255141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.990255141
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2824483872
Short name T1044
Test name
Test status
Simulation time 544058285 ps
CPU time 3.03 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:42 PM PDT 24
Peak memory 215712 kb
Host smart-a190f1ca-ab6a-45b2-bd4f-7d0e0baaf4e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824483872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2824483872
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.466771470
Short name T108
Test name
Test status
Simulation time 1616316064 ps
CPU time 4.45 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:44 PM PDT 24
Peak memory 215920 kb
Host smart-3652bd58-5bef-4d32-b59b-d37987ab64cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466771470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.466771470
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1634607038
Short name T185
Test name
Test status
Simulation time 1437476250 ps
CPU time 8.02 seconds
Started Jun 25 06:30:38 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 216120 kb
Host smart-28fce929-a369-49b9-9b2a-cbf380710ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634607038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1634607038
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3939564397
Short name T117
Test name
Test status
Simulation time 21203744 ps
CPU time 1.21 seconds
Started Jun 25 06:30:46 PM PDT 24
Finished Jun 25 06:30:49 PM PDT 24
Peak memory 207444 kb
Host smart-4286bd30-e6af-47d3-b768-81a4209ea509
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939564397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3939564397
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2590885821
Short name T1078
Test name
Test status
Simulation time 67450319 ps
CPU time 0.75 seconds
Started Jun 25 06:30:46 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 204088 kb
Host smart-f8812450-aa9e-461d-bef1-793ebddd13b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590885821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2590885821
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4123962720
Short name T1053
Test name
Test status
Simulation time 98929724 ps
CPU time 1.81 seconds
Started Jun 25 06:30:43 PM PDT 24
Finished Jun 25 06:30:46 PM PDT 24
Peak memory 215692 kb
Host smart-4424a508-97de-4fba-8eff-8184e6918371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123962720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4123962720
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4021142962
Short name T98
Test name
Test status
Simulation time 29559445 ps
CPU time 1.66 seconds
Started Jun 25 06:30:37 PM PDT 24
Finished Jun 25 06:30:40 PM PDT 24
Peak memory 215812 kb
Host smart-4cb59f9d-fc58-4ac7-a8db-b6038b4df6cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021142962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4021142962
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1948300477
Short name T1101
Test name
Test status
Simulation time 2155724226 ps
CPU time 15.2 seconds
Started Jun 25 06:30:45 PM PDT 24
Finished Jun 25 06:31:02 PM PDT 24
Peak memory 215920 kb
Host smart-934bca80-f57c-40b0-a0e1-3640b18c772b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948300477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1948300477
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2865905727
Short name T1081
Test name
Test status
Simulation time 1617819439 ps
CPU time 17.26 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 215716 kb
Host smart-3c70b38f-49d7-4044-b111-66d85a3d53b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865905727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2865905727
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.4268163985
Short name T1021
Test name
Test status
Simulation time 189695032 ps
CPU time 11.4 seconds
Started Jun 25 06:30:16 PM PDT 24
Finished Jun 25 06:30:30 PM PDT 24
Peak memory 207568 kb
Host smart-c97a2072-ca92-4e87-be18-6bfa239c7de6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268163985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.4268163985
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2338879994
Short name T114
Test name
Test status
Simulation time 52089560 ps
CPU time 1.76 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 215864 kb
Host smart-a69dadf0-834f-4e19-b8b5-3c0eaacaafe6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338879994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2338879994
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4056126686
Short name T123
Test name
Test status
Simulation time 86851422 ps
CPU time 2.08 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:16 PM PDT 24
Peak memory 215752 kb
Host smart-d1399379-5d3d-4767-988c-743ab31fa37f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056126686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
056126686
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3158074108
Short name T1000
Test name
Test status
Simulation time 14969868 ps
CPU time 0.74 seconds
Started Jun 25 06:30:06 PM PDT 24
Finished Jun 25 06:30:08 PM PDT 24
Peak memory 204076 kb
Host smart-2ef608d0-b800-414b-bee6-0e0a944d52d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158074108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
158074108
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2552484758
Short name T1068
Test name
Test status
Simulation time 142028957 ps
CPU time 1.36 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:18 PM PDT 24
Peak memory 215756 kb
Host smart-8e23383d-6864-480a-aa22-04ebb318bb07
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552484758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2552484758
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.15012848
Short name T1030
Test name
Test status
Simulation time 11480516 ps
CPU time 0.67 seconds
Started Jun 25 06:30:17 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 204316 kb
Host smart-13fe72e6-c2ca-4990-829f-6c5bcebbef9a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15012848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_
walk.15012848
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2178203823
Short name T1096
Test name
Test status
Simulation time 151485284 ps
CPU time 4.36 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:20 PM PDT 24
Peak memory 215704 kb
Host smart-204204ca-65de-4655-b59c-ae45aadb11d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178203823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2178203823
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1603495614
Short name T1058
Test name
Test status
Simulation time 566493036 ps
CPU time 14.01 seconds
Started Jun 25 06:30:08 PM PDT 24
Finished Jun 25 06:30:23 PM PDT 24
Peak memory 215692 kb
Host smart-2f6c6422-324c-4f37-b968-4fe7108c937e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603495614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1603495614
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1365992526
Short name T1028
Test name
Test status
Simulation time 25114163 ps
CPU time 0.77 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:46 PM PDT 24
Peak memory 204096 kb
Host smart-907ddd2f-475c-453d-add9-9af58f29ac48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365992526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1365992526
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.189351664
Short name T1015
Test name
Test status
Simulation time 17417865 ps
CPU time 0.79 seconds
Started Jun 25 06:30:45 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 204368 kb
Host smart-ed7c343c-4fb8-403e-a765-d0ac31f1e8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189351664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.189351664
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2720866843
Short name T1009
Test name
Test status
Simulation time 58954661 ps
CPU time 0.87 seconds
Started Jun 25 06:31:01 PM PDT 24
Finished Jun 25 06:31:04 PM PDT 24
Peak memory 203972 kb
Host smart-e92b8fe3-8dcd-4613-8c8e-4e343aa5b1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720866843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2720866843
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1882756589
Short name T1002
Test name
Test status
Simulation time 59404763 ps
CPU time 0.78 seconds
Started Jun 25 06:30:58 PM PDT 24
Finished Jun 25 06:31:02 PM PDT 24
Peak memory 204004 kb
Host smart-461f75a2-aa1d-4541-b548-2e2e39e0b677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882756589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1882756589
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2005686003
Short name T998
Test name
Test status
Simulation time 16192570 ps
CPU time 0.78 seconds
Started Jun 25 06:30:58 PM PDT 24
Finished Jun 25 06:31:02 PM PDT 24
Peak memory 203964 kb
Host smart-e4ce7b93-f89d-41d6-920d-87fb2bc72f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005686003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2005686003
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2915505415
Short name T1008
Test name
Test status
Simulation time 46688174 ps
CPU time 0.71 seconds
Started Jun 25 06:30:45 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 204336 kb
Host smart-5f8d1642-1ee4-48a1-a3cb-01a5ddf4b67a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915505415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2915505415
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3506977634
Short name T1073
Test name
Test status
Simulation time 11271837 ps
CPU time 0.71 seconds
Started Jun 25 06:30:45 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 204040 kb
Host smart-9e6f84c0-300e-4217-97ea-385a4853ec64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506977634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3506977634
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.313628681
Short name T1100
Test name
Test status
Simulation time 57577294 ps
CPU time 0.73 seconds
Started Jun 25 06:30:43 PM PDT 24
Finished Jun 25 06:30:45 PM PDT 24
Peak memory 204060 kb
Host smart-4f664433-edd1-4153-b156-fe0f2c12184a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313628681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.313628681
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2047475727
Short name T1001
Test name
Test status
Simulation time 15483056 ps
CPU time 0.69 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:45 PM PDT 24
Peak memory 203980 kb
Host smart-e22f059a-cfe4-4b13-a50b-92f98cb4c693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047475727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2047475727
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.484983776
Short name T1032
Test name
Test status
Simulation time 11164153 ps
CPU time 0.73 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:46 PM PDT 24
Peak memory 204348 kb
Host smart-12b3ac88-f0d3-4b7f-9761-78a63915e720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484983776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.484983776
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.981620237
Short name T1075
Test name
Test status
Simulation time 219082149 ps
CPU time 14.63 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:32 PM PDT 24
Peak memory 207468 kb
Host smart-f11117f2-7232-46aa-a590-1c3a85042219
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981620237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.981620237
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.458440069
Short name T118
Test name
Test status
Simulation time 1607425657 ps
CPU time 24.12 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:41 PM PDT 24
Peak memory 207540 kb
Host smart-6ad7fc74-e065-4a0d-aa55-3dbb00fbc45b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458440069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.458440069
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1364268560
Short name T71
Test name
Test status
Simulation time 25698985 ps
CPU time 1.13 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 207704 kb
Host smart-396feb4b-c8a7-4757-89e6-c6a0c02b5c21
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364268560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1364268560
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.387213426
Short name T1035
Test name
Test status
Simulation time 651351382 ps
CPU time 3.74 seconds
Started Jun 25 06:30:12 PM PDT 24
Finished Jun 25 06:30:17 PM PDT 24
Peak memory 216852 kb
Host smart-896cb94d-1286-404e-a7f4-477a6d6fbdd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387213426 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.387213426
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.834340238
Short name T1020
Test name
Test status
Simulation time 176975919 ps
CPU time 2.12 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:17 PM PDT 24
Peak memory 215760 kb
Host smart-e41208b3-c506-462b-938c-d87fe3f73c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834340238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.834340238
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3592565667
Short name T1039
Test name
Test status
Simulation time 157895841 ps
CPU time 0.7 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:16 PM PDT 24
Peak memory 204312 kb
Host smart-cc2b6b5c-34bf-48d0-afb7-2a87de851101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592565667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
592565667
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1121267807
Short name T1094
Test name
Test status
Simulation time 257833214 ps
CPU time 1.66 seconds
Started Jun 25 06:30:17 PM PDT 24
Finished Jun 25 06:30:21 PM PDT 24
Peak memory 215808 kb
Host smart-5066dd40-965e-4dbc-a9b1-832be624d67c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121267807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1121267807
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3515240051
Short name T1048
Test name
Test status
Simulation time 37702083 ps
CPU time 0.67 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:15 PM PDT 24
Peak memory 203940 kb
Host smart-d434fae2-d7b9-49b8-a779-455d9d79e2af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515240051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3515240051
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1926870415
Short name T143
Test name
Test status
Simulation time 206876832 ps
CPU time 4.51 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 215736 kb
Host smart-aa690178-a36c-4031-b5cb-c6d32cacd6f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926870415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1926870415
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1128326420
Short name T180
Test name
Test status
Simulation time 12861841475 ps
CPU time 15.82 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:33 PM PDT 24
Peak memory 215832 kb
Host smart-edf22c35-ad87-43ac-aa73-b60055c43c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128326420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1128326420
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3017493118
Short name T1027
Test name
Test status
Simulation time 40146689 ps
CPU time 0.73 seconds
Started Jun 25 06:30:58 PM PDT 24
Finished Jun 25 06:31:02 PM PDT 24
Peak memory 203916 kb
Host smart-c631f3eb-0fcb-40e1-acfb-97475c7dbde3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017493118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3017493118
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1038851124
Short name T996
Test name
Test status
Simulation time 24038683 ps
CPU time 0.73 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 203988 kb
Host smart-051dbdd0-87d0-4cda-970f-1facb0df0e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038851124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1038851124
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1296762518
Short name T1090
Test name
Test status
Simulation time 15416005 ps
CPU time 0.75 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:46 PM PDT 24
Peak memory 204068 kb
Host smart-102e4167-9c2e-44b2-9b29-cefa2d49cf70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296762518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1296762518
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3172724218
Short name T1067
Test name
Test status
Simulation time 14724387 ps
CPU time 0.75 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 204084 kb
Host smart-02e67e1b-a79a-4a0d-9385-5fa164b8735e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172724218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3172724218
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1103281285
Short name T1047
Test name
Test status
Simulation time 57226264 ps
CPU time 0.72 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 204328 kb
Host smart-615b6603-f3c2-4cc7-b37e-ff4f8a0f5b89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103281285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1103281285
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.621241366
Short name T1091
Test name
Test status
Simulation time 42378499 ps
CPU time 0.73 seconds
Started Jun 25 06:30:45 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 204316 kb
Host smart-151dbb07-64fc-4ca1-afac-10dbd31e416b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621241366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.621241366
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2654421523
Short name T1061
Test name
Test status
Simulation time 13774895 ps
CPU time 0.73 seconds
Started Jun 25 06:30:58 PM PDT 24
Finished Jun 25 06:31:02 PM PDT 24
Peak memory 203908 kb
Host smart-2e3efd8f-74b0-40ba-a098-2da9ed1d7f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654421523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2654421523
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.126911180
Short name T1005
Test name
Test status
Simulation time 12384819 ps
CPU time 0.74 seconds
Started Jun 25 06:31:01 PM PDT 24
Finished Jun 25 06:31:04 PM PDT 24
Peak memory 203916 kb
Host smart-bc3702c9-98e2-4dbe-8b02-56ec6d7b2c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126911180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.126911180
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3237568084
Short name T1089
Test name
Test status
Simulation time 25215064 ps
CPU time 0.7 seconds
Started Jun 25 06:30:45 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 204008 kb
Host smart-5d7279b0-e207-4ee5-bba6-9bf063323f6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237568084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3237568084
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3947521789
Short name T1056
Test name
Test status
Simulation time 49581505 ps
CPU time 0.74 seconds
Started Jun 25 06:31:01 PM PDT 24
Finished Jun 25 06:31:04 PM PDT 24
Peak memory 203968 kb
Host smart-292f5158-f1a7-4990-836e-ff9e97496dcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947521789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3947521789
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1106737728
Short name T146
Test name
Test status
Simulation time 390700367 ps
CPU time 8.44 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:25 PM PDT 24
Peak memory 215832 kb
Host smart-5cbbc042-5294-4214-940c-52b9bde9dff2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106737728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1106737728
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1064252443
Short name T128
Test name
Test status
Simulation time 4780407948 ps
CPU time 38.35 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:55 PM PDT 24
Peak memory 207564 kb
Host smart-638af3d7-80ff-48d0-b246-e96765893f71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064252443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1064252443
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1880933612
Short name T72
Test name
Test status
Simulation time 22463974 ps
CPU time 1.41 seconds
Started Jun 25 06:30:16 PM PDT 24
Finished Jun 25 06:30:20 PM PDT 24
Peak memory 207444 kb
Host smart-7aeff774-b798-4ac8-8ab8-8be8f274f599
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880933612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1880933612
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1029729392
Short name T109
Test name
Test status
Simulation time 245341167 ps
CPU time 3.77 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 218520 kb
Host smart-f003315d-3acc-4275-a90e-c2e08a7c6ff4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029729392 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1029729392
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1588655767
Short name T126
Test name
Test status
Simulation time 129011028 ps
CPU time 3.13 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:18 PM PDT 24
Peak memory 215776 kb
Host smart-6cb4af76-5092-444e-a3f8-af4310c6907b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588655767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
588655767
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3334663642
Short name T1013
Test name
Test status
Simulation time 56503134 ps
CPU time 0.8 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:14 PM PDT 24
Peak memory 203992 kb
Host smart-91c1e09b-f405-49fe-8b31-217e34898733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334663642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
334663642
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.711192254
Short name T1074
Test name
Test status
Simulation time 101616457 ps
CPU time 1.83 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:17 PM PDT 24
Peak memory 215664 kb
Host smart-06e9e4bd-b241-416f-a3ac-d146d47f51ee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711192254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.711192254
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3378920807
Short name T994
Test name
Test status
Simulation time 27755755 ps
CPU time 0.67 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:15 PM PDT 24
Peak memory 203976 kb
Host smart-74958967-9478-4a58-96cc-ff31e1cc2f33
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378920807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3378920807
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1988881981
Short name T1076
Test name
Test status
Simulation time 593138341 ps
CPU time 4.19 seconds
Started Jun 25 06:30:16 PM PDT 24
Finished Jun 25 06:30:22 PM PDT 24
Peak memory 215792 kb
Host smart-a9157f81-ac62-4fd0-914c-49c262f78e8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988881981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1988881981
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4077117180
Short name T113
Test name
Test status
Simulation time 42207321 ps
CPU time 2.58 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:18 PM PDT 24
Peak memory 216092 kb
Host smart-63a413cc-da03-47cb-b968-d54a564289a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077117180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
077117180
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3564921350
Short name T1057
Test name
Test status
Simulation time 1074787749 ps
CPU time 22.84 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:39 PM PDT 24
Peak memory 215800 kb
Host smart-6454721f-b620-4381-8d11-c7d6c6a01b35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564921350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3564921350
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2398886191
Short name T1007
Test name
Test status
Simulation time 13624691 ps
CPU time 0.78 seconds
Started Jun 25 06:30:45 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 204052 kb
Host smart-38dced7b-7911-4945-84e1-229b4c68615d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398886191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2398886191
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2965115228
Short name T997
Test name
Test status
Simulation time 97455970 ps
CPU time 0.71 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:47 PM PDT 24
Peak memory 204324 kb
Host smart-2b73b065-d72e-466f-9ec2-aa2676beeef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965115228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2965115228
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.901592702
Short name T1046
Test name
Test status
Simulation time 14677618 ps
CPU time 0.77 seconds
Started Jun 25 06:30:44 PM PDT 24
Finished Jun 25 06:30:46 PM PDT 24
Peak memory 204316 kb
Host smart-81cb0435-7165-4d8f-8ea0-e8a181ae2966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901592702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.901592702
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3852362071
Short name T1049
Test name
Test status
Simulation time 31247744 ps
CPU time 0.76 seconds
Started Jun 25 06:30:46 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 204272 kb
Host smart-837c29c9-24c8-4e5c-84c3-38d39100575f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852362071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3852362071
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3517152416
Short name T1077
Test name
Test status
Simulation time 57797689 ps
CPU time 0.81 seconds
Started Jun 25 06:30:46 PM PDT 24
Finished Jun 25 06:30:48 PM PDT 24
Peak memory 204084 kb
Host smart-d53b74bc-2960-4604-a228-c2cb962d147a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517152416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3517152416
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2516505314
Short name T1084
Test name
Test status
Simulation time 50138683 ps
CPU time 0.75 seconds
Started Jun 25 06:30:56 PM PDT 24
Finished Jun 25 06:30:58 PM PDT 24
Peak memory 204076 kb
Host smart-ce98bd26-3a5d-4a7c-8636-bdcfb26839da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516505314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2516505314
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.84005374
Short name T1006
Test name
Test status
Simulation time 23651618 ps
CPU time 0.75 seconds
Started Jun 25 06:30:56 PM PDT 24
Finished Jun 25 06:30:58 PM PDT 24
Peak memory 204076 kb
Host smart-b2ba3f90-9198-4b41-9e76-98f1ba9fcdea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84005374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.84005374
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1742320009
Short name T1086
Test name
Test status
Simulation time 13772176 ps
CPU time 0.73 seconds
Started Jun 25 06:30:57 PM PDT 24
Finished Jun 25 06:31:01 PM PDT 24
Peak memory 204016 kb
Host smart-f55fa65d-1db4-428c-84eb-5b45ea964617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742320009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1742320009
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.834748292
Short name T1017
Test name
Test status
Simulation time 13872564 ps
CPU time 0.76 seconds
Started Jun 25 06:30:56 PM PDT 24
Finished Jun 25 06:30:59 PM PDT 24
Peak memory 204076 kb
Host smart-6dc4fe33-21f4-40c2-bed8-7b2dce357ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834748292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.834748292
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3235398075
Short name T1099
Test name
Test status
Simulation time 58765032 ps
CPU time 0.75 seconds
Started Jun 25 06:30:56 PM PDT 24
Finished Jun 25 06:30:58 PM PDT 24
Peak memory 204060 kb
Host smart-996111fa-ccae-43ef-a521-9887c9e8b0aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235398075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3235398075
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.254866290
Short name T90
Test name
Test status
Simulation time 59841804 ps
CPU time 4.02 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:21 PM PDT 24
Peak memory 217656 kb
Host smart-c927bdec-660b-40eb-a244-b214151aca05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254866290 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.254866290
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3605003540
Short name T1080
Test name
Test status
Simulation time 232294587 ps
CPU time 1.27 seconds
Started Jun 25 06:30:15 PM PDT 24
Finished Jun 25 06:30:18 PM PDT 24
Peak memory 207492 kb
Host smart-5acd5f58-5e90-40de-8a5c-316676a6f727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605003540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
605003540
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.609354484
Short name T1033
Test name
Test status
Simulation time 30694525 ps
CPU time 0.78 seconds
Started Jun 25 06:30:16 PM PDT 24
Finished Jun 25 06:30:19 PM PDT 24
Peak memory 204188 kb
Host smart-05fc2dcf-7996-44c8-9ff8-f57d9897d3ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609354484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.609354484
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.523526938
Short name T135
Test name
Test status
Simulation time 44099927 ps
CPU time 3.07 seconds
Started Jun 25 06:30:13 PM PDT 24
Finished Jun 25 06:30:18 PM PDT 24
Peak memory 215776 kb
Host smart-2105f0e1-38af-4f86-801c-46c6ac51e756
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523526938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.523526938
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1319260747
Short name T1043
Test name
Test status
Simulation time 286158786 ps
CPU time 2.12 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:18 PM PDT 24
Peak memory 215820 kb
Host smart-e2d14176-62e0-43d9-a9a1-173c7ad5c6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319260747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
319260747
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2584381850
Short name T1052
Test name
Test status
Simulation time 558397866 ps
CPU time 18.86 seconds
Started Jun 25 06:30:14 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 217112 kb
Host smart-b6630bd8-e7f3-4d0a-81ea-10043d26c102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584381850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2584381850
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2268319754
Short name T1059
Test name
Test status
Simulation time 122944511 ps
CPU time 1.74 seconds
Started Jun 25 06:30:22 PM PDT 24
Finished Jun 25 06:30:26 PM PDT 24
Peak memory 215760 kb
Host smart-9dae38f4-6323-4567-bfcf-0fe17b4675a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268319754 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2268319754
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3568355498
Short name T1063
Test name
Test status
Simulation time 78913020 ps
CPU time 1.49 seconds
Started Jun 25 06:30:34 PM PDT 24
Finished Jun 25 06:30:37 PM PDT 24
Peak memory 215800 kb
Host smart-b8e1c8f7-be91-4c45-961c-b7bcfd4c01d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568355498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
568355498
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2787206915
Short name T1004
Test name
Test status
Simulation time 44920778 ps
CPU time 0.77 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:22 PM PDT 24
Peak memory 204260 kb
Host smart-089ead8e-447f-4eab-9d73-4480f1685059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787206915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
787206915
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3740589978
Short name T1060
Test name
Test status
Simulation time 120739167 ps
CPU time 1.98 seconds
Started Jun 25 06:30:22 PM PDT 24
Finished Jun 25 06:30:25 PM PDT 24
Peak memory 215796 kb
Host smart-f9adc2ca-0147-4100-b7b3-8fb9f4a93cba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740589978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3740589978
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.980251923
Short name T112
Test name
Test status
Simulation time 29481374 ps
CPU time 1.76 seconds
Started Jun 25 06:30:34 PM PDT 24
Finished Jun 25 06:30:37 PM PDT 24
Peak memory 215824 kb
Host smart-f1939f26-a377-410a-a43c-c67983dca0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980251923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.980251923
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3735860133
Short name T182
Test name
Test status
Simulation time 575585342 ps
CPU time 18.45 seconds
Started Jun 25 06:30:21 PM PDT 24
Finished Jun 25 06:30:41 PM PDT 24
Peak memory 215888 kb
Host smart-d5a83482-bcb8-4a37-913e-b3775d9d7664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735860133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3735860133
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4068808610
Short name T111
Test name
Test status
Simulation time 289256938 ps
CPU time 2.68 seconds
Started Jun 25 06:30:25 PM PDT 24
Finished Jun 25 06:30:29 PM PDT 24
Peak memory 218264 kb
Host smart-f77c4c8d-f295-416d-aa80-9b415055acfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068808610 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4068808610
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2570107856
Short name T115
Test name
Test status
Simulation time 151205735 ps
CPU time 1.28 seconds
Started Jun 25 06:30:39 PM PDT 24
Finished Jun 25 06:30:42 PM PDT 24
Peak memory 215736 kb
Host smart-5b8f8881-0d64-4238-88d1-bc76bc7af7b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570107856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
570107856
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2598512423
Short name T1085
Test name
Test status
Simulation time 24514381 ps
CPU time 0.76 seconds
Started Jun 25 06:30:33 PM PDT 24
Finished Jun 25 06:30:35 PM PDT 24
Peak memory 204076 kb
Host smart-d8d38d65-4faa-4730-a0f6-ec8b2e8c1fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598512423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
598512423
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4221502910
Short name T142
Test name
Test status
Simulation time 275888980 ps
CPU time 3.26 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:24 PM PDT 24
Peak memory 215792 kb
Host smart-602b75b4-990b-41b2-b3ba-3a86af56fa21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221502910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4221502910
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.998451404
Short name T105
Test name
Test status
Simulation time 768221251 ps
CPU time 5.5 seconds
Started Jun 25 06:30:19 PM PDT 24
Finished Jun 25 06:30:26 PM PDT 24
Peak memory 215832 kb
Host smart-75ead3b3-9f5a-4cf4-9852-6e8d21e15b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998451404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.998451404
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3953566230
Short name T91
Test name
Test status
Simulation time 440646725 ps
CPU time 13.28 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:35 PM PDT 24
Peak memory 215716 kb
Host smart-e516f83b-9e2e-4230-808b-25bd61892992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953566230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3953566230
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2362752256
Short name T1093
Test name
Test status
Simulation time 220829144 ps
CPU time 4.1 seconds
Started Jun 25 06:30:21 PM PDT 24
Finished Jun 25 06:30:27 PM PDT 24
Peak memory 218252 kb
Host smart-4203bffc-79cb-4a88-853a-7dceca2aa2fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362752256 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2362752256
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1836637781
Short name T1055
Test name
Test status
Simulation time 199499802 ps
CPU time 2.62 seconds
Started Jun 25 06:30:23 PM PDT 24
Finished Jun 25 06:30:27 PM PDT 24
Peak memory 215756 kb
Host smart-8d42542f-c66b-489c-86a8-0243f6571036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836637781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
836637781
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3460834848
Short name T1041
Test name
Test status
Simulation time 11239582 ps
CPU time 0.74 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:22 PM PDT 24
Peak memory 204320 kb
Host smart-d13aa6a9-fcfc-47c2-96ba-f2f4316f44fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460834848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
460834848
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1881744060
Short name T136
Test name
Test status
Simulation time 593887129 ps
CPU time 4.33 seconds
Started Jun 25 06:30:21 PM PDT 24
Finished Jun 25 06:30:27 PM PDT 24
Peak memory 216260 kb
Host smart-cbe2317d-41f6-4792-8cba-79ef4d7f6da7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881744060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1881744060
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.431337222
Short name T93
Test name
Test status
Simulation time 54673564 ps
CPU time 1.7 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:23 PM PDT 24
Peak memory 215824 kb
Host smart-e687cbcd-4b6b-4536-ac1f-2908e76078d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431337222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.431337222
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1008736179
Short name T92
Test name
Test status
Simulation time 202166277 ps
CPU time 13.11 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 215728 kb
Host smart-cd322137-ac81-48e9-b5cb-f45f3749f840
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008736179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1008736179
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2245641235
Short name T1026
Test name
Test status
Simulation time 360157280 ps
CPU time 1.8 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:24 PM PDT 24
Peak memory 216880 kb
Host smart-fdce7579-15d7-4083-a409-c63b98fd04d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245641235 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2245641235
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3015134384
Short name T125
Test name
Test status
Simulation time 92569972 ps
CPU time 2.66 seconds
Started Jun 25 06:30:33 PM PDT 24
Finished Jun 25 06:30:37 PM PDT 24
Peak memory 215700 kb
Host smart-18de4a50-5b87-4100-859a-07890a25d28b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015134384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
015134384
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3212588784
Short name T1029
Test name
Test status
Simulation time 17363551 ps
CPU time 0.77 seconds
Started Jun 25 06:30:33 PM PDT 24
Finished Jun 25 06:30:34 PM PDT 24
Peak memory 204328 kb
Host smart-93dc5a57-75f0-4a7a-9b05-83fdac39c9d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212588784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
212588784
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2851717570
Short name T1003
Test name
Test status
Simulation time 63186019 ps
CPU time 3.97 seconds
Started Jun 25 06:30:20 PM PDT 24
Finished Jun 25 06:30:25 PM PDT 24
Peak memory 215696 kb
Host smart-cc9e9c1c-18e0-441a-92bb-e3ced88bc30e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851717570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2851717570
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.768245242
Short name T97
Test name
Test status
Simulation time 143130383 ps
CPU time 3.69 seconds
Started Jun 25 06:30:21 PM PDT 24
Finished Jun 25 06:30:26 PM PDT 24
Peak memory 215952 kb
Host smart-e8ce1ebf-b7bd-4e8d-820e-a4e182625ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768245242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.768245242
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2373973247
Short name T87
Test name
Test status
Simulation time 328785463 ps
CPU time 13.65 seconds
Started Jun 25 06:30:23 PM PDT 24
Finished Jun 25 06:30:38 PM PDT 24
Peak memory 216256 kb
Host smart-562dac43-561f-49d1-9a24-300b06f68d37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373973247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2373973247
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.714310102
Short name T981
Test name
Test status
Simulation time 173666085 ps
CPU time 0.74 seconds
Started Jun 25 06:44:54 PM PDT 24
Finished Jun 25 06:44:56 PM PDT 24
Peak memory 205868 kb
Host smart-4793c2bc-aea0-4481-b0d2-d87f23ae6acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714310102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.714310102
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3985239918
Short name T81
Test name
Test status
Simulation time 39810309 ps
CPU time 2.58 seconds
Started Jun 25 06:44:48 PM PDT 24
Finished Jun 25 06:44:51 PM PDT 24
Peak memory 233132 kb
Host smart-303bfb9e-fabb-40d4-b72f-83145b2912f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985239918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3985239918
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3927048961
Short name T377
Test name
Test status
Simulation time 13535849 ps
CPU time 0.74 seconds
Started Jun 25 06:44:31 PM PDT 24
Finished Jun 25 06:44:33 PM PDT 24
Peak memory 205964 kb
Host smart-fdf6de07-4349-49eb-91f7-81561d41554f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927048961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3927048961
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3471141269
Short name T316
Test name
Test status
Simulation time 95054261142 ps
CPU time 338.88 seconds
Started Jun 25 06:44:55 PM PDT 24
Finished Jun 25 06:50:34 PM PDT 24
Peak memory 250688 kb
Host smart-d3f6aa09-6591-4845-aa73-cab3ac288155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471141269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3471141269
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1302464394
Short name T726
Test name
Test status
Simulation time 26463228078 ps
CPU time 150.1 seconds
Started Jun 25 06:44:54 PM PDT 24
Finished Jun 25 06:47:25 PM PDT 24
Peak memory 249880 kb
Host smart-a8cdc91f-9f76-4c09-b07b-8ce6828ba392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302464394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1302464394
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1832257037
Short name T716
Test name
Test status
Simulation time 9755511794 ps
CPU time 41.56 seconds
Started Jun 25 06:44:54 PM PDT 24
Finished Jun 25 06:45:36 PM PDT 24
Peak memory 241508 kb
Host smart-c37ace09-68b8-41be-8f03-bcf836d150f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832257037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1832257037
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1913858836
Short name T324
Test name
Test status
Simulation time 286477979 ps
CPU time 5.69 seconds
Started Jun 25 06:44:46 PM PDT 24
Finished Jun 25 06:44:52 PM PDT 24
Peak memory 241400 kb
Host smart-2bd46cd7-631d-41ee-8580-de34d38e80bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913858836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1913858836
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2182413727
Short name T522
Test name
Test status
Simulation time 2169536894 ps
CPU time 17.38 seconds
Started Jun 25 06:44:45 PM PDT 24
Finished Jun 25 06:45:03 PM PDT 24
Peak memory 225008 kb
Host smart-cbcda6ad-58f4-4b2d-accd-14e3ccd8e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182413727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2182413727
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1029027512
Short name T274
Test name
Test status
Simulation time 9185738644 ps
CPU time 89.18 seconds
Started Jun 25 06:44:47 PM PDT 24
Finished Jun 25 06:46:17 PM PDT 24
Peak memory 225000 kb
Host smart-d480287b-1b26-455e-90fb-5ee1cd1922fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029027512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1029027512
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3194033561
Short name T787
Test name
Test status
Simulation time 15608075 ps
CPU time 1.1 seconds
Started Jun 25 06:44:33 PM PDT 24
Finished Jun 25 06:44:35 PM PDT 24
Peak memory 217148 kb
Host smart-0583c742-71f4-4a2b-a9f7-52a4fc80fdb1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194033561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3194033561
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4280092691
Short name T299
Test name
Test status
Simulation time 26409143852 ps
CPU time 19.38 seconds
Started Jun 25 06:44:45 PM PDT 24
Finished Jun 25 06:45:06 PM PDT 24
Peak memory 234852 kb
Host smart-ba1dad51-fe51-4170-a04e-ea41c8553616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280092691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4280092691
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2322355300
Short name T405
Test name
Test status
Simulation time 118000735 ps
CPU time 2.42 seconds
Started Jun 25 06:44:40 PM PDT 24
Finished Jun 25 06:44:43 PM PDT 24
Peak memory 232940 kb
Host smart-257b9592-ba40-4222-9375-f459e0c2ea29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322355300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2322355300
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.766002457
Short name T778
Test name
Test status
Simulation time 137027819 ps
CPU time 5.18 seconds
Started Jun 25 06:44:53 PM PDT 24
Finished Jun 25 06:44:59 PM PDT 24
Peak memory 220696 kb
Host smart-1c8b767e-488b-4c83-b6db-2e9b39e292f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=766002457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.766002457
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.690079712
Short name T62
Test name
Test status
Simulation time 117941215 ps
CPU time 1.05 seconds
Started Jun 25 06:44:53 PM PDT 24
Finished Jun 25 06:44:55 PM PDT 24
Peak memory 235812 kb
Host smart-6bef3f38-d520-46bd-b623-c91837277658
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690079712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.690079712
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2956469255
Short name T520
Test name
Test status
Simulation time 4413496836 ps
CPU time 23.45 seconds
Started Jun 25 06:44:41 PM PDT 24
Finished Jun 25 06:45:05 PM PDT 24
Peak memory 216816 kb
Host smart-ccf91eaa-9be7-40bc-ab9f-8be0ecada28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956469255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2956469255
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2108596685
Short name T952
Test name
Test status
Simulation time 1065303461 ps
CPU time 6.36 seconds
Started Jun 25 06:44:32 PM PDT 24
Finished Jun 25 06:44:39 PM PDT 24
Peak memory 216764 kb
Host smart-2031dfa4-29b5-4017-943e-86870f5b0e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108596685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2108596685
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2474434475
Short name T380
Test name
Test status
Simulation time 224597627 ps
CPU time 3.81 seconds
Started Jun 25 06:44:38 PM PDT 24
Finished Jun 25 06:44:42 PM PDT 24
Peak memory 216732 kb
Host smart-39758dff-ad93-492f-a3fa-3c4bcc4b97fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474434475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2474434475
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1154178307
Short name T378
Test name
Test status
Simulation time 60443561 ps
CPU time 0.92 seconds
Started Jun 25 06:44:39 PM PDT 24
Finished Jun 25 06:44:40 PM PDT 24
Peak memory 206356 kb
Host smart-ebd6a013-ceec-4d20-80a8-b8dcf63c932c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154178307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1154178307
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1309760157
Short name T622
Test name
Test status
Simulation time 223124711 ps
CPU time 2.39 seconds
Started Jun 25 06:44:48 PM PDT 24
Finished Jun 25 06:44:51 PM PDT 24
Peak memory 224640 kb
Host smart-00b87b60-2add-4e11-91da-b80ed3fba0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309760157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1309760157
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.871425280
Short name T543
Test name
Test status
Simulation time 11496779 ps
CPU time 0.72 seconds
Started Jun 25 06:45:19 PM PDT 24
Finished Jun 25 06:45:21 PM PDT 24
Peak memory 205224 kb
Host smart-6414ae70-9c03-4886-8d75-9d8398945003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871425280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.871425280
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2247503416
Short name T616
Test name
Test status
Simulation time 7863912939 ps
CPU time 14.74 seconds
Started Jun 25 06:45:20 PM PDT 24
Finished Jun 25 06:45:35 PM PDT 24
Peak memory 233168 kb
Host smart-18df66e0-19cd-4f24-b6d2-1426bf055eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247503416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2247503416
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2858419970
Short name T398
Test name
Test status
Simulation time 118762514 ps
CPU time 0.76 seconds
Started Jun 25 06:45:01 PM PDT 24
Finished Jun 25 06:45:02 PM PDT 24
Peak memory 205948 kb
Host smart-3a8ed08c-1603-4fd8-a10b-a707060ca37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858419970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2858419970
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3801807310
Short name T907
Test name
Test status
Simulation time 754296491 ps
CPU time 7.42 seconds
Started Jun 25 06:45:18 PM PDT 24
Finished Jun 25 06:45:26 PM PDT 24
Peak memory 233188 kb
Host smart-a187d048-b760-49cd-b6bf-9150e713a164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801807310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3801807310
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1275487846
Short name T158
Test name
Test status
Simulation time 46618076146 ps
CPU time 195.72 seconds
Started Jun 25 06:45:18 PM PDT 24
Finished Jun 25 06:48:34 PM PDT 24
Peak memory 249700 kb
Host smart-0d13ddd1-85a8-4139-9efe-cb0cb0b31ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275487846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1275487846
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2257355282
Short name T966
Test name
Test status
Simulation time 14046608405 ps
CPU time 52.92 seconds
Started Jun 25 06:45:19 PM PDT 24
Finished Jun 25 06:46:12 PM PDT 24
Peak memory 225064 kb
Host smart-ea253015-3f1f-48da-89ed-db8fe72a78f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257355282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2257355282
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1695447814
Short name T555
Test name
Test status
Simulation time 2293305854 ps
CPU time 13.08 seconds
Started Jun 25 06:45:20 PM PDT 24
Finished Jun 25 06:45:34 PM PDT 24
Peak memory 249664 kb
Host smart-ebcc2385-505c-4ffb-a6b1-cd690c9f8b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695447814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1695447814
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1026367022
Short name T246
Test name
Test status
Simulation time 654653579 ps
CPU time 6.25 seconds
Started Jun 25 06:45:08 PM PDT 24
Finished Jun 25 06:45:15 PM PDT 24
Peak memory 224808 kb
Host smart-bd361d6e-5636-4521-8ab0-f0888cfb12d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026367022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1026367022
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1506084714
Short name T558
Test name
Test status
Simulation time 7178579232 ps
CPU time 22.42 seconds
Started Jun 25 06:45:10 PM PDT 24
Finished Jun 25 06:45:34 PM PDT 24
Peak memory 235012 kb
Host smart-9e5b6227-e423-4a51-8576-4802f5312aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506084714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1506084714
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2648267527
Short name T925
Test name
Test status
Simulation time 3459677351 ps
CPU time 11.95 seconds
Started Jun 25 06:45:10 PM PDT 24
Finished Jun 25 06:45:24 PM PDT 24
Peak memory 241288 kb
Host smart-f5efa80b-75b3-4f46-8bf0-8ded8b767781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648267527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2648267527
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4157216124
Short name T588
Test name
Test status
Simulation time 351430246 ps
CPU time 4.05 seconds
Started Jun 25 06:45:20 PM PDT 24
Finished Jun 25 06:45:25 PM PDT 24
Peak memory 220804 kb
Host smart-fd4846b5-ee15-46d1-83f6-ef766f35dfd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4157216124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4157216124
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1818716332
Short name T61
Test name
Test status
Simulation time 116193975 ps
CPU time 0.98 seconds
Started Jun 25 06:45:21 PM PDT 24
Finished Jun 25 06:45:23 PM PDT 24
Peak memory 235872 kb
Host smart-5290da46-6b3c-4591-842d-13cbbb8cdb77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818716332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1818716332
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2851320219
Short name T928
Test name
Test status
Simulation time 33909332 ps
CPU time 0.9 seconds
Started Jun 25 06:45:20 PM PDT 24
Finished Jun 25 06:45:22 PM PDT 24
Peak memory 207360 kb
Host smart-b62eb42c-7da2-4f70-ae11-26ef8f5b893c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851320219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2851320219
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1945447351
Short name T409
Test name
Test status
Simulation time 3299613082 ps
CPU time 9.2 seconds
Started Jun 25 06:44:59 PM PDT 24
Finished Jun 25 06:45:09 PM PDT 24
Peak memory 216884 kb
Host smart-23fc02e8-4a6b-452a-bb92-81788273183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945447351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1945447351
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2317705546
Short name T800
Test name
Test status
Simulation time 187423964 ps
CPU time 1.24 seconds
Started Jun 25 06:45:01 PM PDT 24
Finished Jun 25 06:45:03 PM PDT 24
Peak memory 207564 kb
Host smart-8b785a93-202b-41c8-a122-fe494336f5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317705546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2317705546
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.553493324
Short name T585
Test name
Test status
Simulation time 355856938 ps
CPU time 0.83 seconds
Started Jun 25 06:45:09 PM PDT 24
Finished Jun 25 06:45:11 PM PDT 24
Peak memory 206364 kb
Host smart-cddf48ec-52e2-4c5f-8064-e9b56704a0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553493324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.553493324
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.966233983
Short name T383
Test name
Test status
Simulation time 248152776 ps
CPU time 0.96 seconds
Started Jun 25 06:45:00 PM PDT 24
Finished Jun 25 06:45:02 PM PDT 24
Peak memory 206336 kb
Host smart-5abcd252-2536-4982-826d-d535048c5e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966233983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.966233983
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4231543143
Short name T190
Test name
Test status
Simulation time 750697933 ps
CPU time 2.22 seconds
Started Jun 25 06:45:19 PM PDT 24
Finished Jun 25 06:45:23 PM PDT 24
Peak memory 224796 kb
Host smart-e368696b-7d8a-482d-a581-6332539df923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231543143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4231543143
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.727964320
Short name T949
Test name
Test status
Simulation time 32371565 ps
CPU time 0.7 seconds
Started Jun 25 06:47:38 PM PDT 24
Finished Jun 25 06:47:40 PM PDT 24
Peak memory 206244 kb
Host smart-84f59a54-b44b-40e3-b446-abdb83e0b6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727964320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.727964320
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.295484050
Short name T16
Test name
Test status
Simulation time 394206258 ps
CPU time 2.66 seconds
Started Jun 25 06:47:29 PM PDT 24
Finished Jun 25 06:47:35 PM PDT 24
Peak memory 233112 kb
Host smart-68bfdfe2-a51e-4c80-b3e3-cfa0a1febcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295484050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.295484050
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2356346107
Short name T343
Test name
Test status
Simulation time 20382977 ps
CPU time 0.82 seconds
Started Jun 25 06:47:29 PM PDT 24
Finished Jun 25 06:47:34 PM PDT 24
Peak memory 207092 kb
Host smart-f876a661-61be-467a-83f7-ea3e0504951a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356346107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2356346107
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.884651996
Short name T168
Test name
Test status
Simulation time 15068305648 ps
CPU time 100.25 seconds
Started Jun 25 06:47:37 PM PDT 24
Finished Jun 25 06:49:18 PM PDT 24
Peak memory 252260 kb
Host smart-608907c2-e2e4-4b8c-bc09-6aa540d66b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884651996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.884651996
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1574254277
Short name T218
Test name
Test status
Simulation time 17331463896 ps
CPU time 106.64 seconds
Started Jun 25 06:47:37 PM PDT 24
Finished Jun 25 06:49:24 PM PDT 24
Peak memory 250724 kb
Host smart-ca7a5ae1-8826-4166-afaa-71580b751bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574254277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1574254277
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3481264686
Short name T962
Test name
Test status
Simulation time 185476163808 ps
CPU time 486.02 seconds
Started Jun 25 06:47:38 PM PDT 24
Finished Jun 25 06:55:45 PM PDT 24
Peak memory 254596 kb
Host smart-6c3d43c1-7f97-4c23-a76c-efa679a8eed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481264686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3481264686
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2889698327
Short name T930
Test name
Test status
Simulation time 801593465 ps
CPU time 7.52 seconds
Started Jun 25 06:47:37 PM PDT 24
Finished Jun 25 06:47:45 PM PDT 24
Peak memory 233220 kb
Host smart-88218d39-8686-42ff-b129-42ac3ed48f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889698327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2889698327
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.521497937
Short name T162
Test name
Test status
Simulation time 64897078 ps
CPU time 2.74 seconds
Started Jun 25 06:47:28 PM PDT 24
Finished Jun 25 06:47:34 PM PDT 24
Peak memory 232976 kb
Host smart-8d5b6980-8bac-47e2-82b1-36e1d1263aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521497937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.521497937
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.349981737
Short name T854
Test name
Test status
Simulation time 1237581751 ps
CPU time 11.07 seconds
Started Jun 25 06:47:31 PM PDT 24
Finished Jun 25 06:47:45 PM PDT 24
Peak memory 233140 kb
Host smart-6cb73fe2-1a12-4151-b913-ddb36d2e006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349981737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.349981737
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3291071506
Short name T420
Test name
Test status
Simulation time 86133884 ps
CPU time 1.13 seconds
Started Jun 25 06:47:29 PM PDT 24
Finished Jun 25 06:47:33 PM PDT 24
Peak memory 217168 kb
Host smart-1b8571a4-886e-4413-9b5c-028610a869bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291071506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3291071506
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4201292921
Short name T822
Test name
Test status
Simulation time 2432488673 ps
CPU time 6.39 seconds
Started Jun 25 06:47:29 PM PDT 24
Finished Jun 25 06:47:39 PM PDT 24
Peak memory 234216 kb
Host smart-ff6f0ca4-48f5-403f-92ff-aff81ef6b7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201292921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4201292921
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2351422701
Short name T582
Test name
Test status
Simulation time 5756483565 ps
CPU time 17.42 seconds
Started Jun 25 06:47:29 PM PDT 24
Finished Jun 25 06:47:50 PM PDT 24
Peak memory 233284 kb
Host smart-760f8715-72cc-4d33-aae4-608d7e1a1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351422701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2351422701
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.61184299
Short name T784
Test name
Test status
Simulation time 665866706 ps
CPU time 9.08 seconds
Started Jun 25 06:47:38 PM PDT 24
Finished Jun 25 06:47:48 PM PDT 24
Peak memory 222552 kb
Host smart-91b82d12-6149-4779-a882-280c6b1e8d1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=61184299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direc
t.61184299
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1025278939
Short name T944
Test name
Test status
Simulation time 24528780025 ps
CPU time 34.59 seconds
Started Jun 25 06:47:31 PM PDT 24
Finished Jun 25 06:48:09 PM PDT 24
Peak memory 216832 kb
Host smart-5287a9df-f40b-4c6d-bd88-36de3a3cc810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025278939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1025278939
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1218819643
Short name T770
Test name
Test status
Simulation time 370251362 ps
CPU time 1.92 seconds
Started Jun 25 06:47:29 PM PDT 24
Finished Jun 25 06:47:34 PM PDT 24
Peak memory 208388 kb
Host smart-77a9e088-4d59-4812-923d-3588866c300a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218819643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1218819643
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2085841194
Short name T869
Test name
Test status
Simulation time 908008862 ps
CPU time 3.33 seconds
Started Jun 25 06:47:29 PM PDT 24
Finished Jun 25 06:47:36 PM PDT 24
Peak memory 216828 kb
Host smart-dde1ce85-db16-4b6c-bb35-a13717828e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085841194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2085841194
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1011855652
Short name T706
Test name
Test status
Simulation time 431890945 ps
CPU time 0.9 seconds
Started Jun 25 06:47:30 PM PDT 24
Finished Jun 25 06:47:35 PM PDT 24
Peak memory 206364 kb
Host smart-12bf6a78-2900-48a1-b195-8c2e643711f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011855652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1011855652
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2667744966
Short name T866
Test name
Test status
Simulation time 3656412134 ps
CPU time 21.33 seconds
Started Jun 25 06:47:28 PM PDT 24
Finished Jun 25 06:47:52 PM PDT 24
Peak memory 225008 kb
Host smart-51bd59d2-ef71-459a-8a00-c9eafdaa3045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667744966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2667744966
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.554564719
Short name T862
Test name
Test status
Simulation time 17502457 ps
CPU time 0.74 seconds
Started Jun 25 06:47:45 PM PDT 24
Finished Jun 25 06:47:47 PM PDT 24
Peak memory 205356 kb
Host smart-2524f125-d2a7-41ab-be01-110208265243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554564719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.554564719
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2004101676
Short name T775
Test name
Test status
Simulation time 577080684 ps
CPU time 6.75 seconds
Started Jun 25 06:47:49 PM PDT 24
Finished Jun 25 06:47:57 PM PDT 24
Peak memory 233176 kb
Host smart-3426e205-3949-401d-a415-87dd7e05b686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004101676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2004101676
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2436720967
Short name T899
Test name
Test status
Simulation time 40984358 ps
CPU time 0.78 seconds
Started Jun 25 06:47:39 PM PDT 24
Finished Jun 25 06:47:41 PM PDT 24
Peak memory 207316 kb
Host smart-7045da49-2a73-4246-8a5e-9b3aec1d640a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436720967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2436720967
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.173034412
Short name T47
Test name
Test status
Simulation time 17133946990 ps
CPU time 150.97 seconds
Started Jun 25 06:47:49 PM PDT 24
Finished Jun 25 06:50:21 PM PDT 24
Peak memory 253256 kb
Host smart-15e250c8-161c-4c21-815a-8239f3b6ef97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173034412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.173034412
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.978244957
Short name T318
Test name
Test status
Simulation time 24708372077 ps
CPU time 234.42 seconds
Started Jun 25 06:47:45 PM PDT 24
Finished Jun 25 06:51:42 PM PDT 24
Peak memory 245984 kb
Host smart-8efe1f7e-0e1a-4746-860e-cdf5f72caa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978244957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.978244957
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4137411639
Short name T700
Test name
Test status
Simulation time 22365843148 ps
CPU time 115.3 seconds
Started Jun 25 06:47:47 PM PDT 24
Finished Jun 25 06:49:44 PM PDT 24
Peak memory 249700 kb
Host smart-92a812cf-967f-4651-bfc4-b84ff16085bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137411639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4137411639
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4143946162
Short name T782
Test name
Test status
Simulation time 639818098 ps
CPU time 5.81 seconds
Started Jun 25 06:47:46 PM PDT 24
Finished Jun 25 06:47:53 PM PDT 24
Peak memory 224996 kb
Host smart-9d8a58fd-9477-45e5-8461-4027660914e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143946162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4143946162
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3203616190
Short name T933
Test name
Test status
Simulation time 2124859899 ps
CPU time 18.23 seconds
Started Jun 25 06:47:45 PM PDT 24
Finished Jun 25 06:48:04 PM PDT 24
Peak memory 224944 kb
Host smart-0b12c378-8baa-4dbb-86d7-c25534805bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203616190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3203616190
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3088227800
Short name T271
Test name
Test status
Simulation time 5891286308 ps
CPU time 12.11 seconds
Started Jun 25 06:47:46 PM PDT 24
Finished Jun 25 06:48:00 PM PDT 24
Peak memory 233216 kb
Host smart-4230ab72-dfa2-4ba4-8b89-7f311ea29ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088227800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3088227800
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.582567753
Short name T40
Test name
Test status
Simulation time 214621949 ps
CPU time 1.13 seconds
Started Jun 25 06:47:37 PM PDT 24
Finished Jun 25 06:47:40 PM PDT 24
Peak memory 217160 kb
Host smart-015d59f5-e236-4071-9356-7bd8f545e9f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582567753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.582567753
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3388341977
Short name T627
Test name
Test status
Simulation time 5335516247 ps
CPU time 18.48 seconds
Started Jun 25 06:47:46 PM PDT 24
Finished Jun 25 06:48:06 PM PDT 24
Peak memory 233172 kb
Host smart-d91cf8b5-f513-43a2-8ee5-5fcf9cb901a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388341977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3388341977
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3050617315
Short name T234
Test name
Test status
Simulation time 42021489585 ps
CPU time 26.31 seconds
Started Jun 25 06:47:48 PM PDT 24
Finished Jun 25 06:48:15 PM PDT 24
Peak memory 233252 kb
Host smart-21adbda1-7bec-4a0e-a210-667762d7d971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050617315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3050617315
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1177150619
Short name T623
Test name
Test status
Simulation time 942144981 ps
CPU time 11.02 seconds
Started Jun 25 06:47:46 PM PDT 24
Finished Jun 25 06:47:59 PM PDT 24
Peak memory 221164 kb
Host smart-c90f4282-7cab-4b12-a51f-f12b0439e48b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177150619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1177150619
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3762983632
Short name T331
Test name
Test status
Simulation time 1035208241 ps
CPU time 4.64 seconds
Started Jun 25 06:47:44 PM PDT 24
Finished Jun 25 06:47:50 PM PDT 24
Peak memory 216932 kb
Host smart-1068ec35-9077-4eb9-afab-48d30d9e309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762983632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3762983632
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1934468914
Short name T730
Test name
Test status
Simulation time 1319125496 ps
CPU time 3.82 seconds
Started Jun 25 06:47:38 PM PDT 24
Finished Jun 25 06:47:42 PM PDT 24
Peak memory 216776 kb
Host smart-c1017a2b-74f0-49fa-b1e4-ba78ef5c0d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934468914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1934468914
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4232383455
Short name T953
Test name
Test status
Simulation time 53223725 ps
CPU time 0.84 seconds
Started Jun 25 06:47:45 PM PDT 24
Finished Jun 25 06:47:48 PM PDT 24
Peak memory 206896 kb
Host smart-b3961e1a-65c8-4805-8d6c-e9e2e551dac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232383455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4232383455
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3488785124
Short name T809
Test name
Test status
Simulation time 1051659871 ps
CPU time 1 seconds
Started Jun 25 06:47:45 PM PDT 24
Finished Jun 25 06:47:48 PM PDT 24
Peak memory 207376 kb
Host smart-01a76423-00ce-4472-aed8-f9217f12ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488785124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3488785124
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.311045911
Short name T769
Test name
Test status
Simulation time 20724175463 ps
CPU time 18.5 seconds
Started Jun 25 06:47:47 PM PDT 24
Finished Jun 25 06:48:07 PM PDT 24
Peak memory 240864 kb
Host smart-fce93393-d896-4172-8f89-8944757e1c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311045911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.311045911
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2025053863
Short name T655
Test name
Test status
Simulation time 48134007 ps
CPU time 0.7 seconds
Started Jun 25 06:48:07 PM PDT 24
Finished Jun 25 06:48:09 PM PDT 24
Peak memory 205308 kb
Host smart-d15fc55d-1528-45f3-8ace-59dfff8f2da4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025053863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2025053863
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3600366746
Short name T516
Test name
Test status
Simulation time 98777275 ps
CPU time 3.5 seconds
Started Jun 25 06:48:00 PM PDT 24
Finished Jun 25 06:48:04 PM PDT 24
Peak memory 233176 kb
Host smart-0255a60e-a577-488e-a127-2bced6f2d954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600366746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3600366746
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1541711091
Short name T888
Test name
Test status
Simulation time 38181378 ps
CPU time 0.82 seconds
Started Jun 25 06:47:54 PM PDT 24
Finished Jun 25 06:47:56 PM PDT 24
Peak memory 207000 kb
Host smart-6b016562-af97-4e14-a826-4f84b54281b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541711091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1541711091
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.50207885
Short name T408
Test name
Test status
Simulation time 64548584748 ps
CPU time 223.88 seconds
Started Jun 25 06:48:00 PM PDT 24
Finished Jun 25 06:51:45 PM PDT 24
Peak memory 254468 kb
Host smart-1a8d9e31-c485-4598-8111-2bdce0fa567e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50207885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.50207885
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4027067884
Short name T132
Test name
Test status
Simulation time 52353460113 ps
CPU time 516.41 seconds
Started Jun 25 06:48:08 PM PDT 24
Finished Jun 25 06:56:46 PM PDT 24
Peak memory 266116 kb
Host smart-310669b9-9747-4c5e-be64-4498d843dbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027067884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4027067884
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2077834177
Short name T225
Test name
Test status
Simulation time 27352560438 ps
CPU time 231.03 seconds
Started Jun 25 06:48:08 PM PDT 24
Finished Jun 25 06:52:00 PM PDT 24
Peak memory 265948 kb
Host smart-453d7575-16d5-43de-8f5e-1b0c7dbfd78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077834177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2077834177
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1217331515
Short name T750
Test name
Test status
Simulation time 862482329 ps
CPU time 11.21 seconds
Started Jun 25 06:47:58 PM PDT 24
Finished Jun 25 06:48:10 PM PDT 24
Peak memory 233196 kb
Host smart-3870d11e-995d-4c04-887f-01d4fc542f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217331515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1217331515
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2325313223
Short name T828
Test name
Test status
Simulation time 1296649262 ps
CPU time 7.28 seconds
Started Jun 25 06:47:54 PM PDT 24
Finished Jun 25 06:48:02 PM PDT 24
Peak memory 224984 kb
Host smart-b1b421d4-ac34-45f1-9187-7f404b37ce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325313223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2325313223
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.525665605
Short name T794
Test name
Test status
Simulation time 731729825 ps
CPU time 9.55 seconds
Started Jun 25 06:47:53 PM PDT 24
Finished Jun 25 06:48:04 PM PDT 24
Peak memory 233188 kb
Host smart-504a217f-92ad-4136-8077-57f61d202064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525665605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.525665605
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3055020185
Short name T980
Test name
Test status
Simulation time 45618497 ps
CPU time 1.04 seconds
Started Jun 25 06:47:53 PM PDT 24
Finished Jun 25 06:47:56 PM PDT 24
Peak memory 217148 kb
Host smart-4bd12b2c-56d3-4722-bd14-fa156cee2ec4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055020185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3055020185
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2983038644
Short name T416
Test name
Test status
Simulation time 24673795907 ps
CPU time 23.16 seconds
Started Jun 25 06:47:53 PM PDT 24
Finished Jun 25 06:48:17 PM PDT 24
Peak memory 249240 kb
Host smart-ef702687-6b1c-4920-b096-5617d411ac5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983038644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2983038644
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1512014121
Short name T253
Test name
Test status
Simulation time 1840813850 ps
CPU time 8.16 seconds
Started Jun 25 06:47:53 PM PDT 24
Finished Jun 25 06:48:02 PM PDT 24
Peak memory 241316 kb
Host smart-d8d8f97c-e864-4d24-adec-ed06ee3e4c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512014121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1512014121
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.863597828
Short name T140
Test name
Test status
Simulation time 195189173 ps
CPU time 4.43 seconds
Started Jun 25 06:48:00 PM PDT 24
Finished Jun 25 06:48:06 PM PDT 24
Peak memory 223488 kb
Host smart-12544ea7-6ffd-4ac9-905a-683962234e8d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=863597828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.863597828
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3707600455
Short name T154
Test name
Test status
Simulation time 870945719102 ps
CPU time 379.8 seconds
Started Jun 25 06:48:07 PM PDT 24
Finished Jun 25 06:54:28 PM PDT 24
Peak memory 267892 kb
Host smart-73d53db4-3224-4d3d-a3dd-00b0f65f9e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707600455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3707600455
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3304418517
Short name T870
Test name
Test status
Simulation time 4129219639 ps
CPU time 23.72 seconds
Started Jun 25 06:47:53 PM PDT 24
Finished Jun 25 06:48:18 PM PDT 24
Peak memory 216804 kb
Host smart-f1748f97-a1ef-46bb-9cfc-bc19e8818719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304418517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3304418517
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1821620407
Short name T497
Test name
Test status
Simulation time 9162177095 ps
CPU time 7.32 seconds
Started Jun 25 06:47:52 PM PDT 24
Finished Jun 25 06:48:01 PM PDT 24
Peak memory 216728 kb
Host smart-8b17dfea-f5d6-458b-875a-41440b8a1320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821620407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1821620407
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2321773526
Short name T814
Test name
Test status
Simulation time 159860195 ps
CPU time 1.08 seconds
Started Jun 25 06:47:52 PM PDT 24
Finished Jun 25 06:47:55 PM PDT 24
Peak memory 208068 kb
Host smart-f0c9aaed-f790-42d8-8af0-348fca0e5d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321773526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2321773526
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2618364794
Short name T375
Test name
Test status
Simulation time 109898025 ps
CPU time 0.69 seconds
Started Jun 25 06:47:51 PM PDT 24
Finished Jun 25 06:47:53 PM PDT 24
Peak memory 206032 kb
Host smart-edb93cd4-99f5-4409-8d95-19ccc8cbb4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618364794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2618364794
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.750305951
Short name T699
Test name
Test status
Simulation time 3981586717 ps
CPU time 14.6 seconds
Started Jun 25 06:47:52 PM PDT 24
Finished Jun 25 06:48:08 PM PDT 24
Peak memory 233264 kb
Host smart-3753a2ca-83e4-4e39-8ffb-d182c72187da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750305951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.750305951
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2263179899
Short name T526
Test name
Test status
Simulation time 35298002 ps
CPU time 0.72 seconds
Started Jun 25 06:48:15 PM PDT 24
Finished Jun 25 06:48:18 PM PDT 24
Peak memory 205792 kb
Host smart-c5b353ce-98e6-4ef7-b2c2-d88b18572a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263179899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2263179899
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2621353000
Short name T82
Test name
Test status
Simulation time 647553900 ps
CPU time 10.16 seconds
Started Jun 25 06:48:16 PM PDT 24
Finished Jun 25 06:48:28 PM PDT 24
Peak memory 233196 kb
Host smart-4488caed-226a-4b0d-b565-5c88144147f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621353000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2621353000
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3769732717
Short name T766
Test name
Test status
Simulation time 16846964 ps
CPU time 0.78 seconds
Started Jun 25 06:48:06 PM PDT 24
Finished Jun 25 06:48:07 PM PDT 24
Peak memory 206976 kb
Host smart-e9057aa7-5b5f-432f-80a0-53f4debb2898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769732717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3769732717
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.366179844
Short name T235
Test name
Test status
Simulation time 5232967302 ps
CPU time 55.6 seconds
Started Jun 25 06:48:15 PM PDT 24
Finished Jun 25 06:49:13 PM PDT 24
Peak memory 249784 kb
Host smart-30346e80-d0e8-4558-a6cb-cd82052e006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366179844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.366179844
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.730484885
Short name T914
Test name
Test status
Simulation time 391746374 ps
CPU time 5.89 seconds
Started Jun 25 06:48:15 PM PDT 24
Finished Jun 25 06:48:23 PM PDT 24
Peak memory 233224 kb
Host smart-5c637cac-624d-41f2-9d96-295e8604f723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730484885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.730484885
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1184960400
Short name T631
Test name
Test status
Simulation time 86211622 ps
CPU time 3.25 seconds
Started Jun 25 06:48:14 PM PDT 24
Finished Jun 25 06:48:19 PM PDT 24
Peak memory 233180 kb
Host smart-9ac2fbcb-0e7b-4a8a-af4f-ef6ddada34a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184960400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1184960400
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.505940213
Short name T670
Test name
Test status
Simulation time 642306150 ps
CPU time 9.13 seconds
Started Jun 25 06:48:14 PM PDT 24
Finished Jun 25 06:48:25 PM PDT 24
Peak memory 233172 kb
Host smart-7639f75f-558f-4464-ab8c-e7e553210704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505940213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.505940213
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3243614161
Short name T39
Test name
Test status
Simulation time 20355442 ps
CPU time 1.14 seconds
Started Jun 25 06:48:05 PM PDT 24
Finished Jun 25 06:48:07 PM PDT 24
Peak memory 217152 kb
Host smart-904cf53e-1652-4fda-9f39-759651f2e845
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243614161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3243614161
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2361823617
Short name T977
Test name
Test status
Simulation time 4661635630 ps
CPU time 17.05 seconds
Started Jun 25 06:48:29 PM PDT 24
Finished Jun 25 06:48:48 PM PDT 24
Peak memory 225236 kb
Host smart-a81d796f-230c-4454-b850-1d8b77329e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361823617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2361823617
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3055872331
Short name T658
Test name
Test status
Simulation time 9782679823 ps
CPU time 10.58 seconds
Started Jun 25 06:48:07 PM PDT 24
Finished Jun 25 06:48:18 PM PDT 24
Peak memory 233196 kb
Host smart-5f77adca-350c-43c5-a079-ef6bcfe56d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055872331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3055872331
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4226437450
Short name T663
Test name
Test status
Simulation time 2582336360 ps
CPU time 4.85 seconds
Started Jun 25 06:48:15 PM PDT 24
Finished Jun 25 06:48:22 PM PDT 24
Peak memory 222360 kb
Host smart-567f0337-7148-4546-89ad-4cbc4659c6bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4226437450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4226437450
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.224946386
Short name T598
Test name
Test status
Simulation time 51848549182 ps
CPU time 27.88 seconds
Started Jun 25 06:48:07 PM PDT 24
Finished Jun 25 06:48:36 PM PDT 24
Peak memory 216988 kb
Host smart-8ccc3676-70ad-4541-a42d-2295b7c2bcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224946386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.224946386
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3657469796
Short name T896
Test name
Test status
Simulation time 626825178 ps
CPU time 3.28 seconds
Started Jun 25 06:48:07 PM PDT 24
Finished Jun 25 06:48:12 PM PDT 24
Peak memory 216732 kb
Host smart-39cc524e-d636-4fd2-9cbe-b934bac65cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657469796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3657469796
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.451624582
Short name T634
Test name
Test status
Simulation time 131945614 ps
CPU time 1.09 seconds
Started Jun 25 06:48:07 PM PDT 24
Finished Jun 25 06:48:09 PM PDT 24
Peak memory 208424 kb
Host smart-727aaff7-f987-48a7-908b-7849f9a4dfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451624582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.451624582
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1604188409
Short name T967
Test name
Test status
Simulation time 195715752 ps
CPU time 0.84 seconds
Started Jun 25 06:48:08 PM PDT 24
Finished Jun 25 06:48:10 PM PDT 24
Peak memory 206360 kb
Host smart-54b37501-9062-4167-ba31-cd7f21e6c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604188409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1604188409
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2941588445
Short name T275
Test name
Test status
Simulation time 3819889929 ps
CPU time 6.15 seconds
Started Jun 25 06:48:14 PM PDT 24
Finished Jun 25 06:48:21 PM PDT 24
Peak memory 233196 kb
Host smart-88fd7a24-4b1c-4756-b859-372c6d98d25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941588445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2941588445
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.988052107
Short name T883
Test name
Test status
Simulation time 15145802 ps
CPU time 0.77 seconds
Started Jun 25 06:48:33 PM PDT 24
Finished Jun 25 06:48:36 PM PDT 24
Peak memory 205172 kb
Host smart-195175e7-5ef6-4288-8813-a2fcaaa7edea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988052107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.988052107
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3072263323
Short name T189
Test name
Test status
Simulation time 978508689 ps
CPU time 4.47 seconds
Started Jun 25 06:48:22 PM PDT 24
Finished Jun 25 06:48:29 PM PDT 24
Peak memory 233188 kb
Host smart-b58e4ea1-3d20-425c-8cd8-f7b12f77b56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072263323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3072263323
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2456350358
Short name T681
Test name
Test status
Simulation time 19530352 ps
CPU time 0.77 seconds
Started Jun 25 06:48:17 PM PDT 24
Finished Jun 25 06:48:19 PM PDT 24
Peak memory 207000 kb
Host smart-f49ebd5c-2ef3-49fb-a4f7-bf5041f0fc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456350358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2456350358
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1205304332
Short name T172
Test name
Test status
Simulation time 4744758955 ps
CPU time 58.54 seconds
Started Jun 25 06:48:25 PM PDT 24
Finished Jun 25 06:49:25 PM PDT 24
Peak memory 253640 kb
Host smart-8939b19b-030e-44af-a807-f452a9b5be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205304332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1205304332
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2450229691
Short name T643
Test name
Test status
Simulation time 37991305897 ps
CPU time 320.2 seconds
Started Jun 25 06:48:23 PM PDT 24
Finished Jun 25 06:53:45 PM PDT 24
Peak memory 257888 kb
Host smart-b1c42026-78f0-4b2e-a1cb-952ee60eff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450229691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2450229691
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.167699018
Short name T332
Test name
Test status
Simulation time 5156597363 ps
CPU time 28.28 seconds
Started Jun 25 06:48:32 PM PDT 24
Finished Jun 25 06:49:03 PM PDT 24
Peak memory 249684 kb
Host smart-9fbc1f46-0225-4f4a-8962-d1aaedf7fec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167699018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.167699018
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2295982686
Short name T414
Test name
Test status
Simulation time 45670528 ps
CPU time 3.02 seconds
Started Jun 25 06:48:24 PM PDT 24
Finished Jun 25 06:48:28 PM PDT 24
Peak memory 233196 kb
Host smart-af7da764-6ba1-4873-9114-651bb14c24e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295982686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2295982686
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.267556667
Short name T478
Test name
Test status
Simulation time 2772121607 ps
CPU time 8.83 seconds
Started Jun 25 06:48:23 PM PDT 24
Finished Jun 25 06:48:34 PM PDT 24
Peak memory 233292 kb
Host smart-4be73437-5d3c-42dc-9c2f-65fe4d7129c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267556667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.267556667
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3675972510
Short name T355
Test name
Test status
Simulation time 112874839 ps
CPU time 2.2 seconds
Started Jun 25 06:48:23 PM PDT 24
Finished Jun 25 06:48:27 PM PDT 24
Peak memory 232876 kb
Host smart-a435de51-eed9-4bd7-9cd8-b6808543622d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675972510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3675972510
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.282808120
Short name T584
Test name
Test status
Simulation time 30046027 ps
CPU time 1.07 seconds
Started Jun 25 06:48:15 PM PDT 24
Finished Jun 25 06:48:17 PM PDT 24
Peak memory 218272 kb
Host smart-c0ce0f9d-b821-48b8-a7e9-89830d790b90
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282808120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.282808120
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3118516688
Short name T642
Test name
Test status
Simulation time 3137489051 ps
CPU time 11.36 seconds
Started Jun 25 06:48:25 PM PDT 24
Finished Jun 25 06:48:38 PM PDT 24
Peak memory 233132 kb
Host smart-24742799-4037-45c1-a9c3-15c1cee1c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118516688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3118516688
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.925507343
Short name T958
Test name
Test status
Simulation time 11577475905 ps
CPU time 15.88 seconds
Started Jun 25 06:48:23 PM PDT 24
Finished Jun 25 06:48:41 PM PDT 24
Peak memory 233268 kb
Host smart-4144338f-b3b6-4984-a322-ad2ace81c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925507343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.925507343
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2025045312
Short name T517
Test name
Test status
Simulation time 180931566 ps
CPU time 4.4 seconds
Started Jun 25 06:48:25 PM PDT 24
Finished Jun 25 06:48:31 PM PDT 24
Peak memory 221280 kb
Host smart-6361ad54-07e4-4b51-bb23-3f4b6d3d75b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2025045312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2025045312
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1959374372
Short name T153
Test name
Test status
Simulation time 2093220818 ps
CPU time 21.06 seconds
Started Jun 25 06:48:33 PM PDT 24
Finished Jun 25 06:48:56 PM PDT 24
Peak memory 252240 kb
Host smart-b83bee34-d627-42ef-a1c7-ba26f63c701e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959374372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1959374372
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3634832713
Short name T983
Test name
Test status
Simulation time 2440013026 ps
CPU time 14.44 seconds
Started Jun 25 06:48:16 PM PDT 24
Finished Jun 25 06:48:33 PM PDT 24
Peak memory 216720 kb
Host smart-4c1780a0-5924-480c-93dd-e862ad968e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634832713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3634832713
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2033022163
Short name T370
Test name
Test status
Simulation time 1903681982 ps
CPU time 7.07 seconds
Started Jun 25 06:48:15 PM PDT 24
Finished Jun 25 06:48:23 PM PDT 24
Peak memory 216740 kb
Host smart-23deb80a-5fc3-4afa-9cf8-842c311046df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033022163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2033022163
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1051566202
Short name T33
Test name
Test status
Simulation time 71737887 ps
CPU time 1.21 seconds
Started Jun 25 06:48:22 PM PDT 24
Finished Jun 25 06:48:25 PM PDT 24
Peak memory 208416 kb
Host smart-2247d8bf-5f78-4b64-82bf-91d67a4973a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051566202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1051566202
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1729576850
Short name T696
Test name
Test status
Simulation time 506774382 ps
CPU time 0.9 seconds
Started Jun 25 06:48:23 PM PDT 24
Finished Jun 25 06:48:26 PM PDT 24
Peak memory 206380 kb
Host smart-72db722c-ef16-406a-998b-862edecf073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729576850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1729576850
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3570894377
Short name T692
Test name
Test status
Simulation time 9151114571 ps
CPU time 16.72 seconds
Started Jun 25 06:48:23 PM PDT 24
Finished Jun 25 06:48:42 PM PDT 24
Peak memory 225020 kb
Host smart-94a4d2ec-70be-4a25-8c9b-dfe1e1c26800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570894377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3570894377
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4180706515
Short name T29
Test name
Test status
Simulation time 13363989 ps
CPU time 0.83 seconds
Started Jun 25 06:48:40 PM PDT 24
Finished Jun 25 06:48:41 PM PDT 24
Peak memory 205912 kb
Host smart-561cafcd-47cb-42b9-ba31-71ca58839e98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180706515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4180706515
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2388709410
Short name T445
Test name
Test status
Simulation time 28469671 ps
CPU time 2.23 seconds
Started Jun 25 06:48:39 PM PDT 24
Finished Jun 25 06:48:43 PM PDT 24
Peak memory 224420 kb
Host smart-294d6b6e-4f8b-48c4-a79b-daea09389200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388709410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2388709410
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1861190371
Short name T790
Test name
Test status
Simulation time 66188813 ps
CPU time 0.76 seconds
Started Jun 25 06:48:33 PM PDT 24
Finished Jun 25 06:48:36 PM PDT 24
Peak memory 207332 kb
Host smart-75192a45-b7b7-4c34-ae00-2cca5adf8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861190371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1861190371
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3803312383
Short name T973
Test name
Test status
Simulation time 292952102972 ps
CPU time 490.85 seconds
Started Jun 25 06:48:42 PM PDT 24
Finished Jun 25 06:56:54 PM PDT 24
Peak memory 256792 kb
Host smart-3147ced3-46be-419b-94d3-8de07bde5f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803312383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3803312383
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1235186576
Short name T850
Test name
Test status
Simulation time 33985749640 ps
CPU time 57.11 seconds
Started Jun 25 06:48:42 PM PDT 24
Finished Jun 25 06:49:40 PM PDT 24
Peak memory 251140 kb
Host smart-f38439b4-d282-48ec-a0b2-039cefe75ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235186576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1235186576
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1072641103
Short name T707
Test name
Test status
Simulation time 1136682182 ps
CPU time 17.03 seconds
Started Jun 25 06:48:41 PM PDT 24
Finished Jun 25 06:48:59 PM PDT 24
Peak memory 223624 kb
Host smart-d1ac5110-d7ee-4bf9-bad3-44e7bd222d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072641103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1072641103
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2662705325
Short name T573
Test name
Test status
Simulation time 221697261 ps
CPU time 5.55 seconds
Started Jun 25 06:48:40 PM PDT 24
Finished Jun 25 06:48:47 PM PDT 24
Peak memory 224996 kb
Host smart-349cc05e-8bf0-48bb-918d-1ba49129859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662705325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2662705325
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.869433814
Short name T712
Test name
Test status
Simulation time 2224826131 ps
CPU time 19.13 seconds
Started Jun 25 06:48:50 PM PDT 24
Finished Jun 25 06:49:10 PM PDT 24
Peak memory 233488 kb
Host smart-75ca02f0-244c-49d3-9b43-ee753ff7dea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869433814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.869433814
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2191326825
Short name T852
Test name
Test status
Simulation time 9779527534 ps
CPU time 29.11 seconds
Started Jun 25 06:48:41 PM PDT 24
Finished Jun 25 06:49:11 PM PDT 24
Peak memory 241252 kb
Host smart-e57a3ed9-4e65-4565-8684-23f012c8acd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191326825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2191326825
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2699297608
Short name T777
Test name
Test status
Simulation time 249723505 ps
CPU time 1.02 seconds
Started Jun 25 06:48:33 PM PDT 24
Finished Jun 25 06:48:36 PM PDT 24
Peak memory 218408 kb
Host smart-e724549e-826d-4091-b215-3b48453eb3f0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699297608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2699297608
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1627871624
Short name T638
Test name
Test status
Simulation time 1728978866 ps
CPU time 8.68 seconds
Started Jun 25 06:48:33 PM PDT 24
Finished Jun 25 06:48:44 PM PDT 24
Peak memory 235600 kb
Host smart-bc036436-5ff3-4480-8bd9-27b281bb30ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627871624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1627871624
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1787323390
Short name T993
Test name
Test status
Simulation time 3446348572 ps
CPU time 6.54 seconds
Started Jun 25 06:48:33 PM PDT 24
Finished Jun 25 06:48:42 PM PDT 24
Peak memory 233156 kb
Host smart-7275bf43-6e2e-4fac-80b9-3457e93a8f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787323390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1787323390
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2997963553
Short name T774
Test name
Test status
Simulation time 510272069 ps
CPU time 3.76 seconds
Started Jun 25 06:48:41 PM PDT 24
Finished Jun 25 06:48:46 PM PDT 24
Peak memory 220004 kb
Host smart-c7160ad8-fb08-4aa9-a5ca-acff5808dd1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2997963553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2997963553
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1713142258
Short name T18
Test name
Test status
Simulation time 82789765 ps
CPU time 1.14 seconds
Started Jun 25 06:48:42 PM PDT 24
Finished Jun 25 06:48:45 PM PDT 24
Peak memory 207580 kb
Host smart-23d8ad04-03e7-48e8-94a5-ebed038c61d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713142258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1713142258
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.211156257
Short name T512
Test name
Test status
Simulation time 5651209665 ps
CPU time 8.52 seconds
Started Jun 25 06:48:32 PM PDT 24
Finished Jun 25 06:48:42 PM PDT 24
Peak memory 216876 kb
Host smart-9a738f3e-eb99-4adf-b4ba-6f7cb9805da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211156257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.211156257
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2609071747
Short name T391
Test name
Test status
Simulation time 46851108 ps
CPU time 0.8 seconds
Started Jun 25 06:48:33 PM PDT 24
Finished Jun 25 06:48:35 PM PDT 24
Peak memory 207264 kb
Host smart-7913f615-6ec9-49d3-8f10-d86f742c4a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609071747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2609071747
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3614667883
Short name T432
Test name
Test status
Simulation time 47526006 ps
CPU time 0.86 seconds
Started Jun 25 06:48:34 PM PDT 24
Finished Jun 25 06:48:36 PM PDT 24
Peak memory 206376 kb
Host smart-52fa3124-0aaa-4dae-8020-4da9b37dc824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614667883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3614667883
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.458283855
Short name T901
Test name
Test status
Simulation time 2442958266 ps
CPU time 8.55 seconds
Started Jun 25 06:48:42 PM PDT 24
Finished Jun 25 06:48:52 PM PDT 24
Peak memory 233232 kb
Host smart-75086d9b-2bb7-4a15-a77d-50a55c617e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458283855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.458283855
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1272044801
Short name T863
Test name
Test status
Simulation time 19884812 ps
CPU time 0.72 seconds
Started Jun 25 06:48:47 PM PDT 24
Finished Jun 25 06:48:49 PM PDT 24
Peak memory 205896 kb
Host smart-9b18f9e2-e9d4-4d98-a586-a3af06468408
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272044801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1272044801
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2153523919
Short name T346
Test name
Test status
Simulation time 70176659 ps
CPU time 0.83 seconds
Started Jun 25 06:48:40 PM PDT 24
Finished Jun 25 06:48:42 PM PDT 24
Peak memory 206832 kb
Host smart-ef056e24-bf5d-457c-967d-a8d99749457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153523919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2153523919
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2360576217
Short name T954
Test name
Test status
Simulation time 203889759828 ps
CPU time 389.39 seconds
Started Jun 25 06:48:50 PM PDT 24
Finished Jun 25 06:55:21 PM PDT 24
Peak memory 254196 kb
Host smart-52edd644-d0d9-4b67-a17c-cadfa39ac37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360576217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2360576217
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1161483331
Short name T312
Test name
Test status
Simulation time 48116829042 ps
CPU time 140.59 seconds
Started Jun 25 06:48:49 PM PDT 24
Finished Jun 25 06:51:11 PM PDT 24
Peak memory 254184 kb
Host smart-a9fd6877-62c9-4997-9f5b-2c9c8fd1d4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161483331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1161483331
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3981618843
Short name T552
Test name
Test status
Simulation time 35338026 ps
CPU time 0.81 seconds
Started Jun 25 06:48:49 PM PDT 24
Finished Jun 25 06:48:52 PM PDT 24
Peak memory 217276 kb
Host smart-26341941-72cc-462e-abc2-5b06eedac076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981618843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3981618843
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3347291158
Short name T533
Test name
Test status
Simulation time 482107103 ps
CPU time 10.74 seconds
Started Jun 25 06:48:49 PM PDT 24
Finished Jun 25 06:49:01 PM PDT 24
Peak memory 241384 kb
Host smart-a97020d6-992f-490e-9684-57df772839b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347291158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3347291158
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1951830062
Short name T830
Test name
Test status
Simulation time 217066696 ps
CPU time 3.23 seconds
Started Jun 25 06:48:50 PM PDT 24
Finished Jun 25 06:48:55 PM PDT 24
Peak memory 233204 kb
Host smart-0431d33c-af37-4a66-8d95-85d303576970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951830062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1951830062
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3952243517
Short name T687
Test name
Test status
Simulation time 4770556094 ps
CPU time 14.04 seconds
Started Jun 25 06:48:51 PM PDT 24
Finished Jun 25 06:49:06 PM PDT 24
Peak memory 233264 kb
Host smart-efe0e45a-144d-4768-8e14-e9b009fd9be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952243517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3952243517
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1987433139
Short name T539
Test name
Test status
Simulation time 32336173 ps
CPU time 1.07 seconds
Started Jun 25 06:48:42 PM PDT 24
Finished Jun 25 06:48:44 PM PDT 24
Peak memory 218392 kb
Host smart-6c8de08a-002a-4cc6-9b6a-01ca19a46d95
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987433139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1987433139
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2678553464
Short name T231
Test name
Test status
Simulation time 5431092301 ps
CPU time 17.26 seconds
Started Jun 25 06:48:48 PM PDT 24
Finished Jun 25 06:49:07 PM PDT 24
Peak memory 233168 kb
Host smart-f825396c-651a-4d74-a5eb-5d3d6eb39c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678553464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2678553464
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2565686650
Short name T667
Test name
Test status
Simulation time 5918014235 ps
CPU time 10.96 seconds
Started Jun 25 06:48:51 PM PDT 24
Finished Jun 25 06:49:03 PM PDT 24
Peak memory 223528 kb
Host smart-8cb626e8-e96c-4b44-8c3c-3f186f0703bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2565686650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2565686650
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.687994871
Short name T567
Test name
Test status
Simulation time 48607923159 ps
CPU time 33.55 seconds
Started Jun 25 06:48:50 PM PDT 24
Finished Jun 25 06:49:25 PM PDT 24
Peak memory 216828 kb
Host smart-0652f075-7dd6-4efb-a6f8-6844628e2009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687994871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.687994871
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.395497150
Short name T921
Test name
Test status
Simulation time 19938308659 ps
CPU time 17.55 seconds
Started Jun 25 06:48:48 PM PDT 24
Finished Jun 25 06:49:07 PM PDT 24
Peak memory 216872 kb
Host smart-2693badf-48ca-45dd-880e-67b54dd4a1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395497150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.395497150
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2672487243
Short name T792
Test name
Test status
Simulation time 168622728 ps
CPU time 2.26 seconds
Started Jun 25 06:48:49 PM PDT 24
Finished Jun 25 06:48:53 PM PDT 24
Peak memory 216800 kb
Host smart-8ae6306c-cf9f-45a9-99b5-2edc3e743ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672487243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2672487243
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2860139953
Short name T825
Test name
Test status
Simulation time 51932288 ps
CPU time 0.83 seconds
Started Jun 25 06:48:48 PM PDT 24
Finished Jun 25 06:48:50 PM PDT 24
Peak memory 206376 kb
Host smart-5e36612a-94f5-468e-8070-8b57f5e335f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860139953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2860139953
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.168131416
Short name T917
Test name
Test status
Simulation time 1303351678 ps
CPU time 4.56 seconds
Started Jun 25 06:48:48 PM PDT 24
Finished Jun 25 06:48:55 PM PDT 24
Peak memory 224864 kb
Host smart-31e944bc-004d-42b2-993a-d4734cad1a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168131416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.168131416
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.619182964
Short name T545
Test name
Test status
Simulation time 14222040 ps
CPU time 0.75 seconds
Started Jun 25 06:49:04 PM PDT 24
Finished Jun 25 06:49:06 PM PDT 24
Peak memory 205884 kb
Host smart-c75cd162-db0c-43e5-9018-9cec6eb86f7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619182964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.619182964
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2420752850
Short name T978
Test name
Test status
Simulation time 906120421 ps
CPU time 4.69 seconds
Started Jun 25 06:48:56 PM PDT 24
Finished Jun 25 06:49:02 PM PDT 24
Peak memory 224956 kb
Host smart-b5635293-6c00-4d9d-8809-59912eb9a610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420752850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2420752850
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1086686281
Short name T636
Test name
Test status
Simulation time 17505385 ps
CPU time 0.82 seconds
Started Jun 25 06:48:57 PM PDT 24
Finished Jun 25 06:49:00 PM PDT 24
Peak memory 206984 kb
Host smart-c498a54c-42fc-4693-a373-684ae5934219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086686281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1086686281
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2576898977
Short name T875
Test name
Test status
Simulation time 104337709709 ps
CPU time 190.55 seconds
Started Jun 25 06:48:56 PM PDT 24
Finished Jun 25 06:52:08 PM PDT 24
Peak memory 262828 kb
Host smart-398040d5-05b2-4345-8962-3096d492b447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576898977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2576898977
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2751146601
Short name T69
Test name
Test status
Simulation time 3179749936 ps
CPU time 68.88 seconds
Started Jun 25 06:48:55 PM PDT 24
Finished Jun 25 06:50:05 PM PDT 24
Peak memory 252436 kb
Host smart-83838f1a-624c-4a4d-a6e6-cc75f0d07c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751146601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2751146601
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3308565558
Short name T51
Test name
Test status
Simulation time 1866725695 ps
CPU time 11.38 seconds
Started Jun 25 06:49:03 PM PDT 24
Finished Jun 25 06:49:15 PM PDT 24
Peak memory 234724 kb
Host smart-bf07b6f8-c986-4514-8456-7ec9ce41faa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308565558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3308565558
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3109064779
Short name T141
Test name
Test status
Simulation time 11944997260 ps
CPU time 52.15 seconds
Started Jun 25 06:48:57 PM PDT 24
Finished Jun 25 06:49:51 PM PDT 24
Peak memory 221156 kb
Host smart-47718c30-fd41-4326-8084-ec98e233971f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109064779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3109064779
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3986308681
Short name T230
Test name
Test status
Simulation time 1085843843 ps
CPU time 14.68 seconds
Started Jun 25 06:48:55 PM PDT 24
Finished Jun 25 06:49:11 PM PDT 24
Peak memory 225012 kb
Host smart-a39fbd43-7b63-46be-b8ac-6a46bf3e2908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986308681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3986308681
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.224822419
Short name T294
Test name
Test status
Simulation time 273202433 ps
CPU time 5.31 seconds
Started Jun 25 06:48:57 PM PDT 24
Finished Jun 25 06:49:04 PM PDT 24
Peak memory 224924 kb
Host smart-70949bdb-d862-4e1a-b3d9-5a8a19edb44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224822419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.224822419
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1125258789
Short name T386
Test name
Test status
Simulation time 17772499 ps
CPU time 1.03 seconds
Started Jun 25 06:48:55 PM PDT 24
Finished Jun 25 06:48:57 PM PDT 24
Peak memory 217136 kb
Host smart-40c8ba1a-af77-43be-9026-af4a9328aee7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125258789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1125258789
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1268160893
Short name T548
Test name
Test status
Simulation time 15276154274 ps
CPU time 11.78 seconds
Started Jun 25 06:48:56 PM PDT 24
Finished Jun 25 06:49:09 PM PDT 24
Peak memory 225040 kb
Host smart-a4100730-8122-4358-bfb4-4719a44eb388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268160893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1268160893
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3438841120
Short name T936
Test name
Test status
Simulation time 1523748877 ps
CPU time 6.22 seconds
Started Jun 25 06:48:56 PM PDT 24
Finished Jun 25 06:49:04 PM PDT 24
Peak memory 225020 kb
Host smart-96a60485-eed8-477d-9bed-faf318647d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438841120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3438841120
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3942796058
Short name T156
Test name
Test status
Simulation time 197281834 ps
CPU time 4.58 seconds
Started Jun 25 06:48:57 PM PDT 24
Finished Jun 25 06:49:03 PM PDT 24
Peak memory 219876 kb
Host smart-5cf59aae-cbda-483a-8fd3-a7c7dde8912a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3942796058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3942796058
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2695263452
Short name T853
Test name
Test status
Simulation time 6730619554 ps
CPU time 122 seconds
Started Jun 25 06:49:04 PM PDT 24
Finished Jun 25 06:51:07 PM PDT 24
Peak memory 251560 kb
Host smart-d0db86c6-f157-46e2-b658-e84746c90631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695263452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2695263452
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.828012874
Short name T843
Test name
Test status
Simulation time 29425913 ps
CPU time 0.71 seconds
Started Jun 25 06:48:55 PM PDT 24
Finished Jun 25 06:48:57 PM PDT 24
Peak memory 206076 kb
Host smart-c123adc7-7dd1-4313-a382-7e240df16a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828012874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.828012874
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3201433859
Short name T474
Test name
Test status
Simulation time 7543280238 ps
CPU time 7.67 seconds
Started Jun 25 06:48:55 PM PDT 24
Finished Jun 25 06:49:04 PM PDT 24
Peak memory 216840 kb
Host smart-7cd58489-850c-4594-a081-6c33952ffd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201433859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3201433859
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1490305544
Short name T679
Test name
Test status
Simulation time 1089465823 ps
CPU time 6.59 seconds
Started Jun 25 06:48:56 PM PDT 24
Finished Jun 25 06:49:04 PM PDT 24
Peak memory 216912 kb
Host smart-5638b54c-7012-4731-9d08-e93c7796cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490305544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1490305544
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2070280091
Short name T347
Test name
Test status
Simulation time 32240259 ps
CPU time 0.86 seconds
Started Jun 25 06:48:55 PM PDT 24
Finished Jun 25 06:48:57 PM PDT 24
Peak memory 206352 kb
Host smart-9d09b0ac-f583-4872-9dac-ee65393cab55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070280091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2070280091
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2811427249
Short name T273
Test name
Test status
Simulation time 490837932 ps
CPU time 4.12 seconds
Started Jun 25 06:48:56 PM PDT 24
Finished Jun 25 06:49:02 PM PDT 24
Peak memory 224956 kb
Host smart-dd660c82-9dfa-43dc-a9de-1c237c91d338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811427249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2811427249
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.804439547
Short name T157
Test name
Test status
Simulation time 12715821 ps
CPU time 0.76 seconds
Started Jun 25 06:49:18 PM PDT 24
Finished Jun 25 06:49:20 PM PDT 24
Peak memory 205860 kb
Host smart-a34dd867-f473-4294-8a9b-9eae33c2bd4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804439547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.804439547
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2989873685
Short name T426
Test name
Test status
Simulation time 182115670 ps
CPU time 2.85 seconds
Started Jun 25 06:49:11 PM PDT 24
Finished Jun 25 06:49:15 PM PDT 24
Peak memory 233076 kb
Host smart-0cb3cccb-454d-4867-a221-3423ed8af065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989873685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2989873685
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.588230767
Short name T367
Test name
Test status
Simulation time 16478789 ps
CPU time 0.8 seconds
Started Jun 25 06:49:03 PM PDT 24
Finished Jun 25 06:49:04 PM PDT 24
Peak memory 205960 kb
Host smart-30414627-cb66-4972-888c-fc216f8ef0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588230767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.588230767
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2612109228
Short name T943
Test name
Test status
Simulation time 2088646635 ps
CPU time 15.29 seconds
Started Jun 25 06:49:15 PM PDT 24
Finished Jun 25 06:49:31 PM PDT 24
Peak memory 235280 kb
Host smart-1ebbc702-4484-4031-940c-6a66e50ce9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612109228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2612109228
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2336942581
Short name T606
Test name
Test status
Simulation time 29782647231 ps
CPU time 280.71 seconds
Started Jun 25 06:49:12 PM PDT 24
Finished Jun 25 06:53:55 PM PDT 24
Peak memory 249700 kb
Host smart-22acd8ae-cc14-476a-9976-4146e8b9ea50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336942581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2336942581
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3067339197
Short name T471
Test name
Test status
Simulation time 3628782681 ps
CPU time 55.17 seconds
Started Jun 25 06:49:11 PM PDT 24
Finished Jun 25 06:50:07 PM PDT 24
Peak memory 249716 kb
Host smart-be5f5b03-3ad4-4cce-8eb2-d8abc8be0fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067339197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3067339197
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2683692988
Short name T772
Test name
Test status
Simulation time 940770005 ps
CPU time 7.7 seconds
Started Jun 25 06:49:11 PM PDT 24
Finished Jun 25 06:49:20 PM PDT 24
Peak memory 233112 kb
Host smart-7d219323-10f8-49a1-ad55-10ed9e19155f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683692988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2683692988
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1225358622
Short name T765
Test name
Test status
Simulation time 229108531 ps
CPU time 8.94 seconds
Started Jun 25 06:49:12 PM PDT 24
Finished Jun 25 06:49:22 PM PDT 24
Peak memory 233148 kb
Host smart-adfc2473-5a33-44bd-b666-3954ffa4e19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225358622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1225358622
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.4157913466
Short name T371
Test name
Test status
Simulation time 106242008 ps
CPU time 1.1 seconds
Started Jun 25 06:49:03 PM PDT 24
Finished Jun 25 06:49:05 PM PDT 24
Peak memory 217156 kb
Host smart-412eadab-841c-44cb-a474-f7458c81362c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157913466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.4157913466
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1672775043
Short name T571
Test name
Test status
Simulation time 15615733494 ps
CPU time 23.49 seconds
Started Jun 25 06:49:03 PM PDT 24
Finished Jun 25 06:49:28 PM PDT 24
Peak memory 240888 kb
Host smart-d4d10bd7-239d-4535-a442-8db1a89b4bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672775043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1672775043
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2560364217
Short name T592
Test name
Test status
Simulation time 1720144594 ps
CPU time 7.47 seconds
Started Jun 25 06:49:04 PM PDT 24
Finished Jun 25 06:49:13 PM PDT 24
Peak memory 224888 kb
Host smart-5ce584cd-31aa-4d43-a986-c910d8efad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560364217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2560364217
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3773164650
Short name T668
Test name
Test status
Simulation time 444585087 ps
CPU time 4.76 seconds
Started Jun 25 06:49:11 PM PDT 24
Finished Jun 25 06:49:17 PM PDT 24
Peak memory 223536 kb
Host smart-65419f32-1066-4a59-98c1-d9dd9a530dae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3773164650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3773164650
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3426149320
Short name T562
Test name
Test status
Simulation time 8998033846 ps
CPU time 40.97 seconds
Started Jun 25 06:49:11 PM PDT 24
Finished Jun 25 06:49:53 PM PDT 24
Peak memory 220060 kb
Host smart-afe64904-b80c-4aeb-aab4-8cdbf4066a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426149320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3426149320
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1483283507
Short name T955
Test name
Test status
Simulation time 20873482944 ps
CPU time 34.52 seconds
Started Jun 25 06:49:04 PM PDT 24
Finished Jun 25 06:49:40 PM PDT 24
Peak memory 216812 kb
Host smart-a6798ef8-3128-4a84-bc1f-66b38494efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483283507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1483283507
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.367316207
Short name T827
Test name
Test status
Simulation time 10083565108 ps
CPU time 5.89 seconds
Started Jun 25 06:49:04 PM PDT 24
Finished Jun 25 06:49:11 PM PDT 24
Peak memory 216836 kb
Host smart-1adbf02c-74da-43f6-819b-0c37036f45bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367316207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.367316207
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1289936786
Short name T872
Test name
Test status
Simulation time 185188292 ps
CPU time 0.89 seconds
Started Jun 25 06:49:04 PM PDT 24
Finished Jun 25 06:49:07 PM PDT 24
Peak memory 206368 kb
Host smart-6dd64da4-39d3-41ef-a5dd-79f9cc7f1353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289936786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1289936786
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.55500154
Short name T653
Test name
Test status
Simulation time 33457135 ps
CPU time 0.88 seconds
Started Jun 25 06:49:04 PM PDT 24
Finished Jun 25 06:49:06 PM PDT 24
Peak memory 206336 kb
Host smart-33881288-e277-4f86-b7cb-d205a3d51949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55500154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.55500154
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1020096977
Short name T861
Test name
Test status
Simulation time 5163602024 ps
CPU time 19.82 seconds
Started Jun 25 06:49:10 PM PDT 24
Finished Jun 25 06:49:30 PM PDT 24
Peak memory 240988 kb
Host smart-68f41009-322a-421a-a06d-61a6e1797d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020096977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1020096977
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4069044891
Short name T839
Test name
Test status
Simulation time 29850664 ps
CPU time 0.76 seconds
Started Jun 25 06:49:27 PM PDT 24
Finished Jun 25 06:49:30 PM PDT 24
Peak memory 206144 kb
Host smart-16bb3ba4-9dd4-4784-b442-5059ca9779df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069044891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4069044891
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2481087908
Short name T911
Test name
Test status
Simulation time 54279674 ps
CPU time 2.46 seconds
Started Jun 25 06:49:17 PM PDT 24
Finished Jun 25 06:49:21 PM PDT 24
Peak memory 232884 kb
Host smart-12446f09-e721-4695-97bb-162873763437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481087908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2481087908
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2131387837
Short name T492
Test name
Test status
Simulation time 111627381 ps
CPU time 0.8 seconds
Started Jun 25 06:49:17 PM PDT 24
Finished Jun 25 06:49:19 PM PDT 24
Peak memory 205936 kb
Host smart-0056af65-7ca0-489e-91e4-9bb535b7b369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131387837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2131387837
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2858525222
Short name T475
Test name
Test status
Simulation time 40806278123 ps
CPU time 120.89 seconds
Started Jun 25 06:49:28 PM PDT 24
Finished Jun 25 06:51:31 PM PDT 24
Peak memory 257904 kb
Host smart-79823984-cadd-430c-a506-c56641c685a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858525222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2858525222
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2603378112
Short name T406
Test name
Test status
Simulation time 3982562728 ps
CPU time 28.29 seconds
Started Jun 25 06:49:28 PM PDT 24
Finished Jun 25 06:49:58 PM PDT 24
Peak memory 250008 kb
Host smart-db8ef2bb-bff0-41dd-b9e5-fb02de331330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603378112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2603378112
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1241847043
Short name T976
Test name
Test status
Simulation time 484948653 ps
CPU time 8.14 seconds
Started Jun 25 06:49:25 PM PDT 24
Finished Jun 25 06:49:34 PM PDT 24
Peak memory 241396 kb
Host smart-7445f574-b6dc-41fb-96d6-d1da56b4eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241847043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1241847043
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3350634670
Short name T757
Test name
Test status
Simulation time 3260363619 ps
CPU time 8.12 seconds
Started Jun 25 06:49:17 PM PDT 24
Finished Jun 25 06:49:27 PM PDT 24
Peak memory 225028 kb
Host smart-fa7510fd-ef89-4967-b2f9-69738789b270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350634670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3350634670
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2277823658
Short name T646
Test name
Test status
Simulation time 5574388464 ps
CPU time 54.92 seconds
Started Jun 25 06:49:19 PM PDT 24
Finished Jun 25 06:50:16 PM PDT 24
Peak memory 233284 kb
Host smart-4be73e8a-24f4-47f1-8c83-a22982d0c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277823658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2277823658
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2747791196
Short name T831
Test name
Test status
Simulation time 29740260 ps
CPU time 1.18 seconds
Started Jun 25 06:49:19 PM PDT 24
Finished Jun 25 06:49:22 PM PDT 24
Peak memory 217152 kb
Host smart-4304c0d8-7d98-424f-8d62-4f5006e698d1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747791196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2747791196
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1460592104
Short name T691
Test name
Test status
Simulation time 2951850736 ps
CPU time 8.44 seconds
Started Jun 25 06:49:18 PM PDT 24
Finished Jun 25 06:49:28 PM PDT 24
Peak memory 241304 kb
Host smart-4a67e485-9bf7-4aa5-9d5c-e53359ce3d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460592104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1460592104
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4118366029
Short name T542
Test name
Test status
Simulation time 586493890 ps
CPU time 3.04 seconds
Started Jun 25 06:49:20 PM PDT 24
Finished Jun 25 06:49:24 PM PDT 24
Peak memory 225020 kb
Host smart-c151bee1-831e-40e1-b4f6-5717d9451c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118366029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4118366029
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.230387829
Short name T411
Test name
Test status
Simulation time 2072635832 ps
CPU time 8.55 seconds
Started Jun 25 06:49:25 PM PDT 24
Finished Jun 25 06:49:36 PM PDT 24
Peak memory 222780 kb
Host smart-bf94fafd-245c-476c-9d16-c9bdc536bd52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=230387829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.230387829
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.401939254
Short name T607
Test name
Test status
Simulation time 538948765 ps
CPU time 1.88 seconds
Started Jun 25 06:49:19 PM PDT 24
Finished Jun 25 06:49:22 PM PDT 24
Peak memory 217088 kb
Host smart-5e3438e0-0bde-4327-990d-86518be82718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401939254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.401939254
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1182846356
Short name T867
Test name
Test status
Simulation time 1808647439 ps
CPU time 1.94 seconds
Started Jun 25 06:49:19 PM PDT 24
Finished Jun 25 06:49:22 PM PDT 24
Peak memory 208204 kb
Host smart-0eb5426d-c50f-4d9e-9f36-6d7fc802bce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182846356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1182846356
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4077980078
Short name T338
Test name
Test status
Simulation time 446870258 ps
CPU time 5.18 seconds
Started Jun 25 06:49:19 PM PDT 24
Finished Jun 25 06:49:26 PM PDT 24
Peak memory 216808 kb
Host smart-41ef7908-cce6-417d-9590-4bb870da5d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077980078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4077980078
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2576184175
Short name T412
Test name
Test status
Simulation time 11034812 ps
CPU time 0.67 seconds
Started Jun 25 06:49:17 PM PDT 24
Finished Jun 25 06:49:19 PM PDT 24
Peak memory 206020 kb
Host smart-6040eaa3-820f-4cfc-bb62-b23eb50cb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576184175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2576184175
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1449927922
Short name T206
Test name
Test status
Simulation time 646748536 ps
CPU time 7.08 seconds
Started Jun 25 06:49:18 PM PDT 24
Finished Jun 25 06:49:27 PM PDT 24
Peak memory 224948 kb
Host smart-25c1e684-2cd4-47d1-8ca3-1b3bf2cf98bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449927922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1449927922
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4027659875
Short name T785
Test name
Test status
Simulation time 109207460 ps
CPU time 0.76 seconds
Started Jun 25 06:45:42 PM PDT 24
Finished Jun 25 06:45:44 PM PDT 24
Peak memory 205852 kb
Host smart-004faf99-38c3-4792-bd40-1dc40fe7e322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027659875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
027659875
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2955580282
Short name T654
Test name
Test status
Simulation time 5332477630 ps
CPU time 32.36 seconds
Started Jun 25 06:45:34 PM PDT 24
Finished Jun 25 06:46:08 PM PDT 24
Peak memory 233256 kb
Host smart-7d39bb57-826a-444c-af90-f23d0ca1383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955580282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2955580282
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3041765390
Short name T758
Test name
Test status
Simulation time 20719498 ps
CPU time 0.77 seconds
Started Jun 25 06:45:20 PM PDT 24
Finished Jun 25 06:45:21 PM PDT 24
Peak memory 207312 kb
Host smart-cdff14b9-1760-41dd-8d7a-ba6a84bf15f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041765390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3041765390
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2969527495
Short name T821
Test name
Test status
Simulation time 1174448212 ps
CPU time 26.67 seconds
Started Jun 25 06:45:33 PM PDT 24
Finished Jun 25 06:46:01 PM PDT 24
Peak memory 253488 kb
Host smart-7ccff418-194b-48cf-884d-768a98e2481a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969527495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2969527495
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2482428494
Short name T923
Test name
Test status
Simulation time 9913171705 ps
CPU time 104.02 seconds
Started Jun 25 06:45:46 PM PDT 24
Finished Jun 25 06:47:30 PM PDT 24
Peak memory 263968 kb
Host smart-22d72b50-55a9-4d6e-bd94-8d1e095d740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482428494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2482428494
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3601572896
Short name T819
Test name
Test status
Simulation time 583791587 ps
CPU time 9.25 seconds
Started Jun 25 06:45:33 PM PDT 24
Finished Jun 25 06:45:43 PM PDT 24
Peak memory 224956 kb
Host smart-606162bb-86b4-47a6-93cf-b717338da487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601572896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3601572896
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2750684294
Short name T348
Test name
Test status
Simulation time 502958794 ps
CPU time 4.97 seconds
Started Jun 25 06:45:33 PM PDT 24
Finished Jun 25 06:45:40 PM PDT 24
Peak memory 224924 kb
Host smart-1a0e9b78-e70e-4f3c-b30c-81ad2f9c4f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750684294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2750684294
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2023677711
Short name T732
Test name
Test status
Simulation time 27281694 ps
CPU time 1.05 seconds
Started Jun 25 06:45:27 PM PDT 24
Finished Jun 25 06:45:29 PM PDT 24
Peak memory 218388 kb
Host smart-6b54a5fb-1db0-4107-be68-0a20e3e1b931
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023677711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2023677711
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2765551691
Short name T403
Test name
Test status
Simulation time 35449099 ps
CPU time 2.47 seconds
Started Jun 25 06:45:33 PM PDT 24
Finished Jun 25 06:45:36 PM PDT 24
Peak memory 232904 kb
Host smart-efd5f931-7823-43ba-b215-7c49405072a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765551691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2765551691
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2694809386
Short name T3
Test name
Test status
Simulation time 24242824557 ps
CPU time 21.63 seconds
Started Jun 25 06:45:27 PM PDT 24
Finished Jun 25 06:45:49 PM PDT 24
Peak memory 237568 kb
Host smart-53d0fa8d-1084-46ec-b928-b7f84e6455a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694809386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2694809386
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1057776954
Short name T129
Test name
Test status
Simulation time 285666231 ps
CPU time 5.59 seconds
Started Jun 25 06:45:33 PM PDT 24
Finished Jun 25 06:45:40 PM PDT 24
Peak memory 221316 kb
Host smart-55f793d1-8492-4738-98ab-38268ec93a90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1057776954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1057776954
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4061149452
Short name T319
Test name
Test status
Simulation time 8186422994 ps
CPU time 106.55 seconds
Started Jun 25 06:45:45 PM PDT 24
Finished Jun 25 06:47:32 PM PDT 24
Peak memory 255268 kb
Host smart-f37bf6fa-e280-4156-a375-571fe478ca11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061149452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4061149452
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2165792730
Short name T878
Test name
Test status
Simulation time 3644578155 ps
CPU time 21.45 seconds
Started Jun 25 06:45:26 PM PDT 24
Finished Jun 25 06:45:49 PM PDT 24
Peak memory 216836 kb
Host smart-512fb95a-5845-47c9-b947-8951e1531b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165792730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2165792730
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1739471905
Short name T940
Test name
Test status
Simulation time 9676274519 ps
CPU time 9 seconds
Started Jun 25 06:45:26 PM PDT 24
Finished Jun 25 06:45:35 PM PDT 24
Peak memory 216900 kb
Host smart-4bbc90cc-4ca2-4dbf-ae92-7059e79a20e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739471905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1739471905
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4247763622
Short name T389
Test name
Test status
Simulation time 10562362 ps
CPU time 0.68 seconds
Started Jun 25 06:45:27 PM PDT 24
Finished Jun 25 06:45:28 PM PDT 24
Peak memory 206028 kb
Host smart-62bd9738-a991-452b-81ed-ecc23b54e066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247763622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4247763622
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3178749607
Short name T425
Test name
Test status
Simulation time 289887761 ps
CPU time 0.82 seconds
Started Jun 25 06:45:25 PM PDT 24
Finished Jun 25 06:45:26 PM PDT 24
Peak memory 206364 kb
Host smart-03785797-8cdf-4e39-a9ef-4313bff11cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178749607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3178749607
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1804273973
Short name T748
Test name
Test status
Simulation time 2385081656 ps
CPU time 10.05 seconds
Started Jun 25 06:45:34 PM PDT 24
Finished Jun 25 06:45:45 PM PDT 24
Peak memory 225020 kb
Host smart-15441625-4006-444f-807d-3616459c01db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804273973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1804273973
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3286414323
Short name T363
Test name
Test status
Simulation time 37046582 ps
CPU time 0.71 seconds
Started Jun 25 06:49:34 PM PDT 24
Finished Jun 25 06:49:36 PM PDT 24
Peak memory 205332 kb
Host smart-db72235e-858b-4217-ac98-f41b98003819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286414323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3286414323
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1171271678
Short name T261
Test name
Test status
Simulation time 1742001748 ps
CPU time 6.86 seconds
Started Jun 25 06:49:27 PM PDT 24
Finished Jun 25 06:49:36 PM PDT 24
Peak memory 225020 kb
Host smart-1a3f9f80-7ffb-495b-b80b-24e47d639a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171271678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1171271678
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2253300596
Short name T948
Test name
Test status
Simulation time 15328150 ps
CPU time 0.8 seconds
Started Jun 25 06:49:26 PM PDT 24
Finished Jun 25 06:49:29 PM PDT 24
Peak memory 206284 kb
Host smart-9781e260-2d99-4be7-bb11-325f95f983f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253300596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2253300596
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.542994030
Short name T171
Test name
Test status
Simulation time 9978025615 ps
CPU time 106.18 seconds
Started Jun 25 06:49:35 PM PDT 24
Finished Jun 25 06:51:23 PM PDT 24
Peak memory 249548 kb
Host smart-564b3801-be27-4294-a52f-93efe63186bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542994030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.542994030
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4065833911
Short name T240
Test name
Test status
Simulation time 913625698335 ps
CPU time 597.03 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:59:32 PM PDT 24
Peak memory 265160 kb
Host smart-7ea7bd42-3f3d-48af-b25a-940671966d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065833911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4065833911
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3551832590
Short name T265
Test name
Test status
Simulation time 58209648100 ps
CPU time 145.97 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:52:01 PM PDT 24
Peak memory 253764 kb
Host smart-8c545414-b4f0-49b1-bd81-7701552ee748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551832590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3551832590
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1985581263
Short name T173
Test name
Test status
Simulation time 1629694908 ps
CPU time 7.65 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:49:43 PM PDT 24
Peak memory 235364 kb
Host smart-4ac0bade-bb54-4432-8628-b5259ce38abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985581263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1985581263
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2245504125
Short name T922
Test name
Test status
Simulation time 380563892 ps
CPU time 6.12 seconds
Started Jun 25 06:49:28 PM PDT 24
Finished Jun 25 06:49:36 PM PDT 24
Peak memory 224980 kb
Host smart-5804c11e-e60c-494c-95e8-61545c94e25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245504125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2245504125
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1745788432
Short name T972
Test name
Test status
Simulation time 20189862638 ps
CPU time 26.87 seconds
Started Jun 25 06:49:28 PM PDT 24
Finished Jun 25 06:49:57 PM PDT 24
Peak memory 233212 kb
Host smart-5fe6e2a1-69cc-401f-b434-9554afba1178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745788432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1745788432
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2460147203
Short name T295
Test name
Test status
Simulation time 33476917905 ps
CPU time 18.32 seconds
Started Jun 25 06:49:28 PM PDT 24
Finished Jun 25 06:49:48 PM PDT 24
Peak memory 248988 kb
Host smart-95da9d98-cf50-4b4d-83c6-e270e7d884ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460147203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2460147203
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2384745311
Short name T510
Test name
Test status
Simulation time 9139803427 ps
CPU time 8.08 seconds
Started Jun 25 06:49:32 PM PDT 24
Finished Jun 25 06:49:42 PM PDT 24
Peak memory 219776 kb
Host smart-6c66565d-c530-4a03-a4cb-4932bec67529
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2384745311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2384745311
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.727496634
Short name T575
Test name
Test status
Simulation time 41359510899 ps
CPU time 16.49 seconds
Started Jun 25 06:49:26 PM PDT 24
Finished Jun 25 06:49:44 PM PDT 24
Peak memory 216728 kb
Host smart-deb9d046-d635-4ce7-a7e7-2315879695a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727496634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.727496634
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2814787136
Short name T916
Test name
Test status
Simulation time 766734827 ps
CPU time 5.37 seconds
Started Jun 25 06:49:25 PM PDT 24
Finished Jun 25 06:49:32 PM PDT 24
Peak memory 216736 kb
Host smart-a504def9-e7be-4c91-97dc-89d8fd55e32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814787136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2814787136
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3027663974
Short name T339
Test name
Test status
Simulation time 203168297 ps
CPU time 5.75 seconds
Started Jun 25 06:49:26 PM PDT 24
Finished Jun 25 06:49:34 PM PDT 24
Peak memory 216812 kb
Host smart-dd788c3b-332e-49fd-ba18-8cd5f66f418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027663974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3027663974
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1365537962
Short name T835
Test name
Test status
Simulation time 32020713 ps
CPU time 0.85 seconds
Started Jun 25 06:49:27 PM PDT 24
Finished Jun 25 06:49:30 PM PDT 24
Peak memory 206356 kb
Host smart-980a248b-84ca-41a0-b6c3-327516a36958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365537962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1365537962
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2358440231
Short name T988
Test name
Test status
Simulation time 72194240298 ps
CPU time 58.77 seconds
Started Jun 25 06:49:27 PM PDT 24
Finished Jun 25 06:50:28 PM PDT 24
Peak memory 237744 kb
Host smart-92583928-ab65-4ebf-9ed9-1d323643afc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358440231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2358440231
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2422348071
Short name T514
Test name
Test status
Simulation time 36908016 ps
CPU time 0.76 seconds
Started Jun 25 06:49:41 PM PDT 24
Finished Jun 25 06:49:44 PM PDT 24
Peak memory 205772 kb
Host smart-21ba2793-3683-442a-8e0c-932a2d46d8a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422348071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2422348071
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2326330648
Short name T549
Test name
Test status
Simulation time 520736954 ps
CPU time 2.95 seconds
Started Jun 25 06:49:41 PM PDT 24
Finished Jun 25 06:49:46 PM PDT 24
Peak memory 233184 kb
Host smart-7fa6cbbd-116b-4f54-9ea3-fc3cfb8d2fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326330648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2326330648
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2739696146
Short name T618
Test name
Test status
Simulation time 13824486 ps
CPU time 0.81 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:49:36 PM PDT 24
Peak memory 207300 kb
Host smart-4d948bcf-c09f-4751-9be2-1063bd920eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739696146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2739696146
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1707448091
Short name T259
Test name
Test status
Simulation time 3391559754 ps
CPU time 40.18 seconds
Started Jun 25 06:49:42 PM PDT 24
Finished Jun 25 06:50:24 PM PDT 24
Peak memory 238884 kb
Host smart-c3d4e413-b840-48d1-a69f-04ca7dc5af68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707448091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1707448091
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3643544131
Short name T587
Test name
Test status
Simulation time 18967415569 ps
CPU time 106 seconds
Started Jun 25 06:49:42 PM PDT 24
Finished Jun 25 06:51:30 PM PDT 24
Peak memory 249816 kb
Host smart-87f3ae9a-603f-46e7-a6ca-8ea5f2be29c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643544131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3643544131
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1504092997
Short name T15
Test name
Test status
Simulation time 42304852502 ps
CPU time 23.6 seconds
Started Jun 25 06:49:42 PM PDT 24
Finished Jun 25 06:50:07 PM PDT 24
Peak memory 225048 kb
Host smart-43fd3d5a-5c37-4076-bb5f-74798e020f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504092997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1504092997
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3627326769
Short name T848
Test name
Test status
Simulation time 427790340 ps
CPU time 2.8 seconds
Started Jun 25 06:49:42 PM PDT 24
Finished Jun 25 06:49:47 PM PDT 24
Peak memory 224968 kb
Host smart-3c81ab8e-ed38-4523-9d1a-b34c35846698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627326769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3627326769
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4078610146
Short name T250
Test name
Test status
Simulation time 1686789315 ps
CPU time 7.77 seconds
Started Jun 25 06:49:43 PM PDT 24
Finished Jun 25 06:49:53 PM PDT 24
Peak memory 233220 kb
Host smart-35735850-187d-44d5-bb1f-dc0ac799e50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078610146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4078610146
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.972844671
Short name T550
Test name
Test status
Simulation time 109784161 ps
CPU time 2.76 seconds
Started Jun 25 06:49:41 PM PDT 24
Finished Jun 25 06:49:45 PM PDT 24
Peak memory 232948 kb
Host smart-7407e826-6096-4153-8554-b49279e6d32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972844671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.972844671
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3512441935
Short name T302
Test name
Test status
Simulation time 140341385 ps
CPU time 3.15 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:49:38 PM PDT 24
Peak memory 233160 kb
Host smart-c5f12e52-23cc-4521-a2db-856e7821a596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512441935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3512441935
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3332324745
Short name T751
Test name
Test status
Simulation time 598803471 ps
CPU time 2.81 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:49:38 PM PDT 24
Peak memory 233200 kb
Host smart-9b6c8b24-b216-4e31-9ec4-14df031cd850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332324745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3332324745
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1026506852
Short name T427
Test name
Test status
Simulation time 1361051578 ps
CPU time 8.38 seconds
Started Jun 25 06:49:41 PM PDT 24
Finished Jun 25 06:49:51 PM PDT 24
Peak memory 220600 kb
Host smart-9aa3d55e-9fde-4df0-8c70-357cfe493496
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1026506852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1026506852
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2235031843
Short name T170
Test name
Test status
Simulation time 86729629505 ps
CPU time 147.99 seconds
Started Jun 25 06:49:42 PM PDT 24
Finished Jun 25 06:52:12 PM PDT 24
Peak memory 266472 kb
Host smart-5f46d8bf-89aa-42bd-b5f7-6b8d7e423756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235031843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2235031843
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1494796763
Short name T394
Test name
Test status
Simulation time 2852897556 ps
CPU time 8.58 seconds
Started Jun 25 06:49:33 PM PDT 24
Finished Jun 25 06:49:44 PM PDT 24
Peak memory 216772 kb
Host smart-fbfff7df-1f96-42cd-8bf6-fd8ec7a6b6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494796763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1494796763
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2866206058
Short name T30
Test name
Test status
Simulation time 359930119 ps
CPU time 2.55 seconds
Started Jun 25 06:49:34 PM PDT 24
Finished Jun 25 06:49:38 PM PDT 24
Peak memory 216748 kb
Host smart-b8f78a48-70ab-4c5a-9f92-3329cc99fa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866206058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2866206058
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1257886760
Short name T566
Test name
Test status
Simulation time 127934859 ps
CPU time 0.92 seconds
Started Jun 25 06:49:32 PM PDT 24
Finished Jun 25 06:49:35 PM PDT 24
Peak memory 206388 kb
Host smart-0310152f-76fc-41ae-8579-d634dd777665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257886760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1257886760
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3109139058
Short name T160
Test name
Test status
Simulation time 134615812 ps
CPU time 3.52 seconds
Started Jun 25 06:49:42 PM PDT 24
Finished Jun 25 06:49:47 PM PDT 24
Peak memory 233196 kb
Host smart-964b8cba-9b6c-4b57-8d22-d713cabea1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109139058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3109139058
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3313116785
Short name T276
Test name
Test status
Simulation time 1647345762 ps
CPU time 3.44 seconds
Started Jun 25 06:49:48 PM PDT 24
Finished Jun 25 06:49:53 PM PDT 24
Peak memory 233108 kb
Host smart-b3c3d795-0389-4567-9923-120f0e7f6336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313116785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3313116785
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.375155665
Short name T789
Test name
Test status
Simulation time 24393362 ps
CPU time 0.75 seconds
Started Jun 25 06:49:43 PM PDT 24
Finished Jun 25 06:49:45 PM PDT 24
Peak memory 206976 kb
Host smart-5589d27d-3f2e-443f-ade5-acf39817f713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375155665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.375155665
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1773096171
Short name T211
Test name
Test status
Simulation time 10343084164 ps
CPU time 136.21 seconds
Started Jun 25 06:49:49 PM PDT 24
Finished Jun 25 06:52:07 PM PDT 24
Peak memory 265392 kb
Host smart-7ac50d86-abe4-4e4b-b558-bb6e29a63c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773096171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1773096171
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2401770371
Short name T245
Test name
Test status
Simulation time 45965686461 ps
CPU time 78.98 seconds
Started Jun 25 06:49:48 PM PDT 24
Finished Jun 25 06:51:08 PM PDT 24
Peak memory 224976 kb
Host smart-51bb86b9-5506-4528-8e32-895cc231d35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401770371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2401770371
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2988837979
Short name T466
Test name
Test status
Simulation time 7910841408 ps
CPU time 49.61 seconds
Started Jun 25 06:49:49 PM PDT 24
Finished Jun 25 06:50:41 PM PDT 24
Peak memory 225112 kb
Host smart-cab199e1-0394-4f48-8a9c-0a81210cec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988837979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2988837979
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2198909938
Short name T887
Test name
Test status
Simulation time 370968778 ps
CPU time 7.61 seconds
Started Jun 25 06:49:48 PM PDT 24
Finished Jun 25 06:49:57 PM PDT 24
Peak memory 251292 kb
Host smart-ee9fc74a-c5f6-48bc-b492-3c502a0457f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198909938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2198909938
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2383851485
Short name T354
Test name
Test status
Simulation time 95714083 ps
CPU time 3.65 seconds
Started Jun 25 06:49:41 PM PDT 24
Finished Jun 25 06:49:46 PM PDT 24
Peak memory 228928 kb
Host smart-697eed59-f70d-4e06-a051-ef54ad387d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383851485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2383851485
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.662150988
Short name T735
Test name
Test status
Simulation time 160839061 ps
CPU time 4.17 seconds
Started Jun 25 06:49:48 PM PDT 24
Finished Jun 25 06:49:54 PM PDT 24
Peak memory 224988 kb
Host smart-ee1dc7cc-7cd4-45c5-8cf2-d1cd339baf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662150988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.662150988
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3886300480
Short name T482
Test name
Test status
Simulation time 13788385458 ps
CPU time 11.35 seconds
Started Jun 25 06:49:42 PM PDT 24
Finished Jun 25 06:49:55 PM PDT 24
Peak memory 224968 kb
Host smart-26517613-02ad-4656-9f31-86c7af9ee076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886300480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3886300480
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1593224669
Short name T882
Test name
Test status
Simulation time 415368897 ps
CPU time 4.01 seconds
Started Jun 25 06:49:40 PM PDT 24
Finished Jun 25 06:49:45 PM PDT 24
Peak memory 233216 kb
Host smart-f908fb6f-0912-4a2e-a445-16dccf4fe302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593224669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1593224669
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.551122561
Short name T764
Test name
Test status
Simulation time 912652452 ps
CPU time 8.89 seconds
Started Jun 25 06:49:48 PM PDT 24
Finished Jun 25 06:49:59 PM PDT 24
Peak memory 219692 kb
Host smart-10943aeb-aa9d-47f8-8bbf-6fee68a80b1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=551122561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.551122561
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2615134420
Short name T147
Test name
Test status
Simulation time 6543512050 ps
CPU time 157.97 seconds
Started Jun 25 06:49:48 PM PDT 24
Finished Jun 25 06:52:28 PM PDT 24
Peak memory 264812 kb
Host smart-de3b6286-ed3f-4fb2-a660-38f40c2f4e01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615134420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2615134420
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1267862151
Short name T335
Test name
Test status
Simulation time 11184369705 ps
CPU time 20.26 seconds
Started Jun 25 06:49:41 PM PDT 24
Finished Jun 25 06:50:03 PM PDT 24
Peak memory 216848 kb
Host smart-833993af-73b9-4237-a37a-13a34385e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267862151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1267862151
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.392858159
Short name T614
Test name
Test status
Simulation time 13363801738 ps
CPU time 10.32 seconds
Started Jun 25 06:49:43 PM PDT 24
Finished Jun 25 06:49:55 PM PDT 24
Peak memory 216836 kb
Host smart-fae92282-ab33-4c34-a450-7f336bda2d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392858159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.392858159
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2218855238
Short name T499
Test name
Test status
Simulation time 25741698 ps
CPU time 0.69 seconds
Started Jun 25 06:49:43 PM PDT 24
Finished Jun 25 06:49:46 PM PDT 24
Peak memory 206028 kb
Host smart-df78b60f-0c14-4961-83d6-f9dfe26cc4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218855238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2218855238
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.119907185
Short name T742
Test name
Test status
Simulation time 147269989 ps
CPU time 0.86 seconds
Started Jun 25 06:49:41 PM PDT 24
Finished Jun 25 06:49:43 PM PDT 24
Peak memory 207396 kb
Host smart-07894546-ae98-422c-b0b4-faa80b413e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119907185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.119907185
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2476544141
Short name T632
Test name
Test status
Simulation time 28158235002 ps
CPU time 15.6 seconds
Started Jun 25 06:49:49 PM PDT 24
Finished Jun 25 06:50:07 PM PDT 24
Peak memory 233264 kb
Host smart-63dede70-2668-43b4-8524-384678b1084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476544141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2476544141
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3477119277
Short name T927
Test name
Test status
Simulation time 12958770 ps
CPU time 0.72 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:06 PM PDT 24
Peak memory 205772 kb
Host smart-62e03f46-bf1c-4090-bc35-7fb6f7e95e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477119277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3477119277
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3048804437
Short name T609
Test name
Test status
Simulation time 490522720 ps
CPU time 4.09 seconds
Started Jun 25 06:49:57 PM PDT 24
Finished Jun 25 06:50:02 PM PDT 24
Peak memory 224948 kb
Host smart-6d27d454-12c6-409e-af01-f087d7e6c5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048804437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3048804437
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1467334998
Short name T560
Test name
Test status
Simulation time 32726459 ps
CPU time 0.83 seconds
Started Jun 25 06:49:49 PM PDT 24
Finished Jun 25 06:49:51 PM PDT 24
Peak memory 207212 kb
Host smart-68636fab-3abb-4824-b752-5a564e16f98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467334998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1467334998
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2599733260
Short name T199
Test name
Test status
Simulation time 13700393340 ps
CPU time 67.87 seconds
Started Jun 25 06:49:56 PM PDT 24
Finished Jun 25 06:51:05 PM PDT 24
Peak memory 257932 kb
Host smart-b07a3267-f9d1-4213-9669-fc0e66c1d7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599733260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2599733260
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2859432370
Short name T217
Test name
Test status
Simulation time 87661611194 ps
CPU time 204.47 seconds
Started Jun 25 06:49:56 PM PDT 24
Finished Jun 25 06:53:21 PM PDT 24
Peak memory 241484 kb
Host smart-41afc84c-dbdb-495a-9cbf-0312ecddf4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859432370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2859432370
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1421917925
Short name T841
Test name
Test status
Simulation time 26130542072 ps
CPU time 234.94 seconds
Started Jun 25 06:49:56 PM PDT 24
Finished Jun 25 06:53:52 PM PDT 24
Peak memory 253180 kb
Host smart-41e9fb17-839d-43d9-8bd7-83b41cb927d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421917925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1421917925
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2426398627
Short name T648
Test name
Test status
Simulation time 327296183 ps
CPU time 5.62 seconds
Started Jun 25 06:49:55 PM PDT 24
Finished Jun 25 06:50:01 PM PDT 24
Peak memory 224880 kb
Host smart-c6bbb44f-ccad-44d5-ae55-1bedc1b7f2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426398627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2426398627
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3606694132
Short name T603
Test name
Test status
Simulation time 6458101498 ps
CPU time 19.36 seconds
Started Jun 25 06:49:55 PM PDT 24
Finished Jun 25 06:50:15 PM PDT 24
Peak memory 225000 kb
Host smart-96ce659f-1d9a-49aa-b901-ca4bfb356a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606694132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3606694132
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3551367482
Short name T352
Test name
Test status
Simulation time 3743888985 ps
CPU time 11.42 seconds
Started Jun 25 06:49:57 PM PDT 24
Finished Jun 25 06:50:10 PM PDT 24
Peak memory 229796 kb
Host smart-68684ba1-fa62-46f2-9638-c1a9a331f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551367482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3551367482
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4292550673
Short name T851
Test name
Test status
Simulation time 4789410396 ps
CPU time 15.83 seconds
Started Jun 25 06:49:48 PM PDT 24
Finished Jun 25 06:50:05 PM PDT 24
Peak memory 241296 kb
Host smart-72ed70a7-92d2-473f-aa4f-4f59a49ce9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292550673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4292550673
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3373544138
Short name T534
Test name
Test status
Simulation time 181109794 ps
CPU time 4.96 seconds
Started Jun 25 06:49:50 PM PDT 24
Finished Jun 25 06:49:56 PM PDT 24
Peak memory 241224 kb
Host smart-37ee7453-d9d3-4808-a195-3b6133d66d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373544138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3373544138
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2826107928
Short name T806
Test name
Test status
Simulation time 1047423986 ps
CPU time 10.06 seconds
Started Jun 25 06:49:57 PM PDT 24
Finished Jun 25 06:50:08 PM PDT 24
Peak memory 223608 kb
Host smart-1bfd9c45-baa3-4ad7-8b09-4c285da02858
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2826107928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2826107928
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4027646697
Short name T37
Test name
Test status
Simulation time 79817471679 ps
CPU time 60.76 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:51:06 PM PDT 24
Peak memory 241500 kb
Host smart-62a4dedb-dd1e-4703-b73f-217e33ce64c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027646697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4027646697
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.772461559
Short name T440
Test name
Test status
Simulation time 280851134 ps
CPU time 2.33 seconds
Started Jun 25 06:49:50 PM PDT 24
Finished Jun 25 06:49:54 PM PDT 24
Peak memory 216936 kb
Host smart-ae0a37a4-c8c2-4e91-b2d7-30f41de47705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772461559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.772461559
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.159348342
Short name T155
Test name
Test status
Simulation time 6321553450 ps
CPU time 3.01 seconds
Started Jun 25 06:49:49 PM PDT 24
Finished Jun 25 06:49:54 PM PDT 24
Peak memory 208420 kb
Host smart-2acb381b-d42f-4e9e-9910-5d5731b56196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159348342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.159348342
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1990372260
Short name T991
Test name
Test status
Simulation time 213295489 ps
CPU time 1.75 seconds
Started Jun 25 06:49:47 PM PDT 24
Finished Jun 25 06:49:50 PM PDT 24
Peak memory 216756 kb
Host smart-7352e81d-a8fe-41ab-9ca5-1a9a093fa73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990372260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1990372260
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2708785978
Short name T701
Test name
Test status
Simulation time 144140569 ps
CPU time 0.86 seconds
Started Jun 25 06:49:49 PM PDT 24
Finished Jun 25 06:49:52 PM PDT 24
Peak memory 206336 kb
Host smart-d37fb497-b4b4-491b-8b37-782db4d9613d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708785978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2708785978
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.873982266
Short name T283
Test name
Test status
Simulation time 145252549 ps
CPU time 2.66 seconds
Started Jun 25 06:49:54 PM PDT 24
Finished Jun 25 06:49:58 PM PDT 24
Peak memory 224972 kb
Host smart-426a99ec-c766-45fa-8a4b-1faa3df4737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873982266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.873982266
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2492167180
Short name T740
Test name
Test status
Simulation time 15963010 ps
CPU time 0.77 seconds
Started Jun 25 06:50:14 PM PDT 24
Finished Jun 25 06:50:16 PM PDT 24
Peak memory 205316 kb
Host smart-d527e684-209a-4f3a-818c-966bbe7a14c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492167180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2492167180
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3191897016
Short name T570
Test name
Test status
Simulation time 993420894 ps
CPU time 8.92 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:14 PM PDT 24
Peak memory 225008 kb
Host smart-c6ca32f9-fa7c-4e49-a482-000fb46e5821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191897016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3191897016
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.893538018
Short name T388
Test name
Test status
Simulation time 57537459 ps
CPU time 0.79 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:06 PM PDT 24
Peak memory 206876 kb
Host smart-27903f8e-e0e6-4676-aa2f-4bc20f85ee11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893538018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.893538018
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.29487814
Short name T713
Test name
Test status
Simulation time 4097324434 ps
CPU time 39.09 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:54 PM PDT 24
Peak memory 241404 kb
Host smart-82b11ded-ce73-4507-888b-eaf53286d190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29487814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.29487814
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1744741351
Short name T781
Test name
Test status
Simulation time 8559330977 ps
CPU time 25.48 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:41 PM PDT 24
Peak memory 236396 kb
Host smart-6534c7a3-b1ef-4dd9-a6fa-c2b85af528dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744741351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1744741351
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.65788221
Short name T4
Test name
Test status
Simulation time 441795549 ps
CPU time 6.37 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:21 PM PDT 24
Peak memory 217700 kb
Host smart-af95d859-0442-423d-a34f-af5a979e9946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65788221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.65788221
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1443925067
Short name T323
Test name
Test status
Simulation time 113667646 ps
CPU time 5.21 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:10 PM PDT 24
Peak memory 224928 kb
Host smart-03008397-ea71-412d-9558-5ff722cb4f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443925067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1443925067
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3736880411
Short name T459
Test name
Test status
Simulation time 546094790 ps
CPU time 6.41 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:11 PM PDT 24
Peak memory 233200 kb
Host smart-6c842680-2385-43b0-86e1-083b536fb25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736880411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3736880411
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.409567201
Short name T945
Test name
Test status
Simulation time 15485057325 ps
CPU time 20.9 seconds
Started Jun 25 06:50:03 PM PDT 24
Finished Jun 25 06:50:25 PM PDT 24
Peak memory 225004 kb
Host smart-117c82cc-cb3e-41d5-9bcf-691e00317a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409567201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.409567201
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2150986097
Short name T733
Test name
Test status
Simulation time 76173670 ps
CPU time 3.4 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:08 PM PDT 24
Peak memory 233176 kb
Host smart-71d91752-8b83-4137-a37d-598ba0cddcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150986097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2150986097
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2636136076
Short name T890
Test name
Test status
Simulation time 15633766493 ps
CPU time 9.32 seconds
Started Jun 25 06:50:03 PM PDT 24
Finished Jun 25 06:50:13 PM PDT 24
Peak memory 225020 kb
Host smart-03f9e806-3a79-466d-8004-2cf5a77f5bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636136076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2636136076
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3430262196
Short name T810
Test name
Test status
Simulation time 119022944 ps
CPU time 4.71 seconds
Started Jun 25 06:50:03 PM PDT 24
Finished Jun 25 06:50:09 PM PDT 24
Peak memory 222784 kb
Host smart-82038804-7357-4146-ae49-f774012be37c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430262196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3430262196
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1561178678
Short name T788
Test name
Test status
Simulation time 41985167 ps
CPU time 1.06 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:15 PM PDT 24
Peak memory 207384 kb
Host smart-f5a7c7aa-6dc4-474c-b28d-ed53477867ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561178678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1561178678
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3184756644
Short name T519
Test name
Test status
Simulation time 2951167770 ps
CPU time 25.96 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:30 PM PDT 24
Peak memory 216952 kb
Host smart-3714e86d-3d8f-41a5-941e-03e4a5542593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184756644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3184756644
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2593986938
Short name T753
Test name
Test status
Simulation time 11822069 ps
CPU time 0.73 seconds
Started Jun 25 06:50:03 PM PDT 24
Finished Jun 25 06:50:05 PM PDT 24
Peak memory 205980 kb
Host smart-15804b88-833f-4f6a-9a06-9973d30eeea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593986938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2593986938
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1122894896
Short name T530
Test name
Test status
Simulation time 132775702 ps
CPU time 1.11 seconds
Started Jun 25 06:50:05 PM PDT 24
Finished Jun 25 06:50:07 PM PDT 24
Peak memory 207616 kb
Host smart-ea6d7476-8ccd-4a7f-aeea-eefc7ff8b260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122894896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1122894896
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1378307232
Short name T590
Test name
Test status
Simulation time 35790018 ps
CPU time 0.73 seconds
Started Jun 25 06:50:04 PM PDT 24
Finished Jun 25 06:50:05 PM PDT 24
Peak memory 206004 kb
Host smart-3bcdce10-f945-4a1b-bba4-71d5951c7611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378307232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1378307232
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.644863621
Short name T762
Test name
Test status
Simulation time 4848396885 ps
CPU time 9.21 seconds
Started Jun 25 06:50:05 PM PDT 24
Finished Jun 25 06:50:15 PM PDT 24
Peak memory 224984 kb
Host smart-f7167051-a92f-4310-bb6e-4895905f744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644863621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.644863621
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.372709380
Short name T446
Test name
Test status
Simulation time 38502862 ps
CPU time 0.71 seconds
Started Jun 25 06:50:22 PM PDT 24
Finished Jun 25 06:50:24 PM PDT 24
Peak memory 205892 kb
Host smart-27394483-da49-4e46-bcbc-34e4007a0b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372709380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.372709380
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2105794417
Short name T449
Test name
Test status
Simulation time 133701097 ps
CPU time 2.88 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:17 PM PDT 24
Peak memory 233112 kb
Host smart-5a0f2fdf-1edf-4a0b-ac45-a3fcb185a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105794417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2105794417
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3252571748
Short name T5
Test name
Test status
Simulation time 58322824 ps
CPU time 0.8 seconds
Started Jun 25 06:50:12 PM PDT 24
Finished Jun 25 06:50:14 PM PDT 24
Peak memory 206976 kb
Host smart-16aeeb9c-d216-4399-9625-e19d56f2ffcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252571748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3252571748
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4202048366
Short name T309
Test name
Test status
Simulation time 84120053646 ps
CPU time 291.31 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:55:13 PM PDT 24
Peak memory 264512 kb
Host smart-4a938fc6-db18-4305-a787-6d9ecd620a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202048366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4202048366
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.430178424
Short name T803
Test name
Test status
Simulation time 12896387992 ps
CPU time 59.77 seconds
Started Jun 25 06:50:23 PM PDT 24
Finished Jun 25 06:51:24 PM PDT 24
Peak memory 257292 kb
Host smart-13499fe2-3c80-485e-b3eb-bb03d518ae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430178424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.430178424
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.4119685244
Short name T451
Test name
Test status
Simulation time 2798793522 ps
CPU time 82.37 seconds
Started Jun 25 06:50:21 PM PDT 24
Finished Jun 25 06:51:45 PM PDT 24
Peak memory 257784 kb
Host smart-17bf5327-e2ec-41e9-b8b7-cf2d8b65dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119685244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.4119685244
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.574203892
Short name T613
Test name
Test status
Simulation time 2358759231 ps
CPU time 10.71 seconds
Started Jun 25 06:50:12 PM PDT 24
Finished Jun 25 06:50:24 PM PDT 24
Peak memory 233504 kb
Host smart-d18cbcb1-af50-4cd0-9726-ec624086d923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574203892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.574203892
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1514656352
Short name T975
Test name
Test status
Simulation time 1016756426 ps
CPU time 5.64 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:20 PM PDT 24
Peak memory 233196 kb
Host smart-8867b1ca-760a-4cd6-81ba-68d7761f0244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514656352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1514656352
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2603406192
Short name T221
Test name
Test status
Simulation time 5389544237 ps
CPU time 10.24 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:25 PM PDT 24
Peak memory 233268 kb
Host smart-6d1351e4-2af0-4ede-af4d-785da142ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603406192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2603406192
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3954258463
Short name T535
Test name
Test status
Simulation time 95144085 ps
CPU time 2.36 seconds
Started Jun 25 06:50:12 PM PDT 24
Finished Jun 25 06:50:16 PM PDT 24
Peak memory 224888 kb
Host smart-be484320-5ad3-4c25-9635-0e1d18a88dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954258463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3954258463
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2082474429
Short name T495
Test name
Test status
Simulation time 376399969 ps
CPU time 3.85 seconds
Started Jun 25 06:50:14 PM PDT 24
Finished Jun 25 06:50:19 PM PDT 24
Peak memory 233168 kb
Host smart-d561b3d7-5405-40b7-89e1-8a975bf2388d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082474429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2082474429
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1719452312
Short name T400
Test name
Test status
Simulation time 3321949427 ps
CPU time 10.84 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:25 PM PDT 24
Peak memory 219832 kb
Host smart-0e5f2885-15fc-49c3-91b5-f96af8f98539
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1719452312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1719452312
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2766577896
Short name T441
Test name
Test status
Simulation time 14198828358 ps
CPU time 116.24 seconds
Started Jun 25 06:50:19 PM PDT 24
Finished Jun 25 06:52:16 PM PDT 24
Peak memory 241512 kb
Host smart-4f9a365f-be91-444c-8861-19dda39afc66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766577896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2766577896
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3008014789
Short name T743
Test name
Test status
Simulation time 9077332409 ps
CPU time 24.52 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:39 PM PDT 24
Peak memory 216876 kb
Host smart-d545de3d-35c1-4b0e-9f9c-1fabc65c8c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008014789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3008014789
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2392597303
Short name T811
Test name
Test status
Simulation time 1106413698 ps
CPU time 2.85 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:18 PM PDT 24
Peak memory 216756 kb
Host smart-eb03209b-9bf7-46ba-9b66-a6c851585aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392597303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2392597303
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4251581916
Short name T395
Test name
Test status
Simulation time 56734077 ps
CPU time 1.58 seconds
Started Jun 25 06:50:13 PM PDT 24
Finished Jun 25 06:50:16 PM PDT 24
Peak memory 216816 kb
Host smart-50c2f802-de4f-4c3a-868e-018679ffb28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251581916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4251581916
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.622049934
Short name T879
Test name
Test status
Simulation time 20917218 ps
CPU time 0.8 seconds
Started Jun 25 06:50:14 PM PDT 24
Finished Jun 25 06:50:16 PM PDT 24
Peak memory 206380 kb
Host smart-5e61794f-266b-46d8-a8df-ffc03a86d568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622049934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.622049934
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.703941397
Short name T258
Test name
Test status
Simulation time 381617578 ps
CPU time 3.19 seconds
Started Jun 25 06:50:12 PM PDT 24
Finished Jun 25 06:50:16 PM PDT 24
Peak memory 233024 kb
Host smart-0af2da8b-eafc-4972-924f-8953c1e5a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703941397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.703941397
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3287067904
Short name T897
Test name
Test status
Simulation time 11853632 ps
CPU time 0.71 seconds
Started Jun 25 06:50:27 PM PDT 24
Finished Jun 25 06:50:29 PM PDT 24
Peak memory 205320 kb
Host smart-c7d43957-09f8-4477-8775-3c7d4842fe04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287067904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3287067904
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2403724283
Short name T462
Test name
Test status
Simulation time 147679199 ps
CPU time 5.14 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:50:28 PM PDT 24
Peak memory 225000 kb
Host smart-ac695761-4b3a-4c36-ba63-50efda305159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403724283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2403724283
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1462865889
Short name T450
Test name
Test status
Simulation time 16622871 ps
CPU time 0.82 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:50:22 PM PDT 24
Peak memory 206864 kb
Host smart-b509c27e-3655-414c-9474-dc900708295f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462865889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1462865889
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1291437319
Short name T280
Test name
Test status
Simulation time 118545255177 ps
CPU time 200.84 seconds
Started Jun 25 06:50:26 PM PDT 24
Finished Jun 25 06:53:48 PM PDT 24
Peak memory 249636 kb
Host smart-0209288f-8f6d-4a76-bab9-559be9d0dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291437319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1291437319
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2649146460
Short name T619
Test name
Test status
Simulation time 2688181116 ps
CPU time 20.28 seconds
Started Jun 25 06:50:30 PM PDT 24
Finished Jun 25 06:50:52 PM PDT 24
Peak memory 239464 kb
Host smart-dcca0aea-ef4d-4a18-a45e-85c01cc43799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649146460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2649146460
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.295692455
Short name T990
Test name
Test status
Simulation time 28025970719 ps
CPU time 273.2 seconds
Started Jun 25 06:50:28 PM PDT 24
Finished Jun 25 06:55:03 PM PDT 24
Peak memory 256836 kb
Host smart-c4ffe10b-3f75-434e-9238-a71eec962c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295692455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.295692455
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.241692391
Short name T422
Test name
Test status
Simulation time 154480384 ps
CPU time 4.34 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:50:25 PM PDT 24
Peak memory 233192 kb
Host smart-09417236-53e3-490b-b9f0-177850bd7197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241692391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.241692391
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2698871806
Short name T525
Test name
Test status
Simulation time 200525383 ps
CPU time 3.6 seconds
Started Jun 25 06:50:24 PM PDT 24
Finished Jun 25 06:50:29 PM PDT 24
Peak memory 224964 kb
Host smart-7c295227-2f43-4c4b-b68a-071a3012b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698871806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2698871806
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.469862890
Short name T473
Test name
Test status
Simulation time 5108362815 ps
CPU time 41.31 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:51:03 PM PDT 24
Peak memory 233204 kb
Host smart-8c457b38-3f9d-4a67-9dcf-0cda05bfab8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469862890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.469862890
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1692950573
Short name T836
Test name
Test status
Simulation time 2366811784 ps
CPU time 5.31 seconds
Started Jun 25 06:50:25 PM PDT 24
Finished Jun 25 06:50:31 PM PDT 24
Peak memory 225008 kb
Host smart-5cf3c6c8-fa7a-44b2-8c39-c957beb08add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692950573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1692950573
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.18389106
Short name T300
Test name
Test status
Simulation time 2421723476 ps
CPU time 7.82 seconds
Started Jun 25 06:50:19 PM PDT 24
Finished Jun 25 06:50:28 PM PDT 24
Peak memory 241336 kb
Host smart-a6e6c41a-edf9-4d6d-bc3c-ea29cf9a37c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18389106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.18389106
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3640511128
Short name T42
Test name
Test status
Simulation time 3027974840 ps
CPU time 10.9 seconds
Started Jun 25 06:50:19 PM PDT 24
Finished Jun 25 06:50:31 PM PDT 24
Peak memory 223476 kb
Host smart-fe087b46-11ef-4333-858c-7e831bb03c8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3640511128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3640511128
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2998198209
Short name T149
Test name
Test status
Simulation time 18152390130 ps
CPU time 143.93 seconds
Started Jun 25 06:50:29 PM PDT 24
Finished Jun 25 06:52:54 PM PDT 24
Peak memory 265020 kb
Host smart-9ef4a91b-eea0-4af9-b249-7e0aa6baa214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998198209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2998198209
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3679134334
Short name T877
Test name
Test status
Simulation time 204510367 ps
CPU time 0.73 seconds
Started Jun 25 06:50:23 PM PDT 24
Finished Jun 25 06:50:25 PM PDT 24
Peak memory 206096 kb
Host smart-523dd21d-9a49-4660-b569-0be8cca00e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679134334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3679134334
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.700766313
Short name T783
Test name
Test status
Simulation time 6659375952 ps
CPU time 5.8 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:50:28 PM PDT 24
Peak memory 216836 kb
Host smart-1a386e4d-ec65-4403-b817-2dcd01c4b752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700766313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.700766313
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2475842625
Short name T384
Test name
Test status
Simulation time 18373173 ps
CPU time 0.71 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:50:23 PM PDT 24
Peak memory 205984 kb
Host smart-ab38e327-1f3b-4faa-8417-513717abd7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475842625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2475842625
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.772201048
Short name T1
Test name
Test status
Simulation time 27363676 ps
CPU time 0.68 seconds
Started Jun 25 06:50:19 PM PDT 24
Finished Jun 25 06:50:22 PM PDT 24
Peak memory 205908 kb
Host smart-34269964-1c6f-40ed-9bc6-c8ea928b6858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772201048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.772201048
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2640115269
Short name T931
Test name
Test status
Simulation time 868892817 ps
CPU time 3.06 seconds
Started Jun 25 06:50:20 PM PDT 24
Finished Jun 25 06:50:25 PM PDT 24
Peak memory 224960 kb
Host smart-0cd75240-b9f8-4669-9dfc-ae1843edeb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640115269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2640115269
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4220398380
Short name T8
Test name
Test status
Simulation time 78368987 ps
CPU time 0.71 seconds
Started Jun 25 06:50:34 PM PDT 24
Finished Jun 25 06:50:36 PM PDT 24
Peak memory 205896 kb
Host smart-fcdffffa-5c57-4460-bbd8-5cda73382adc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220398380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4220398380
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.424305840
Short name T433
Test name
Test status
Simulation time 62173403 ps
CPU time 2.8 seconds
Started Jun 25 06:50:28 PM PDT 24
Finished Jun 25 06:50:32 PM PDT 24
Peak memory 233160 kb
Host smart-c9013e5a-dc69-456f-b824-11ff890f2fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424305840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.424305840
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3382771379
Short name T490
Test name
Test status
Simulation time 31207367 ps
CPU time 0.8 seconds
Started Jun 25 06:50:26 PM PDT 24
Finished Jun 25 06:50:28 PM PDT 24
Peak memory 206976 kb
Host smart-f221bd0c-e356-49d8-ae19-48ca128c4746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382771379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3382771379
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3718860558
Short name T891
Test name
Test status
Simulation time 19095494 ps
CPU time 0.79 seconds
Started Jun 25 06:50:36 PM PDT 24
Finished Jun 25 06:50:38 PM PDT 24
Peak memory 216312 kb
Host smart-ec2ae2dc-33f8-4f4d-bbb8-392258786b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718860558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3718860558
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1297932485
Short name T697
Test name
Test status
Simulation time 16330085845 ps
CPU time 164.28 seconds
Started Jun 25 06:50:33 PM PDT 24
Finished Jun 25 06:53:18 PM PDT 24
Peak memory 249696 kb
Host smart-6be73046-02bd-4008-a568-567c80c73153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297932485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1297932485
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.176238427
Short name T404
Test name
Test status
Simulation time 51242484267 ps
CPU time 360.63 seconds
Started Jun 25 06:50:35 PM PDT 24
Finished Jun 25 06:56:38 PM PDT 24
Peak memory 266108 kb
Host smart-a2d27d89-d248-4a6e-9aa3-2b087f09494f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176238427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.176238427
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1232696307
Short name T745
Test name
Test status
Simulation time 9724876203 ps
CPU time 39.51 seconds
Started Jun 25 06:50:27 PM PDT 24
Finished Jun 25 06:51:08 PM PDT 24
Peak memory 224756 kb
Host smart-3d7cb018-4595-4262-8ae2-b4d41838f990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232696307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1232696307
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.932292883
Short name T435
Test name
Test status
Simulation time 9268780932 ps
CPU time 18.52 seconds
Started Jun 25 06:50:25 PM PDT 24
Finished Jun 25 06:50:45 PM PDT 24
Peak memory 225016 kb
Host smart-ad851062-641c-4627-99af-7c1cacfe7c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932292883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.932292883
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.224115624
Short name T518
Test name
Test status
Simulation time 763692937 ps
CPU time 10.45 seconds
Started Jun 25 06:50:26 PM PDT 24
Finished Jun 25 06:50:37 PM PDT 24
Peak memory 224936 kb
Host smart-5de69e27-8816-437c-9694-5c49cd6b1290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224115624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.224115624
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4215049020
Short name T50
Test name
Test status
Simulation time 324562453 ps
CPU time 2.93 seconds
Started Jun 25 06:50:28 PM PDT 24
Finished Jun 25 06:50:32 PM PDT 24
Peak memory 225008 kb
Host smart-0437f51d-65ea-4620-a073-5e10df4415c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215049020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4215049020
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.265384639
Short name T263
Test name
Test status
Simulation time 2948290906 ps
CPU time 6.2 seconds
Started Jun 25 06:50:28 PM PDT 24
Finished Jun 25 06:50:36 PM PDT 24
Peak memory 225032 kb
Host smart-ed8f4ac6-2884-468c-a85d-550198065e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265384639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.265384639
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.29092149
Short name T438
Test name
Test status
Simulation time 435091904 ps
CPU time 6.42 seconds
Started Jun 25 06:50:35 PM PDT 24
Finished Jun 25 06:50:43 PM PDT 24
Peak memory 222432 kb
Host smart-07e43b03-f3e4-44ef-ba61-e3032c321ae0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=29092149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direc
t.29092149
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2244136342
Short name T333
Test name
Test status
Simulation time 1150646760 ps
CPU time 8.51 seconds
Started Jun 25 06:50:26 PM PDT 24
Finished Jun 25 06:50:36 PM PDT 24
Peak memory 216852 kb
Host smart-cd5036f6-2bee-4217-91b2-ef5fe9fe3167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244136342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2244136342
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3138318891
Short name T591
Test name
Test status
Simulation time 1067968354 ps
CPU time 2.26 seconds
Started Jun 25 06:50:27 PM PDT 24
Finished Jun 25 06:50:30 PM PDT 24
Peak memory 216584 kb
Host smart-2dde16f6-c301-4534-900b-34b2d9cad145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138318891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3138318891
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3964171460
Short name T892
Test name
Test status
Simulation time 157736094 ps
CPU time 1.96 seconds
Started Jun 25 06:50:28 PM PDT 24
Finished Jun 25 06:50:31 PM PDT 24
Peak memory 216828 kb
Host smart-2cc298b8-700b-4775-92c9-ee52e63d296d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964171460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3964171460
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1342828576
Short name T456
Test name
Test status
Simulation time 18951267 ps
CPU time 0.73 seconds
Started Jun 25 06:50:28 PM PDT 24
Finished Jun 25 06:50:30 PM PDT 24
Peak memory 206376 kb
Host smart-d6606f44-7028-4438-9b8f-3176e21d2b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342828576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1342828576
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1087689131
Short name T291
Test name
Test status
Simulation time 22838457714 ps
CPU time 16.32 seconds
Started Jun 25 06:50:30 PM PDT 24
Finished Jun 25 06:50:48 PM PDT 24
Peak memory 233212 kb
Host smart-63d9c7b2-ad8b-4912-89e6-9b8509d96863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087689131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1087689131
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1928466393
Short name T341
Test name
Test status
Simulation time 11682702 ps
CPU time 0.76 seconds
Started Jun 25 06:50:45 PM PDT 24
Finished Jun 25 06:50:47 PM PDT 24
Peak memory 205196 kb
Host smart-516c0954-7a53-41d1-8bb3-e8cdec0d9e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928466393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1928466393
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1643968828
Short name T358
Test name
Test status
Simulation time 241065714 ps
CPU time 4.42 seconds
Started Jun 25 06:50:44 PM PDT 24
Finished Jun 25 06:50:50 PM PDT 24
Peak memory 233208 kb
Host smart-9e5ec23d-be98-4d94-94c5-b40202099d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643968828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1643968828
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1486757473
Short name T369
Test name
Test status
Simulation time 23886888 ps
CPU time 0.76 seconds
Started Jun 25 06:50:34 PM PDT 24
Finished Jun 25 06:50:36 PM PDT 24
Peak memory 205824 kb
Host smart-376dcf04-4814-4c18-b3d6-223aceefb971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486757473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1486757473
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.688416815
Short name T205
Test name
Test status
Simulation time 48220784640 ps
CPU time 355.03 seconds
Started Jun 25 06:50:43 PM PDT 24
Finished Jun 25 06:56:39 PM PDT 24
Peak memory 262720 kb
Host smart-0cbd06e5-6005-4cfc-9b77-9c534345cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688416815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.688416815
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.426319894
Short name T204
Test name
Test status
Simulation time 17242666375 ps
CPU time 181.81 seconds
Started Jun 25 06:50:43 PM PDT 24
Finished Jun 25 06:53:45 PM PDT 24
Peak memory 256224 kb
Host smart-6bfd92af-ceae-4dfe-b133-2200bd05a03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426319894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.426319894
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2624887962
Short name T207
Test name
Test status
Simulation time 9833864800 ps
CPU time 76.3 seconds
Started Jun 25 06:50:44 PM PDT 24
Finished Jun 25 06:52:02 PM PDT 24
Peak memory 225004 kb
Host smart-347c8bca-9a28-42ab-b9c1-d1d4a0ec5f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624887962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2624887962
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2609318494
Short name T672
Test name
Test status
Simulation time 949635014 ps
CPU time 11.36 seconds
Started Jun 25 06:50:43 PM PDT 24
Finished Jun 25 06:50:55 PM PDT 24
Peak memory 234228 kb
Host smart-974e8071-6aed-4f7e-bee3-4c8d8a514da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609318494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2609318494
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.830582295
Short name T815
Test name
Test status
Simulation time 7604442014 ps
CPU time 11.82 seconds
Started Jun 25 06:50:32 PM PDT 24
Finished Jun 25 06:50:45 PM PDT 24
Peak memory 233276 kb
Host smart-c0d6438c-42c8-4604-a35d-f490b27d169d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830582295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.830582295
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1602541219
Short name T277
Test name
Test status
Simulation time 6990013537 ps
CPU time 16.1 seconds
Started Jun 25 06:50:34 PM PDT 24
Finished Jun 25 06:50:51 PM PDT 24
Peak memory 224976 kb
Host smart-0832a7ae-8d42-4ba9-bc7a-21136d5cd3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602541219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1602541219
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.621038358
Short name T49
Test name
Test status
Simulation time 5066112394 ps
CPU time 5.52 seconds
Started Jun 25 06:50:34 PM PDT 24
Finished Jun 25 06:50:41 PM PDT 24
Peak memory 225004 kb
Host smart-5cf15717-2f22-45f4-9f8e-84b1329d6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621038358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.621038358
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2264777749
Short name T418
Test name
Test status
Simulation time 8865909437 ps
CPU time 7.09 seconds
Started Jun 25 06:50:35 PM PDT 24
Finished Jun 25 06:50:44 PM PDT 24
Peak memory 224996 kb
Host smart-d09b1223-1ea6-4c9c-bdeb-51025593df15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264777749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2264777749
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1222060229
Short name T906
Test name
Test status
Simulation time 195402921 ps
CPU time 4.03 seconds
Started Jun 25 06:50:43 PM PDT 24
Finished Jun 25 06:50:48 PM PDT 24
Peak memory 223656 kb
Host smart-b7cf8b62-2ef2-4f88-89b1-180ae0c8bca2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1222060229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1222060229
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1733188619
Short name T152
Test name
Test status
Simulation time 4858104016 ps
CPU time 75.77 seconds
Started Jun 25 06:50:43 PM PDT 24
Finished Jun 25 06:51:59 PM PDT 24
Peak memory 249732 kb
Host smart-8ebc6327-db2b-401a-8f00-4f4627025bfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733188619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1733188619
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4020129282
Short name T330
Test name
Test status
Simulation time 4958715392 ps
CPU time 29.03 seconds
Started Jun 25 06:50:35 PM PDT 24
Finished Jun 25 06:51:06 PM PDT 24
Peak memory 216832 kb
Host smart-8a6939d7-58de-4bec-9c80-a15bbf6a1203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020129282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4020129282
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2052706098
Short name T576
Test name
Test status
Simulation time 2197108915 ps
CPU time 2.42 seconds
Started Jun 25 06:50:35 PM PDT 24
Finished Jun 25 06:50:39 PM PDT 24
Peak memory 216788 kb
Host smart-2da6eea2-6214-4d1c-80fc-f3265b527760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052706098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2052706098
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3230756841
Short name T421
Test name
Test status
Simulation time 128654438 ps
CPU time 1.8 seconds
Started Jun 25 06:50:34 PM PDT 24
Finished Jun 25 06:50:37 PM PDT 24
Peak memory 216748 kb
Host smart-e4e7d7b8-de4d-4e6b-a2e2-06309049bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230756841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3230756841
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3124430293
Short name T454
Test name
Test status
Simulation time 310752941 ps
CPU time 0.97 seconds
Started Jun 25 06:50:36 PM PDT 24
Finished Jun 25 06:50:38 PM PDT 24
Peak memory 206588 kb
Host smart-1b36b307-d5a2-40e5-a0e5-5e3996b40a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124430293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3124430293
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.154725363
Short name T860
Test name
Test status
Simulation time 1820011180 ps
CPU time 9.05 seconds
Started Jun 25 06:50:45 PM PDT 24
Finished Jun 25 06:50:55 PM PDT 24
Peak memory 225028 kb
Host smart-76a8fc2b-e2dd-4aac-980c-2735bce7f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154725363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.154725363
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2382090468
Short name T452
Test name
Test status
Simulation time 31357911 ps
CPU time 0.76 seconds
Started Jun 25 06:50:51 PM PDT 24
Finished Jun 25 06:50:54 PM PDT 24
Peak memory 205316 kb
Host smart-bfe810ad-c35e-49f2-b713-c07073863b65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382090468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2382090468
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3101795385
Short name T581
Test name
Test status
Simulation time 243916470 ps
CPU time 2.75 seconds
Started Jun 25 06:50:51 PM PDT 24
Finished Jun 25 06:50:55 PM PDT 24
Peak memory 224940 kb
Host smart-e6c91e13-9a7a-41de-8f18-95953311f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101795385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3101795385
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3085092113
Short name T816
Test name
Test status
Simulation time 74673827 ps
CPU time 0.84 seconds
Started Jun 25 06:50:43 PM PDT 24
Finished Jun 25 06:50:45 PM PDT 24
Peak memory 206832 kb
Host smart-f0ba73d7-133b-440a-8885-f97636d42ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085092113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3085092113
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2390293616
Short name T70
Test name
Test status
Simulation time 15892226803 ps
CPU time 64.92 seconds
Started Jun 25 06:50:51 PM PDT 24
Finished Jun 25 06:51:58 PM PDT 24
Peak memory 249772 kb
Host smart-4cc00c6a-c6d7-48d5-b2fd-f652789dbd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390293616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2390293616
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3652163874
Short name T314
Test name
Test status
Simulation time 39552578952 ps
CPU time 72.86 seconds
Started Jun 25 06:50:51 PM PDT 24
Finished Jun 25 06:52:05 PM PDT 24
Peak memory 262468 kb
Host smart-df3e737d-6765-4d74-b51b-e06672ad96e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652163874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3652163874
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1744896443
Short name T48
Test name
Test status
Simulation time 90610644536 ps
CPU time 214.8 seconds
Started Jun 25 06:50:52 PM PDT 24
Finished Jun 25 06:54:29 PM PDT 24
Peak memory 257856 kb
Host smart-727dd015-eefb-499d-be80-caddfde179a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744896443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1744896443
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3560129449
Short name T10
Test name
Test status
Simulation time 483207794 ps
CPU time 5.58 seconds
Started Jun 25 06:50:51 PM PDT 24
Finished Jun 25 06:50:58 PM PDT 24
Peak memory 233112 kb
Host smart-ddb05da8-a965-4d46-8043-c880cd0f71ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560129449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3560129449
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4190848160
Short name T278
Test name
Test status
Simulation time 5919030725 ps
CPU time 14.71 seconds
Started Jun 25 06:50:54 PM PDT 24
Finished Jun 25 06:51:10 PM PDT 24
Peak memory 228880 kb
Host smart-81290296-8f4e-4ba0-ad45-3862182b8b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190848160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4190848160
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2762916206
Short name T256
Test name
Test status
Simulation time 9830883726 ps
CPU time 53.27 seconds
Started Jun 25 06:50:52 PM PDT 24
Finished Jun 25 06:51:47 PM PDT 24
Peak memory 241008 kb
Host smart-6e226ebc-a616-45f2-bf65-1c2851cc6f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762916206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2762916206
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.61166909
Short name T690
Test name
Test status
Simulation time 11642050450 ps
CPU time 9.18 seconds
Started Jun 25 06:50:51 PM PDT 24
Finished Jun 25 06:51:02 PM PDT 24
Peak memory 241160 kb
Host smart-9f43cdfb-a43a-4495-b451-ba91e1d55924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61166909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.61166909
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4065605148
Short name T223
Test name
Test status
Simulation time 889513235 ps
CPU time 8.21 seconds
Started Jun 25 06:50:52 PM PDT 24
Finished Jun 25 06:51:02 PM PDT 24
Peak memory 225000 kb
Host smart-5d9a2479-e40a-48b4-b0e9-54f742a24f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065605148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4065605148
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3331185182
Short name T43
Test name
Test status
Simulation time 1591546533 ps
CPU time 5.15 seconds
Started Jun 25 06:50:53 PM PDT 24
Finished Jun 25 06:51:00 PM PDT 24
Peak memory 220684 kb
Host smart-5a5dacf6-3b3a-42f1-8da0-12b551006fc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3331185182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3331185182
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3073875869
Short name T505
Test name
Test status
Simulation time 56642290 ps
CPU time 1.2 seconds
Started Jun 25 06:50:52 PM PDT 24
Finished Jun 25 06:50:55 PM PDT 24
Peak memory 208256 kb
Host smart-d1f5c066-fb82-4503-9ba1-fca084b43bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073875869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3073875869
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2194575723
Short name T589
Test name
Test status
Simulation time 2273748509 ps
CPU time 11.73 seconds
Started Jun 25 06:50:52 PM PDT 24
Finished Jun 25 06:51:06 PM PDT 24
Peak memory 216888 kb
Host smart-ce6ac394-3b56-4025-b727-abbe1dd3db99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194575723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2194575723
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2083025230
Short name T504
Test name
Test status
Simulation time 11862770 ps
CPU time 0.72 seconds
Started Jun 25 06:50:51 PM PDT 24
Finished Jun 25 06:50:53 PM PDT 24
Peak memory 206072 kb
Host smart-f3ba2b91-b6c2-4c4e-804a-3099c31b0bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083025230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2083025230
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1161569758
Short name T812
Test name
Test status
Simulation time 27920168 ps
CPU time 1.56 seconds
Started Jun 25 06:50:59 PM PDT 24
Finished Jun 25 06:51:02 PM PDT 24
Peak memory 216808 kb
Host smart-4c28c470-0e37-414d-994b-1a8dd379be59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161569758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1161569758
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1249463039
Short name T718
Test name
Test status
Simulation time 78926917 ps
CPU time 0.78 seconds
Started Jun 25 06:50:52 PM PDT 24
Finished Jun 25 06:50:54 PM PDT 24
Peak memory 206372 kb
Host smart-f8931243-7a7a-4ecc-b1cd-4a8570041254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249463039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1249463039
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1670916964
Short name T165
Test name
Test status
Simulation time 2319598966 ps
CPU time 7.31 seconds
Started Jun 25 06:50:52 PM PDT 24
Finished Jun 25 06:51:01 PM PDT 24
Peak memory 241428 kb
Host smart-3f747566-8a4e-44b5-a00a-801d1dec991c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670916964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1670916964
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2184352224
Short name T551
Test name
Test status
Simulation time 12026347 ps
CPU time 0.72 seconds
Started Jun 25 06:45:57 PM PDT 24
Finished Jun 25 06:45:58 PM PDT 24
Peak memory 206008 kb
Host smart-49e93d06-9bfe-46c4-b617-740defe8af5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184352224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
184352224
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2089704547
Short name T884
Test name
Test status
Simulation time 3623220835 ps
CPU time 8.86 seconds
Started Jun 25 06:45:51 PM PDT 24
Finished Jun 25 06:46:02 PM PDT 24
Peak memory 225024 kb
Host smart-bac6724b-0f2d-454a-a34d-4e66600f7998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089704547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2089704547
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.436300851
Short name T572
Test name
Test status
Simulation time 12426440 ps
CPU time 0.78 seconds
Started Jun 25 06:45:43 PM PDT 24
Finished Jun 25 06:45:45 PM PDT 24
Peak memory 206280 kb
Host smart-c2e1f154-f955-4efd-86cf-f6060a449522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436300851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.436300851
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4260719645
Short name T738
Test name
Test status
Simulation time 20186901155 ps
CPU time 131.68 seconds
Started Jun 25 06:45:52 PM PDT 24
Finished Jun 25 06:48:05 PM PDT 24
Peak memory 255128 kb
Host smart-145061ef-51d8-47a9-8d97-056d6a0efb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260719645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4260719645
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2870210930
Short name T216
Test name
Test status
Simulation time 39390534955 ps
CPU time 326.76 seconds
Started Jun 25 06:45:58 PM PDT 24
Finished Jun 25 06:51:25 PM PDT 24
Peak memory 255784 kb
Host smart-244faf20-13e3-43da-ba22-a265a2dee1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870210930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2870210930
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.908619156
Short name T53
Test name
Test status
Simulation time 217347435472 ps
CPU time 331.57 seconds
Started Jun 25 06:45:57 PM PDT 24
Finished Jun 25 06:51:30 PM PDT 24
Peak memory 255252 kb
Host smart-4c20c517-5b98-4efe-9604-f271de7f620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908619156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
908619156
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2134613614
Short name T938
Test name
Test status
Simulation time 1677269622 ps
CPU time 18.15 seconds
Started Jun 25 06:45:51 PM PDT 24
Finished Jun 25 06:46:11 PM PDT 24
Peak memory 233236 kb
Host smart-4c3da7f0-c887-4a2f-8431-5e5e8e9b86e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134613614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2134613614
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1190652159
Short name T201
Test name
Test status
Simulation time 88677798 ps
CPU time 2.74 seconds
Started Jun 25 06:45:52 PM PDT 24
Finished Jun 25 06:45:56 PM PDT 24
Peak memory 224992 kb
Host smart-4abfe5b4-c592-406f-9816-09125afc5b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190652159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1190652159
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4165345306
Short name T481
Test name
Test status
Simulation time 1199732137 ps
CPU time 6.73 seconds
Started Jun 25 06:45:53 PM PDT 24
Finished Jun 25 06:46:01 PM PDT 24
Peak memory 224948 kb
Host smart-aced02b6-741d-4656-a613-5e9879e66ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165345306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4165345306
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2469994212
Short name T802
Test name
Test status
Simulation time 50329018 ps
CPU time 1.06 seconds
Started Jun 25 06:45:43 PM PDT 24
Finished Jun 25 06:45:45 PM PDT 24
Peak memory 217156 kb
Host smart-b207f749-ee19-4991-b20b-ea8c4b995f15
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469994212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2469994212
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1512202886
Short name T837
Test name
Test status
Simulation time 145549827 ps
CPU time 2.82 seconds
Started Jun 25 06:45:53 PM PDT 24
Finished Jun 25 06:45:57 PM PDT 24
Peak memory 224940 kb
Host smart-72f07600-d485-492f-bbc7-f10f38404a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512202886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1512202886
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.814537691
Short name T484
Test name
Test status
Simulation time 8911262250 ps
CPU time 15.91 seconds
Started Jun 25 06:45:50 PM PDT 24
Finished Jun 25 06:46:08 PM PDT 24
Peak memory 240920 kb
Host smart-8e147452-c74e-49bf-85ea-bccc9bac4583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814537691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.814537691
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3040561386
Short name T443
Test name
Test status
Simulation time 449174588 ps
CPU time 3.47 seconds
Started Jun 25 06:45:52 PM PDT 24
Finished Jun 25 06:45:57 PM PDT 24
Peak memory 219236 kb
Host smart-1ffc40c8-c50e-48ac-8453-c306c25150d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3040561386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3040561386
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1199593736
Short name T21
Test name
Test status
Simulation time 63002230 ps
CPU time 1.13 seconds
Started Jun 25 06:45:56 PM PDT 24
Finished Jun 25 06:45:58 PM PDT 24
Peak memory 236180 kb
Host smart-41f2ec03-bcb3-412d-abae-cfb2df0a6bf6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199593736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1199593736
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.51689440
Short name T329
Test name
Test status
Simulation time 2274062208 ps
CPU time 10.63 seconds
Started Jun 25 06:45:43 PM PDT 24
Finished Jun 25 06:45:54 PM PDT 24
Peak memory 220596 kb
Host smart-6540ec3f-b05c-4473-9379-eaf23a40679a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51689440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.51689440
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2355668062
Short name T744
Test name
Test status
Simulation time 13251299046 ps
CPU time 10.94 seconds
Started Jun 25 06:45:44 PM PDT 24
Finished Jun 25 06:45:56 PM PDT 24
Peak memory 216800 kb
Host smart-d8a653d5-1618-47a1-a1e2-7ebcd6084c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355668062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2355668062
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1241924149
Short name T541
Test name
Test status
Simulation time 107417408 ps
CPU time 0.91 seconds
Started Jun 25 06:45:43 PM PDT 24
Finished Jun 25 06:45:45 PM PDT 24
Peak memory 207228 kb
Host smart-418b82da-6d38-4e8d-a202-0801143cf289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241924149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1241924149
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1123914509
Short name T597
Test name
Test status
Simulation time 58149381 ps
CPU time 0.8 seconds
Started Jun 25 06:45:44 PM PDT 24
Finished Jun 25 06:45:46 PM PDT 24
Peak memory 206360 kb
Host smart-005028ad-41f7-4f58-bae0-de1a535f3b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123914509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1123914509
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1670445765
Short name T755
Test name
Test status
Simulation time 396069641 ps
CPU time 4.19 seconds
Started Jun 25 06:45:50 PM PDT 24
Finished Jun 25 06:45:57 PM PDT 24
Peak memory 240932 kb
Host smart-6f455e39-fece-4e4e-b2e4-aac499bb1499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670445765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1670445765
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2496955212
Short name T25
Test name
Test status
Simulation time 38964063 ps
CPU time 0.72 seconds
Started Jun 25 06:50:58 PM PDT 24
Finished Jun 25 06:51:00 PM PDT 24
Peak memory 205312 kb
Host smart-8a7acc26-24aa-43dd-a3c8-45b3cfa175b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496955212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2496955212
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3659224242
Short name T301
Test name
Test status
Simulation time 644218732 ps
CPU time 9.16 seconds
Started Jun 25 06:50:58 PM PDT 24
Finished Jun 25 06:51:09 PM PDT 24
Peak memory 233176 kb
Host smart-6a6963bf-666d-45f9-b881-36a749865558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659224242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3659224242
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4172640753
Short name T617
Test name
Test status
Simulation time 13794684 ps
CPU time 0.81 seconds
Started Jun 25 06:50:53 PM PDT 24
Finished Jun 25 06:50:56 PM PDT 24
Peak memory 206972 kb
Host smart-1fe4f82e-6662-4e14-bed6-83c56338e0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172640753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4172640753
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2026435985
Short name T244
Test name
Test status
Simulation time 2099669089 ps
CPU time 16.05 seconds
Started Jun 25 06:50:58 PM PDT 24
Finished Jun 25 06:51:15 PM PDT 24
Peak memory 219524 kb
Host smart-2483f3f8-1968-4f8e-abd5-d03b8af36a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026435985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2026435985
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2600173743
Short name T208
Test name
Test status
Simulation time 61856144423 ps
CPU time 154.5 seconds
Started Jun 25 06:50:58 PM PDT 24
Finished Jun 25 06:53:34 PM PDT 24
Peak memory 256260 kb
Host smart-1ebbd2ef-5588-4a99-bc5d-fdaa68d339fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600173743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2600173743
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3174718629
Short name T521
Test name
Test status
Simulation time 8806218432 ps
CPU time 52.81 seconds
Started Jun 25 06:50:58 PM PDT 24
Finished Jun 25 06:51:52 PM PDT 24
Peak memory 234692 kb
Host smart-eb3b98ce-de8c-4d49-bc46-0b94d26d47a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174718629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3174718629
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1434222818
Short name T773
Test name
Test status
Simulation time 5966936950 ps
CPU time 4.83 seconds
Started Jun 25 06:50:59 PM PDT 24
Finished Jun 25 06:51:05 PM PDT 24
Peak memory 225244 kb
Host smart-f37b058b-6f8e-4f0b-b7d4-bf4fcf99702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434222818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1434222818
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.802123126
Short name T801
Test name
Test status
Simulation time 30407999927 ps
CPU time 127.63 seconds
Started Jun 25 06:50:57 PM PDT 24
Finished Jun 25 06:53:05 PM PDT 24
Peak memory 241424 kb
Host smart-3e148f04-a9d3-4188-b40f-a54d23bc5b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802123126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.802123126
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3315151449
Short name T289
Test name
Test status
Simulation time 1321032032 ps
CPU time 5.18 seconds
Started Jun 25 06:50:57 PM PDT 24
Finished Jun 25 06:51:04 PM PDT 24
Peak memory 224928 kb
Host smart-d00522a2-b089-49e4-9efa-4959cdaea573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315151449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3315151449
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2684331341
Short name T64
Test name
Test status
Simulation time 4276028500 ps
CPU time 14.01 seconds
Started Jun 25 06:50:58 PM PDT 24
Finished Jun 25 06:51:13 PM PDT 24
Peak memory 225028 kb
Host smart-500d6204-9dd8-41ec-95b7-25ce87432fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684331341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2684331341
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4205963455
Short name T880
Test name
Test status
Simulation time 1218144480 ps
CPU time 5.59 seconds
Started Jun 25 06:50:59 PM PDT 24
Finished Jun 25 06:51:06 PM PDT 24
Peak memory 219616 kb
Host smart-f8b23ee4-8dea-42bf-a0bf-8d8d2344d545
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205963455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4205963455
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2633929260
Short name T151
Test name
Test status
Simulation time 328319661 ps
CPU time 1.35 seconds
Started Jun 25 06:50:58 PM PDT 24
Finished Jun 25 06:51:01 PM PDT 24
Peak memory 207716 kb
Host smart-296a6256-80db-4696-9b40-0102b8db2808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633929260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2633929260
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4222148888
Short name T915
Test name
Test status
Simulation time 1850184327 ps
CPU time 24.42 seconds
Started Jun 25 06:50:57 PM PDT 24
Finished Jun 25 06:51:22 PM PDT 24
Peak memory 216784 kb
Host smart-5326f0cb-6775-4a20-ac09-7633589e55e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222148888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4222148888
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2010334399
Short name T417
Test name
Test status
Simulation time 1018642014 ps
CPU time 4.1 seconds
Started Jun 25 06:50:54 PM PDT 24
Finished Jun 25 06:50:59 PM PDT 24
Peak memory 216288 kb
Host smart-aa148dc1-9a8a-4a83-b900-cb34a5305d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010334399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2010334399
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.141124841
Short name T791
Test name
Test status
Simulation time 48157336 ps
CPU time 0.92 seconds
Started Jun 25 06:51:00 PM PDT 24
Finished Jun 25 06:51:02 PM PDT 24
Peak memory 207392 kb
Host smart-6b27fc14-33b6-4830-b603-effbc7ec8a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141124841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.141124841
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3011104621
Short name T793
Test name
Test status
Simulation time 236749034 ps
CPU time 0.95 seconds
Started Jun 25 06:50:57 PM PDT 24
Finished Jun 25 06:50:59 PM PDT 24
Peak memory 207384 kb
Host smart-8106b7b8-c117-4653-88e3-0b9b97040193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011104621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3011104621
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1490332260
Short name T292
Test name
Test status
Simulation time 18108998120 ps
CPU time 16.74 seconds
Started Jun 25 06:50:59 PM PDT 24
Finished Jun 25 06:51:17 PM PDT 24
Peak memory 233192 kb
Host smart-7b93452c-f79f-4c50-86bc-61bbf40b3155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490332260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1490332260
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.220385096
Short name T881
Test name
Test status
Simulation time 18261425 ps
CPU time 0.73 seconds
Started Jun 25 06:51:07 PM PDT 24
Finished Jun 25 06:51:09 PM PDT 24
Peak memory 205892 kb
Host smart-0325683e-02ab-4094-86ec-955c11176135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220385096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.220385096
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2758741373
Short name T920
Test name
Test status
Simulation time 57253475 ps
CPU time 2.31 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:10 PM PDT 24
Peak memory 232920 kb
Host smart-c963a0fa-c506-4ea2-8ee2-3198c4f0a178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758741373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2758741373
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3166812994
Short name T351
Test name
Test status
Simulation time 55661319 ps
CPU time 0.78 seconds
Started Jun 25 06:50:59 PM PDT 24
Finished Jun 25 06:51:00 PM PDT 24
Peak memory 206268 kb
Host smart-4d96abe3-ca92-4b7a-9b93-b2fc1139249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166812994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3166812994
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1603832993
Short name T68
Test name
Test status
Simulation time 134964533771 ps
CPU time 234.89 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:55:01 PM PDT 24
Peak memory 249676 kb
Host smart-95b5a98b-7dc0-4b26-b513-340a1b506bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603832993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1603832993
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1132223259
Short name T187
Test name
Test status
Simulation time 13765129511 ps
CPU time 45.18 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:51:52 PM PDT 24
Peak memory 253672 kb
Host smart-f8717a40-24ad-4a68-9042-98fcb439e009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132223259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1132223259
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.839398356
Short name T479
Test name
Test status
Simulation time 8908313665 ps
CPU time 33.7 seconds
Started Jun 25 06:51:07 PM PDT 24
Finished Jun 25 06:51:42 PM PDT 24
Peak memory 238944 kb
Host smart-29e4fb8d-ac79-408b-9f9a-60f5651e5d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839398356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.839398356
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2983231671
Short name T563
Test name
Test status
Simulation time 364745390 ps
CPU time 4.12 seconds
Started Jun 25 06:51:07 PM PDT 24
Finished Jun 25 06:51:12 PM PDT 24
Peak memory 224992 kb
Host smart-135b7534-eba5-47be-9dd2-36cfe8a5e2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983231671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2983231671
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3366723028
Short name T859
Test name
Test status
Simulation time 17977259792 ps
CPU time 19.92 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:27 PM PDT 24
Peak memory 224976 kb
Host smart-92effe2f-7d61-47ff-966d-55ffca3de1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366723028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3366723028
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.448148458
Short name T635
Test name
Test status
Simulation time 772205535 ps
CPU time 12.71 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:20 PM PDT 24
Peak memory 233140 kb
Host smart-b9c88f10-0bb6-4948-b8f8-d53da6893eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448148458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.448148458
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1439990615
Short name T285
Test name
Test status
Simulation time 679033476 ps
CPU time 2.75 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:10 PM PDT 24
Peak memory 224992 kb
Host smart-5ac3125a-78f2-4a8b-b018-ae32d6b0f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439990615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1439990615
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.105326494
Short name T704
Test name
Test status
Simulation time 11311565567 ps
CPU time 9.18 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:51:16 PM PDT 24
Peak memory 233228 kb
Host smart-93923b53-fc57-42ef-91c9-d1630c6225a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105326494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.105326494
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2243086138
Short name T529
Test name
Test status
Simulation time 4430281346 ps
CPU time 15.87 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:51:22 PM PDT 24
Peak memory 219668 kb
Host smart-897e93ba-edae-41df-9851-10250c71c4c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2243086138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2243086138
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2745020765
Short name T19
Test name
Test status
Simulation time 357716869 ps
CPU time 1.12 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:51:08 PM PDT 24
Peak memory 207412 kb
Host smart-c824e6c4-96bd-4910-b701-d91baa1d7acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745020765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2745020765
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.538888254
Short name T447
Test name
Test status
Simulation time 1221088223 ps
CPU time 12.08 seconds
Started Jun 25 06:50:57 PM PDT 24
Finished Jun 25 06:51:10 PM PDT 24
Peak memory 216976 kb
Host smart-6dcfc627-5ef7-4dcd-8fcf-db8c8ea8c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538888254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.538888254
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1027565160
Short name T472
Test name
Test status
Simulation time 2100651510 ps
CPU time 5.74 seconds
Started Jun 25 06:51:00 PM PDT 24
Finished Jun 25 06:51:06 PM PDT 24
Peak memory 216716 kb
Host smart-25eb0f72-de10-4518-9d90-891db276ce44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027565160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1027565160
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.749643126
Short name T483
Test name
Test status
Simulation time 253830453 ps
CPU time 2.96 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:51:10 PM PDT 24
Peak memory 216744 kb
Host smart-dc8b3446-28ca-443b-a562-4b1f6b7dd911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749643126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.749643126
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3884236240
Short name T437
Test name
Test status
Simulation time 70964876 ps
CPU time 0.88 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:08 PM PDT 24
Peak memory 206300 kb
Host smart-a8bf652c-1bbe-4df3-a708-fedb3971ce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884236240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3884236240
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1478129740
Short name T46
Test name
Test status
Simulation time 3907914200 ps
CPU time 4.67 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:12 PM PDT 24
Peak memory 233260 kb
Host smart-0e0eba69-5e3f-41e2-a06d-6e31d040a5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478129740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1478129740
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1641183930
Short name T629
Test name
Test status
Simulation time 14279035 ps
CPU time 0.72 seconds
Started Jun 25 06:51:22 PM PDT 24
Finished Jun 25 06:51:25 PM PDT 24
Peak memory 206216 kb
Host smart-c10441e2-306d-49e7-9f16-f994bb878edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641183930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1641183930
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3059383312
Short name T749
Test name
Test status
Simulation time 192421913 ps
CPU time 3.8 seconds
Started Jun 25 06:51:14 PM PDT 24
Finished Jun 25 06:51:18 PM PDT 24
Peak memory 224928 kb
Host smart-a0ddc2a4-09b7-4fc3-8f77-feceb599bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059383312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3059383312
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2478457846
Short name T786
Test name
Test status
Simulation time 181114884 ps
CPU time 0.77 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:51:07 PM PDT 24
Peak memory 205952 kb
Host smart-591a34e5-9f90-488b-b57d-cc8ded01bcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478457846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2478457846
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.763980494
Short name T198
Test name
Test status
Simulation time 245142636746 ps
CPU time 327.93 seconds
Started Jun 25 06:51:14 PM PDT 24
Finished Jun 25 06:56:43 PM PDT 24
Peak memory 257628 kb
Host smart-d42a9bb3-4d67-40e0-92bc-b04d8289abd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763980494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.763980494
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1482223002
Short name T864
Test name
Test status
Simulation time 121525944940 ps
CPU time 255.05 seconds
Started Jun 25 06:51:13 PM PDT 24
Finished Jun 25 06:55:29 PM PDT 24
Peak memory 252056 kb
Host smart-75a83ce8-0e24-49bb-bab6-1ad4c5728de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482223002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1482223002
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3812136326
Short name T159
Test name
Test status
Simulation time 1198149264 ps
CPU time 21.96 seconds
Started Jun 25 06:51:17 PM PDT 24
Finished Jun 25 06:51:40 PM PDT 24
Peak memory 241416 kb
Host smart-72e2c255-0e35-4cca-bc30-840ff6d03ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812136326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3812136326
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2943116683
Short name T909
Test name
Test status
Simulation time 2166062261 ps
CPU time 19.24 seconds
Started Jun 25 06:51:15 PM PDT 24
Finished Jun 25 06:51:35 PM PDT 24
Peak memory 233180 kb
Host smart-58393773-6509-4c3f-9743-9a933e1b29d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943116683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2943116683
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4115876571
Short name T266
Test name
Test status
Simulation time 18561378574 ps
CPU time 17.46 seconds
Started Jun 25 06:51:15 PM PDT 24
Finished Jun 25 06:51:33 PM PDT 24
Peak memory 233260 kb
Host smart-d0072e27-927b-4958-82e4-9e497ea1901c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115876571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4115876571
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2755508950
Short name T577
Test name
Test status
Simulation time 22030407400 ps
CPU time 17.69 seconds
Started Jun 25 06:51:17 PM PDT 24
Finished Jun 25 06:51:35 PM PDT 24
Peak memory 241236 kb
Host smart-94e0e7bd-b24c-45b7-81fd-b2d22951a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755508950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2755508950
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.941680595
Short name T649
Test name
Test status
Simulation time 12302304075 ps
CPU time 20.02 seconds
Started Jun 25 06:51:15 PM PDT 24
Finished Jun 25 06:51:37 PM PDT 24
Peak memory 233256 kb
Host smart-8f4546f4-1f73-4c0c-8ee0-d35478ff2491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941680595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.941680595
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3642879347
Short name T725
Test name
Test status
Simulation time 2073996561 ps
CPU time 5.37 seconds
Started Jun 25 06:51:15 PM PDT 24
Finished Jun 25 06:51:22 PM PDT 24
Peak memory 219688 kb
Host smart-a48a6532-7f79-4f80-a58b-cec6e198fd9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3642879347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3642879347
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1289586121
Short name T164
Test name
Test status
Simulation time 14738880550 ps
CPU time 34.39 seconds
Started Jun 25 06:51:23 PM PDT 24
Finished Jun 25 06:51:59 PM PDT 24
Peak memory 250384 kb
Host smart-25eab6e5-fe57-490c-8c97-3479efd165ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289586121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1289586121
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3206069150
Short name T971
Test name
Test status
Simulation time 4448922430 ps
CPU time 18.26 seconds
Started Jun 25 06:51:05 PM PDT 24
Finished Jun 25 06:51:25 PM PDT 24
Peak memory 216968 kb
Host smart-ceb441f0-4410-45e3-a934-d84ff4a0f923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206069150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3206069150
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1897593347
Short name T682
Test name
Test status
Simulation time 542585695 ps
CPU time 3.61 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:11 PM PDT 24
Peak memory 216732 kb
Host smart-7998e679-3c2f-4652-8c44-abf35a1494fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897593347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1897593347
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.954054165
Short name T413
Test name
Test status
Simulation time 22666902 ps
CPU time 0.73 seconds
Started Jun 25 06:51:15 PM PDT 24
Finished Jun 25 06:51:17 PM PDT 24
Peak memory 206364 kb
Host smart-82299d09-7a7d-4492-b214-acb159dd348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954054165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.954054165
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1814428144
Short name T941
Test name
Test status
Simulation time 426134836 ps
CPU time 0.96 seconds
Started Jun 25 06:51:06 PM PDT 24
Finished Jun 25 06:51:09 PM PDT 24
Peak memory 206588 kb
Host smart-43238b19-2774-4b99-97ff-d2da77171864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814428144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1814428144
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3522145199
Short name T544
Test name
Test status
Simulation time 14178684428 ps
CPU time 14.84 seconds
Started Jun 25 06:51:15 PM PDT 24
Finished Jun 25 06:51:31 PM PDT 24
Peak memory 225004 kb
Host smart-c93ebb64-d276-4ecf-94ba-a7863e7de86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522145199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3522145199
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4210281366
Short name T511
Test name
Test status
Simulation time 26366797 ps
CPU time 0.71 seconds
Started Jun 25 06:51:29 PM PDT 24
Finished Jun 25 06:51:30 PM PDT 24
Peak memory 205196 kb
Host smart-fc1cf511-36a5-4c7d-a2cb-e04c39a9e533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210281366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4210281366
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1492323679
Short name T961
Test name
Test status
Simulation time 700133151 ps
CPU time 10.92 seconds
Started Jun 25 06:51:22 PM PDT 24
Finished Jun 25 06:51:34 PM PDT 24
Peak memory 233176 kb
Host smart-5feee3dd-f7bb-4c4c-a6dc-69d93f2b6870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492323679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1492323679
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4157895607
Short name T161
Test name
Test status
Simulation time 14145644 ps
CPU time 0.75 seconds
Started Jun 25 06:51:21 PM PDT 24
Finished Jun 25 06:51:23 PM PDT 24
Peak memory 205952 kb
Host smart-08ac1cbc-5931-4d98-a9a1-0a6842afe077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157895607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4157895607
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2901140035
Short name T7
Test name
Test status
Simulation time 28274435206 ps
CPU time 159.72 seconds
Started Jun 25 06:51:22 PM PDT 24
Finished Jun 25 06:54:04 PM PDT 24
Peak memory 250504 kb
Host smart-6aa6ee6e-0d42-4994-8a83-0dbbf6381bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901140035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2901140035
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1786282728
Short name T320
Test name
Test status
Simulation time 18997273957 ps
CPU time 96.16 seconds
Started Jun 25 06:51:28 PM PDT 24
Finished Jun 25 06:53:05 PM PDT 24
Peak memory 265792 kb
Host smart-12472f04-fc6f-4846-a3cd-3362c8939e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786282728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1786282728
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2599600152
Short name T715
Test name
Test status
Simulation time 2697839857 ps
CPU time 34.68 seconds
Started Jun 25 06:51:21 PM PDT 24
Finished Jun 25 06:51:57 PM PDT 24
Peak memory 233212 kb
Host smart-e0ca757f-8ca8-4eeb-93be-466f8d6f05f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599600152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2599600152
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.24664870
Short name T305
Test name
Test status
Simulation time 1427436247 ps
CPU time 6.04 seconds
Started Jun 25 06:51:23 PM PDT 24
Finished Jun 25 06:51:31 PM PDT 24
Peak memory 224940 kb
Host smart-be0f1715-df5f-49b1-bfa7-a8b08295868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24664870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.24664870
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1364516444
Short name T247
Test name
Test status
Simulation time 135795367283 ps
CPU time 79.12 seconds
Started Jun 25 06:51:21 PM PDT 24
Finished Jun 25 06:52:42 PM PDT 24
Peak memory 241384 kb
Host smart-301e0fd9-bba4-49c5-ae2f-0f3249918ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364516444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1364516444
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1104079844
Short name T396
Test name
Test status
Simulation time 1468061528 ps
CPU time 11.59 seconds
Started Jun 25 06:51:20 PM PDT 24
Finished Jun 25 06:51:33 PM PDT 24
Peak memory 233016 kb
Host smart-ea1b7b7d-1a4a-45b5-a3b4-1a619c3e9efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104079844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1104079844
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1858761955
Short name T677
Test name
Test status
Simulation time 1878945117 ps
CPU time 8.51 seconds
Started Jun 25 06:51:21 PM PDT 24
Finished Jun 25 06:51:30 PM PDT 24
Peak memory 233216 kb
Host smart-7795c9da-96e6-482a-a16a-7e4fdc69dcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858761955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1858761955
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2330146911
Short name T131
Test name
Test status
Simulation time 541330286 ps
CPU time 5.01 seconds
Started Jun 25 06:51:21 PM PDT 24
Finished Jun 25 06:51:27 PM PDT 24
Peak memory 219284 kb
Host smart-4ace1347-0072-44eb-9fb7-c1b10719a8bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2330146911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2330146911
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2932681937
Short name T134
Test name
Test status
Simulation time 271270182599 ps
CPU time 195.09 seconds
Started Jun 25 06:51:27 PM PDT 24
Finished Jun 25 06:54:43 PM PDT 24
Peak memory 266940 kb
Host smart-fd04f89d-d6cd-4c2f-8f40-df56f3c0abf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932681937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2932681937
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1602079083
Short name T328
Test name
Test status
Simulation time 17439692933 ps
CPU time 24.02 seconds
Started Jun 25 06:51:23 PM PDT 24
Finished Jun 25 06:51:48 PM PDT 24
Peak memory 216828 kb
Host smart-a5a02c58-dbd2-4332-ba5f-8959106982ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602079083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1602079083
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1481265157
Short name T362
Test name
Test status
Simulation time 33596492930 ps
CPU time 14.15 seconds
Started Jun 25 06:51:23 PM PDT 24
Finished Jun 25 06:51:39 PM PDT 24
Peak memory 216812 kb
Host smart-a023a79e-8482-4648-b945-2e8c1099eea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481265157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1481265157
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1524766253
Short name T528
Test name
Test status
Simulation time 51542968 ps
CPU time 1.61 seconds
Started Jun 25 06:51:21 PM PDT 24
Finished Jun 25 06:51:24 PM PDT 24
Peak memory 216628 kb
Host smart-dd5f7f50-4ecb-4e19-bbdd-fe1772de146d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524766253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1524766253
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.651454885
Short name T442
Test name
Test status
Simulation time 71871078 ps
CPU time 0.95 seconds
Started Jun 25 06:51:20 PM PDT 24
Finished Jun 25 06:51:22 PM PDT 24
Peak memory 206380 kb
Host smart-0212e2c5-7e74-45d0-bcf0-d91d5af86d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651454885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.651454885
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2504593149
Short name T476
Test name
Test status
Simulation time 45265871 ps
CPU time 2.25 seconds
Started Jun 25 06:51:21 PM PDT 24
Finished Jun 25 06:51:25 PM PDT 24
Peak memory 224684 kb
Host smart-409509bb-009c-4b28-8fdb-21a180a5cd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504593149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2504593149
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1606862150
Short name T556
Test name
Test status
Simulation time 33194130 ps
CPU time 0.71 seconds
Started Jun 25 06:51:38 PM PDT 24
Finished Jun 25 06:51:40 PM PDT 24
Peak memory 205356 kb
Host smart-d02cbddc-dcf2-4970-a2b6-8713ca080934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606862150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1606862150
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.300447873
Short name T574
Test name
Test status
Simulation time 1550814644 ps
CPU time 18.38 seconds
Started Jun 25 06:51:35 PM PDT 24
Finished Jun 25 06:51:55 PM PDT 24
Peak memory 233188 kb
Host smart-7297342c-b364-498f-b2f5-08f388d009df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300447873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.300447873
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.223640454
Short name T356
Test name
Test status
Simulation time 14263951 ps
CPU time 0.77 seconds
Started Jun 25 06:51:30 PM PDT 24
Finished Jun 25 06:51:31 PM PDT 24
Peak memory 205952 kb
Host smart-b6200d91-a6de-42a6-86d3-f408f70edd4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223640454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.223640454
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2227142926
Short name T719
Test name
Test status
Simulation time 9365915382 ps
CPU time 61.49 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:52:39 PM PDT 24
Peak memory 235308 kb
Host smart-a2258c06-2ab8-42c2-8c3e-884c7819fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227142926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2227142926
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3922218523
Short name T838
Test name
Test status
Simulation time 33419925252 ps
CPU time 84.35 seconds
Started Jun 25 06:51:38 PM PDT 24
Finished Jun 25 06:53:04 PM PDT 24
Peak memory 257868 kb
Host smart-c15e77a1-664c-4379-9a40-87437667bfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922218523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3922218523
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2617869427
Short name T660
Test name
Test status
Simulation time 63859592661 ps
CPU time 140.38 seconds
Started Jun 25 06:51:38 PM PDT 24
Finished Jun 25 06:54:00 PM PDT 24
Peak memory 241736 kb
Host smart-fed08584-8c39-4c00-989e-181118eb8f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617869427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2617869427
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1669198953
Short name T871
Test name
Test status
Simulation time 3349957646 ps
CPU time 33.89 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:52:11 PM PDT 24
Peak memory 233268 kb
Host smart-f766d5ad-c494-4b4d-8b40-b2430b987fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669198953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1669198953
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.643534172
Short name T799
Test name
Test status
Simulation time 2085425118 ps
CPU time 13.63 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:51:52 PM PDT 24
Peak memory 233216 kb
Host smart-047c3427-8efe-4563-b803-6a68887371ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643534172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.643534172
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.927205581
Short name T381
Test name
Test status
Simulation time 569676280 ps
CPU time 8.57 seconds
Started Jun 25 06:51:37 PM PDT 24
Finished Jun 25 06:51:47 PM PDT 24
Peak memory 233152 kb
Host smart-380c0b3b-221c-44c8-9d58-ce00b76ec992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927205581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.927205581
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1258394476
Short name T494
Test name
Test status
Simulation time 3668335776 ps
CPU time 12.96 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:51:51 PM PDT 24
Peak memory 225056 kb
Host smart-b9ffd715-b306-4a38-aad7-4095bf99fcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258394476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1258394476
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.863131273
Short name T695
Test name
Test status
Simulation time 1810978296 ps
CPU time 10.39 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:51:48 PM PDT 24
Peak memory 241168 kb
Host smart-9fad0614-c32c-4c50-a4bc-f568185f0b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863131273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.863131273
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2703098183
Short name T611
Test name
Test status
Simulation time 178477489 ps
CPU time 5.38 seconds
Started Jun 25 06:51:37 PM PDT 24
Finished Jun 25 06:51:44 PM PDT 24
Peak memory 223060 kb
Host smart-b49dcfec-7f56-417d-aed4-ef6b1179869f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2703098183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2703098183
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2646687271
Short name T895
Test name
Test status
Simulation time 1346796565 ps
CPU time 13.39 seconds
Started Jun 25 06:51:28 PM PDT 24
Finished Jun 25 06:51:43 PM PDT 24
Peak memory 219336 kb
Host smart-adc15221-6e6c-4898-b7b5-0a737d6a5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646687271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2646687271
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3361007026
Short name T813
Test name
Test status
Simulation time 2908425400 ps
CPU time 7.12 seconds
Started Jun 25 06:51:28 PM PDT 24
Finished Jun 25 06:51:36 PM PDT 24
Peak memory 216848 kb
Host smart-caeea42e-e9a6-431c-8346-fdf27d24dc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361007026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3361007026
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.921351689
Short name T52
Test name
Test status
Simulation time 942002394 ps
CPU time 4.65 seconds
Started Jun 25 06:51:28 PM PDT 24
Finished Jun 25 06:51:34 PM PDT 24
Peak memory 216776 kb
Host smart-0648edd3-6433-4148-aa2e-eb9b4a1c5c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921351689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.921351689
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2253420805
Short name T601
Test name
Test status
Simulation time 29033748 ps
CPU time 0.78 seconds
Started Jun 25 06:51:31 PM PDT 24
Finished Jun 25 06:51:33 PM PDT 24
Peak memory 206372 kb
Host smart-2d14e3db-ca89-4997-a49b-d591c5c84864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253420805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2253420805
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4110214141
Short name T424
Test name
Test status
Simulation time 3473815375 ps
CPU time 6.6 seconds
Started Jun 25 06:51:37 PM PDT 24
Finished Jun 25 06:51:45 PM PDT 24
Peak memory 233260 kb
Host smart-f401581c-ad79-4a9c-bb6e-8d5ad33672db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110214141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4110214141
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.62636136
Short name T950
Test name
Test status
Simulation time 19577397 ps
CPU time 0.7 seconds
Started Jun 25 06:51:47 PM PDT 24
Finished Jun 25 06:51:49 PM PDT 24
Peak memory 205308 kb
Host smart-0e25d93f-1e39-414e-ad92-c7b2902b379a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62636136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.62636136
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3262151067
Short name T918
Test name
Test status
Simulation time 4722408858 ps
CPU time 10.79 seconds
Started Jun 25 06:51:50 PM PDT 24
Finished Jun 25 06:52:02 PM PDT 24
Peak memory 233432 kb
Host smart-ebd18c8b-fb95-43af-a7d8-1ae7eb8b8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262151067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3262151067
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1005322428
Short name T771
Test name
Test status
Simulation time 31690165 ps
CPU time 0.79 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:51:38 PM PDT 24
Peak memory 206980 kb
Host smart-62979115-10bb-46e9-9539-5a83991c8bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005322428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1005322428
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2093487011
Short name T970
Test name
Test status
Simulation time 12498078132 ps
CPU time 83.55 seconds
Started Jun 25 06:51:45 PM PDT 24
Finished Jun 25 06:53:10 PM PDT 24
Peak memory 255684 kb
Host smart-3bbfff4f-f601-44a4-8263-1b15d95a1df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093487011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2093487011
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2167925564
Short name T56
Test name
Test status
Simulation time 15682172608 ps
CPU time 184.16 seconds
Started Jun 25 06:51:45 PM PDT 24
Finished Jun 25 06:54:51 PM PDT 24
Peak memory 265756 kb
Host smart-6bb6c261-e9d1-45a7-8b11-73025afdcc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167925564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2167925564
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4045887047
Short name T397
Test name
Test status
Simulation time 2594688248 ps
CPU time 9.34 seconds
Started Jun 25 06:51:43 PM PDT 24
Finished Jun 25 06:51:53 PM PDT 24
Peak memory 225008 kb
Host smart-a34eaede-767a-4478-8dff-0b00df23e2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045887047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4045887047
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1020029378
Short name T855
Test name
Test status
Simulation time 1833491180 ps
CPU time 6.19 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:51:51 PM PDT 24
Peak memory 233232 kb
Host smart-49f09b61-b3b2-40dc-9bd4-87728f08c134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020029378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1020029378
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.188700016
Short name T580
Test name
Test status
Simulation time 1231799628 ps
CPU time 11.36 seconds
Started Jun 25 06:51:45 PM PDT 24
Finished Jun 25 06:51:57 PM PDT 24
Peak memory 224920 kb
Host smart-df2719f4-c7bf-491e-b39f-b163890bed7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188700016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.188700016
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.992421287
Short name T506
Test name
Test status
Simulation time 1029274699 ps
CPU time 2.36 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:51:47 PM PDT 24
Peak memory 224716 kb
Host smart-93c8e057-18af-4380-b21c-7a61d81f24f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992421287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.992421287
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.206554498
Short name T448
Test name
Test status
Simulation time 20047750656 ps
CPU time 11.59 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:51:57 PM PDT 24
Peak memory 233260 kb
Host smart-59c20ed8-d7f9-4ce3-87da-7d0661aab2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206554498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.206554498
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1444864372
Short name T540
Test name
Test status
Simulation time 944324303 ps
CPU time 3.18 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:51:48 PM PDT 24
Peak memory 219332 kb
Host smart-563f2309-0f97-4dd2-b823-34fcc569788d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1444864372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1444864372
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1483231548
Short name T929
Test name
Test status
Simulation time 10637509370 ps
CPU time 250.66 seconds
Started Jun 25 06:51:46 PM PDT 24
Finished Jun 25 06:55:58 PM PDT 24
Peak memory 286664 kb
Host smart-0cf427b4-8270-4e4d-949f-4afefd89b47c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483231548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1483231548
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1383584155
Short name T419
Test name
Test status
Simulation time 1856357687 ps
CPU time 5.41 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:51:43 PM PDT 24
Peak memory 216820 kb
Host smart-8fd9134e-e81e-4509-b094-c20442149f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383584155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1383584155
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3192647617
Short name T537
Test name
Test status
Simulation time 243941315 ps
CPU time 1.61 seconds
Started Jun 25 06:51:35 PM PDT 24
Finished Jun 25 06:51:38 PM PDT 24
Peak memory 208280 kb
Host smart-eb82971d-0417-44e4-a484-65de560ea398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192647617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3192647617
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.162333678
Short name T531
Test name
Test status
Simulation time 254176062 ps
CPU time 5.1 seconds
Started Jun 25 06:51:45 PM PDT 24
Finished Jun 25 06:51:52 PM PDT 24
Peak memory 216752 kb
Host smart-3f09a059-d680-4de2-af93-10935d6e6b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162333678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.162333678
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2895489812
Short name T77
Test name
Test status
Simulation time 66063670 ps
CPU time 0.84 seconds
Started Jun 25 06:51:36 PM PDT 24
Finished Jun 25 06:51:38 PM PDT 24
Peak memory 206356 kb
Host smart-70e3f5d0-2c0d-486b-858a-29eefc329a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895489812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2895489812
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1505053612
Short name T626
Test name
Test status
Simulation time 122060928 ps
CPU time 2.51 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:51:48 PM PDT 24
Peak memory 225104 kb
Host smart-bb2f0b09-2d7e-4355-8b9f-cada43f94477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505053612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1505053612
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3427313148
Short name T463
Test name
Test status
Simulation time 12429245 ps
CPU time 0.74 seconds
Started Jun 25 06:52:00 PM PDT 24
Finished Jun 25 06:52:02 PM PDT 24
Peak memory 204792 kb
Host smart-a1217bf6-5e13-4ea3-b89e-7fc9a19bb68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427313148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3427313148
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1718986667
Short name T647
Test name
Test status
Simulation time 2418785291 ps
CPU time 4.3 seconds
Started Jun 25 06:51:51 PM PDT 24
Finished Jun 25 06:51:57 PM PDT 24
Peak memory 225008 kb
Host smart-4b76e7e9-a339-4ee7-8f66-44ac4820f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718986667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1718986667
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3571766456
Short name T746
Test name
Test status
Simulation time 65377486 ps
CPU time 0.81 seconds
Started Jun 25 06:51:46 PM PDT 24
Finished Jun 25 06:51:48 PM PDT 24
Peak memory 207336 kb
Host smart-e6f6c1d5-2ba8-4e2d-8ac7-ac72abfe5717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571766456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3571766456
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.607005553
Short name T195
Test name
Test status
Simulation time 1549787951 ps
CPU time 39.78 seconds
Started Jun 25 06:51:59 PM PDT 24
Finished Jun 25 06:52:40 PM PDT 24
Peak memory 256988 kb
Host smart-55426385-a3ba-4813-b186-e256b5e310a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607005553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.607005553
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2024848334
Short name T639
Test name
Test status
Simulation time 140675629355 ps
CPU time 280.5 seconds
Started Jun 25 06:51:52 PM PDT 24
Finished Jun 25 06:56:34 PM PDT 24
Peak memory 249700 kb
Host smart-98c7cf9e-217a-446a-92d1-a8d4f0995218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024848334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2024848334
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2138266522
Short name T823
Test name
Test status
Simulation time 37779568637 ps
CPU time 340.04 seconds
Started Jun 25 06:51:53 PM PDT 24
Finished Jun 25 06:57:34 PM PDT 24
Peak memory 249860 kb
Host smart-2b13d3c6-9d27-4277-ae29-dc510b8fa169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138266522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2138266522
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.56490649
Short name T615
Test name
Test status
Simulation time 11936298866 ps
CPU time 85.48 seconds
Started Jun 25 06:51:52 PM PDT 24
Finished Jun 25 06:53:19 PM PDT 24
Peak memory 256260 kb
Host smart-a3cddbff-dca4-4ea3-bdee-f701a6bb84c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56490649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.56490649
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2954894187
Short name T269
Test name
Test status
Simulation time 8599567921 ps
CPU time 23.93 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:52:09 PM PDT 24
Peak memory 233264 kb
Host smart-407fdcd7-2931-4004-9f17-dd8ecc82d993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954894187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2954894187
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.628895569
Short name T249
Test name
Test status
Simulation time 1214819378 ps
CPU time 12.01 seconds
Started Jun 25 06:51:46 PM PDT 24
Finished Jun 25 06:52:00 PM PDT 24
Peak memory 249976 kb
Host smart-6e8a7e13-ae30-4bd7-927b-4356bf1ed953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628895569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.628895569
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3287648373
Short name T756
Test name
Test status
Simulation time 1100801672 ps
CPU time 4.5 seconds
Started Jun 25 06:51:49 PM PDT 24
Finished Jun 25 06:51:54 PM PDT 24
Peak memory 233392 kb
Host smart-e4445911-ad46-4e5e-b3cc-9733b77a1ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287648373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3287648373
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1443034111
Short name T237
Test name
Test status
Simulation time 7385713822 ps
CPU time 23.31 seconds
Started Jun 25 06:51:47 PM PDT 24
Finished Jun 25 06:52:11 PM PDT 24
Peak memory 241396 kb
Host smart-c56dd52c-8b70-40e5-bca9-577552108a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443034111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1443034111
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4251719729
Short name T947
Test name
Test status
Simulation time 258154285 ps
CPU time 4.38 seconds
Started Jun 25 06:51:53 PM PDT 24
Finished Jun 25 06:51:58 PM PDT 24
Peak memory 221792 kb
Host smart-7b560f73-0116-42bd-8964-e4084a7d9dfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4251719729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4251719729
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3278598476
Short name T593
Test name
Test status
Simulation time 22330423727 ps
CPU time 33.97 seconds
Started Jun 25 06:51:45 PM PDT 24
Finished Jun 25 06:52:21 PM PDT 24
Peak memory 216788 kb
Host smart-99dd275a-ca82-4b79-8f9d-476769b7954b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278598476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3278598476
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1257472726
Short name T66
Test name
Test status
Simulation time 24710661425 ps
CPU time 15.66 seconds
Started Jun 25 06:51:46 PM PDT 24
Finished Jun 25 06:52:03 PM PDT 24
Peak memory 216840 kb
Host smart-5270798a-5d9a-4e83-974b-54bb91307520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257472726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1257472726
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2964599549
Short name T992
Test name
Test status
Simulation time 119588482 ps
CPU time 4.64 seconds
Started Jun 25 06:51:44 PM PDT 24
Finished Jun 25 06:51:49 PM PDT 24
Peak memory 216724 kb
Host smart-013793ef-7563-488c-8f27-c80163362f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964599549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2964599549
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4136124002
Short name T468
Test name
Test status
Simulation time 25565912 ps
CPU time 0.78 seconds
Started Jun 25 06:51:43 PM PDT 24
Finished Jun 25 06:51:45 PM PDT 24
Peak memory 206372 kb
Host smart-6d615d42-6952-4631-adc1-0e85b0faeb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136124002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4136124002
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3401809663
Short name T644
Test name
Test status
Simulation time 1271420152 ps
CPU time 11.51 seconds
Started Jun 25 06:51:43 PM PDT 24
Finished Jun 25 06:51:55 PM PDT 24
Peak memory 233112 kb
Host smart-1c03b1d0-2b1a-4c01-b3e0-b0826f415189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401809663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3401809663
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.608603962
Short name T779
Test name
Test status
Simulation time 13655597 ps
CPU time 0.73 seconds
Started Jun 25 06:51:59 PM PDT 24
Finished Jun 25 06:52:01 PM PDT 24
Peak memory 205868 kb
Host smart-be8da321-8829-4af7-8d6b-88c57aeff662
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608603962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.608603962
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4273904207
Short name T926
Test name
Test status
Simulation time 98866335 ps
CPU time 2.56 seconds
Started Jun 25 06:52:00 PM PDT 24
Finished Jun 25 06:52:04 PM PDT 24
Peak memory 232940 kb
Host smart-99cdae8e-d59c-4d0e-8048-fb0bbf668e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273904207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4273904207
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4257457775
Short name T376
Test name
Test status
Simulation time 14617467 ps
CPU time 0.83 seconds
Started Jun 25 06:52:00 PM PDT 24
Finished Jun 25 06:52:02 PM PDT 24
Peak memory 205320 kb
Host smart-092ea494-a858-40e9-8332-5f4330d819e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257457775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4257457775
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1342535893
Short name T390
Test name
Test status
Simulation time 21231800985 ps
CPU time 116.51 seconds
Started Jun 25 06:52:00 PM PDT 24
Finished Jun 25 06:53:58 PM PDT 24
Peak memory 265740 kb
Host smart-8014a2ac-3a67-463c-b7f0-af1344442097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342535893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1342535893
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.2997649556
Short name T760
Test name
Test status
Simulation time 34567015584 ps
CPU time 32.46 seconds
Started Jun 25 06:51:58 PM PDT 24
Finished Jun 25 06:52:31 PM PDT 24
Peak memory 238116 kb
Host smart-639dbca9-3686-43ba-b1e1-da76dcdc6de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997649556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.2997649556
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3391995035
Short name T986
Test name
Test status
Simulation time 5361041096 ps
CPU time 51.75 seconds
Started Jun 25 06:51:59 PM PDT 24
Finished Jun 25 06:52:52 PM PDT 24
Peak memory 233196 kb
Host smart-0d9ff7ed-ed08-45cf-8bc8-d6ccd4cb54a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391995035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3391995035
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.576255739
Short name T728
Test name
Test status
Simulation time 213747045 ps
CPU time 6.09 seconds
Started Jun 25 06:52:01 PM PDT 24
Finished Jun 25 06:52:08 PM PDT 24
Peak memory 241396 kb
Host smart-82878223-5afe-4669-b62a-cd1aaa71e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576255739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.576255739
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.963551379
Short name T761
Test name
Test status
Simulation time 2518675885 ps
CPU time 16.28 seconds
Started Jun 25 06:51:52 PM PDT 24
Finished Jun 25 06:52:09 PM PDT 24
Peak memory 233280 kb
Host smart-fce27c4e-f7df-4c78-a501-c29eba8d514e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963551379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.963551379
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1628815526
Short name T293
Test name
Test status
Simulation time 735381710 ps
CPU time 11.59 seconds
Started Jun 25 06:51:51 PM PDT 24
Finished Jun 25 06:52:03 PM PDT 24
Peak memory 233176 kb
Host smart-2816ad77-f665-4556-92d6-baea00858f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628815526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1628815526
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3891354968
Short name T610
Test name
Test status
Simulation time 360509887 ps
CPU time 3.52 seconds
Started Jun 25 06:51:53 PM PDT 24
Finished Jun 25 06:51:57 PM PDT 24
Peak memory 233176 kb
Host smart-ea11e210-e7f4-4809-b233-48885188af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891354968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3891354968
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.468507082
Short name T826
Test name
Test status
Simulation time 4242869128 ps
CPU time 13.38 seconds
Started Jun 25 06:51:51 PM PDT 24
Finished Jun 25 06:52:06 PM PDT 24
Peak memory 225024 kb
Host smart-c391ee2c-d278-4279-a239-4dfc9b82fc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468507082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.468507082
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1308344114
Short name T964
Test name
Test status
Simulation time 858315173 ps
CPU time 12.95 seconds
Started Jun 25 06:51:59 PM PDT 24
Finished Jun 25 06:52:14 PM PDT 24
Peak memory 219792 kb
Host smart-1b7dc865-40de-4796-863c-7b118a615e9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1308344114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1308344114
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.641558221
Short name T215
Test name
Test status
Simulation time 18813662191 ps
CPU time 58.13 seconds
Started Jun 25 06:52:00 PM PDT 24
Finished Jun 25 06:52:59 PM PDT 24
Peak memory 253344 kb
Host smart-c0567b05-ce0b-4b08-8285-52714f4f69a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641558221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.641558221
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.504317823
Short name T737
Test name
Test status
Simulation time 20251132374 ps
CPU time 27.37 seconds
Started Jun 25 06:51:53 PM PDT 24
Finished Jun 25 06:52:21 PM PDT 24
Peak memory 216876 kb
Host smart-5998f28d-7a7b-402e-a761-a2fd2f0d4c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504317823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.504317823
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2118951242
Short name T902
Test name
Test status
Simulation time 2038152572 ps
CPU time 5.03 seconds
Started Jun 25 06:52:00 PM PDT 24
Finished Jun 25 06:52:06 PM PDT 24
Peak memory 216780 kb
Host smart-be7d9364-97d4-4a99-8d65-433390597a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118951242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2118951242
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4253201756
Short name T130
Test name
Test status
Simulation time 21424692 ps
CPU time 0.76 seconds
Started Jun 25 06:52:00 PM PDT 24
Finished Jun 25 06:52:02 PM PDT 24
Peak memory 206020 kb
Host smart-7774b68f-bb74-4db9-a7c0-45f091da88f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253201756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4253201756
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.609450340
Short name T657
Test name
Test status
Simulation time 21526986 ps
CPU time 0.74 seconds
Started Jun 25 06:51:51 PM PDT 24
Finished Jun 25 06:51:53 PM PDT 24
Peak memory 206372 kb
Host smart-60890ffa-9b77-485b-8823-8c4932ab2d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609450340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.609450340
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3116420321
Short name T303
Test name
Test status
Simulation time 5006363477 ps
CPU time 15.12 seconds
Started Jun 25 06:51:52 PM PDT 24
Finished Jun 25 06:52:08 PM PDT 24
Peak memory 225008 kb
Host smart-2a99bdc6-5dcc-45b5-b034-4380f13b6eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116420321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3116420321
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1100665561
Short name T689
Test name
Test status
Simulation time 32443804 ps
CPU time 0.73 seconds
Started Jun 25 06:52:14 PM PDT 24
Finished Jun 25 06:52:16 PM PDT 24
Peak memory 205788 kb
Host smart-d1183139-c174-4ae8-a3fa-5524e76ea7df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100665561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1100665561
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2699902428
Short name T662
Test name
Test status
Simulation time 248896970 ps
CPU time 3.1 seconds
Started Jun 25 06:52:06 PM PDT 24
Finished Jun 25 06:52:10 PM PDT 24
Peak memory 224940 kb
Host smart-32b6623e-aa35-4459-bb28-962b3ce881ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699902428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2699902428
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1787533815
Short name T410
Test name
Test status
Simulation time 15497785 ps
CPU time 0.79 seconds
Started Jun 25 06:51:59 PM PDT 24
Finished Jun 25 06:52:01 PM PDT 24
Peak memory 207288 kb
Host smart-44ea0b44-98f5-431b-8db8-d3070ff3160f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787533815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1787533815
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3332436927
Short name T536
Test name
Test status
Simulation time 4853644311 ps
CPU time 38.42 seconds
Started Jun 25 06:52:06 PM PDT 24
Finished Jun 25 06:52:45 PM PDT 24
Peak memory 249660 kb
Host smart-3687b110-1514-4a7b-a1b6-024ba78fd826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332436927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3332436927
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1541941310
Short name T894
Test name
Test status
Simulation time 9392881694 ps
CPU time 20.54 seconds
Started Jun 25 06:52:06 PM PDT 24
Finished Jun 25 06:52:28 PM PDT 24
Peak memory 239156 kb
Host smart-f5653500-cd11-4201-9311-3d474ef8fdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541941310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1541941310
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3869945933
Short name T239
Test name
Test status
Simulation time 10094724613 ps
CPU time 52.24 seconds
Started Jun 25 06:52:06 PM PDT 24
Finished Jun 25 06:52:59 PM PDT 24
Peak memory 254016 kb
Host smart-2434cdfb-9c0c-4120-b839-255f20d9110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869945933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3869945933
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3288563788
Short name T664
Test name
Test status
Simulation time 100026058 ps
CPU time 3.04 seconds
Started Jun 25 06:52:26 PM PDT 24
Finished Jun 25 06:52:30 PM PDT 24
Peak memory 225204 kb
Host smart-7246e04e-c0ab-4711-8eaa-206a7948d2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288563788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3288563788
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1142263237
Short name T768
Test name
Test status
Simulation time 2913486851 ps
CPU time 4.91 seconds
Started Jun 25 06:52:09 PM PDT 24
Finished Jun 25 06:52:15 PM PDT 24
Peak memory 233292 kb
Host smart-b214efc3-50cb-4732-915f-5a7b99744f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142263237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1142263237
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3456453860
Short name T602
Test name
Test status
Simulation time 113605010 ps
CPU time 3.61 seconds
Started Jun 25 06:52:08 PM PDT 24
Finished Jun 25 06:52:13 PM PDT 24
Peak memory 219176 kb
Host smart-83ade1ff-64d3-4447-9a60-959da326a572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456453860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3456453860
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3788838470
Short name T254
Test name
Test status
Simulation time 31715581 ps
CPU time 2.28 seconds
Started Jun 25 06:52:06 PM PDT 24
Finished Jun 25 06:52:09 PM PDT 24
Peak memory 224772 kb
Host smart-47e14b57-78a3-4c6b-8fdb-64f67575777a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788838470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3788838470
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2413368948
Short name T251
Test name
Test status
Simulation time 12918038151 ps
CPU time 11.91 seconds
Started Jun 25 06:52:07 PM PDT 24
Finished Jun 25 06:52:20 PM PDT 24
Peak memory 241392 kb
Host smart-4833b9a4-9273-469a-9e74-4c24bf207465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413368948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2413368948
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3659600687
Short name T523
Test name
Test status
Simulation time 1691032065 ps
CPU time 15.34 seconds
Started Jun 25 06:52:07 PM PDT 24
Finished Jun 25 06:52:23 PM PDT 24
Peak memory 223588 kb
Host smart-9e9cf573-2b6b-48e6-977a-97c5472772d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3659600687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3659600687
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.277444420
Short name T599
Test name
Test status
Simulation time 111692648 ps
CPU time 1.13 seconds
Started Jun 25 06:52:06 PM PDT 24
Finished Jun 25 06:52:08 PM PDT 24
Peak memory 207276 kb
Host smart-48994b9f-c88e-4a4d-a904-12c977f7f80e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277444420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.277444420
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4069714189
Short name T498
Test name
Test status
Simulation time 4292384507 ps
CPU time 21.08 seconds
Started Jun 25 06:51:58 PM PDT 24
Finished Jun 25 06:52:21 PM PDT 24
Peak memory 216896 kb
Host smart-8b3e9986-7e31-4da0-902c-1cf3b6f7dce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069714189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4069714189
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1288647526
Short name T656
Test name
Test status
Simulation time 471051811 ps
CPU time 3.73 seconds
Started Jun 25 06:52:01 PM PDT 24
Finished Jun 25 06:52:06 PM PDT 24
Peak memory 216688 kb
Host smart-b27544b2-8009-4024-80f4-62bf49d81094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288647526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1288647526
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.320068036
Short name T833
Test name
Test status
Simulation time 304944331 ps
CPU time 0.84 seconds
Started Jun 25 06:52:07 PM PDT 24
Finished Jun 25 06:52:08 PM PDT 24
Peak memory 206248 kb
Host smart-b48d919d-b105-4e15-8ac4-0e9268218eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320068036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.320068036
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1922111179
Short name T163
Test name
Test status
Simulation time 97857424 ps
CPU time 0.89 seconds
Started Jun 25 06:52:06 PM PDT 24
Finished Jun 25 06:52:07 PM PDT 24
Peak memory 206364 kb
Host smart-3e9681cf-c38e-4be5-9ecc-bc4fbf22e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922111179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1922111179
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2191561163
Short name T488
Test name
Test status
Simulation time 32124121081 ps
CPU time 31.82 seconds
Started Jun 25 06:52:08 PM PDT 24
Finished Jun 25 06:52:41 PM PDT 24
Peak memory 235312 kb
Host smart-fa5b42c9-9cdb-4c13-81ad-b6365c1b90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191561163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2191561163
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2042146701
Short name T28
Test name
Test status
Simulation time 36411920 ps
CPU time 0.74 seconds
Started Jun 25 06:52:22 PM PDT 24
Finished Jun 25 06:52:23 PM PDT 24
Peak memory 205316 kb
Host smart-aa2443ec-cfec-460e-8523-0cbbba902993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042146701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2042146701
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2714371188
Short name T675
Test name
Test status
Simulation time 28429180 ps
CPU time 2.39 seconds
Started Jun 25 06:52:13 PM PDT 24
Finished Jun 25 06:52:17 PM PDT 24
Peak memory 232856 kb
Host smart-8f9678e3-edbc-46d3-b40f-b294c1e90197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714371188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2714371188
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1759287548
Short name T434
Test name
Test status
Simulation time 36418337 ps
CPU time 0.77 seconds
Started Jun 25 06:52:15 PM PDT 24
Finished Jun 25 06:52:16 PM PDT 24
Peak memory 205984 kb
Host smart-d0a03dea-1bc1-43c2-b3f0-9f537075765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759287548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1759287548
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2007029118
Short name T849
Test name
Test status
Simulation time 911200435 ps
CPU time 21.68 seconds
Started Jun 25 06:52:14 PM PDT 24
Finished Jun 25 06:52:37 PM PDT 24
Peak memory 249624 kb
Host smart-02f92652-a1fb-47a5-b9d4-af597e4feb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007029118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2007029118
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1365760520
Short name T727
Test name
Test status
Simulation time 14947376016 ps
CPU time 101.84 seconds
Started Jun 25 06:52:14 PM PDT 24
Finished Jun 25 06:53:57 PM PDT 24
Peak memory 225128 kb
Host smart-1d5b6c2a-d61a-4240-ada7-0bb94e228dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365760520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1365760520
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3235217306
Short name T919
Test name
Test status
Simulation time 53499993935 ps
CPU time 193.32 seconds
Started Jun 25 06:52:15 PM PDT 24
Finished Jun 25 06:55:29 PM PDT 24
Peak memory 249704 kb
Host smart-7382f9fe-ac19-4057-81da-b5289dad0e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235217306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3235217306
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2778520255
Short name T327
Test name
Test status
Simulation time 407142969 ps
CPU time 7.59 seconds
Started Jun 25 06:52:16 PM PDT 24
Finished Jun 25 06:52:24 PM PDT 24
Peak memory 224944 kb
Host smart-ffce8b5b-4c02-4d42-bfa1-32dab12c43e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778520255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2778520255
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1115985049
Short name T842
Test name
Test status
Simulation time 122984662 ps
CPU time 2.19 seconds
Started Jun 25 06:52:15 PM PDT 24
Finished Jun 25 06:52:19 PM PDT 24
Peak memory 223504 kb
Host smart-b6855469-1d62-40b9-8a64-5927d94d21bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115985049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1115985049
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.33374734
Short name T723
Test name
Test status
Simulation time 5496629551 ps
CPU time 33.25 seconds
Started Jun 25 06:52:13 PM PDT 24
Finished Jun 25 06:52:48 PM PDT 24
Peak memory 230608 kb
Host smart-3b2828c5-6966-4854-ab15-c5551b376a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33374734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.33374734
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4248705016
Short name T290
Test name
Test status
Simulation time 463534508 ps
CPU time 3.56 seconds
Started Jun 25 06:52:14 PM PDT 24
Finished Jun 25 06:52:19 PM PDT 24
Peak memory 233196 kb
Host smart-af2928f3-8b00-4085-874a-bd1ded16e325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248705016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4248705016
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.102923051
Short name T722
Test name
Test status
Simulation time 555960960 ps
CPU time 3.03 seconds
Started Jun 25 06:52:16 PM PDT 24
Finished Jun 25 06:52:20 PM PDT 24
Peak memory 224912 kb
Host smart-0658cf33-6fbc-4c10-b960-bd6afca563b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102923051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.102923051
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2397873065
Short name T374
Test name
Test status
Simulation time 6947879442 ps
CPU time 14.77 seconds
Started Jun 25 06:52:16 PM PDT 24
Finished Jun 25 06:52:32 PM PDT 24
Peak memory 220772 kb
Host smart-f6f5f796-289e-45c8-b820-4cfff5cbacfe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2397873065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2397873065
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1739991110
Short name T307
Test name
Test status
Simulation time 702937413100 ps
CPU time 548.27 seconds
Started Jun 25 06:52:14 PM PDT 24
Finished Jun 25 07:01:24 PM PDT 24
Peak memory 270192 kb
Host smart-14fd3fbf-b60e-4107-81e4-0164c4a62151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739991110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1739991110
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.411140466
Short name T960
Test name
Test status
Simulation time 603597335 ps
CPU time 1.9 seconds
Started Jun 25 06:52:14 PM PDT 24
Finished Jun 25 06:52:17 PM PDT 24
Peak memory 216768 kb
Host smart-5e6295dc-ad13-49d2-9255-892fc31ee3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411140466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.411140466
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2470213107
Short name T379
Test name
Test status
Simulation time 781027395 ps
CPU time 5.56 seconds
Started Jun 25 06:52:13 PM PDT 24
Finished Jun 25 06:52:20 PM PDT 24
Peak memory 216796 kb
Host smart-b0563085-bbb5-45ca-b541-becf9bf8a7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470213107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2470213107
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.210363921
Short name T935
Test name
Test status
Simulation time 645916136 ps
CPU time 5.91 seconds
Started Jun 25 06:52:14 PM PDT 24
Finished Jun 25 06:52:21 PM PDT 24
Peak memory 216888 kb
Host smart-5bd6f73b-25bb-4d27-9d1e-07910bc8b3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210363921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.210363921
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.155876776
Short name T26
Test name
Test status
Simulation time 12460642 ps
CPU time 0.73 seconds
Started Jun 25 06:52:16 PM PDT 24
Finished Jun 25 06:52:18 PM PDT 24
Peak memory 206004 kb
Host smart-e484e488-9f59-4d51-96c9-b1c027a78ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155876776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.155876776
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3596636391
Short name T485
Test name
Test status
Simulation time 25215263522 ps
CPU time 9.13 seconds
Started Jun 25 06:52:13 PM PDT 24
Finished Jun 25 06:52:23 PM PDT 24
Peak memory 224856 kb
Host smart-f457d0b3-25b7-46df-9352-4ee27c98fad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596636391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3596636391
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2929346843
Short name T554
Test name
Test status
Simulation time 13881527 ps
CPU time 0.73 seconds
Started Jun 25 06:46:13 PM PDT 24
Finished Jun 25 06:46:15 PM PDT 24
Peak memory 205880 kb
Host smart-afb07e3d-c695-4dca-9066-5a04573b281c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929346843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
929346843
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1903790532
Short name T857
Test name
Test status
Simulation time 301830465 ps
CPU time 2.44 seconds
Started Jun 25 06:46:07 PM PDT 24
Finished Jun 25 06:46:11 PM PDT 24
Peak memory 224984 kb
Host smart-e0972934-278f-4f98-a7f2-e4c7e6945a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903790532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1903790532
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3442914801
Short name T987
Test name
Test status
Simulation time 33467755 ps
CPU time 0.81 seconds
Started Jun 25 06:45:59 PM PDT 24
Finished Jun 25 06:46:00 PM PDT 24
Peak memory 207328 kb
Host smart-024aaca1-e589-46cc-bd74-9503bf793e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442914801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3442914801
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3072686647
Short name T565
Test name
Test status
Simulation time 13540361544 ps
CPU time 123.48 seconds
Started Jun 25 06:46:13 PM PDT 24
Finished Jun 25 06:48:17 PM PDT 24
Peak memory 254652 kb
Host smart-a56e89e3-cf51-4a83-9ba8-92f6162d32b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072686647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3072686647
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.314751955
Short name T720
Test name
Test status
Simulation time 238100312 ps
CPU time 2.91 seconds
Started Jun 25 06:46:05 PM PDT 24
Finished Jun 25 06:46:09 PM PDT 24
Peak memory 233188 kb
Host smart-45b2c2a8-9804-4b70-b095-a002f0087eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314751955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.314751955
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2764343042
Short name T304
Test name
Test status
Simulation time 153474213 ps
CPU time 2.82 seconds
Started Jun 25 06:46:06 PM PDT 24
Finished Jun 25 06:46:10 PM PDT 24
Peak memory 224964 kb
Host smart-e69fd5fa-18cc-4540-a422-0877b332a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764343042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2764343042
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3683844418
Short name T219
Test name
Test status
Simulation time 1946675584 ps
CPU time 17.1 seconds
Started Jun 25 06:46:06 PM PDT 24
Finished Jun 25 06:46:24 PM PDT 24
Peak memory 241340 kb
Host smart-b8c61c41-7c41-4c99-a0e7-a70b0bed28d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683844418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3683844418
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4228989565
Short name T547
Test name
Test status
Simulation time 50580732 ps
CPU time 1.06 seconds
Started Jun 25 06:45:56 PM PDT 24
Finished Jun 25 06:45:58 PM PDT 24
Peak memory 217148 kb
Host smart-d0d80a03-fb5a-458d-87a0-299e5bd8d038
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228989565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4228989565
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3044852287
Short name T968
Test name
Test status
Simulation time 1171611836 ps
CPU time 4.38 seconds
Started Jun 25 06:46:04 PM PDT 24
Finished Jun 25 06:46:10 PM PDT 24
Peak memory 224924 kb
Host smart-dbeb1f3e-04bd-4670-9218-d13305db02f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044852287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3044852287
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.312175458
Short name T220
Test name
Test status
Simulation time 15557251670 ps
CPU time 15.38 seconds
Started Jun 25 06:46:04 PM PDT 24
Finished Jun 25 06:46:20 PM PDT 24
Peak memory 225008 kb
Host smart-956fd454-77d9-48be-a8f4-4f2e047f9d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312175458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.312175458
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2625808693
Short name T138
Test name
Test status
Simulation time 2307128804 ps
CPU time 4.17 seconds
Started Jun 25 06:46:14 PM PDT 24
Finished Jun 25 06:46:19 PM PDT 24
Peak memory 220672 kb
Host smart-e8661c43-6ea4-41da-9c39-972b2a8cf0ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2625808693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2625808693
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2108487510
Short name T60
Test name
Test status
Simulation time 219155905 ps
CPU time 1.22 seconds
Started Jun 25 06:46:13 PM PDT 24
Finished Jun 25 06:46:15 PM PDT 24
Peak memory 235884 kb
Host smart-c17d0407-abb5-45ab-9556-f31a768bf6da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108487510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2108487510
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.419370294
Short name T805
Test name
Test status
Simulation time 166995060 ps
CPU time 2.68 seconds
Started Jun 25 06:46:06 PM PDT 24
Finished Jun 25 06:46:11 PM PDT 24
Peak memory 218832 kb
Host smart-17a2998e-2ce4-40a2-885e-f3912cf1d875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419370294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.419370294
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3437668712
Short name T359
Test name
Test status
Simulation time 1725566120 ps
CPU time 5.18 seconds
Started Jun 25 06:46:09 PM PDT 24
Finished Jun 25 06:46:15 PM PDT 24
Peak memory 216780 kb
Host smart-54e9eaeb-56d6-4a0d-9921-d0c505a6f282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437668712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3437668712
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2817781865
Short name T741
Test name
Test status
Simulation time 138444198 ps
CPU time 1.04 seconds
Started Jun 25 06:46:06 PM PDT 24
Finished Jun 25 06:46:08 PM PDT 24
Peak memory 207600 kb
Host smart-a9addab5-303c-422f-a88f-ad32ff4ca437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817781865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2817781865
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3273565819
Short name T6
Test name
Test status
Simulation time 99339625 ps
CPU time 0.89 seconds
Started Jun 25 06:46:04 PM PDT 24
Finished Jun 25 06:46:06 PM PDT 24
Peak memory 206244 kb
Host smart-742caa52-5b52-4a54-8566-3547a7ebf913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273565819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3273565819
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3685274830
Short name T564
Test name
Test status
Simulation time 3388859282 ps
CPU time 5.22 seconds
Started Jun 25 06:46:06 PM PDT 24
Finished Jun 25 06:46:12 PM PDT 24
Peak memory 241104 kb
Host smart-d9e9dcc8-819c-4db0-a0ab-407fd3e1ba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685274830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3685274830
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.822519237
Short name T503
Test name
Test status
Simulation time 13796228 ps
CPU time 0.73 seconds
Started Jun 25 06:52:28 PM PDT 24
Finished Jun 25 06:52:30 PM PDT 24
Peak memory 205308 kb
Host smart-34c42447-a6b8-4bd5-97e6-f2ed833e7d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822519237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.822519237
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3605349429
Short name T709
Test name
Test status
Simulation time 7434449332 ps
CPU time 15.99 seconds
Started Jun 25 06:52:20 PM PDT 24
Finished Jun 25 06:52:37 PM PDT 24
Peak memory 233252 kb
Host smart-99d93bde-0310-4046-96f4-c338e9b9c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605349429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3605349429
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1150218922
Short name T501
Test name
Test status
Simulation time 63365961 ps
CPU time 0.78 seconds
Started Jun 25 06:52:22 PM PDT 24
Finished Jun 25 06:52:23 PM PDT 24
Peak memory 205968 kb
Host smart-e61591ab-ea45-4ce6-9f6d-35fa73aaa530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150218922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1150218922
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1276421784
Short name T924
Test name
Test status
Simulation time 111438879193 ps
CPU time 156.06 seconds
Started Jun 25 06:52:32 PM PDT 24
Finished Jun 25 06:55:09 PM PDT 24
Peak memory 241492 kb
Host smart-b22e8114-5175-4837-8844-724f8be869da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276421784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1276421784
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.437424997
Short name T310
Test name
Test status
Simulation time 72053112139 ps
CPU time 345.73 seconds
Started Jun 25 06:52:30 PM PDT 24
Finished Jun 25 06:58:17 PM PDT 24
Peak memory 265224 kb
Host smart-da53bff7-f3c0-4144-a9c6-9004d87f96d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437424997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.437424997
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3962696722
Short name T169
Test name
Test status
Simulation time 53187371623 ps
CPU time 135.81 seconds
Started Jun 25 06:52:31 PM PDT 24
Finished Jun 25 06:54:48 PM PDT 24
Peak memory 249724 kb
Host smart-15b2f074-05e2-410a-b26d-656b8527e2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962696722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3962696722
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2740407917
Short name T325
Test name
Test status
Simulation time 4273660466 ps
CPU time 18.67 seconds
Started Jun 25 06:52:28 PM PDT 24
Finished Jun 25 06:52:47 PM PDT 24
Peak memory 241448 kb
Host smart-705d9177-b8d1-4548-97c9-5e9ea22521cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740407917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2740407917
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1179490045
Short name T900
Test name
Test status
Simulation time 130299737 ps
CPU time 2.71 seconds
Started Jun 25 06:52:24 PM PDT 24
Finished Jun 25 06:52:27 PM PDT 24
Peak memory 233204 kb
Host smart-5af64943-5d18-4150-be28-b7f0d0d00aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179490045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1179490045
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4099163388
Short name T717
Test name
Test status
Simulation time 34308240849 ps
CPU time 30.34 seconds
Started Jun 25 06:52:22 PM PDT 24
Finished Jun 25 06:52:53 PM PDT 24
Peak memory 225008 kb
Host smart-c374effc-33aa-449a-90df-9c571e6f6fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099163388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4099163388
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1924601787
Short name T296
Test name
Test status
Simulation time 6000192871 ps
CPU time 15.19 seconds
Started Jun 25 06:52:22 PM PDT 24
Finished Jun 25 06:52:38 PM PDT 24
Peak memory 233216 kb
Host smart-5c79dcf7-c120-4814-9836-667178f6a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924601787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1924601787
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2599336187
Short name T885
Test name
Test status
Simulation time 181247591 ps
CPU time 2.17 seconds
Started Jun 25 06:52:21 PM PDT 24
Finished Jun 25 06:52:24 PM PDT 24
Peak memory 223508 kb
Host smart-5a079d3f-c578-433e-92a1-c4161160496b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599336187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2599336187
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1778733044
Short name T684
Test name
Test status
Simulation time 93579730 ps
CPU time 4.05 seconds
Started Jun 25 06:52:27 PM PDT 24
Finished Jun 25 06:52:32 PM PDT 24
Peak memory 223140 kb
Host smart-53168994-8c92-4939-a277-0dda326339b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1778733044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1778733044
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2718164217
Short name T148
Test name
Test status
Simulation time 16190103877 ps
CPU time 158.92 seconds
Started Jun 25 06:52:29 PM PDT 24
Finished Jun 25 06:55:09 PM PDT 24
Peak memory 250760 kb
Host smart-ce696ebe-40e4-44f8-910e-02c30bc50d6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718164217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2718164217
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3688854252
Short name T739
Test name
Test status
Simulation time 8687781009 ps
CPU time 43.3 seconds
Started Jun 25 06:52:21 PM PDT 24
Finished Jun 25 06:53:05 PM PDT 24
Peak memory 216836 kb
Host smart-407379a4-2e2a-428a-89c2-098853c5c66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688854252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3688854252
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.4170756083
Short name T487
Test name
Test status
Simulation time 179070814 ps
CPU time 1.04 seconds
Started Jun 25 06:52:22 PM PDT 24
Finished Jun 25 06:52:24 PM PDT 24
Peak memory 208204 kb
Host smart-3affc66a-1a7f-4022-87ad-5671be7e5494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170756083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.4170756083
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.99223765
Short name T360
Test name
Test status
Simulation time 779844513 ps
CPU time 2.85 seconds
Started Jun 25 06:52:21 PM PDT 24
Finished Jun 25 06:52:25 PM PDT 24
Peak memory 216832 kb
Host smart-98d2c7e1-2267-4fb1-824f-1ff183892326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99223765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.99223765
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2572783265
Short name T578
Test name
Test status
Simulation time 78570694 ps
CPU time 0.82 seconds
Started Jun 25 06:52:23 PM PDT 24
Finished Jun 25 06:52:25 PM PDT 24
Peak memory 206360 kb
Host smart-67c0b462-09e5-49e2-98a8-7c7e8244abad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572783265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2572783265
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3721357827
Short name T257
Test name
Test status
Simulation time 7305136916 ps
CPU time 10.77 seconds
Started Jun 25 06:52:23 PM PDT 24
Finished Jun 25 06:52:34 PM PDT 24
Peak memory 249500 kb
Host smart-c7d166f4-33d4-45b3-916f-62b0e3d0d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721357827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3721357827
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2130913046
Short name T513
Test name
Test status
Simulation time 27006694 ps
CPU time 0.74 seconds
Started Jun 25 06:52:36 PM PDT 24
Finished Jun 25 06:52:38 PM PDT 24
Peak memory 205316 kb
Host smart-55fb1bd2-84f6-4435-8366-b91c441049e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130913046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2130913046
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2174232086
Short name T939
Test name
Test status
Simulation time 212315230 ps
CPU time 3.42 seconds
Started Jun 25 06:52:30 PM PDT 24
Finished Jun 25 06:52:34 PM PDT 24
Peak memory 225008 kb
Host smart-e9936db3-765f-4c21-a84e-8e5a63eb855f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174232086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2174232086
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2668792425
Short name T676
Test name
Test status
Simulation time 23548165 ps
CPU time 0.8 seconds
Started Jun 25 06:52:29 PM PDT 24
Finished Jun 25 06:52:30 PM PDT 24
Peak memory 206980 kb
Host smart-3e8da59b-a0e4-44f2-8f10-94f02d09ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668792425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2668792425
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3321474262
Short name T673
Test name
Test status
Simulation time 5160182040 ps
CPU time 20.93 seconds
Started Jun 25 06:52:28 PM PDT 24
Finished Jun 25 06:52:50 PM PDT 24
Peak memory 237928 kb
Host smart-c9fa4ad4-89dd-4aeb-a656-154daefc2ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321474262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3321474262
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2394188804
Short name T444
Test name
Test status
Simulation time 1147157720 ps
CPU time 14.13 seconds
Started Jun 25 06:52:30 PM PDT 24
Finished Jun 25 06:52:45 PM PDT 24
Peak memory 239864 kb
Host smart-e9c4aa49-f720-4366-a708-8011c2423b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394188804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2394188804
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.412865996
Short name T982
Test name
Test status
Simulation time 60247433090 ps
CPU time 47.94 seconds
Started Jun 25 06:52:38 PM PDT 24
Finished Jun 25 06:53:27 PM PDT 24
Peak memory 225076 kb
Host smart-c8e536bc-c602-4328-9a5b-af8d0cf47ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412865996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.412865996
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3353371531
Short name T527
Test name
Test status
Simulation time 3670040692 ps
CPU time 16.41 seconds
Started Jun 25 06:52:33 PM PDT 24
Finished Jun 25 06:52:51 PM PDT 24
Peak memory 225084 kb
Host smart-2e3c2780-c0d9-46f6-9bc2-9b7a7142ea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353371531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3353371531
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3604165606
Short name T297
Test name
Test status
Simulation time 2955715452 ps
CPU time 32.09 seconds
Started Jun 25 06:52:32 PM PDT 24
Finished Jun 25 06:53:05 PM PDT 24
Peak memory 225024 kb
Host smart-110018c8-1774-47f4-92e9-99ac2a4405c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604165606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3604165606
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1245269466
Short name T721
Test name
Test status
Simulation time 2915926035 ps
CPU time 22.87 seconds
Started Jun 25 06:52:29 PM PDT 24
Finished Jun 25 06:52:53 PM PDT 24
Peak memory 241448 kb
Host smart-1b00eb28-87b9-47bf-9483-fe5e1ff1c29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245269466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1245269466
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.4050645867
Short name T287
Test name
Test status
Simulation time 666326251 ps
CPU time 6.53 seconds
Started Jun 25 06:52:31 PM PDT 24
Finished Jun 25 06:52:39 PM PDT 24
Peak memory 241248 kb
Host smart-fa80f6fe-a25e-45d8-9910-26d84e0e5cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050645867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.4050645867
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1137085301
Short name T284
Test name
Test status
Simulation time 769078099 ps
CPU time 6.25 seconds
Started Jun 25 06:52:29 PM PDT 24
Finished Jun 25 06:52:37 PM PDT 24
Peak memory 233200 kb
Host smart-3aa6f28a-9f4a-47ed-8a97-d025983766cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137085301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1137085301
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4006175551
Short name T904
Test name
Test status
Simulation time 1274162064 ps
CPU time 7.7 seconds
Started Jun 25 06:52:30 PM PDT 24
Finished Jun 25 06:52:38 PM PDT 24
Peak memory 219460 kb
Host smart-e644a747-e9b3-483b-b9a5-82866136ae36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4006175551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4006175551
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1937233467
Short name T317
Test name
Test status
Simulation time 6257797129 ps
CPU time 90.59 seconds
Started Jun 25 06:52:37 PM PDT 24
Finished Jun 25 06:54:08 PM PDT 24
Peak memory 254792 kb
Host smart-4252c497-f2cb-4f4d-94a7-eb1e27ca5036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937233467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1937233467
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.100624854
Short name T807
Test name
Test status
Simulation time 8578688191 ps
CPU time 11.53 seconds
Started Jun 25 06:52:32 PM PDT 24
Finished Jun 25 06:52:44 PM PDT 24
Peak memory 216892 kb
Host smart-8b24507c-8c2f-4d05-b888-0e8c58722884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100624854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.100624854
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2445914252
Short name T361
Test name
Test status
Simulation time 33877533397 ps
CPU time 22.95 seconds
Started Jun 25 06:52:29 PM PDT 24
Finished Jun 25 06:52:53 PM PDT 24
Peak memory 216804 kb
Host smart-9fb1cc79-8edb-4cdd-bbf9-40bea48cad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445914252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2445914252
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3083802695
Short name T436
Test name
Test status
Simulation time 1109388721 ps
CPU time 3.32 seconds
Started Jun 25 06:52:29 PM PDT 24
Finished Jun 25 06:52:33 PM PDT 24
Peak memory 216772 kb
Host smart-1c03ea0c-a49a-411a-8fc0-4aadf2aaaf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083802695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3083802695
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2496527430
Short name T818
Test name
Test status
Simulation time 14982874 ps
CPU time 0.7 seconds
Started Jun 25 06:52:33 PM PDT 24
Finished Jun 25 06:52:34 PM PDT 24
Peak memory 206036 kb
Host smart-f9f0efa0-44d9-4504-be12-c7ffe59625f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496527430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2496527430
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1102193698
Short name T780
Test name
Test status
Simulation time 225900388 ps
CPU time 2.74 seconds
Started Jun 25 06:52:33 PM PDT 24
Finished Jun 25 06:52:37 PM PDT 24
Peak memory 225012 kb
Host smart-68732c18-b9cd-4a65-831f-f48a81afc6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102193698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1102193698
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2061675266
Short name T342
Test name
Test status
Simulation time 62046357 ps
CPU time 0.7 seconds
Started Jun 25 06:52:44 PM PDT 24
Finished Jun 25 06:52:46 PM PDT 24
Peak memory 205832 kb
Host smart-0d89250a-600c-4872-a990-c7422ad6447d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061675266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2061675266
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.880668687
Short name T186
Test name
Test status
Simulation time 227611409 ps
CPU time 2.09 seconds
Started Jun 25 06:52:36 PM PDT 24
Finished Jun 25 06:52:38 PM PDT 24
Peak memory 224928 kb
Host smart-91dd4b06-c42c-4535-bc0e-e5734f728e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880668687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.880668687
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3200585696
Short name T430
Test name
Test status
Simulation time 54077188 ps
CPU time 0.78 seconds
Started Jun 25 06:52:37 PM PDT 24
Finished Jun 25 06:52:39 PM PDT 24
Peak memory 206972 kb
Host smart-a0b647db-9836-45c9-a6cf-8b50b81d10c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200585696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3200585696
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2927349230
Short name T546
Test name
Test status
Simulation time 6448488946 ps
CPU time 27.62 seconds
Started Jun 25 06:52:36 PM PDT 24
Finished Jun 25 06:53:04 PM PDT 24
Peak memory 236680 kb
Host smart-953f8188-0ee4-4df9-a3e2-9d70ac982de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927349230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2927349230
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.149791879
Short name T989
Test name
Test status
Simulation time 20699402269 ps
CPU time 94.96 seconds
Started Jun 25 06:52:46 PM PDT 24
Finished Jun 25 06:54:22 PM PDT 24
Peak memory 257544 kb
Host smart-f34a0632-63d0-4478-b46e-d531b79224f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149791879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.149791879
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2574004685
Short name T868
Test name
Test status
Simulation time 2712202549 ps
CPU time 31.41 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:53:18 PM PDT 24
Peak memory 239576 kb
Host smart-c4cdb0dc-ee01-4635-b9b8-936889f971de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574004685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2574004685
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3017394581
Short name T640
Test name
Test status
Simulation time 1736422673 ps
CPU time 34.11 seconds
Started Jun 25 06:52:38 PM PDT 24
Finished Jun 25 06:53:13 PM PDT 24
Peak memory 233140 kb
Host smart-729f6d64-ab7c-4c17-9326-0b924c2d3f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017394581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3017394581
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.864656834
Short name T665
Test name
Test status
Simulation time 520924663 ps
CPU time 4.5 seconds
Started Jun 25 06:52:37 PM PDT 24
Finished Jun 25 06:52:43 PM PDT 24
Peak memory 224824 kb
Host smart-abaf1704-d9a5-4f3c-9f98-204df2d161a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864656834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.864656834
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.16531678
Short name T942
Test name
Test status
Simulation time 2895819130 ps
CPU time 18.37 seconds
Started Jun 25 06:52:36 PM PDT 24
Finished Jun 25 06:52:56 PM PDT 24
Peak memory 249224 kb
Host smart-f0816c64-0ce2-47c0-af73-852aa729b821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16531678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.16531678
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.344355964
Short name T228
Test name
Test status
Simulation time 6149957573 ps
CPU time 14.84 seconds
Started Jun 25 06:52:38 PM PDT 24
Finished Jun 25 06:52:53 PM PDT 24
Peak memory 224988 kb
Host smart-8f551466-98c3-4a45-a8fd-035cbca28086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344355964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.344355964
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3332570995
Short name T946
Test name
Test status
Simulation time 3561687273 ps
CPU time 10.47 seconds
Started Jun 25 06:52:36 PM PDT 24
Finished Jun 25 06:52:48 PM PDT 24
Peak memory 233292 kb
Host smart-0464330c-c6e6-498e-a571-066d888f7ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332570995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3332570995
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1066052443
Short name T829
Test name
Test status
Simulation time 233889496 ps
CPU time 4.54 seconds
Started Jun 25 06:52:36 PM PDT 24
Finished Jun 25 06:52:41 PM PDT 24
Peak memory 223460 kb
Host smart-48a61178-2f1b-4c56-bbd2-ab4685734a4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1066052443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1066052443
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1398251356
Short name T569
Test name
Test status
Simulation time 239301038 ps
CPU time 1.21 seconds
Started Jun 25 06:52:47 PM PDT 24
Finished Jun 25 06:52:49 PM PDT 24
Peak memory 207496 kb
Host smart-e6f6a068-4daf-4fb9-a151-74d04f6608fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398251356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1398251356
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3380503966
Short name T515
Test name
Test status
Simulation time 3922714793 ps
CPU time 7.05 seconds
Started Jun 25 06:52:37 PM PDT 24
Finished Jun 25 06:52:45 PM PDT 24
Peak memory 216808 kb
Host smart-89ab4af6-9214-432b-a2f2-a0b300166821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380503966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3380503966
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3827554630
Short name T349
Test name
Test status
Simulation time 15226009 ps
CPU time 0.73 seconds
Started Jun 25 06:52:37 PM PDT 24
Finished Jun 25 06:52:39 PM PDT 24
Peak memory 206088 kb
Host smart-75293a06-f165-45e4-a6e4-c2c8906777ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827554630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3827554630
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1325256093
Short name T605
Test name
Test status
Simulation time 12333300 ps
CPU time 0.81 seconds
Started Jun 25 06:52:37 PM PDT 24
Finished Jun 25 06:52:39 PM PDT 24
Peak memory 207356 kb
Host smart-edea3b2e-e422-4627-9f0d-a4aa3439336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325256093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1325256093
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3234122199
Short name T824
Test name
Test status
Simulation time 329096580 ps
CPU time 0.88 seconds
Started Jun 25 06:52:38 PM PDT 24
Finished Jun 25 06:52:40 PM PDT 24
Peak memory 207508 kb
Host smart-92af8795-c13c-4ac1-bff3-e9621ce26660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234122199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3234122199
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2841682177
Short name T832
Test name
Test status
Simulation time 7611909958 ps
CPU time 12.96 seconds
Started Jun 25 06:52:36 PM PDT 24
Finished Jun 25 06:52:50 PM PDT 24
Peak memory 233144 kb
Host smart-8c06b6a7-2e09-4970-a4b9-e83f8ec2eddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841682177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2841682177
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3328766685
Short name T886
Test name
Test status
Simulation time 13676756 ps
CPU time 0.7 seconds
Started Jun 25 06:52:58 PM PDT 24
Finished Jun 25 06:53:00 PM PDT 24
Peak memory 205904 kb
Host smart-aa665a30-7d25-4396-ac8e-465d4f7bc883
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328766685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3328766685
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3763746051
Short name T912
Test name
Test status
Simulation time 116750371 ps
CPU time 4.44 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:52:50 PM PDT 24
Peak memory 233080 kb
Host smart-7f724f3f-7781-43ed-a768-47bff7ad29d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763746051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3763746051
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4007046108
Short name T502
Test name
Test status
Simulation time 98443035 ps
CPU time 0.78 seconds
Started Jun 25 06:52:44 PM PDT 24
Finished Jun 25 06:52:46 PM PDT 24
Peak memory 206992 kb
Host smart-d69b1faf-87f7-4454-9d89-e179d76da310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007046108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4007046108
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4005100879
Short name T693
Test name
Test status
Simulation time 1805292164 ps
CPU time 13.27 seconds
Started Jun 25 06:52:47 PM PDT 24
Finished Jun 25 06:53:01 PM PDT 24
Peak memory 235920 kb
Host smart-96c3c9d5-d7e2-46f9-b3ef-03733acb5a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005100879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4005100879
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1182313151
Short name T65
Test name
Test status
Simulation time 13115933106 ps
CPU time 120.57 seconds
Started Jun 25 06:52:49 PM PDT 24
Finished Jun 25 06:54:51 PM PDT 24
Peak memory 249720 kb
Host smart-352b8a82-e814-4b64-94ae-110ac12b9c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182313151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1182313151
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3626713400
Short name T236
Test name
Test status
Simulation time 2231431871 ps
CPU time 32.88 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:53:19 PM PDT 24
Peak memory 234384 kb
Host smart-cc921397-8f77-4a81-bc7e-bbcc2d3420cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626713400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3626713400
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.789641842
Short name T804
Test name
Test status
Simulation time 349927628 ps
CPU time 6.77 seconds
Started Jun 25 06:52:44 PM PDT 24
Finished Jun 25 06:52:52 PM PDT 24
Peak memory 224968 kb
Host smart-79d3718a-cf58-496b-b3cc-47d35497608b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789641842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.789641842
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.340469633
Short name T724
Test name
Test status
Simulation time 2821177387 ps
CPU time 35.11 seconds
Started Jun 25 06:52:51 PM PDT 24
Finished Jun 25 06:53:27 PM PDT 24
Peak memory 240564 kb
Host smart-2dd532c9-e4e6-4ba2-be97-371e26eb0b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340469633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.340469633
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4013585319
Short name T399
Test name
Test status
Simulation time 19203251142 ps
CPU time 13.78 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:53:00 PM PDT 24
Peak memory 233176 kb
Host smart-45da1595-61ec-4469-b4b9-fba19d6f9aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013585319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4013585319
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.738079736
Short name T279
Test name
Test status
Simulation time 498525669 ps
CPU time 2.93 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:52:49 PM PDT 24
Peak memory 224972 kb
Host smart-64d804f9-33e7-4ead-ab60-65924c4e9728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738079736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.738079736
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3066602716
Short name T467
Test name
Test status
Simulation time 7895793423 ps
CPU time 14.72 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:53:00 PM PDT 24
Peak memory 219324 kb
Host smart-fb82355e-cdf7-42f8-8697-a83540e514d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3066602716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3066602716
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.559430778
Short name T908
Test name
Test status
Simulation time 2488345387 ps
CPU time 29.3 seconds
Started Jun 25 06:52:47 PM PDT 24
Finished Jun 25 06:53:17 PM PDT 24
Peak memory 238580 kb
Host smart-758524ed-7577-45f8-9db1-a809fd2de9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559430778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.559430778
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1674820247
Short name T594
Test name
Test status
Simulation time 22057596 ps
CPU time 0.72 seconds
Started Jun 25 06:52:50 PM PDT 24
Finished Jun 25 06:52:52 PM PDT 24
Peak memory 206128 kb
Host smart-520e14c7-2928-4c1a-8e20-ed25aed03c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674820247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1674820247
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1118404268
Short name T460
Test name
Test status
Simulation time 9807004943 ps
CPU time 6.08 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:52:52 PM PDT 24
Peak memory 216824 kb
Host smart-7f73cb45-8b3e-436e-91d9-d2ac70c30322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118404268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1118404268
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1094489290
Short name T429
Test name
Test status
Simulation time 124387423 ps
CPU time 1.59 seconds
Started Jun 25 06:52:45 PM PDT 24
Finished Jun 25 06:52:48 PM PDT 24
Peak memory 216828 kb
Host smart-73f5be7f-d8e9-4f82-aed1-b801be09bfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094489290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1094489290
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.529395623
Short name T493
Test name
Test status
Simulation time 152728773 ps
CPU time 1.05 seconds
Started Jun 25 06:52:47 PM PDT 24
Finished Jun 25 06:52:49 PM PDT 24
Peak memory 206360 kb
Host smart-ffffbf13-604e-414a-939d-0229f763333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529395623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.529395623
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2031942507
Short name T382
Test name
Test status
Simulation time 443862091 ps
CPU time 2.24 seconds
Started Jun 25 06:52:44 PM PDT 24
Finished Jun 25 06:52:48 PM PDT 24
Peak memory 217068 kb
Host smart-bd9820b7-64bd-4f38-8400-5d7adfa92741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031942507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2031942507
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2748948736
Short name T496
Test name
Test status
Simulation time 96950655 ps
CPU time 0.74 seconds
Started Jun 25 06:53:00 PM PDT 24
Finished Jun 25 06:53:02 PM PDT 24
Peak memory 205900 kb
Host smart-87f14c5a-3dc1-4808-af0e-2ace307fb17f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748948736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2748948736
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.153912761
Short name T457
Test name
Test status
Simulation time 368826257 ps
CPU time 5.55 seconds
Started Jun 25 06:52:54 PM PDT 24
Finished Jun 25 06:53:01 PM PDT 24
Peak memory 225012 kb
Host smart-2a20873f-eae7-4e35-95cf-4a5f8b4c3a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153912761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.153912761
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1354219010
Short name T561
Test name
Test status
Simulation time 72259213 ps
CPU time 0.8 seconds
Started Jun 25 06:52:55 PM PDT 24
Finished Jun 25 06:52:57 PM PDT 24
Peak memory 207332 kb
Host smart-43a01ba2-a3f4-431e-b5ed-e19ca5a0c488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354219010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1354219010
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2931205625
Short name T873
Test name
Test status
Simulation time 20250528424 ps
CPU time 126.87 seconds
Started Jun 25 06:52:58 PM PDT 24
Finished Jun 25 06:55:06 PM PDT 24
Peak memory 249720 kb
Host smart-e5e34ad7-7daa-4446-be8d-478e639d54f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931205625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2931205625
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3832162707
Short name T350
Test name
Test status
Simulation time 65640212 ps
CPU time 3.19 seconds
Started Jun 25 06:52:54 PM PDT 24
Finished Jun 25 06:52:58 PM PDT 24
Peak memory 233212 kb
Host smart-d16648a4-e136-4cc6-bf4d-f0dc30d4942c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832162707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3832162707
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3134281576
Short name T820
Test name
Test status
Simulation time 57990028 ps
CPU time 2.24 seconds
Started Jun 25 06:52:52 PM PDT 24
Finished Jun 25 06:52:55 PM PDT 24
Peak memory 232980 kb
Host smart-17b7a56b-662d-4868-934f-b3ff0bafbaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134281576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3134281576
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2238664600
Short name T747
Test name
Test status
Simulation time 56538451479 ps
CPU time 136.89 seconds
Started Jun 25 06:52:57 PM PDT 24
Finished Jun 25 06:55:15 PM PDT 24
Peak memory 241376 kb
Host smart-2cc205a9-a0f2-43dd-bb9e-c0eff84b8353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238664600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2238664600
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4226423476
Short name T227
Test name
Test status
Simulation time 1372914734 ps
CPU time 7.15 seconds
Started Jun 25 06:52:52 PM PDT 24
Finished Jun 25 06:53:00 PM PDT 24
Peak memory 233000 kb
Host smart-d3e29968-d42f-47b7-81fb-ad975b2b4307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226423476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4226423476
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.280614033
Short name T898
Test name
Test status
Simulation time 1204049546 ps
CPU time 4.49 seconds
Started Jun 25 06:52:57 PM PDT 24
Finished Jun 25 06:53:02 PM PDT 24
Peak memory 225008 kb
Host smart-46850230-6f55-49fc-896f-3356ff62b9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280614033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.280614033
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.235666782
Short name T553
Test name
Test status
Simulation time 955084964 ps
CPU time 12.47 seconds
Started Jun 25 06:52:58 PM PDT 24
Finished Jun 25 06:53:11 PM PDT 24
Peak memory 221080 kb
Host smart-7dcba433-354c-474a-87fb-adb78f3ba400
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=235666782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.235666782
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4277254226
Short name T202
Test name
Test status
Simulation time 92543251084 ps
CPU time 138.13 seconds
Started Jun 25 06:53:02 PM PDT 24
Finished Jun 25 06:55:21 PM PDT 24
Peak memory 272856 kb
Host smart-39148d19-fe58-4523-bef6-88626a3a993b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277254226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4277254226
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.280537046
Short name T465
Test name
Test status
Simulation time 1244765687 ps
CPU time 13.13 seconds
Started Jun 25 06:52:51 PM PDT 24
Finished Jun 25 06:53:05 PM PDT 24
Peak memory 216760 kb
Host smart-881a12ee-8575-4821-9688-94496c6b2266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280537046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.280537046
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4247101708
Short name T608
Test name
Test status
Simulation time 7660849430 ps
CPU time 3.78 seconds
Started Jun 25 06:52:51 PM PDT 24
Finished Jun 25 06:52:56 PM PDT 24
Peak memory 216844 kb
Host smart-9662ee99-841a-4e40-b9a6-fd49e33a7980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247101708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4247101708
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3272779756
Short name T645
Test name
Test status
Simulation time 114347441 ps
CPU time 1.69 seconds
Started Jun 25 06:52:58 PM PDT 24
Finished Jun 25 06:53:00 PM PDT 24
Peak memory 208632 kb
Host smart-ad526de5-dae0-4a0b-83ae-2cf53e430b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272779756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3272779756
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4025014298
Short name T31
Test name
Test status
Simulation time 132467482 ps
CPU time 0.9 seconds
Started Jun 25 06:52:59 PM PDT 24
Finished Jun 25 06:53:00 PM PDT 24
Peak memory 206388 kb
Host smart-699d8eaf-ec50-435f-b08d-2d978c133f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025014298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4025014298
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1886957300
Short name T579
Test name
Test status
Simulation time 470159301 ps
CPU time 2.97 seconds
Started Jun 25 06:52:52 PM PDT 24
Finished Jun 25 06:52:56 PM PDT 24
Peak memory 224952 kb
Host smart-04b1268b-f3cf-4740-8c9e-a4a86dc94ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886957300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1886957300
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.342183251
Short name T711
Test name
Test status
Simulation time 14113543 ps
CPU time 0.75 seconds
Started Jun 25 06:53:09 PM PDT 24
Finished Jun 25 06:53:11 PM PDT 24
Peak memory 206212 kb
Host smart-3e5d3393-d272-4aad-b46a-438bf44d37e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342183251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.342183251
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2069499772
Short name T604
Test name
Test status
Simulation time 20172935006 ps
CPU time 34.46 seconds
Started Jun 25 06:53:01 PM PDT 24
Finished Jun 25 06:53:37 PM PDT 24
Peak memory 224892 kb
Host smart-eb967865-f493-490b-ae55-7f7e51b9f18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069499772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2069499772
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.198652929
Short name T373
Test name
Test status
Simulation time 16747281 ps
CPU time 0.8 seconds
Started Jun 25 06:53:01 PM PDT 24
Finished Jun 25 06:53:03 PM PDT 24
Peak memory 206992 kb
Host smart-451962ad-e6a0-4e4d-9ef3-fed244b382f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198652929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.198652929
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.4158251241
Short name T191
Test name
Test status
Simulation time 25350347388 ps
CPU time 93.61 seconds
Started Jun 25 06:53:02 PM PDT 24
Finished Jun 25 06:54:37 PM PDT 24
Peak memory 249688 kb
Host smart-3bd83888-6716-4c92-92b5-606903feb628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158251241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.4158251241
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.127125586
Short name T538
Test name
Test status
Simulation time 60057694936 ps
CPU time 84.1 seconds
Started Jun 25 06:53:06 PM PDT 24
Finished Jun 25 06:54:31 PM PDT 24
Peak memory 256744 kb
Host smart-69530374-064c-4faa-8c10-5134e8adb08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127125586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.127125586
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.597681884
Short name T313
Test name
Test status
Simulation time 76418257186 ps
CPU time 406.47 seconds
Started Jun 25 06:53:01 PM PDT 24
Finished Jun 25 06:59:49 PM PDT 24
Peak memory 273164 kb
Host smart-e935c83d-c3e6-462f-a363-51797b1ce982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597681884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.597681884
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1163743893
Short name T734
Test name
Test status
Simulation time 786049334 ps
CPU time 15.65 seconds
Started Jun 25 06:53:01 PM PDT 24
Finished Jun 25 06:53:17 PM PDT 24
Peak memory 233136 kb
Host smart-d51e6fe6-944a-4313-ac34-95aac683d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163743893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1163743893
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3136383180
Short name T233
Test name
Test status
Simulation time 1010864785 ps
CPU time 11.04 seconds
Started Jun 25 06:53:02 PM PDT 24
Finished Jun 25 06:53:14 PM PDT 24
Peak memory 224964 kb
Host smart-504d879a-8ddd-4e99-b3fb-1dc584d7b07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136383180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3136383180
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3532445837
Short name T480
Test name
Test status
Simulation time 63149456 ps
CPU time 3.07 seconds
Started Jun 25 06:53:00 PM PDT 24
Finished Jun 25 06:53:04 PM PDT 24
Peak memory 228248 kb
Host smart-d6a48406-3502-414e-ade2-59ffff4b1756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532445837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3532445837
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3406156090
Short name T913
Test name
Test status
Simulation time 3812257720 ps
CPU time 6.6 seconds
Started Jun 25 06:53:01 PM PDT 24
Finished Jun 25 06:53:08 PM PDT 24
Peak memory 225000 kb
Host smart-356e170e-6938-4132-bda7-d7174986f494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406156090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3406156090
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2208256739
Short name T845
Test name
Test status
Simulation time 95473446 ps
CPU time 2.35 seconds
Started Jun 25 06:53:02 PM PDT 24
Finished Jun 25 06:53:05 PM PDT 24
Peak memory 224928 kb
Host smart-d7a08236-e019-4b70-9a81-e7f8986c3e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208256739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2208256739
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3237740348
Short name T139
Test name
Test status
Simulation time 3833985120 ps
CPU time 16.46 seconds
Started Jun 25 06:53:02 PM PDT 24
Finished Jun 25 06:53:19 PM PDT 24
Peak memory 221084 kb
Host smart-aa624b15-5484-4446-b7c5-ee416f1b14c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3237740348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3237740348
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2244361246
Short name T625
Test name
Test status
Simulation time 26036342575 ps
CPU time 201.2 seconds
Started Jun 25 06:53:11 PM PDT 24
Finished Jun 25 06:56:33 PM PDT 24
Peak memory 272820 kb
Host smart-6a8eef2d-1ae6-4eab-b5c2-1e549711784c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244361246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2244361246
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3197510562
Short name T959
Test name
Test status
Simulation time 6639883249 ps
CPU time 15.32 seconds
Started Jun 25 06:53:01 PM PDT 24
Finished Jun 25 06:53:18 PM PDT 24
Peak memory 217220 kb
Host smart-6b71f85f-eec9-4439-85c5-48294ca35de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197510562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3197510562
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.699028677
Short name T595
Test name
Test status
Simulation time 4658253550 ps
CPU time 15.93 seconds
Started Jun 25 06:53:03 PM PDT 24
Finished Jun 25 06:53:19 PM PDT 24
Peak memory 216892 kb
Host smart-b6e95b43-5fef-43fc-9478-21067c68ed4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699028677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.699028677
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1702271566
Short name T340
Test name
Test status
Simulation time 198789793 ps
CPU time 3.19 seconds
Started Jun 25 06:53:03 PM PDT 24
Finished Jun 25 06:53:07 PM PDT 24
Peak memory 216756 kb
Host smart-dda0333d-ee27-4aab-8dae-6a168340f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702271566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1702271566
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.150679389
Short name T650
Test name
Test status
Simulation time 28343725 ps
CPU time 0.85 seconds
Started Jun 25 06:53:02 PM PDT 24
Finished Jun 25 06:53:04 PM PDT 24
Peak memory 206584 kb
Host smart-0b74c677-274c-40f7-8679-7ded49be9f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150679389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.150679389
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2250196405
Short name T731
Test name
Test status
Simulation time 3811661151 ps
CPU time 10.84 seconds
Started Jun 25 06:53:03 PM PDT 24
Finished Jun 25 06:53:15 PM PDT 24
Peak memory 233248 kb
Host smart-9976addd-c60d-41c8-bd9f-94fc31794582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250196405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2250196405
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3613764393
Short name T612
Test name
Test status
Simulation time 46602317 ps
CPU time 0.7 seconds
Started Jun 25 06:53:17 PM PDT 24
Finished Jun 25 06:53:20 PM PDT 24
Peak memory 206232 kb
Host smart-875a4a69-1e8c-4aeb-96f4-86b47c85774d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613764393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3613764393
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1150652020
Short name T688
Test name
Test status
Simulation time 108716806 ps
CPU time 2.61 seconds
Started Jun 25 06:53:10 PM PDT 24
Finished Jun 25 06:53:14 PM PDT 24
Peak memory 232860 kb
Host smart-29f51452-d9fc-4302-8bc5-998769ed3c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150652020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1150652020
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.716758432
Short name T345
Test name
Test status
Simulation time 34859396 ps
CPU time 0.74 seconds
Started Jun 25 06:53:08 PM PDT 24
Finished Jun 25 06:53:10 PM PDT 24
Peak memory 205908 kb
Host smart-667bb6cb-bede-41cf-9ca8-bf47f4a3aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716758432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.716758432
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3947100502
Short name T524
Test name
Test status
Simulation time 34740426866 ps
CPU time 235.34 seconds
Started Jun 25 06:53:15 PM PDT 24
Finished Jun 25 06:57:11 PM PDT 24
Peak memory 263136 kb
Host smart-abf53c12-fd53-4719-a9d0-58eb2ad593f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947100502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3947100502
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1794161837
Short name T798
Test name
Test status
Simulation time 34161927589 ps
CPU time 302.61 seconds
Started Jun 25 06:53:18 PM PDT 24
Finished Jun 25 06:58:22 PM PDT 24
Peak memory 249708 kb
Host smart-fa0433c8-7a28-4e59-8bb8-eb0ea879c4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794161837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1794161837
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.673782406
Short name T847
Test name
Test status
Simulation time 6209730516 ps
CPU time 62.16 seconds
Started Jun 25 06:53:16 PM PDT 24
Finished Jun 25 06:54:19 PM PDT 24
Peak memory 249700 kb
Host smart-e3a47571-44a4-4511-9f77-98a0093add43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673782406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.673782406
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4138270670
Short name T568
Test name
Test status
Simulation time 615359527 ps
CPU time 4.64 seconds
Started Jun 25 06:53:15 PM PDT 24
Finished Jun 25 06:53:20 PM PDT 24
Peak memory 233204 kb
Host smart-33df2566-067f-4ee6-86f8-a104e0d11c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138270670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4138270670
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4082749909
Short name T80
Test name
Test status
Simulation time 2046319633 ps
CPU time 20.91 seconds
Started Jun 25 06:53:11 PM PDT 24
Finished Jun 25 06:53:33 PM PDT 24
Peak memory 224952 kb
Host smart-3b5a2c2b-8c0e-4e6e-bb1c-0c76754cf076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082749909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4082749909
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1953770619
Short name T491
Test name
Test status
Simulation time 5746831626 ps
CPU time 15.88 seconds
Started Jun 25 06:53:15 PM PDT 24
Finished Jun 25 06:53:32 PM PDT 24
Peak memory 227996 kb
Host smart-ea75ef10-1f23-4f46-b230-e4830c62edc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953770619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1953770619
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1861010233
Short name T752
Test name
Test status
Simulation time 63447591 ps
CPU time 2.64 seconds
Started Jun 25 06:53:15 PM PDT 24
Finished Jun 25 06:53:18 PM PDT 24
Peak memory 232932 kb
Host smart-d4dc83ac-1f60-4f98-84c4-0db7bf7c1a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861010233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1861010233
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3489187653
Short name T865
Test name
Test status
Simulation time 1691562381 ps
CPU time 3.52 seconds
Started Jun 25 06:53:09 PM PDT 24
Finished Jun 25 06:53:13 PM PDT 24
Peak memory 233184 kb
Host smart-3275b9d9-7e6c-4b8b-9f0f-3ed340158782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489187653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3489187653
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.4055934901
Short name T461
Test name
Test status
Simulation time 3915126737 ps
CPU time 6.86 seconds
Started Jun 25 06:53:14 PM PDT 24
Finished Jun 25 06:53:22 PM PDT 24
Peak memory 219856 kb
Host smart-46e9d4b7-276e-43a3-a6cd-1555c4919673
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4055934901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.4055934901
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.481753324
Short name T470
Test name
Test status
Simulation time 162479713 ps
CPU time 0.96 seconds
Started Jun 25 06:53:18 PM PDT 24
Finished Jun 25 06:53:20 PM PDT 24
Peak memory 207412 kb
Host smart-0047e3c7-f627-4076-acde-af0e1da0e665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481753324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.481753324
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3370502005
Short name T661
Test name
Test status
Simulation time 10491431968 ps
CPU time 27.33 seconds
Started Jun 25 06:53:09 PM PDT 24
Finished Jun 25 06:53:37 PM PDT 24
Peak memory 220644 kb
Host smart-296a96ff-8206-4c4b-bedf-710410d613f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370502005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3370502005
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1375130310
Short name T368
Test name
Test status
Simulation time 1377412459 ps
CPU time 9.3 seconds
Started Jun 25 06:53:08 PM PDT 24
Finished Jun 25 06:53:18 PM PDT 24
Peak memory 216756 kb
Host smart-66dc4402-e979-43ff-aa14-568ddf4a5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375130310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1375130310
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4105075135
Short name T979
Test name
Test status
Simulation time 71681993 ps
CPU time 0.85 seconds
Started Jun 25 06:53:09 PM PDT 24
Finished Jun 25 06:53:10 PM PDT 24
Peak memory 206368 kb
Host smart-f1f920cb-f76a-4242-9ea3-beb0b31f61e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105075135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4105075135
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3855853413
Short name T353
Test name
Test status
Simulation time 175451373 ps
CPU time 0.94 seconds
Started Jun 25 06:53:09 PM PDT 24
Finished Jun 25 06:53:11 PM PDT 24
Peak memory 206356 kb
Host smart-a08810fb-7a55-4fce-bb6f-5713a3ea9004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855853413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3855853413
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3727064023
Short name T710
Test name
Test status
Simulation time 16337619813 ps
CPU time 13.1 seconds
Started Jun 25 06:53:10 PM PDT 24
Finished Jun 25 06:53:24 PM PDT 24
Peak memory 225012 kb
Host smart-883f8c0b-dfd3-4352-97b1-605a2c73b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727064023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3727064023
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3487147352
Short name T600
Test name
Test status
Simulation time 22364157 ps
CPU time 0.77 seconds
Started Jun 25 06:53:27 PM PDT 24
Finished Jun 25 06:53:29 PM PDT 24
Peak memory 204908 kb
Host smart-8a59b067-6a6c-4d14-8f6b-718321fb3535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487147352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3487147352
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.149220225
Short name T703
Test name
Test status
Simulation time 488432383 ps
CPU time 3.63 seconds
Started Jun 25 06:53:24 PM PDT 24
Finished Jun 25 06:53:28 PM PDT 24
Peak memory 224936 kb
Host smart-777881b6-62a9-4251-9c87-ed7655d5ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149220225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.149220225
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3539881632
Short name T934
Test name
Test status
Simulation time 27733244 ps
CPU time 0.8 seconds
Started Jun 25 06:53:18 PM PDT 24
Finished Jun 25 06:53:20 PM PDT 24
Peak memory 206996 kb
Host smart-1ceaec52-aaf3-4f14-a24f-242191e1d585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539881632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3539881632
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.433219087
Short name T35
Test name
Test status
Simulation time 9873938551 ps
CPU time 27.99 seconds
Started Jun 25 06:53:25 PM PDT 24
Finished Jun 25 06:53:54 PM PDT 24
Peak memory 241452 kb
Host smart-5dac1843-9af3-4658-91da-3568d6596ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433219087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.433219087
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.487137096
Short name T874
Test name
Test status
Simulation time 62278787637 ps
CPU time 612.34 seconds
Started Jun 25 06:53:23 PM PDT 24
Finished Jun 25 07:03:36 PM PDT 24
Peak memory 263624 kb
Host smart-53bb8da5-7a75-44dc-9969-a9c1c34b47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487137096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.487137096
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2764797516
Short name T876
Test name
Test status
Simulation time 66005931163 ps
CPU time 139.48 seconds
Started Jun 25 06:53:24 PM PDT 24
Finished Jun 25 06:55:45 PM PDT 24
Peak memory 249720 kb
Host smart-16f18ab8-c93b-4284-b23a-0f1b0370fdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764797516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2764797516
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2018911694
Short name T321
Test name
Test status
Simulation time 18271918001 ps
CPU time 54.32 seconds
Started Jun 25 06:53:18 PM PDT 24
Finished Jun 25 06:54:14 PM PDT 24
Peak memory 233240 kb
Host smart-a20c556c-948d-4f94-8e22-a8b76585d5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018911694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2018911694
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2972452159
Short name T222
Test name
Test status
Simulation time 288530100 ps
CPU time 5.31 seconds
Started Jun 25 06:53:17 PM PDT 24
Finished Jun 25 06:53:24 PM PDT 24
Peak memory 233212 kb
Host smart-910db14b-9f16-4372-9246-f465db1b4879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972452159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2972452159
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4090065336
Short name T659
Test name
Test status
Simulation time 20477301384 ps
CPU time 45.94 seconds
Started Jun 25 06:53:17 PM PDT 24
Finished Jun 25 06:54:04 PM PDT 24
Peak memory 241232 kb
Host smart-ef55f75d-078b-488a-85c3-a02beaad677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090065336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4090065336
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3908285206
Short name T288
Test name
Test status
Simulation time 864980593 ps
CPU time 6.82 seconds
Started Jun 25 06:53:18 PM PDT 24
Finished Jun 25 06:53:27 PM PDT 24
Peak memory 233156 kb
Host smart-935dc27d-0117-49be-87d2-6ec70bbc4c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908285206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3908285206
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3628176181
Short name T268
Test name
Test status
Simulation time 79464932 ps
CPU time 2.33 seconds
Started Jun 25 06:53:17 PM PDT 24
Finished Jun 25 06:53:20 PM PDT 24
Peak memory 224972 kb
Host smart-d40287ff-afdf-4530-a65e-925b777c4875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628176181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3628176181
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1752584082
Short name T407
Test name
Test status
Simulation time 2875213295 ps
CPU time 7.29 seconds
Started Jun 25 06:53:17 PM PDT 24
Finished Jun 25 06:53:26 PM PDT 24
Peak memory 222828 kb
Host smart-8c87c174-d523-4c5c-9a55-b4f756ddacb6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1752584082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1752584082
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.890466211
Short name T224
Test name
Test status
Simulation time 120486579430 ps
CPU time 380.31 seconds
Started Jun 25 06:53:30 PM PDT 24
Finished Jun 25 06:59:51 PM PDT 24
Peak memory 255100 kb
Host smart-9187fcd3-d518-4dc2-818c-f1d336e4d6d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890466211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.890466211
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2826932153
Short name T67
Test name
Test status
Simulation time 42802839 ps
CPU time 0.72 seconds
Started Jun 25 06:53:17 PM PDT 24
Finished Jun 25 06:53:20 PM PDT 24
Peak memory 206104 kb
Host smart-84d227d5-94f3-4785-9edd-1ec8e9894421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826932153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2826932153
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2136414552
Short name T423
Test name
Test status
Simulation time 7347131605 ps
CPU time 4.45 seconds
Started Jun 25 06:53:17 PM PDT 24
Finished Jun 25 06:53:24 PM PDT 24
Peak memory 216884 kb
Host smart-6c0e2557-c3fd-4338-86fc-f8a4436eb788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136414552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2136414552
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1625214215
Short name T337
Test name
Test status
Simulation time 31468034 ps
CPU time 0.81 seconds
Started Jun 25 06:53:16 PM PDT 24
Finished Jun 25 06:53:18 PM PDT 24
Peak memory 206212 kb
Host smart-9ba2ddfe-a0b0-4c08-a444-759247349d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625214215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1625214215
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.116624529
Short name T78
Test name
Test status
Simulation time 77398162 ps
CPU time 0.79 seconds
Started Jun 25 06:53:18 PM PDT 24
Finished Jun 25 06:53:20 PM PDT 24
Peak memory 206476 kb
Host smart-fa7a9704-dda7-450c-8195-ceeb2dbc6513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116624529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.116624529
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1749852854
Short name T797
Test name
Test status
Simulation time 3398384650 ps
CPU time 11.82 seconds
Started Jun 25 06:53:16 PM PDT 24
Finished Jun 25 06:53:29 PM PDT 24
Peak memory 225028 kb
Host smart-d787e907-b81d-45a2-87cf-06ad45fae846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749852854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1749852854
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.427067572
Short name T365
Test name
Test status
Simulation time 41014262 ps
CPU time 0.7 seconds
Started Jun 25 06:53:30 PM PDT 24
Finished Jun 25 06:53:31 PM PDT 24
Peak memory 205868 kb
Host smart-187e56a8-5696-4ec3-ad06-2a42fd4728ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427067572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.427067572
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2652100253
Short name T974
Test name
Test status
Simulation time 299979866 ps
CPU time 3.78 seconds
Started Jun 25 06:53:24 PM PDT 24
Finished Jun 25 06:53:29 PM PDT 24
Peak memory 233116 kb
Host smart-8ec9e35d-1a55-4d88-9c40-96ac212be4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652100253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2652100253
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.13515544
Short name T402
Test name
Test status
Simulation time 24576664 ps
CPU time 0.8 seconds
Started Jun 25 06:53:25 PM PDT 24
Finished Jun 25 06:53:27 PM PDT 24
Peak memory 206832 kb
Host smart-3b605ceb-9f17-42d0-9fdd-370f9ef0c4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13515544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.13515544
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.171842831
Short name T311
Test name
Test status
Simulation time 22473454712 ps
CPU time 156.87 seconds
Started Jun 25 06:53:32 PM PDT 24
Finished Jun 25 06:56:10 PM PDT 24
Peak memory 252536 kb
Host smart-a36ff79a-1cef-4ee0-9bbf-e93b84801da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171842831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.171842831
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1446673173
Short name T507
Test name
Test status
Simulation time 17702177128 ps
CPU time 73.01 seconds
Started Jun 25 06:53:30 PM PDT 24
Finished Jun 25 06:54:44 PM PDT 24
Peak memory 252136 kb
Host smart-c8dc7e00-b339-4e4b-8861-bacd6b15b28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446673173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1446673173
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2099502394
Short name T334
Test name
Test status
Simulation time 83095007239 ps
CPU time 96.26 seconds
Started Jun 25 06:53:30 PM PDT 24
Finished Jun 25 06:55:08 PM PDT 24
Peak memory 257384 kb
Host smart-dffc3d35-3bf7-4247-a034-e1409ef4b678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099502394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2099502394
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2536442235
Short name T357
Test name
Test status
Simulation time 45001755 ps
CPU time 2.76 seconds
Started Jun 25 06:53:30 PM PDT 24
Finished Jun 25 06:53:34 PM PDT 24
Peak memory 233196 kb
Host smart-799a93be-7768-4a5f-83dc-5b3d2593adf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536442235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2536442235
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.742849389
Short name T260
Test name
Test status
Simulation time 1173001467 ps
CPU time 15.14 seconds
Started Jun 25 06:53:26 PM PDT 24
Finished Jun 25 06:53:42 PM PDT 24
Peak memory 225072 kb
Host smart-03940170-ab02-43b9-aaaf-0e97e88335d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742849389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.742849389
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1374203002
Short name T252
Test name
Test status
Simulation time 88079207 ps
CPU time 4.32 seconds
Started Jun 25 06:53:24 PM PDT 24
Finished Jun 25 06:53:30 PM PDT 24
Peak memory 233192 kb
Host smart-9e8011b8-2835-4eca-a202-b6cfdf7d4a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374203002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1374203002
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1012716239
Short name T464
Test name
Test status
Simulation time 114436378 ps
CPU time 2.42 seconds
Started Jun 25 06:53:22 PM PDT 24
Finished Jun 25 06:53:25 PM PDT 24
Peak memory 232960 kb
Host smart-92e89a0a-c43f-4bc8-9dba-2d01f0c0c2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012716239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1012716239
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.659849977
Short name T702
Test name
Test status
Simulation time 621216888 ps
CPU time 3.34 seconds
Started Jun 25 06:53:27 PM PDT 24
Finished Jun 25 06:53:32 PM PDT 24
Peak memory 224540 kb
Host smart-a741eee1-480a-4798-8c79-7515864677c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659849977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.659849977
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1659706817
Short name T628
Test name
Test status
Simulation time 1154036262 ps
CPU time 10.44 seconds
Started Jun 25 06:53:32 PM PDT 24
Finished Jun 25 06:53:43 PM PDT 24
Peak memory 221056 kb
Host smart-423f928d-33ae-4048-8382-31fd8e5f97cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1659706817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1659706817
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3787061230
Short name T34
Test name
Test status
Simulation time 56510690230 ps
CPU time 358.47 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:59:31 PM PDT 24
Peak memory 262948 kb
Host smart-65f68d05-1d3a-449b-bda8-612ee37be813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787061230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3787061230
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2294929331
Short name T455
Test name
Test status
Simulation time 33701423181 ps
CPU time 14.63 seconds
Started Jun 25 06:53:30 PM PDT 24
Finished Jun 25 06:53:46 PM PDT 24
Peak memory 216876 kb
Host smart-7efe0f9a-18a6-4495-b111-1bdab0e241df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294929331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2294929331
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3614898823
Short name T76
Test name
Test status
Simulation time 6674270217 ps
CPU time 9.83 seconds
Started Jun 25 06:53:30 PM PDT 24
Finished Jun 25 06:53:41 PM PDT 24
Peak memory 216872 kb
Host smart-1b633c4c-414a-4155-8790-f84eae610f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614898823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3614898823
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.611637091
Short name T509
Test name
Test status
Simulation time 201494255 ps
CPU time 2.16 seconds
Started Jun 25 06:53:24 PM PDT 24
Finished Jun 25 06:53:28 PM PDT 24
Peak memory 216712 kb
Host smart-fa946ac1-5a65-4dcc-ba77-c21f61b34dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611637091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.611637091
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.369735762
Short name T705
Test name
Test status
Simulation time 158197584 ps
CPU time 0.88 seconds
Started Jun 25 06:53:25 PM PDT 24
Finished Jun 25 06:53:27 PM PDT 24
Peak memory 206356 kb
Host smart-9ed90d9a-494a-4237-af30-140da23783d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369735762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.369735762
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.796495075
Short name T242
Test name
Test status
Simulation time 40776003083 ps
CPU time 29.91 seconds
Started Jun 25 06:53:23 PM PDT 24
Finished Jun 25 06:53:53 PM PDT 24
Peak memory 240320 kb
Host smart-3d8b4a3d-cbea-40e4-b820-5855f956c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796495075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.796495075
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3686962500
Short name T344
Test name
Test status
Simulation time 101636489 ps
CPU time 0.72 seconds
Started Jun 25 06:53:40 PM PDT 24
Finished Jun 25 06:53:42 PM PDT 24
Peak memory 205336 kb
Host smart-4c430146-56fe-4970-9e29-8141aae5b29b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686962500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3686962500
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1705237503
Short name T963
Test name
Test status
Simulation time 34606521 ps
CPU time 2.14 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:53:34 PM PDT 24
Peak memory 224936 kb
Host smart-6b3beef5-8b9e-48c2-aba7-5aca8d8c0c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705237503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1705237503
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3825186528
Short name T652
Test name
Test status
Simulation time 14822757 ps
CPU time 0.86 seconds
Started Jun 25 06:53:32 PM PDT 24
Finished Jun 25 06:53:34 PM PDT 24
Peak memory 206988 kb
Host smart-f09f090a-b7c6-48c4-a326-d820c5d634d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825186528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3825186528
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.375785411
Short name T796
Test name
Test status
Simulation time 70643606975 ps
CPU time 126 seconds
Started Jun 25 06:53:38 PM PDT 24
Finished Jun 25 06:55:44 PM PDT 24
Peak memory 249580 kb
Host smart-86edb0d1-9b37-4806-ab4c-0a3ccf98b935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375785411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.375785411
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1757364873
Short name T306
Test name
Test status
Simulation time 86070125865 ps
CPU time 197.23 seconds
Started Jun 25 06:53:38 PM PDT 24
Finished Jun 25 06:56:57 PM PDT 24
Peak memory 256604 kb
Host smart-e5919895-865e-4b6e-8431-6c32cc3c4634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757364873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1757364873
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2650619782
Short name T212
Test name
Test status
Simulation time 66668964550 ps
CPU time 212.66 seconds
Started Jun 25 06:53:39 PM PDT 24
Finished Jun 25 06:57:12 PM PDT 24
Peak memory 274284 kb
Host smart-20c209e3-9d24-42eb-8888-c4e113e1c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650619782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2650619782
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.245129322
Short name T754
Test name
Test status
Simulation time 108420597 ps
CPU time 5.01 seconds
Started Jun 25 06:53:32 PM PDT 24
Finished Jun 25 06:53:38 PM PDT 24
Peak memory 240688 kb
Host smart-1361f7ec-3c26-4f34-a2e9-bc2f5c83d49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245129322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.245129322
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3272997239
Short name T85
Test name
Test status
Simulation time 1068515676 ps
CPU time 6.37 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:53:38 PM PDT 24
Peak memory 233200 kb
Host smart-7876ca62-a7ea-468b-beaa-d4336e836b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272997239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3272997239
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.982613471
Short name T714
Test name
Test status
Simulation time 5238002238 ps
CPU time 45.05 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:54:17 PM PDT 24
Peak memory 241344 kb
Host smart-1aa0c7ef-b6e6-4f3c-a247-e27d360a74c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982613471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.982613471
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3196610185
Short name T893
Test name
Test status
Simulation time 1445741684 ps
CPU time 4.13 seconds
Started Jun 25 06:53:32 PM PDT 24
Finished Jun 25 06:53:37 PM PDT 24
Peak memory 225012 kb
Host smart-0046d96a-11bc-4079-8a41-6ad437f76138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196610185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3196610185
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.68342626
Short name T586
Test name
Test status
Simulation time 4412088806 ps
CPU time 11.06 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:53:43 PM PDT 24
Peak memory 224964 kb
Host smart-a62d327a-adb1-4b1a-b36c-7b200861eb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68342626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.68342626
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1352381136
Short name T486
Test name
Test status
Simulation time 5203038296 ps
CPU time 10.69 seconds
Started Jun 25 06:53:32 PM PDT 24
Finished Jun 25 06:53:44 PM PDT 24
Peak memory 223628 kb
Host smart-a57e2b9d-cd6e-42b6-bb74-1c1421b069ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1352381136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1352381136
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4165630848
Short name T20
Test name
Test status
Simulation time 85649126 ps
CPU time 0.92 seconds
Started Jun 25 06:53:38 PM PDT 24
Finished Jun 25 06:53:39 PM PDT 24
Peak memory 205928 kb
Host smart-ca11f3ee-b901-4139-b151-57825463c9cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165630848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4165630848
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.843706253
Short name T508
Test name
Test status
Simulation time 7220227408 ps
CPU time 45.79 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:54:18 PM PDT 24
Peak memory 216868 kb
Host smart-67e777dd-25a4-49a4-869b-e4ea55be6f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843706253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.843706253
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1942688973
Short name T633
Test name
Test status
Simulation time 781051171 ps
CPU time 1.95 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:53:34 PM PDT 24
Peak memory 207624 kb
Host smart-cd267d87-785f-4f53-a8e6-edac92c0a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942688973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1942688973
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.84055891
Short name T984
Test name
Test status
Simulation time 233649201 ps
CPU time 2.28 seconds
Started Jun 25 06:53:32 PM PDT 24
Finished Jun 25 06:53:35 PM PDT 24
Peak memory 216740 kb
Host smart-6442bed2-8ac9-437d-bd2a-954968ceaa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84055891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.84055891
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3031135271
Short name T669
Test name
Test status
Simulation time 32823098 ps
CPU time 0.72 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:53:33 PM PDT 24
Peak memory 206376 kb
Host smart-1a24447d-9e4e-4ee5-86d5-18070f058c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031135271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3031135271
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1979259092
Short name T956
Test name
Test status
Simulation time 3653755441 ps
CPU time 16.37 seconds
Started Jun 25 06:53:31 PM PDT 24
Finished Jun 25 06:53:49 PM PDT 24
Peak memory 249260 kb
Host smart-b882900b-9fe5-47fa-82df-348b30c091a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979259092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1979259092
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2434450476
Short name T500
Test name
Test status
Simulation time 22758525 ps
CPU time 0.73 seconds
Started Jun 25 06:46:32 PM PDT 24
Finished Jun 25 06:46:34 PM PDT 24
Peak memory 205312 kb
Host smart-ee026e08-5962-4ac7-ac28-c9229b777a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434450476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
434450476
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2514827322
Short name T808
Test name
Test status
Simulation time 377634927 ps
CPU time 2.44 seconds
Started Jun 25 06:46:32 PM PDT 24
Finished Jun 25 06:46:36 PM PDT 24
Peak memory 224352 kb
Host smart-e88062d8-05a8-4c26-9358-fb816c430786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514827322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2514827322
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3323287212
Short name T385
Test name
Test status
Simulation time 20781545 ps
CPU time 0.79 seconds
Started Jun 25 06:46:24 PM PDT 24
Finished Jun 25 06:46:25 PM PDT 24
Peak memory 206988 kb
Host smart-3323ce91-6df2-4214-b067-2ba8b726a739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323287212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3323287212
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3331786971
Short name T282
Test name
Test status
Simulation time 7616057588 ps
CPU time 35.22 seconds
Started Jun 25 06:46:33 PM PDT 24
Finished Jun 25 06:47:09 PM PDT 24
Peak memory 240904 kb
Host smart-7f5bc55c-42f8-40d0-9868-69fc3d1cfaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331786971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3331786971
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2276860174
Short name T57
Test name
Test status
Simulation time 138456422301 ps
CPU time 174.41 seconds
Started Jun 25 06:46:34 PM PDT 24
Finished Jun 25 06:49:29 PM PDT 24
Peak memory 252796 kb
Host smart-095c3c5b-b50f-40d7-a255-92b3504bd6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276860174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2276860174
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3734200605
Short name T264
Test name
Test status
Simulation time 29389805409 ps
CPU time 129.51 seconds
Started Jun 25 06:46:32 PM PDT 24
Finished Jun 25 06:48:43 PM PDT 24
Peak memory 249916 kb
Host smart-6a98d882-17f2-4216-ad71-9fbb8d10587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734200605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3734200605
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.635279090
Short name T322
Test name
Test status
Simulation time 801457759 ps
CPU time 15.42 seconds
Started Jun 25 06:46:34 PM PDT 24
Finished Jun 25 06:46:50 PM PDT 24
Peak memory 236864 kb
Host smart-6d543581-c9ef-47f5-a041-2aed1c016ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635279090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.635279090
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4113465468
Short name T736
Test name
Test status
Simulation time 1489196003 ps
CPU time 5.37 seconds
Started Jun 25 06:46:25 PM PDT 24
Finished Jun 25 06:46:32 PM PDT 24
Peak memory 233164 kb
Host smart-1ba749c6-e7b0-4a7c-b749-154659104bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113465468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4113465468
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.305395514
Short name T262
Test name
Test status
Simulation time 558302210 ps
CPU time 2.81 seconds
Started Jun 25 06:46:24 PM PDT 24
Finished Jun 25 06:46:28 PM PDT 24
Peak memory 233200 kb
Host smart-287dd7d0-965c-4ef9-b228-fcbef499e5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305395514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.305395514
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3506391488
Short name T969
Test name
Test status
Simulation time 25601944 ps
CPU time 1.13 seconds
Started Jun 25 06:46:24 PM PDT 24
Finished Jun 25 06:46:27 PM PDT 24
Peak memory 217176 kb
Host smart-7a3c413b-9364-485d-bba6-f9f9e233d1c7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506391488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3506391488
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2479293417
Short name T532
Test name
Test status
Simulation time 164875940 ps
CPU time 2.71 seconds
Started Jun 25 06:46:24 PM PDT 24
Finished Jun 25 06:46:29 PM PDT 24
Peak memory 224904 kb
Host smart-73c9506e-18e5-4627-9eff-58c6831819ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479293417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2479293417
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1666033158
Short name T196
Test name
Test status
Simulation time 249116198348 ps
CPU time 38.6 seconds
Started Jun 25 06:46:25 PM PDT 24
Finished Jun 25 06:47:05 PM PDT 24
Peak memory 233256 kb
Host smart-8f14751c-b21b-4b4d-a728-3522b33d95f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666033158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1666033158
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3544109599
Short name T651
Test name
Test status
Simulation time 722615758 ps
CPU time 4.05 seconds
Started Jun 25 06:46:32 PM PDT 24
Finished Jun 25 06:46:37 PM PDT 24
Peak memory 223120 kb
Host smart-60b157e8-105b-4405-85b6-842cfe1579b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3544109599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3544109599
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2527604952
Short name T229
Test name
Test status
Simulation time 10513795620 ps
CPU time 221 seconds
Started Jun 25 06:46:32 PM PDT 24
Finished Jun 25 06:50:14 PM PDT 24
Peak memory 269284 kb
Host smart-a4496dd3-61b5-4965-95ef-9ae9ca600db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527604952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2527604952
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1387430324
Short name T336
Test name
Test status
Simulation time 8154121528 ps
CPU time 26.64 seconds
Started Jun 25 06:46:25 PM PDT 24
Finished Jun 25 06:46:53 PM PDT 24
Peak memory 216780 kb
Host smart-4030de7b-5246-4bcf-96af-d636b8e70f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387430324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1387430324
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1162770293
Short name T596
Test name
Test status
Simulation time 663461047 ps
CPU time 2.08 seconds
Started Jun 25 06:46:25 PM PDT 24
Finished Jun 25 06:46:29 PM PDT 24
Peak memory 216556 kb
Host smart-2eddc846-fc30-4dae-8fbd-5cbf3d590107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162770293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1162770293
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2242245542
Short name T729
Test name
Test status
Simulation time 183280640 ps
CPU time 3.12 seconds
Started Jun 25 06:46:24 PM PDT 24
Finished Jun 25 06:46:28 PM PDT 24
Peak memory 216712 kb
Host smart-ed28bd35-2e60-479b-a46e-ac31483d00ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242245542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2242245542
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2758367740
Short name T366
Test name
Test status
Simulation time 16484558 ps
CPU time 0.77 seconds
Started Jun 25 06:46:24 PM PDT 24
Finished Jun 25 06:46:27 PM PDT 24
Peak memory 206368 kb
Host smart-f163c91e-06ee-4edd-9d20-d518544ddfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758367740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2758367740
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3610063880
Short name T281
Test name
Test status
Simulation time 10013815626 ps
CPU time 9.25 seconds
Started Jun 25 06:46:26 PM PDT 24
Finished Jun 25 06:46:37 PM PDT 24
Peak memory 233208 kb
Host smart-83933b1c-401c-400c-85b6-1d8bd2b98a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610063880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3610063880
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2228740013
Short name T620
Test name
Test status
Simulation time 15704066 ps
CPU time 0.75 seconds
Started Jun 25 06:46:50 PM PDT 24
Finished Jun 25 06:46:52 PM PDT 24
Peak memory 206244 kb
Host smart-e4042771-ce8e-46d4-a5f4-9910ce972e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228740013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
228740013
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3371938970
Short name T671
Test name
Test status
Simulation time 5617852644 ps
CPU time 11.76 seconds
Started Jun 25 06:46:41 PM PDT 24
Finished Jun 25 06:46:55 PM PDT 24
Peak memory 225024 kb
Host smart-d70351a3-156c-4977-a9d9-4068bc9734fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371938970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3371938970
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2084909438
Short name T621
Test name
Test status
Simulation time 23618707 ps
CPU time 0.78 seconds
Started Jun 25 06:46:32 PM PDT 24
Finished Jun 25 06:46:34 PM PDT 24
Peak memory 207340 kb
Host smart-c726a72f-dd3f-424f-a1ee-2d5e2235499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084909438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2084909438
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2527954881
Short name T192
Test name
Test status
Simulation time 31121972994 ps
CPU time 35.96 seconds
Started Jun 25 06:46:41 PM PDT 24
Finished Jun 25 06:47:18 PM PDT 24
Peak memory 224928 kb
Host smart-3708980f-3711-4cf4-a9a7-ac86dc4e04f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527954881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2527954881
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3144768708
Short name T763
Test name
Test status
Simulation time 801070931 ps
CPU time 16.55 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:46:58 PM PDT 24
Peak memory 225072 kb
Host smart-e50ac268-b973-4c2b-9536-c7e20d56b0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144768708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3144768708
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.368214736
Short name T469
Test name
Test status
Simulation time 161835696 ps
CPU time 2.68 seconds
Started Jun 25 06:46:39 PM PDT 24
Finished Jun 25 06:46:42 PM PDT 24
Peak memory 233112 kb
Host smart-3f584a3e-9061-4d97-8edc-0c541cac567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368214736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.368214736
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.711517962
Short name T84
Test name
Test status
Simulation time 1912341752 ps
CPU time 6.55 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:46:48 PM PDT 24
Peak memory 224968 kb
Host smart-c82abbb4-deeb-4c28-b208-0971eeb45c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711517962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.711517962
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3632652517
Short name T937
Test name
Test status
Simulation time 5997886387 ps
CPU time 46.97 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:47:29 PM PDT 24
Peak memory 233208 kb
Host smart-2fdebb95-2561-486d-80ed-a09084a6b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632652517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3632652517
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3955220439
Short name T951
Test name
Test status
Simulation time 25584879 ps
CPU time 1.07 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:46:43 PM PDT 24
Peak memory 217152 kb
Host smart-9fe63458-d9a0-4cab-ab24-fb004a1a5c4c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955220439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3955220439
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3564499137
Short name T685
Test name
Test status
Simulation time 234904850 ps
CPU time 2.19 seconds
Started Jun 25 06:46:39 PM PDT 24
Finished Jun 25 06:46:43 PM PDT 24
Peak memory 224228 kb
Host smart-92b66fb1-37fd-4ab5-8052-959b034396fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564499137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3564499137
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3582181589
Short name T858
Test name
Test status
Simulation time 281931554 ps
CPU time 6.19 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:46:48 PM PDT 24
Peak memory 233196 kb
Host smart-24324634-0dba-4cfe-b7ad-e3d37d01a13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582181589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3582181589
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.444383733
Short name T856
Test name
Test status
Simulation time 742267167 ps
CPU time 4.73 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:46:46 PM PDT 24
Peak memory 223644 kb
Host smart-73a9b811-8bc5-4ca1-8da1-b7c743fb26f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=444383733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.444383733
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1117552550
Short name T392
Test name
Test status
Simulation time 20000567 ps
CPU time 0.76 seconds
Started Jun 25 06:46:39 PM PDT 24
Finished Jun 25 06:46:41 PM PDT 24
Peak memory 206088 kb
Host smart-ea8d2ab6-9bc1-455f-8953-9d5c4da3faf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117552550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1117552550
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.999349784
Short name T776
Test name
Test status
Simulation time 1826952623 ps
CPU time 10.38 seconds
Started Jun 25 06:46:41 PM PDT 24
Finished Jun 25 06:46:53 PM PDT 24
Peak memory 216788 kb
Host smart-1c247d96-3684-452b-aae4-6852d5995356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999349784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.999349784
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.377960374
Short name T680
Test name
Test status
Simulation time 128495008 ps
CPU time 0.81 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:46:42 PM PDT 24
Peak memory 206356 kb
Host smart-75103b11-34c4-4b75-bd28-56760c069d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377960374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.377960374
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3935672658
Short name T393
Test name
Test status
Simulation time 79907655 ps
CPU time 0.76 seconds
Started Jun 25 06:46:41 PM PDT 24
Finished Jun 25 06:46:43 PM PDT 24
Peak memory 206224 kb
Host smart-8be38568-fa72-4c45-a7f0-cb5ca6e5c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935672658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3935672658
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.464682722
Short name T795
Test name
Test status
Simulation time 41947711879 ps
CPU time 29.97 seconds
Started Jun 25 06:46:40 PM PDT 24
Finished Jun 25 06:47:12 PM PDT 24
Peak memory 241008 kb
Host smart-2b51d295-5fa6-4ae3-88f6-7ca03852bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464682722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.464682722
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3483661721
Short name T759
Test name
Test status
Simulation time 14078947 ps
CPU time 0.71 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:47:01 PM PDT 24
Peak memory 205884 kb
Host smart-0bce63a7-c614-4dbe-8c8c-eeaf3aad297e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483661721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
483661721
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2310355574
Short name T272
Test name
Test status
Simulation time 3147021575 ps
CPU time 9.03 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:47:09 PM PDT 24
Peak memory 225060 kb
Host smart-faf53d31-173f-42d0-958f-1f4a8d4d90b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310355574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2310355574
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3036449884
Short name T58
Test name
Test status
Simulation time 74802624 ps
CPU time 0.79 seconds
Started Jun 25 06:46:48 PM PDT 24
Finished Jun 25 06:46:50 PM PDT 24
Peak memory 206288 kb
Host smart-e81b544b-bfc7-4a2f-8a66-47768c20fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036449884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3036449884
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.4028365574
Short name T193
Test name
Test status
Simulation time 75582949685 ps
CPU time 271.36 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:51:32 PM PDT 24
Peak memory 249684 kb
Host smart-d36a2ba0-1721-4ceb-bb0f-98bad53102bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028365574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.4028365574
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.608401373
Short name T834
Test name
Test status
Simulation time 8310094433 ps
CPU time 60.94 seconds
Started Jun 25 06:47:01 PM PDT 24
Finished Jun 25 06:48:03 PM PDT 24
Peak memory 249732 kb
Host smart-e992911c-4106-4888-9af7-ba11d5b96639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608401373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.608401373
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.764404141
Short name T767
Test name
Test status
Simulation time 12720028542 ps
CPU time 104.33 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:48:45 PM PDT 24
Peak memory 249756 kb
Host smart-fb59c7f7-b109-43c4-9f9a-04607cd7b4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764404141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
764404141
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3945471217
Short name T458
Test name
Test status
Simulation time 44849553 ps
CPU time 2.94 seconds
Started Jun 25 06:46:58 PM PDT 24
Finished Jun 25 06:47:02 PM PDT 24
Peak memory 224948 kb
Host smart-61c5938c-1322-4b87-b8b4-35f9e7c1f0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945471217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3945471217
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.467432910
Short name T270
Test name
Test status
Simulation time 3593779407 ps
CPU time 10.47 seconds
Started Jun 25 06:46:49 PM PDT 24
Finished Jun 25 06:47:00 PM PDT 24
Peak memory 233276 kb
Host smart-fb8a493a-55b9-4102-858d-5f465b2bb8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467432910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.467432910
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.518508236
Short name T213
Test name
Test status
Simulation time 6604302861 ps
CPU time 64.91 seconds
Started Jun 25 06:46:50 PM PDT 24
Finished Jun 25 06:47:56 PM PDT 24
Peak memory 233224 kb
Host smart-a1074ac3-06a1-4ffd-b68f-2abeaf5166af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518508236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.518508236
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1509075350
Short name T666
Test name
Test status
Simulation time 124501502 ps
CPU time 1.14 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:47:01 PM PDT 24
Peak memory 217156 kb
Host smart-7fe95dce-7d9a-4c33-9c32-7f2244fb1bd5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509075350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1509075350
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2395033936
Short name T985
Test name
Test status
Simulation time 82071105 ps
CPU time 2.79 seconds
Started Jun 25 06:46:50 PM PDT 24
Finished Jun 25 06:46:55 PM PDT 24
Peak memory 233164 kb
Host smart-e1d2554b-38f3-44a5-8683-d8860be5e1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395033936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2395033936
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3247595124
Short name T12
Test name
Test status
Simulation time 4170594768 ps
CPU time 13.57 seconds
Started Jun 25 06:46:49 PM PDT 24
Finished Jun 25 06:47:04 PM PDT 24
Peak memory 233224 kb
Host smart-f914d1fd-a225-49e0-a0ce-e33b0e1ac267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247595124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3247595124
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1866109299
Short name T840
Test name
Test status
Simulation time 795359344 ps
CPU time 7.89 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:47:07 PM PDT 24
Peak memory 222776 kb
Host smart-bd7c64de-6861-4661-b083-342caa04d789
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1866109299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1866109299
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3712426063
Short name T267
Test name
Test status
Simulation time 18543716870 ps
CPU time 174.88 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:49:55 PM PDT 24
Peak memory 257132 kb
Host smart-0a70a1e4-066a-45ea-835e-4e25a2b87cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712426063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3712426063
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.659876048
Short name T477
Test name
Test status
Simulation time 1354206859 ps
CPU time 7.94 seconds
Started Jun 25 06:46:50 PM PDT 24
Finished Jun 25 06:46:59 PM PDT 24
Peak memory 216904 kb
Host smart-c883868f-d7d2-4c21-a801-36dab07fb184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659876048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.659876048
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.855347075
Short name T630
Test name
Test status
Simulation time 741049180 ps
CPU time 2.87 seconds
Started Jun 25 06:47:00 PM PDT 24
Finished Jun 25 06:47:04 PM PDT 24
Peak memory 216740 kb
Host smart-08c4aa07-53c8-47b2-8ff5-7eb5ffaf3519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855347075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.855347075
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3996838505
Short name T694
Test name
Test status
Simulation time 138113072 ps
CPU time 2.03 seconds
Started Jun 25 06:46:50 PM PDT 24
Finished Jun 25 06:46:54 PM PDT 24
Peak memory 216584 kb
Host smart-254bb61a-dac0-4d84-a285-96d729e10246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996838505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3996838505
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1438047416
Short name T453
Test name
Test status
Simulation time 44333922 ps
CPU time 0.77 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:47:01 PM PDT 24
Peak memory 206236 kb
Host smart-3781ab8b-0f1a-4350-b635-2355929d723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438047416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1438047416
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2858525105
Short name T846
Test name
Test status
Simulation time 107500922 ps
CPU time 2.66 seconds
Started Jun 25 06:47:00 PM PDT 24
Finished Jun 25 06:47:04 PM PDT 24
Peak memory 224736 kb
Host smart-0d30d87c-ca71-4a12-84ed-0076c6af4678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858525105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2858525105
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3679395637
Short name T387
Test name
Test status
Simulation time 23140956 ps
CPU time 0.72 seconds
Started Jun 25 06:47:14 PM PDT 24
Finished Jun 25 06:47:16 PM PDT 24
Peak memory 205740 kb
Host smart-ab035d7d-b27f-43a8-ba5c-c1ae30468eb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679395637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
679395637
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1543915824
Short name T83
Test name
Test status
Simulation time 13093179633 ps
CPU time 32.6 seconds
Started Jun 25 06:47:15 PM PDT 24
Finished Jun 25 06:47:48 PM PDT 24
Peak memory 233280 kb
Host smart-f6277b49-e099-4ae0-899e-a0227adb9928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543915824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1543915824
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3798095418
Short name T557
Test name
Test status
Simulation time 207729040 ps
CPU time 0.78 seconds
Started Jun 25 06:46:58 PM PDT 24
Finished Jun 25 06:47:00 PM PDT 24
Peak memory 206268 kb
Host smart-a5ae2da8-af13-4828-9c41-8114606f52c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798095418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3798095418
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2110464123
Short name T11
Test name
Test status
Simulation time 27413758684 ps
CPU time 12.17 seconds
Started Jun 25 06:47:15 PM PDT 24
Finished Jun 25 06:47:28 PM PDT 24
Peak memory 225076 kb
Host smart-da829727-93b8-4ebd-8876-6cc53ca723f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110464123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2110464123
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2243842422
Short name T166
Test name
Test status
Simulation time 274735819730 ps
CPU time 330.57 seconds
Started Jun 25 06:47:13 PM PDT 24
Finished Jun 25 06:52:45 PM PDT 24
Peak memory 257892 kb
Host smart-c5bc0514-3f72-4042-9c0d-0d5a3064238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243842422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2243842422
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.316204870
Short name T241
Test name
Test status
Simulation time 6599376438 ps
CPU time 58.64 seconds
Started Jun 25 06:47:14 PM PDT 24
Finished Jun 25 06:48:13 PM PDT 24
Peak memory 225064 kb
Host smart-3c9dc1bc-6b2d-440b-b4df-cb4dc5b45abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316204870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
316204870
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2708060297
Short name T364
Test name
Test status
Simulation time 146685973 ps
CPU time 4.03 seconds
Started Jun 25 06:47:03 PM PDT 24
Finished Jun 25 06:47:08 PM PDT 24
Peak memory 233204 kb
Host smart-f965226d-741c-4bc7-8034-d95443cf43fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708060297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2708060297
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.567566934
Short name T238
Test name
Test status
Simulation time 20511564143 ps
CPU time 180.59 seconds
Started Jun 25 06:47:06 PM PDT 24
Finished Jun 25 06:50:07 PM PDT 24
Peak memory 233208 kb
Host smart-061de5ce-43ed-4d9c-a302-ffee89c0adf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567566934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.567566934
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.21185586
Short name T708
Test name
Test status
Simulation time 104923018 ps
CPU time 1.1 seconds
Started Jun 25 06:46:59 PM PDT 24
Finished Jun 25 06:47:02 PM PDT 24
Peak memory 217164 kb
Host smart-b5fc2510-1d20-4be5-9083-44ead2d6b2d6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.21185586
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3700975526
Short name T243
Test name
Test status
Simulation time 1356969674 ps
CPU time 8 seconds
Started Jun 25 06:47:05 PM PDT 24
Finished Jun 25 06:47:14 PM PDT 24
Peak memory 241372 kb
Host smart-ab8ba7aa-af1f-4774-a6ef-faf6d8c623c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700975526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3700975526
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3229203874
Short name T903
Test name
Test status
Simulation time 407431726 ps
CPU time 2.42 seconds
Started Jun 25 06:47:04 PM PDT 24
Finished Jun 25 06:47:07 PM PDT 24
Peak memory 224940 kb
Host smart-aab4031f-f8d8-4d2f-9cd4-60bb3ec6ff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229203874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3229203874
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2199012722
Short name T415
Test name
Test status
Simulation time 392757775 ps
CPU time 3.59 seconds
Started Jun 25 06:47:15 PM PDT 24
Finished Jun 25 06:47:20 PM PDT 24
Peak memory 221036 kb
Host smart-b7bd4b4e-4ef4-4c89-a228-656c820dee57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2199012722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2199012722
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2146106779
Short name T910
Test name
Test status
Simulation time 291852370 ps
CPU time 3.69 seconds
Started Jun 25 06:47:06 PM PDT 24
Finished Jun 25 06:47:11 PM PDT 24
Peak memory 216740 kb
Host smart-c90fbc0a-9e2a-49b8-9484-63bb08e6f575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146106779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2146106779
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3668049433
Short name T489
Test name
Test status
Simulation time 742967055 ps
CPU time 4.77 seconds
Started Jun 25 06:47:07 PM PDT 24
Finished Jun 25 06:47:12 PM PDT 24
Peak memory 216816 kb
Host smart-56b35a9a-a46f-44ee-ae75-5bddfde1cbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668049433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3668049433
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.556069905
Short name T957
Test name
Test status
Simulation time 956736457 ps
CPU time 6.66 seconds
Started Jun 25 06:47:07 PM PDT 24
Finished Jun 25 06:47:15 PM PDT 24
Peak memory 216640 kb
Host smart-fdce82de-535b-4041-abcc-3fbc878e0839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556069905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.556069905
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2727535226
Short name T401
Test name
Test status
Simulation time 91224492 ps
CPU time 0.77 seconds
Started Jun 25 06:47:05 PM PDT 24
Finished Jun 25 06:47:07 PM PDT 24
Peak memory 206380 kb
Host smart-2a06c6ec-c48c-43e6-a1a8-8b565c31dc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727535226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2727535226
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4062589712
Short name T678
Test name
Test status
Simulation time 105573231 ps
CPU time 2.42 seconds
Started Jun 25 06:47:06 PM PDT 24
Finished Jun 25 06:47:09 PM PDT 24
Peak memory 224976 kb
Host smart-14dc21aa-6724-4b47-ab4b-5eb1fcfeb0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062589712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4062589712
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.615047273
Short name T905
Test name
Test status
Simulation time 69893582 ps
CPU time 0.73 seconds
Started Jun 25 06:47:30 PM PDT 24
Finished Jun 25 06:47:34 PM PDT 24
Peak memory 205860 kb
Host smart-cb21b81b-cc94-48c7-8c48-03ed91241fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615047273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.615047273
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2908077407
Short name T674
Test name
Test status
Simulation time 1172374339 ps
CPU time 6.75 seconds
Started Jun 25 06:47:21 PM PDT 24
Finished Jun 25 06:47:30 PM PDT 24
Peak memory 233080 kb
Host smart-7e52ed59-f2c8-4b7c-9b83-accc21c6bfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908077407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2908077407
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1541119696
Short name T431
Test name
Test status
Simulation time 52491677 ps
CPU time 0.78 seconds
Started Jun 25 06:47:15 PM PDT 24
Finished Jun 25 06:47:17 PM PDT 24
Peak memory 207328 kb
Host smart-2351c5d6-ca17-49c0-92ee-a3c71c053dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541119696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1541119696
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.4067622073
Short name T965
Test name
Test status
Simulation time 73555371 ps
CPU time 0.87 seconds
Started Jun 25 06:47:22 PM PDT 24
Finished Jun 25 06:47:25 PM PDT 24
Peak memory 216512 kb
Host smart-955cc383-ac0b-4006-bcea-2d786b29a3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067622073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.4067622073
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3914355375
Short name T686
Test name
Test status
Simulation time 2634453467 ps
CPU time 66.65 seconds
Started Jun 25 06:47:22 PM PDT 24
Finished Jun 25 06:48:30 PM PDT 24
Peak memory 252524 kb
Host smart-12e0a347-8b81-4933-8767-0a0bb29633c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914355375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3914355375
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2260902187
Short name T683
Test name
Test status
Simulation time 39678352070 ps
CPU time 291.95 seconds
Started Jun 25 06:47:22 PM PDT 24
Finished Jun 25 06:52:16 PM PDT 24
Peak memory 254204 kb
Host smart-2c6825bd-a602-4504-b149-3817fcf26757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260902187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2260902187
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1438293667
Short name T63
Test name
Test status
Simulation time 1291026465 ps
CPU time 7.78 seconds
Started Jun 25 06:47:22 PM PDT 24
Finished Jun 25 06:47:32 PM PDT 24
Peak memory 224972 kb
Host smart-5cf25776-53a8-4692-9068-497aa1f84eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438293667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1438293667
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3690970777
Short name T439
Test name
Test status
Simulation time 351547199 ps
CPU time 3.11 seconds
Started Jun 25 06:47:22 PM PDT 24
Finished Jun 25 06:47:27 PM PDT 24
Peak memory 224944 kb
Host smart-833459bd-0d4f-4a21-88d7-159f504dd850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690970777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3690970777
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3684401038
Short name T79
Test name
Test status
Simulation time 1907468976 ps
CPU time 8.59 seconds
Started Jun 25 06:47:21 PM PDT 24
Finished Jun 25 06:47:31 PM PDT 24
Peak memory 240888 kb
Host smart-7e632e01-734a-43a8-b52f-18f28d522023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684401038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3684401038
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2447977881
Short name T38
Test name
Test status
Simulation time 52852966 ps
CPU time 1.08 seconds
Started Jun 25 06:47:16 PM PDT 24
Finished Jun 25 06:47:18 PM PDT 24
Peak memory 217408 kb
Host smart-db0886ee-ccaf-4aab-8084-f3eb06bb55ba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447977881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2447977881
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3141349952
Short name T298
Test name
Test status
Simulation time 945999012 ps
CPU time 2.71 seconds
Started Jun 25 06:47:22 PM PDT 24
Finished Jun 25 06:47:27 PM PDT 24
Peak memory 233160 kb
Host smart-957e9cb0-ebd9-4e26-8bce-9e0fccd7e263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141349952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3141349952
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1970172915
Short name T698
Test name
Test status
Simulation time 1339407429 ps
CPU time 4.72 seconds
Started Jun 25 06:47:20 PM PDT 24
Finished Jun 25 06:47:27 PM PDT 24
Peak memory 233192 kb
Host smart-f826cdaf-597c-406d-8c83-313839005d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970172915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1970172915
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1147339335
Short name T641
Test name
Test status
Simulation time 278985292 ps
CPU time 6.21 seconds
Started Jun 25 06:47:21 PM PDT 24
Finished Jun 25 06:47:29 PM PDT 24
Peak memory 223476 kb
Host smart-9f9d2671-25e9-472c-9584-2a7a45413112
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1147339335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1147339335
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.122458087
Short name T583
Test name
Test status
Simulation time 4331290118 ps
CPU time 62.78 seconds
Started Jun 25 06:47:21 PM PDT 24
Finished Jun 25 06:48:25 PM PDT 24
Peak memory 256468 kb
Host smart-ee95129b-a6ca-40df-8979-ced6b3b1027a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122458087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.122458087
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1243478378
Short name T559
Test name
Test status
Simulation time 4625597474 ps
CPU time 23.87 seconds
Started Jun 25 06:47:14 PM PDT 24
Finished Jun 25 06:47:39 PM PDT 24
Peak memory 216736 kb
Host smart-15640ef2-ef36-4df9-bc19-8178d72ad02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243478378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1243478378
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2778616120
Short name T624
Test name
Test status
Simulation time 4524554351 ps
CPU time 12.32 seconds
Started Jun 25 06:47:13 PM PDT 24
Finished Jun 25 06:47:27 PM PDT 24
Peak memory 216816 kb
Host smart-4dfec76c-c546-4a3b-948f-5926cee82c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778616120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2778616120
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3996216424
Short name T932
Test name
Test status
Simulation time 247893415 ps
CPU time 6.29 seconds
Started Jun 25 06:47:21 PM PDT 24
Finished Jun 25 06:47:29 PM PDT 24
Peak memory 216744 kb
Host smart-fae1eb48-5cee-49d2-bd42-8fabd4500d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996216424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3996216424
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.86916668
Short name T889
Test name
Test status
Simulation time 76104207 ps
CPU time 0.91 seconds
Started Jun 25 06:47:16 PM PDT 24
Finished Jun 25 06:47:18 PM PDT 24
Peak memory 206364 kb
Host smart-79f31350-dfd7-412c-90d7-fb076228ba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86916668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.86916668
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2290272821
Short name T210
Test name
Test status
Simulation time 1650286373 ps
CPU time 8.3 seconds
Started Jun 25 06:47:23 PM PDT 24
Finished Jun 25 06:47:33 PM PDT 24
Peak memory 233160 kb
Host smart-be96aa1d-d980-47ca-8605-c984a8726e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290272821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2290272821
Directory /workspace/9.spi_device_upload/latest
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