Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3347604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3841566

1

T1

26

T2

890

T3

45674

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3972846	1			T1	1		T2	9		T3	72607
values[0x0]	1606861	1			T1	18		T2	451		T3	23784
values[0x1]	1609463	1			T1	16		T2	438		T3	23459

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2372302	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4816868

1

T1

28

T2

892

T3

69033

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28611	1			T3	376		T5	24		T6	457
valid_sources[0x01]	30849	1			T1	1		T3	387		T5	22
valid_sources[0x02]	26912	1			T3	246		T5	11		T6	557
valid_sources[0x03]	26550	1			T3	671		T5	18		T6	499
valid_sources[0x04]	33757	1			T3	744		T4	1		T5	15
valid_sources[0x05]	27416	1			T3	294		T5	15		T6	500
valid_sources[0x06]	31593	1			T3	592		T5	24		T6	453
valid_sources[0x07]	24987	1			T3	831		T5	31		T6	33
valid_sources[0x08]	28747	1			T3	498		T5	11		T6	571
valid_sources[0x09]	26879	1			T3	665		T5	20		T6	55
valid_sources[0x0a]	26702	1			T3	254		T5	36		T6	402
valid_sources[0x0b]	26622	1			T1	6		T3	209		T5	26
valid_sources[0x0c]	29869	1			T3	521		T5	30		T6	831
valid_sources[0x0d]	26791	1			T3	338		T5	22		T6	551
valid_sources[0x0e]	26867	1			T3	599		T5	12		T6	185
valid_sources[0x0f]	27325	1			T3	570		T5	34		T6	291
valid_sources[0x10]	28334	1			T3	193		T5	21		T6	996
valid_sources[0x11]	28007	1			T3	615		T5	17		T6	333
valid_sources[0x12]	25797	1			T3	937		T5	22		T6	218
valid_sources[0x13]	24426	1			T1	1		T3	292		T5	16
valid_sources[0x14]	26423	1			T3	474		T5	20		T6	354
valid_sources[0x15]	28940	1			T3	290		T5	23		T6	843
valid_sources[0x16]	27072	1			T3	558		T5	17		T6	334
valid_sources[0x17]	26987	1			T1	2		T3	287		T5	38
valid_sources[0x18]	27785	1			T3	251		T5	11		T6	219
valid_sources[0x19]	29432	1			T3	491		T5	11		T6	262
valid_sources[0x1a]	29626	1			T1	1		T3	415		T5	15
valid_sources[0x1b]	27192	1			T3	363		T5	22		T6	479
valid_sources[0x1c]	28936	1			T3	1110		T5	22		T6	434
valid_sources[0x1d]	29336	1			T1	1		T3	405		T5	39
valid_sources[0x1e]	26045	1			T3	378		T5	26		T6	158
valid_sources[0x1f]	29110	1			T3	562		T5	29		T6	178
valid_sources[0x20]	28005	1			T3	561		T4	4		T5	30
valid_sources[0x21]	26424	1			T3	358		T5	22		T6	358
valid_sources[0x22]	30985	1			T3	579		T5	24		T6	390
valid_sources[0x23]	28078	1			T3	356		T5	28		T6	632
valid_sources[0x24]	26487	1			T3	514		T5	15		T6	112
valid_sources[0x25]	24279	1			T3	375		T5	17		T6	113
valid_sources[0x26]	27425	1			T3	307		T5	16		T6	388
valid_sources[0x27]	25593	1			T3	271		T5	8		T6	235
valid_sources[0x28]	28422	1			T3	305		T5	26		T6	231
valid_sources[0x29]	29440	1			T3	431		T5	26		T6	220
valid_sources[0x2a]	28694	1			T3	467		T5	19		T6	772
valid_sources[0x2b]	28830	1			T3	376		T5	10		T6	1139
valid_sources[0x2c]	25409	1			T3	287		T5	25		T6	413
valid_sources[0x2d]	26539	1			T3	490		T5	28		T6	340
valid_sources[0x2e]	29166	1			T3	393		T5	25		T6	371
valid_sources[0x2f]	30534	1			T3	584		T5	33		T6	373
valid_sources[0x30]	26249	1			T1	2		T3	446		T5	23
valid_sources[0x31]	28433	1			T1	5		T3	290		T5	24
valid_sources[0x32]	25187	1			T2	898		T3	197		T5	20
valid_sources[0x33]	24748	1			T3	456		T5	18		T6	224
valid_sources[0x34]	30671	1			T3	1164		T5	20		T6	652
valid_sources[0x35]	31283	1			T3	558		T4	4		T5	13
valid_sources[0x36]	28109	1			T3	663		T5	34		T6	484
valid_sources[0x37]	27783	1			T3	476		T5	12		T6	357
valid_sources[0x38]	30460	1			T3	288		T5	34		T6	382
valid_sources[0x39]	25302	1			T3	417		T5	18		T6	182
valid_sources[0x3a]	28025	1			T3	814		T5	17		T6	564
valid_sources[0x3b]	26644	1			T3	517		T5	11		T6	78
valid_sources[0x3c]	26104	1			T3	544		T5	22		T6	213
valid_sources[0x3d]	25286	1			T3	354		T5	13		T6	345
valid_sources[0x3e]	26696	1			T3	328		T5	26		T6	389
valid_sources[0x3f]	27783	1			T3	499		T5	21		T6	1932
valid_sources[0x40]	30061	1			T3	177		T5	36		T6	383
valid_sources[0x41]	29443	1			T3	660		T5	27		T6	343
valid_sources[0x42]	27559	1			T3	304		T5	19		T6	91
valid_sources[0x43]	27272	1			T3	1097		T5	26		T6	350
valid_sources[0x44]	26728	1			T1	1		T3	437		T5	28
valid_sources[0x45]	29631	1			T3	586		T5	21		T6	229
valid_sources[0x46]	28024	1			T3	515		T5	27		T6	2001
valid_sources[0x47]	24776	1			T3	464		T4	2		T5	31
valid_sources[0x48]	30439	1			T3	200		T5	23		T6	884
valid_sources[0x49]	29899	1			T3	381		T5	22		T6	689
valid_sources[0x4a]	29458	1			T3	481		T5	12		T6	767
valid_sources[0x4b]	27152	1			T3	170		T5	13		T6	577
valid_sources[0x4c]	29681	1			T3	433		T5	20		T6	88
valid_sources[0x4d]	25029	1			T1	2		T3	836		T5	16
valid_sources[0x4e]	30848	1			T3	449		T5	15		T6	338
valid_sources[0x4f]	27675	1			T3	282		T5	18		T6	546
valid_sources[0x50]	27165	1			T3	530		T5	25		T6	327
valid_sources[0x51]	31428	1			T3	362		T5	32		T6	307
valid_sources[0x52]	28650	1			T3	331		T5	24		T6	794
valid_sources[0x53]	30136	1			T3	175		T5	15		T6	272
valid_sources[0x54]	27834	1			T3	741		T5	18		T6	881
valid_sources[0x55]	26196	1			T3	369		T5	17		T6	205
valid_sources[0x56]	25956	1			T3	246		T5	17		T6	653
valid_sources[0x57]	32037	1			T3	629		T5	10		T6	725
valid_sources[0x58]	27346	1			T3	396		T5	25		T6	369
valid_sources[0x59]	26598	1			T3	665		T4	1		T5	27
valid_sources[0x5a]	25944	1			T3	253		T5	15		T6	703
valid_sources[0x5b]	25974	1			T3	400		T5	16		T6	545
valid_sources[0x5c]	28868	1			T3	593		T5	29		T6	611
valid_sources[0x5d]	32449	1			T3	1051		T5	16		T6	260
valid_sources[0x5e]	24787	1			T3	333		T5	34		T6	300
valid_sources[0x5f]	27362	1			T3	269		T5	15		T6	178
valid_sources[0x60]	26056	1			T3	324		T5	22		T6	289
valid_sources[0x61]	25356	1			T3	194		T5	21		T6	296
valid_sources[0x62]	33185	1			T3	689		T5	32		T6	94
valid_sources[0x63]	28292	1			T3	1023		T5	25		T6	214
valid_sources[0x64]	28547	1			T3	382		T5	17		T6	333
valid_sources[0x65]	25805	1			T3	607		T5	22		T6	61
valid_sources[0x66]	27589	1			T3	388		T5	25		T6	1348
valid_sources[0x67]	27032	1			T3	540		T5	15		T6	160
valid_sources[0x68]	26300	1			T3	536		T5	21		T6	547
valid_sources[0x69]	27980	1			T3	850		T5	13		T6	319
valid_sources[0x6a]	27191	1			T3	959		T5	30		T6	70
valid_sources[0x6b]	28623	1			T3	147		T5	45		T6	231
valid_sources[0x6c]	30655	1			T3	474		T5	19		T6	204
valid_sources[0x6d]	26369	1			T3	513		T5	20		T6	427
valid_sources[0x6e]	29314	1			T3	747		T5	14		T6	837
valid_sources[0x6f]	24389	1			T3	311		T5	19		T6	531
valid_sources[0x70]	29910	1			T3	695		T5	21		T6	457
valid_sources[0x71]	33388	1			T3	392		T5	22		T6	525
valid_sources[0x72]	29318	1			T3	203		T5	22		T6	308
valid_sources[0x73]	29435	1			T3	630		T5	29		T6	231
valid_sources[0x74]	24933	1			T3	362		T5	26		T6	141
valid_sources[0x75]	26425	1			T1	2		T3	303		T5	23
valid_sources[0x76]	31172	1			T3	739		T5	11		T6	286
valid_sources[0x77]	27147	1			T3	516		T5	18		T6	633
valid_sources[0x78]	25388	1			T3	514		T5	18		T6	262
valid_sources[0x79]	26052	1			T3	682		T5	17		T6	408
valid_sources[0x7a]	34887	1			T3	127		T5	19		T6	194
valid_sources[0x7b]	27858	1			T3	66		T5	32		T6	614
valid_sources[0x7c]	26650	1			T3	1126		T5	15		T6	350
valid_sources[0x7d]	27405	1			T1	2		T3	271		T5	16
valid_sources[0x7e]	25866	1			T3	406		T5	15		T6	605
valid_sources[0x7f]	33151	1			T3	191		T5	28		T6	1437
valid_sources[0x80]	25772	1			T3	391		T5	18		T6	258

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

945764

1

T1

1

T2

4

T3

5387

values[0x0]

all_enables

biggest_size

1458341

1

T1

12

T2

451

T3

20434

values[0x1]

all_enables

biggest_size

1437461

1

T1

13

T2

435

T3

19853