Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3364972

1

T1

9

T2

8

T3

74176

full_word

3840480

1

T1

26

T2

890

T3

45674

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7204972	1			T1	35		T2	898		T3	119850
auto[TlIntgErrCmd]	163	1			T84	6		T89	10		T90	13
auto[TlIntgErrData]	152	1			T84	5		T89	12		T90	6
auto[TlIntgErrBoth]	165	1			T84	9		T89	8		T90	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3974256

1

T1

1

T2

9

T3

72607

auto[1]

3231196

1

T1

34

T2

889

T3

47243

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3028175	1			T2	5		T3	67220		T4	1
auto[TlIntgErrNone]	partial	auto[1]	336349	1			T1	9		T2	3		T3	6956
auto[TlIntgErrNone]	full_word	auto[0]	945854	1			T1	1		T2	4		T3	5387
auto[TlIntgErrNone]	full_word	auto[1]	2894594	1			T1	25		T2	886		T3	40287
auto[TlIntgErrCmd]	partial	auto[0]	72	1			T84	2		T89	4		T90	8
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T84	4		T89	6		T90	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T90	1		T96	1		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T163	1		T143	1		T164	1
auto[TlIntgErrData]	partial	auto[0]	75	1			T84	5		T89	6		T90	4
auto[TlIntgErrData]	partial	auto[1]	67	1			T89	4		T90	2		T96	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T143	1		T164	1		T146	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T89	2		T163	1		T164	1
auto[TlIntgErrBoth]	partial	auto[0]	64	1			T84	3		T89	3		T90	4
auto[TlIntgErrBoth]	partial	auto[1]	91	1			T84	5		T89	4		T90	6
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T163	1		T165	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T84	1		T89	1		T90	1