Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376052860	2490979	0	0
DepthKnown_A	376052860	375915952	0	0
RvalidKnown_A	376052860	375915952	0	0
WreadyKnown_A	376052860	375915952	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	2490979	0	0
T2	690871	832	0	0
T3	620577	16658	0	0
T4	6204	0	0	0
T5	112480	1670	0	0
T6	824003	18311	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	1672	0	0
T10	659860	832	0	0
T11	0	1854	0	0
T13	0	30790	0	0
T22	1129	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376052860	2776228	0	0
DepthKnown_A	376052860	375915952	0	0
RvalidKnown_A	376052860	375915952	0	0
WreadyKnown_A	376052860	375915952	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	2776228	0	0
T2	690871	832	0	0
T3	620577	21792	0	0
T4	6204	0	0	0
T5	112480	839	0	0
T6	824003	35115	0	0
T7	117050	832	0	0
T8	37605	2645	0	0
T9	50294	841	0	0
T10	659860	832	0	0
T11	0	3028	0	0
T13	0	40129	0	0
T22	1129	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376052860	183205	0	0
DepthKnown_A	376052860	375915952	0	0
RvalidKnown_A	376052860	375915952	0	0
WreadyKnown_A	376052860	375915952	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	183205	0	0
T3	620577	963	0	0
T4	6204	0	0	0
T5	112480	0	0	0
T6	824003	1105	0	0
T7	117050	0	0	0
T8	37605	0	0	0
T9	50294	0	0	0
T10	659860	0	0	0
T11	24023	0	0	0
T12	0	6	0	0
T13	0	3441	0	0
T14	0	1550	0	0
T22	1129	0	0	0
T24	0	471	0	0
T25	0	250	0	0
T27	0	409	0	0
T32	0	673	0	0
T33	0	1183	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376052860	424932	0	0
DepthKnown_A	376052860	375915952	0	0
RvalidKnown_A	376052860	375915952	0	0
WreadyKnown_A	376052860	375915952	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	424932	0	0
T3	620577	4256	0	0
T4	6204	0	0	0
T5	112480	0	0	0
T6	824003	3554	0	0
T7	117050	0	0	0
T8	37605	0	0	0
T9	50294	0	0	0
T10	659860	0	0	0
T11	24023	0	0	0
T12	0	6	0	0
T13	0	8619	0	0
T14	0	7011	0	0
T22	1129	0	0	0
T24	0	2106	0	0
T25	0	250	0	0
T27	0	1904	0	0
T32	0	3101	0	0
T33	0	5564	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376052860	5849122	0	0
DepthKnown_A	376052860	375915952	0	0
RvalidKnown_A	376052860	375915952	0	0
WreadyKnown_A	376052860	375915952	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	5849122	0	0
T1	2474	35	0	0
T2	690871	66	0	0
T3	620577	121837	0	0
T4	6204	32	0	0
T5	112480	4697	0	0
T6	824003	97057	0	0
T7	117050	72	0	0
T8	37605	789	0	0
T9	50294	68	0	0
T10	659860	26664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	376052860	13170644	0	0
DepthKnown_A	376052860	375915952	0	0
RvalidKnown_A	376052860	375915952	0	0
WreadyKnown_A	376052860	375915952	0	0
gen_passthru_fifo.paramCheckPass	1101	1101	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	13170644	0	0
T1	2474	35	0	0
T2	690871	66	0	0
T3	620577	482593	0	0
T4	6204	132	0	0
T5	112480	20686	0	0
T6	824003	284042	0	0
T7	117050	72	0	0
T8	37605	2544	0	0
T9	50294	285	0	0
T10	659860	26664	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	376052860	375915952	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1101	1101	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0