Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T3,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T13
1	0	Covered	T3,T6,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T6,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	650546336	510720168	0	0
CheckNGreaterZero_A	2778	2778	0	0
GntImpliesReady_A	650546336	3456574	0	0
GntImpliesValid_A	650546336	3456574	0	0
GrantKnown_A	650546336	510720168	0	0
IdxKnown_A	650546336	510720168	0	0
IndexIsCorrect_A	650546336	3456574	0	0
LockArbDecision_A	650546336	0	0	0
NoReadyValidNoGrant_A	650546336	0	0	0
ReadyAndValidImplyGrant_A	650546336	3456574	0	0
ReqAndReadyImplyGrant_A	650546336	3456574	0	0
ReqImpliesValid_A	650546336	3456574	0	0
ReqStaysHighUntilGranted0_M	650546336	0	0	0
RoundRobin_A	650546336	4	0	926
ValidKnown_A	650546336	510720168	0	0
gen_data_port_assertion.DataFlow_A	650546336	3456574	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	510720168	0	0
T1	3266	3215	0	0
T2	920119	805413	0	0
T3	2399115	1503111	0	0
T4	7644	6830	0	0
T5	156334	134152	0	0
T6	1096723	1015863	0	0
T7	505562	310795	0	0
T8	85447	61028	0	0
T9	257780	152742	0	0
T10	846776	752910	0	0
T11	27200	26924	0	0
T12	0	400	0	0
T13	0	554388	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2778	2778	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	3456574	0	0
T2	690871	832	0	0
T3	2399115	18689	0	0
T4	7644	0	0	0
T5	156334	832	0	0
T6	1096723	33421	0	0
T7	505562	832	0	0
T8	85447	832	0	0
T9	257780	832	0	0
T10	846776	832	0	0
T11	54400	1344	0	0
T12	800	35	0	0
T13	0	24595	0	0
T14	0	9209	0	0
T22	1129	0	0	0
T24	0	6281	0	0
T25	0	1482	0	0
T27	0	4257	0	0
T32	0	8476	0	0
T33	0	10872	0	0
T36	0	8040	0	0
T39	0	1028	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	3456574	0	0
T2	690871	832	0	0
T3	2399115	18689	0	0
T4	7644	0	0	0
T5	156334	832	0	0
T6	1096723	33421	0	0
T7	505562	832	0	0
T8	85447	832	0	0
T9	257780	832	0	0
T10	846776	832	0	0
T11	54400	1344	0	0
T12	800	35	0	0
T13	0	24595	0	0
T14	0	9209	0	0
T22	1129	0	0	0
T24	0	6281	0	0
T25	0	1482	0	0
T27	0	4257	0	0
T32	0	8476	0	0
T33	0	10872	0	0
T36	0	8040	0	0
T39	0	1028	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	510720168	0	0
T1	3266	3215	0	0
T2	920119	805413	0	0
T3	2399115	1503111	0	0
T4	7644	6830	0	0
T5	156334	134152	0	0
T6	1096723	1015863	0	0
T7	505562	310795	0	0
T8	85447	61028	0	0
T9	257780	152742	0	0
T10	846776	752910	0	0
T11	27200	26924	0	0
T12	0	400	0	0
T13	0	554388	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	510720168	0	0
T1	3266	3215	0	0
T2	920119	805413	0	0
T3	2399115	1503111	0	0
T4	7644	6830	0	0
T5	156334	134152	0	0
T6	1096723	1015863	0	0
T7	505562	310795	0	0
T8	85447	61028	0	0
T9	257780	152742	0	0
T10	846776	752910	0	0
T11	27200	26924	0	0
T12	0	400	0	0
T13	0	554388	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	3456574	0	0
T2	690871	832	0	0
T3	2399115	18689	0	0
T4	7644	0	0	0
T5	156334	832	0	0
T6	1096723	33421	0	0
T7	505562	832	0	0
T8	85447	832	0	0
T9	257780	832	0	0
T10	846776	832	0	0
T11	54400	1344	0	0
T12	800	35	0	0
T13	0	24595	0	0
T14	0	9209	0	0
T22	1129	0	0	0
T24	0	6281	0	0
T25	0	1482	0	0
T27	0	4257	0	0
T32	0	8476	0	0
T33	0	10872	0	0
T36	0	8040	0	0
T39	0	1028	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	3456574	0	0
T2	690871	832	0	0
T3	2399115	18689	0	0
T4	7644	0	0	0
T5	156334	832	0	0
T6	1096723	33421	0	0
T7	505562	832	0	0
T8	85447	832	0	0
T9	257780	832	0	0
T10	846776	832	0	0
T11	54400	1344	0	0
T12	800	35	0	0
T13	0	24595	0	0
T14	0	9209	0	0
T22	1129	0	0	0
T24	0	6281	0	0
T25	0	1482	0	0
T27	0	4257	0	0
T32	0	8476	0	0
T33	0	10872	0	0
T36	0	8040	0	0
T39	0	1028	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	3456574	0	0
T2	690871	832	0	0
T3	2399115	18689	0	0
T4	7644	0	0	0
T5	156334	832	0	0
T6	1096723	33421	0	0
T7	505562	832	0	0
T8	85447	832	0	0
T9	257780	832	0	0
T10	846776	832	0	0
T11	54400	1344	0	0
T12	800	35	0	0
T13	0	24595	0	0
T14	0	9209	0	0
T22	1129	0	0	0
T24	0	6281	0	0
T25	0	1482	0	0
T27	0	4257	0	0
T32	0	8476	0	0
T33	0	10872	0	0
T36	0	8040	0	0
T39	0	1028	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	3456574	0	0
T2	690871	832	0	0
T3	2399115	18689	0	0
T4	7644	0	0	0
T5	156334	832	0	0
T6	1096723	33421	0	0
T7	505562	832	0	0
T8	85447	832	0	0
T9	257780	832	0	0
T10	846776	832	0	0
T11	54400	1344	0	0
T12	800	35	0	0
T13	0	24595	0	0
T14	0	9209	0	0
T22	1129	0	0	0
T24	0	6281	0	0
T25	0	1482	0	0
T27	0	4257	0	0
T32	0	8476	0	0
T33	0	10872	0	0
T36	0	8040	0	0
T39	0	1028	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	4	0	926
T40	276357	1	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	144404	0	0	1
T45	4899	0	0	1
T46	612716	0	0	1
T47	3331	0	0	1
T48	375503	0	0	1
T49	1028	0	0	1
T50	4232	0	0	1
T51	3318	0	0	1
T52	18756	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	510720168	0	0
T1	3266	3215	0	0
T2	920119	805413	0	0
T3	2399115	1503111	0	0
T4	7644	6830	0	0
T5	156334	134152	0	0
T6	1096723	1015863	0	0
T7	505562	310795	0	0
T8	85447	61028	0	0
T9	257780	152742	0	0
T10	846776	752910	0	0
T11	27200	26924	0	0
T12	0	400	0	0
T13	0	554388	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	650546336	3456574	0	0
T2	690871	832	0	0
T3	2399115	18689	0	0
T4	7644	0	0	0
T5	156334	832	0	0
T6	1096723	33421	0	0
T7	505562	832	0	0
T8	85447	832	0	0
T9	257780	832	0	0
T10	846776	832	0	0
T11	54400	1344	0	0
T12	800	35	0	0
T13	0	24595	0	0
T14	0	9209	0	0
T22	1129	0	0	0
T24	0	6281	0	0
T25	0	1482	0	0
T27	0	4257	0	0
T32	0	8476	0	0
T33	0	10872	0	0
T36	0	8040	0	0
T39	0	1028	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T3,T6,T12

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T3,T6,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T6,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138459396	32124803	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	138459396	654083	0	0
GntImpliesValid_A	138459396	654083	0	0
GrantKnown_A	138459396	32124803	0	0
IdxKnown_A	138459396	32124803	0	0
IndexIsCorrect_A	138459396	654083	0	0
LockArbDecision_A	138459396	0	0	0
NoReadyValidNoGrant_A	138459396	0	0	0
ReadyAndValidImplyGrant_A	138459396	654083	0	0
ReqAndReadyImplyGrant_A	138459396	654083	0	0
ReqImpliesValid_A	138459396	654083	0	0
ReqStaysHighUntilGranted0_M	138459396	0	0	0
RoundRobin_A	138459396	0	0	0
ValidKnown_A	138459396	32124803	0	0
gen_data_port_assertion.DataFlow_A	138459396	654083	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	32124803	0	0
T1	792	792	0	0
T2	114624	0	0	0
T3	889269	123192	0	0
T4	720	720	0	0
T5	21927	0	0	0
T6	136360	62512	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T12	0	400	0	0
T13	0	435080	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	654083	0	0
T3	889269	4504	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	2537	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	27	0	0
T13	0	14937	0	0
T14	0	6576	0	0
T24	0	890	0	0
T25	0	1482	0	0
T27	0	457	0	0
T32	0	1572	0	0
T33	0	4257	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	654083	0	0
T3	889269	4504	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	2537	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	27	0	0
T13	0	14937	0	0
T14	0	6576	0	0
T24	0	890	0	0
T25	0	1482	0	0
T27	0	457	0	0
T32	0	1572	0	0
T33	0	4257	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	32124803	0	0
T1	792	792	0	0
T2	114624	0	0	0
T3	889269	123192	0	0
T4	720	720	0	0
T5	21927	0	0	0
T6	136360	62512	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T12	0	400	0	0
T13	0	435080	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	32124803	0	0
T1	792	792	0	0
T2	114624	0	0	0
T3	889269	123192	0	0
T4	720	720	0	0
T5	21927	0	0	0
T6	136360	62512	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T12	0	400	0	0
T13	0	435080	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	654083	0	0
T3	889269	4504	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	2537	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	27	0	0
T13	0	14937	0	0
T14	0	6576	0	0
T24	0	890	0	0
T25	0	1482	0	0
T27	0	457	0	0
T32	0	1572	0	0
T33	0	4257	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	654083	0	0
T3	889269	4504	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	2537	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	27	0	0
T13	0	14937	0	0
T14	0	6576	0	0
T24	0	890	0	0
T25	0	1482	0	0
T27	0	457	0	0
T32	0	1572	0	0
T33	0	4257	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	654083	0	0
T3	889269	4504	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	2537	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	27	0	0
T13	0	14937	0	0
T14	0	6576	0	0
T24	0	890	0	0
T25	0	1482	0	0
T27	0	457	0	0
T32	0	1572	0	0
T33	0	4257	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	654083	0	0
T3	889269	4504	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	2537	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	27	0	0
T13	0	14937	0	0
T14	0	6576	0	0
T24	0	890	0	0
T25	0	1482	0	0
T27	0	457	0	0
T32	0	1572	0	0
T33	0	4257	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	32124803	0	0
T1	792	792	0	0
T2	114624	0	0	0
T3	889269	123192	0	0
T4	720	720	0	0
T5	21927	0	0	0
T6	136360	62512	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T12	0	400	0	0
T13	0	435080	0	0
T24	0	23488	0	0
T25	0	37192	0	0
T26	0	1008	0	0
T27	0	21040	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	654083	0	0
T3	889269	4504	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	2537	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	27	0	0
T13	0	14937	0	0
T14	0	6576	0	0
T24	0	890	0	0
T25	0	1482	0	0
T27	0	457	0	0
T32	0	1572	0	0
T33	0	4257	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T13
1	0	Covered	T3,T6,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Unreachable
1	1	Covered	T3,T6,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T6,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	138459396	105053903	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	138459396	782154	0	0
GntImpliesValid_A	138459396	782154	0	0
GrantKnown_A	138459396	105053903	0	0
IdxKnown_A	138459396	105053903	0	0
IndexIsCorrect_A	138459396	782154	0	0
LockArbDecision_A	138459396	0	0	0
NoReadyValidNoGrant_A	138459396	0	0	0
ReadyAndValidImplyGrant_A	138459396	782154	0	0
ReqAndReadyImplyGrant_A	138459396	782154	0	0
ReqImpliesValid_A	138459396	782154	0	0
ReqStaysHighUntilGranted0_M	138459396	0	0	0
RoundRobin_A	138459396	0	0	0
ValidKnown_A	138459396	105053903	0	0
gen_data_port_assertion.DataFlow_A	138459396	782154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	105053903	0	0
T2	114624	114624	0	0
T3	889269	759350	0	0
T4	720	0	0	0
T5	21927	21760	0	0
T6	136360	129378	0	0
T7	194256	193752	0	0
T8	23921	23488	0	0
T9	103743	102518	0	0
T10	93458	93136	0	0
T11	27200	26924	0	0
T13	0	119308	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	782154	0	0
T3	889269	1561	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	14807	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	0	0	0
T13	0	9658	0	0
T14	0	2633	0	0
T24	0	5391	0	0
T27	0	3800	0	0
T32	0	6904	0	0
T33	0	6615	0	0
T36	0	8040	0	0
T39	0	1028	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	782154	0	0
T3	889269	1561	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	14807	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	0	0	0
T13	0	9658	0	0
T14	0	2633	0	0
T24	0	5391	0	0
T27	0	3800	0	0
T32	0	6904	0	0
T33	0	6615	0	0
T36	0	8040	0	0
T39	0	1028	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	105053903	0	0
T2	114624	114624	0	0
T3	889269	759350	0	0
T4	720	0	0	0
T5	21927	21760	0	0
T6	136360	129378	0	0
T7	194256	193752	0	0
T8	23921	23488	0	0
T9	103743	102518	0	0
T10	93458	93136	0	0
T11	27200	26924	0	0
T13	0	119308	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	105053903	0	0
T2	114624	114624	0	0
T3	889269	759350	0	0
T4	720	0	0	0
T5	21927	21760	0	0
T6	136360	129378	0	0
T7	194256	193752	0	0
T8	23921	23488	0	0
T9	103743	102518	0	0
T10	93458	93136	0	0
T11	27200	26924	0	0
T13	0	119308	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	782154	0	0
T3	889269	1561	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	14807	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	0	0	0
T13	0	9658	0	0
T14	0	2633	0	0
T24	0	5391	0	0
T27	0	3800	0	0
T32	0	6904	0	0
T33	0	6615	0	0
T36	0	8040	0	0
T39	0	1028	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	782154	0	0
T3	889269	1561	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	14807	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	0	0	0
T13	0	9658	0	0
T14	0	2633	0	0
T24	0	5391	0	0
T27	0	3800	0	0
T32	0	6904	0	0
T33	0	6615	0	0
T36	0	8040	0	0
T39	0	1028	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	782154	0	0
T3	889269	1561	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	14807	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	0	0	0
T13	0	9658	0	0
T14	0	2633	0	0
T24	0	5391	0	0
T27	0	3800	0	0
T32	0	6904	0	0
T33	0	6615	0	0
T36	0	8040	0	0
T39	0	1028	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	782154	0	0
T3	889269	1561	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	14807	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	0	0	0
T13	0	9658	0	0
T14	0	2633	0	0
T24	0	5391	0	0
T27	0	3800	0	0
T32	0	6904	0	0
T33	0	6615	0	0
T36	0	8040	0	0
T39	0	1028	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	105053903	0	0
T2	114624	114624	0	0
T3	889269	759350	0	0
T4	720	0	0	0
T5	21927	21760	0	0
T6	136360	129378	0	0
T7	194256	193752	0	0
T8	23921	23488	0	0
T9	103743	102518	0	0
T10	93458	93136	0	0
T11	27200	26924	0	0
T13	0	119308	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138459396	782154	0	0
T3	889269	1561	0	0
T4	720	0	0	0
T5	21927	0	0	0
T6	136360	14807	0	0
T7	194256	0	0	0
T8	23921	0	0	0
T9	103743	0	0	0
T10	93458	0	0	0
T11	27200	0	0	0
T12	400	0	0	0
T13	0	9658	0	0
T14	0	2633	0	0
T24	0	5391	0	0
T27	0	3800	0	0
T32	0	6904	0	0
T33	0	6615	0	0
T36	0	8040	0	0
T39	0	1028	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T6,T12

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T12
1	0	Covered	T2,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	373627544	373541462	0	0
CheckNGreaterZero_A	926	926	0	0
GntImpliesReady_A	373627544	2020337	0	0
GntImpliesValid_A	373627544	2020337	0	0
GrantKnown_A	373627544	373541462	0	0
IdxKnown_A	373627544	373541462	0	0
IndexIsCorrect_A	373627544	2020337	0	0
LockArbDecision_A	373627544	0	0	0
NoReadyValidNoGrant_A	373627544	0	0	0
ReadyAndValidImplyGrant_A	373627544	2020337	0	0
ReqAndReadyImplyGrant_A	373627544	2020337	0	0
ReqImpliesValid_A	373627544	2020337	0	0
ReqStaysHighUntilGranted0_M	373627544	0	0	0
RoundRobin_A	373627544	4	0	926
ValidKnown_A	373627544	373541462	0	0
gen_data_port_assertion.DataFlow_A	373627544	2020337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	373541462	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	926	926	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	2020337	0	0
T2	690871	832	0	0
T3	620577	12624	0	0
T4	6204	0	0	0
T5	112480	832	0	0
T6	824003	16077	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	832	0	0
T10	659860	832	0	0
T11	0	1344	0	0
T12	0	8	0	0
T22	1129	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	2020337	0	0
T2	690871	832	0	0
T3	620577	12624	0	0
T4	6204	0	0	0
T5	112480	832	0	0
T6	824003	16077	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	832	0	0
T10	659860	832	0	0
T11	0	1344	0	0
T12	0	8	0	0
T22	1129	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	373541462	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	373541462	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	2020337	0	0
T2	690871	832	0	0
T3	620577	12624	0	0
T4	6204	0	0	0
T5	112480	832	0	0
T6	824003	16077	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	832	0	0
T10	659860	832	0	0
T11	0	1344	0	0
T12	0	8	0	0
T22	1129	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	2020337	0	0
T2	690871	832	0	0
T3	620577	12624	0	0
T4	6204	0	0	0
T5	112480	832	0	0
T6	824003	16077	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	832	0	0
T10	659860	832	0	0
T11	0	1344	0	0
T12	0	8	0	0
T22	1129	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	2020337	0	0
T2	690871	832	0	0
T3	620577	12624	0	0
T4	6204	0	0	0
T5	112480	832	0	0
T6	824003	16077	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	832	0	0
T10	659860	832	0	0
T11	0	1344	0	0
T12	0	8	0	0
T22	1129	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	2020337	0	0
T2	690871	832	0	0
T3	620577	12624	0	0
T4	6204	0	0	0
T5	112480	832	0	0
T6	824003	16077	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	832	0	0
T10	659860	832	0	0
T11	0	1344	0	0
T12	0	8	0	0
T22	1129	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	4	0	926
T40	276357	1	0	1
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	144404	0	0	1
T45	4899	0	0	1
T46	612716	0	0	1
T47	3331	0	0	1
T48	375503	0	0	1
T49	1028	0	0	1
T50	4232	0	0	1
T51	3318	0	0	1
T52	18756	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	373541462	0	0
T1	2474	2423	0	0
T2	690871	690789	0	0
T3	620577	620569	0	0
T4	6204	6110	0	0
T5	112480	112392	0	0
T6	824003	823973	0	0
T7	117050	117043	0	0
T8	37605	37540	0	0
T9	50294	50224	0	0
T10	659860	659774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	373627544	2020337	0	0
T2	690871	832	0	0
T3	620577	12624	0	0
T4	6204	0	0	0
T5	112480	832	0	0
T6	824003	16077	0	0
T7	117050	832	0	0
T8	37605	832	0	0
T9	50294	832	0	0
T10	659860	832	0	0
T11	0	1344	0	0
T12	0	8	0	0
T22	1129	0	0	0