Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
3155 |
0 |
0 |
T84 |
19993 |
3 |
0 |
0 |
T85 |
14966 |
213 |
0 |
0 |
T86 |
18453 |
249 |
0 |
0 |
T87 |
1925 |
1 |
0 |
0 |
T88 |
5380 |
3 |
0 |
0 |
T89 |
83094 |
5 |
0 |
0 |
T90 |
27362 |
3 |
0 |
0 |
T95 |
5441 |
56 |
0 |
0 |
T96 |
56669 |
3 |
0 |
0 |
T100 |
2268 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1871 |
0 |
0 |
T73 |
4361 |
8 |
0 |
0 |
T101 |
5533 |
5 |
0 |
0 |
T130 |
6432 |
9 |
0 |
0 |
T131 |
4188 |
2 |
0 |
0 |
T141 |
42031 |
220 |
0 |
0 |
T142 |
15381 |
29 |
0 |
0 |
T143 |
100628 |
121 |
0 |
0 |
T144 |
8718 |
12 |
0 |
0 |
T145 |
4874 |
1 |
0 |
0 |
T146 |
64735 |
97 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1905 |
0 |
0 |
T73 |
4361 |
12 |
0 |
0 |
T101 |
5533 |
17 |
0 |
0 |
T131 |
4188 |
4 |
0 |
0 |
T141 |
42031 |
243 |
0 |
0 |
T142 |
15381 |
30 |
0 |
0 |
T143 |
100628 |
125 |
0 |
0 |
T144 |
8718 |
19 |
0 |
0 |
T145 |
4874 |
4 |
0 |
0 |
T146 |
64735 |
57 |
0 |
0 |
T147 |
4697 |
4 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2320 |
0 |
0 |
T73 |
4361 |
13 |
0 |
0 |
T101 |
5533 |
9 |
0 |
0 |
T130 |
6432 |
18 |
0 |
0 |
T131 |
4188 |
3 |
0 |
0 |
T141 |
42031 |
285 |
0 |
0 |
T142 |
15381 |
29 |
0 |
0 |
T143 |
100628 |
176 |
0 |
0 |
T144 |
8718 |
27 |
0 |
0 |
T145 |
4874 |
11 |
0 |
0 |
T146 |
64735 |
130 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
11870 |
0 |
0 |
T73 |
4361 |
12 |
0 |
0 |
T101 |
5533 |
3 |
0 |
0 |
T130 |
6432 |
118 |
0 |
0 |
T131 |
4188 |
7 |
0 |
0 |
T141 |
42031 |
255 |
0 |
0 |
T142 |
15381 |
266 |
0 |
0 |
T143 |
100628 |
2036 |
0 |
0 |
T144 |
8718 |
295 |
0 |
0 |
T145 |
4874 |
7 |
0 |
0 |
T146 |
64735 |
1163 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
11111 |
0 |
0 |
T73 |
4361 |
4 |
0 |
0 |
T101 |
5533 |
7 |
0 |
0 |
T130 |
6432 |
187 |
0 |
0 |
T131 |
4188 |
108 |
0 |
0 |
T141 |
42031 |
243 |
0 |
0 |
T142 |
15381 |
272 |
0 |
0 |
T143 |
100628 |
1886 |
0 |
0 |
T144 |
8718 |
124 |
0 |
0 |
T145 |
4874 |
6 |
0 |
0 |
T147 |
4697 |
6 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
11592 |
0 |
0 |
T73 |
4361 |
18 |
0 |
0 |
T101 |
5533 |
122 |
0 |
0 |
T130 |
6432 |
81 |
0 |
0 |
T131 |
4188 |
1 |
0 |
0 |
T141 |
42031 |
261 |
0 |
0 |
T142 |
15381 |
17 |
0 |
0 |
T143 |
100628 |
2160 |
0 |
0 |
T144 |
8718 |
135 |
0 |
0 |
T145 |
4874 |
15 |
0 |
0 |
T147 |
4697 |
8 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
11559 |
0 |
0 |
T73 |
4361 |
7 |
0 |
0 |
T101 |
5533 |
133 |
0 |
0 |
T131 |
4188 |
144 |
0 |
0 |
T141 |
42031 |
244 |
0 |
0 |
T142 |
15381 |
266 |
0 |
0 |
T143 |
100628 |
2277 |
0 |
0 |
T144 |
8718 |
242 |
0 |
0 |
T145 |
4874 |
145 |
0 |
0 |
T146 |
64735 |
1098 |
0 |
0 |
T148 |
15212 |
34 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
12236 |
0 |
0 |
T73 |
4361 |
1 |
0 |
0 |
T101 |
5533 |
113 |
0 |
0 |
T130 |
6432 |
1 |
0 |
0 |
T131 |
4188 |
9 |
0 |
0 |
T141 |
42031 |
265 |
0 |
0 |
T142 |
15381 |
276 |
0 |
0 |
T143 |
100628 |
1583 |
0 |
0 |
T144 |
8718 |
121 |
0 |
0 |
T145 |
4874 |
9 |
0 |
0 |
T147 |
4697 |
73 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
12904 |
0 |
0 |
T73 |
4361 |
18 |
0 |
0 |
T101 |
5533 |
1 |
0 |
0 |
T130 |
6432 |
65 |
0 |
0 |
T131 |
4188 |
140 |
0 |
0 |
T141 |
42031 |
264 |
0 |
0 |
T142 |
15381 |
157 |
0 |
0 |
T143 |
100628 |
1690 |
0 |
0 |
T144 |
8718 |
140 |
0 |
0 |
T145 |
4874 |
2 |
0 |
0 |
T147 |
4697 |
82 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
12452 |
0 |
0 |
T73 |
4361 |
11 |
0 |
0 |
T101 |
5533 |
6 |
0 |
0 |
T130 |
6432 |
71 |
0 |
0 |
T141 |
42031 |
265 |
0 |
0 |
T142 |
15381 |
331 |
0 |
0 |
T143 |
100628 |
1776 |
0 |
0 |
T144 |
8718 |
148 |
0 |
0 |
T145 |
4874 |
5 |
0 |
0 |
T146 |
64735 |
1252 |
0 |
0 |
T147 |
4697 |
68 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
11707 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T101 |
5533 |
8 |
0 |
0 |
T130 |
6432 |
4 |
0 |
0 |
T131 |
4188 |
2 |
0 |
0 |
T141 |
42031 |
277 |
0 |
0 |
T142 |
15381 |
123 |
0 |
0 |
T143 |
100628 |
1958 |
0 |
0 |
T144 |
8718 |
103 |
0 |
0 |
T145 |
4874 |
155 |
0 |
0 |
T147 |
4697 |
65 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5584 |
0 |
0 |
T73 |
4361 |
5 |
0 |
0 |
T101 |
5533 |
60 |
0 |
0 |
T130 |
6432 |
10 |
0 |
0 |
T141 |
42031 |
296 |
0 |
0 |
T142 |
15381 |
17 |
0 |
0 |
T143 |
100628 |
687 |
0 |
0 |
T144 |
8718 |
69 |
0 |
0 |
T145 |
4874 |
57 |
0 |
0 |
T146 |
64735 |
351 |
0 |
0 |
T147 |
4697 |
5 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5808 |
0 |
0 |
T73 |
4361 |
14 |
0 |
0 |
T101 |
5533 |
42 |
0 |
0 |
T130 |
6432 |
36 |
0 |
0 |
T141 |
42031 |
240 |
0 |
0 |
T142 |
15381 |
78 |
0 |
0 |
T143 |
100628 |
894 |
0 |
0 |
T144 |
8718 |
43 |
0 |
0 |
T145 |
4874 |
32 |
0 |
0 |
T146 |
64735 |
359 |
0 |
0 |
T147 |
4697 |
23 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5838 |
0 |
0 |
T73 |
4361 |
11 |
0 |
0 |
T101 |
5533 |
5 |
0 |
0 |
T130 |
6432 |
43 |
0 |
0 |
T131 |
4188 |
44 |
0 |
0 |
T141 |
42031 |
240 |
0 |
0 |
T142 |
15381 |
82 |
0 |
0 |
T143 |
100628 |
953 |
0 |
0 |
T144 |
8718 |
97 |
0 |
0 |
T145 |
4874 |
9 |
0 |
0 |
T146 |
64735 |
546 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
6611 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T101 |
5533 |
5 |
0 |
0 |
T130 |
6432 |
1 |
0 |
0 |
T131 |
4188 |
73 |
0 |
0 |
T141 |
42031 |
253 |
0 |
0 |
T142 |
15381 |
117 |
0 |
0 |
T143 |
100628 |
817 |
0 |
0 |
T144 |
8718 |
124 |
0 |
0 |
T145 |
4874 |
4 |
0 |
0 |
T147 |
4697 |
35 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5883 |
0 |
0 |
T73 |
4361 |
5 |
0 |
0 |
T101 |
5533 |
3 |
0 |
0 |
T130 |
6432 |
2 |
0 |
0 |
T131 |
4188 |
9 |
0 |
0 |
T141 |
42031 |
248 |
0 |
0 |
T142 |
15381 |
36 |
0 |
0 |
T143 |
100628 |
827 |
0 |
0 |
T144 |
8718 |
143 |
0 |
0 |
T145 |
4874 |
40 |
0 |
0 |
T147 |
4697 |
41 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5769 |
0 |
0 |
T73 |
4361 |
7 |
0 |
0 |
T101 |
5533 |
6 |
0 |
0 |
T130 |
6432 |
30 |
0 |
0 |
T131 |
4188 |
7 |
0 |
0 |
T141 |
42031 |
244 |
0 |
0 |
T142 |
15381 |
17 |
0 |
0 |
T143 |
100628 |
865 |
0 |
0 |
T144 |
8718 |
7 |
0 |
0 |
T145 |
4874 |
44 |
0 |
0 |
T147 |
4697 |
20 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5897 |
0 |
0 |
T73 |
4361 |
19 |
0 |
0 |
T101 |
5533 |
56 |
0 |
0 |
T130 |
6432 |
48 |
0 |
0 |
T131 |
4188 |
2 |
0 |
0 |
T141 |
42031 |
234 |
0 |
0 |
T142 |
15381 |
117 |
0 |
0 |
T143 |
100628 |
815 |
0 |
0 |
T144 |
8718 |
92 |
0 |
0 |
T146 |
64735 |
552 |
0 |
0 |
T148 |
15212 |
88 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
6228 |
0 |
0 |
T73 |
4361 |
11 |
0 |
0 |
T101 |
5533 |
13 |
0 |
0 |
T130 |
6432 |
74 |
0 |
0 |
T131 |
4188 |
7 |
0 |
0 |
T141 |
42031 |
271 |
0 |
0 |
T142 |
15381 |
87 |
0 |
0 |
T143 |
100628 |
732 |
0 |
0 |
T144 |
8718 |
60 |
0 |
0 |
T145 |
4874 |
8 |
0 |
0 |
T147 |
4697 |
41 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5422 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T101 |
5533 |
53 |
0 |
0 |
T130 |
6432 |
27 |
0 |
0 |
T131 |
4188 |
48 |
0 |
0 |
T141 |
42031 |
280 |
0 |
0 |
T142 |
15381 |
66 |
0 |
0 |
T143 |
100628 |
652 |
0 |
0 |
T144 |
8718 |
128 |
0 |
0 |
T145 |
4874 |
39 |
0 |
0 |
T149 |
21241 |
3 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5248 |
0 |
0 |
T73 |
4361 |
10 |
0 |
0 |
T101 |
5533 |
8 |
0 |
0 |
T131 |
4188 |
36 |
0 |
0 |
T141 |
42031 |
290 |
0 |
0 |
T142 |
15381 |
138 |
0 |
0 |
T143 |
100628 |
827 |
0 |
0 |
T144 |
8718 |
33 |
0 |
0 |
T145 |
4874 |
10 |
0 |
0 |
T146 |
64735 |
431 |
0 |
0 |
T147 |
4697 |
15 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5702 |
0 |
0 |
T73 |
4361 |
10 |
0 |
0 |
T101 |
5533 |
37 |
0 |
0 |
T130 |
6432 |
75 |
0 |
0 |
T131 |
4188 |
7 |
0 |
0 |
T141 |
42031 |
279 |
0 |
0 |
T142 |
15381 |
28 |
0 |
0 |
T143 |
100628 |
718 |
0 |
0 |
T144 |
8718 |
4 |
0 |
0 |
T145 |
4874 |
11 |
0 |
0 |
T147 |
4697 |
32 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5774 |
0 |
0 |
T73 |
4361 |
10 |
0 |
0 |
T85 |
14966 |
6 |
0 |
0 |
T101 |
5533 |
45 |
0 |
0 |
T130 |
6432 |
25 |
0 |
0 |
T131 |
4188 |
56 |
0 |
0 |
T141 |
42031 |
318 |
0 |
0 |
T142 |
15381 |
114 |
0 |
0 |
T143 |
100628 |
806 |
0 |
0 |
T144 |
8718 |
51 |
0 |
0 |
T147 |
4697 |
27 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5853 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T101 |
5533 |
3 |
0 |
0 |
T130 |
6432 |
24 |
0 |
0 |
T131 |
4188 |
4 |
0 |
0 |
T141 |
42031 |
256 |
0 |
0 |
T142 |
15381 |
28 |
0 |
0 |
T143 |
100628 |
865 |
0 |
0 |
T144 |
8718 |
38 |
0 |
0 |
T145 |
4874 |
1 |
0 |
0 |
T147 |
4697 |
18 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5372 |
0 |
0 |
T73 |
4361 |
12 |
0 |
0 |
T85 |
14966 |
1 |
0 |
0 |
T101 |
5533 |
4 |
0 |
0 |
T131 |
4188 |
57 |
0 |
0 |
T141 |
42031 |
252 |
0 |
0 |
T142 |
15381 |
10 |
0 |
0 |
T143 |
100628 |
711 |
0 |
0 |
T144 |
8718 |
9 |
0 |
0 |
T145 |
4874 |
36 |
0 |
0 |
T147 |
4697 |
4 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5980 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T130 |
6432 |
21 |
0 |
0 |
T131 |
4188 |
1 |
0 |
0 |
T141 |
42031 |
265 |
0 |
0 |
T142 |
15381 |
123 |
0 |
0 |
T143 |
100628 |
847 |
0 |
0 |
T144 |
8718 |
73 |
0 |
0 |
T145 |
4874 |
10 |
0 |
0 |
T146 |
64735 |
440 |
0 |
0 |
T147 |
4697 |
18 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5787 |
0 |
0 |
T73 |
4361 |
12 |
0 |
0 |
T101 |
5533 |
2 |
0 |
0 |
T130 |
6432 |
2 |
0 |
0 |
T131 |
4188 |
6 |
0 |
0 |
T141 |
42031 |
292 |
0 |
0 |
T142 |
15381 |
86 |
0 |
0 |
T143 |
100628 |
665 |
0 |
0 |
T144 |
8718 |
123 |
0 |
0 |
T145 |
4874 |
39 |
0 |
0 |
T147 |
4697 |
48 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
6205 |
0 |
0 |
T73 |
4361 |
1 |
0 |
0 |
T101 |
5533 |
9 |
0 |
0 |
T130 |
6432 |
48 |
0 |
0 |
T131 |
4188 |
7 |
0 |
0 |
T141 |
42031 |
262 |
0 |
0 |
T142 |
15381 |
23 |
0 |
0 |
T143 |
100628 |
996 |
0 |
0 |
T144 |
8718 |
114 |
0 |
0 |
T145 |
4874 |
18 |
0 |
0 |
T147 |
4697 |
24 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
6213 |
0 |
0 |
T73 |
4361 |
7 |
0 |
0 |
T101 |
5533 |
46 |
0 |
0 |
T130 |
6432 |
27 |
0 |
0 |
T131 |
4188 |
3 |
0 |
0 |
T141 |
42031 |
236 |
0 |
0 |
T142 |
15381 |
105 |
0 |
0 |
T143 |
100628 |
875 |
0 |
0 |
T144 |
8718 |
57 |
0 |
0 |
T145 |
4874 |
15 |
0 |
0 |
T146 |
64735 |
670 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
6095 |
0 |
0 |
T73 |
4361 |
3 |
0 |
0 |
T101 |
5533 |
7 |
0 |
0 |
T130 |
6432 |
9 |
0 |
0 |
T131 |
4188 |
5 |
0 |
0 |
T141 |
42031 |
241 |
0 |
0 |
T142 |
15381 |
66 |
0 |
0 |
T143 |
100628 |
895 |
0 |
0 |
T144 |
8718 |
120 |
0 |
0 |
T145 |
4874 |
11 |
0 |
0 |
T147 |
4697 |
3 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
6139 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T101 |
5533 |
47 |
0 |
0 |
T130 |
6432 |
37 |
0 |
0 |
T131 |
4188 |
39 |
0 |
0 |
T141 |
42031 |
279 |
0 |
0 |
T142 |
15381 |
116 |
0 |
0 |
T143 |
100628 |
908 |
0 |
0 |
T144 |
8718 |
61 |
0 |
0 |
T145 |
4874 |
46 |
0 |
0 |
T147 |
4697 |
24 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5894 |
0 |
0 |
T73 |
4361 |
11 |
0 |
0 |
T101 |
5533 |
7 |
0 |
0 |
T130 |
6432 |
61 |
0 |
0 |
T131 |
4188 |
48 |
0 |
0 |
T141 |
42031 |
251 |
0 |
0 |
T142 |
15381 |
140 |
0 |
0 |
T143 |
100628 |
816 |
0 |
0 |
T144 |
8718 |
11 |
0 |
0 |
T145 |
4874 |
73 |
0 |
0 |
T146 |
64735 |
499 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5853 |
0 |
0 |
T73 |
4361 |
7 |
0 |
0 |
T101 |
5533 |
16 |
0 |
0 |
T130 |
6432 |
77 |
0 |
0 |
T131 |
4188 |
57 |
0 |
0 |
T141 |
42031 |
252 |
0 |
0 |
T142 |
15381 |
135 |
0 |
0 |
T143 |
100628 |
840 |
0 |
0 |
T144 |
8718 |
102 |
0 |
0 |
T145 |
4874 |
54 |
0 |
0 |
T147 |
4697 |
17 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
5763 |
0 |
0 |
T73 |
4361 |
5 |
0 |
0 |
T101 |
5533 |
59 |
0 |
0 |
T130 |
6432 |
67 |
0 |
0 |
T131 |
4188 |
3 |
0 |
0 |
T141 |
42031 |
227 |
0 |
0 |
T142 |
15381 |
62 |
0 |
0 |
T143 |
100628 |
892 |
0 |
0 |
T144 |
8718 |
64 |
0 |
0 |
T145 |
4874 |
10 |
0 |
0 |
T147 |
4697 |
2 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
6291 |
0 |
0 |
T73 |
4361 |
11 |
0 |
0 |
T101 |
5533 |
7 |
0 |
0 |
T130 |
6432 |
54 |
0 |
0 |
T131 |
4188 |
59 |
0 |
0 |
T141 |
42031 |
262 |
0 |
0 |
T142 |
15381 |
120 |
0 |
0 |
T143 |
100628 |
848 |
0 |
0 |
T144 |
8718 |
61 |
0 |
0 |
T147 |
4697 |
5 |
0 |
0 |
T149 |
21241 |
8 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2192 |
0 |
0 |
T73 |
4361 |
13 |
0 |
0 |
T101 |
5533 |
15 |
0 |
0 |
T131 |
4188 |
8 |
0 |
0 |
T141 |
42031 |
202 |
0 |
0 |
T142 |
15381 |
34 |
0 |
0 |
T143 |
100628 |
151 |
0 |
0 |
T144 |
8718 |
16 |
0 |
0 |
T145 |
4874 |
7 |
0 |
0 |
T146 |
64735 |
156 |
0 |
0 |
T147 |
4697 |
4 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2266 |
0 |
0 |
T73 |
4361 |
20 |
0 |
0 |
T101 |
5533 |
11 |
0 |
0 |
T130 |
6432 |
6 |
0 |
0 |
T141 |
42031 |
258 |
0 |
0 |
T142 |
15381 |
19 |
0 |
0 |
T143 |
100628 |
162 |
0 |
0 |
T144 |
8718 |
10 |
0 |
0 |
T145 |
4874 |
5 |
0 |
0 |
T146 |
64735 |
128 |
0 |
0 |
T147 |
4697 |
1 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2165 |
0 |
0 |
T73 |
4361 |
20 |
0 |
0 |
T101 |
5533 |
14 |
0 |
0 |
T131 |
4188 |
11 |
0 |
0 |
T141 |
42031 |
235 |
0 |
0 |
T142 |
15381 |
40 |
0 |
0 |
T143 |
100628 |
204 |
0 |
0 |
T144 |
8718 |
1 |
0 |
0 |
T146 |
64735 |
98 |
0 |
0 |
T147 |
4697 |
1 |
0 |
0 |
T148 |
15212 |
15 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2211 |
0 |
0 |
T73 |
4361 |
17 |
0 |
0 |
T101 |
5533 |
9 |
0 |
0 |
T131 |
4188 |
9 |
0 |
0 |
T141 |
42031 |
235 |
0 |
0 |
T142 |
15381 |
32 |
0 |
0 |
T143 |
100628 |
153 |
0 |
0 |
T144 |
8718 |
19 |
0 |
0 |
T145 |
4874 |
12 |
0 |
0 |
T146 |
64735 |
116 |
0 |
0 |
T148 |
15212 |
16 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2725 |
0 |
0 |
T73 |
4361 |
10 |
0 |
0 |
T101 |
5533 |
6 |
0 |
0 |
T130 |
6432 |
14 |
0 |
0 |
T131 |
4188 |
8 |
0 |
0 |
T141 |
42031 |
234 |
0 |
0 |
T142 |
15381 |
24 |
0 |
0 |
T143 |
100628 |
324 |
0 |
0 |
T144 |
8718 |
4 |
0 |
0 |
T145 |
4874 |
1 |
0 |
0 |
T147 |
4697 |
4 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
4882 |
0 |
0 |
T6 |
824003 |
18 |
0 |
0 |
T7 |
117050 |
0 |
0 |
0 |
T8 |
37605 |
0 |
0 |
0 |
T9 |
50294 |
0 |
0 |
0 |
T10 |
659860 |
0 |
0 |
0 |
T11 |
24023 |
0 |
0 |
0 |
T12 |
1485 |
0 |
0 |
0 |
T13 |
462605 |
0 |
0 |
0 |
T14 |
0 |
6 |
0 |
0 |
T18 |
0 |
21 |
0 |
0 |
T22 |
1129 |
0 |
0 |
0 |
T23 |
9179 |
0 |
0 |
0 |
T28 |
0 |
21 |
0 |
0 |
T150 |
0 |
26 |
0 |
0 |
T151 |
0 |
31 |
0 |
0 |
T152 |
0 |
28 |
0 |
0 |
T153 |
0 |
4 |
0 |
0 |
T154 |
0 |
14 |
0 |
0 |
T155 |
0 |
24 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2304 |
0 |
0 |
T73 |
4361 |
18 |
0 |
0 |
T101 |
5533 |
13 |
0 |
0 |
T130 |
6432 |
15 |
0 |
0 |
T131 |
4188 |
8 |
0 |
0 |
T141 |
42031 |
244 |
0 |
0 |
T142 |
15381 |
31 |
0 |
0 |
T143 |
100628 |
189 |
0 |
0 |
T144 |
8718 |
7 |
0 |
0 |
T145 |
4874 |
10 |
0 |
0 |
T147 |
4697 |
1 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2136 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T101 |
5533 |
4 |
0 |
0 |
T130 |
6432 |
5 |
0 |
0 |
T131 |
4188 |
6 |
0 |
0 |
T141 |
42031 |
259 |
0 |
0 |
T142 |
15381 |
16 |
0 |
0 |
T143 |
100628 |
169 |
0 |
0 |
T144 |
8718 |
23 |
0 |
0 |
T145 |
4874 |
5 |
0 |
0 |
T146 |
64735 |
112 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1782 |
0 |
0 |
T73 |
4361 |
21 |
0 |
0 |
T101 |
5533 |
14 |
0 |
0 |
T130 |
6432 |
13 |
0 |
0 |
T131 |
4188 |
2 |
0 |
0 |
T141 |
42031 |
249 |
0 |
0 |
T142 |
15381 |
10 |
0 |
0 |
T143 |
100628 |
122 |
0 |
0 |
T144 |
8718 |
13 |
0 |
0 |
T145 |
4874 |
4 |
0 |
0 |
T146 |
64735 |
80 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1855 |
0 |
0 |
T73 |
4361 |
5 |
0 |
0 |
T101 |
5533 |
12 |
0 |
0 |
T131 |
4188 |
6 |
0 |
0 |
T141 |
42031 |
268 |
0 |
0 |
T142 |
15381 |
26 |
0 |
0 |
T143 |
100628 |
117 |
0 |
0 |
T144 |
8718 |
8 |
0 |
0 |
T145 |
4874 |
4 |
0 |
0 |
T146 |
64735 |
83 |
0 |
0 |
T147 |
4697 |
4 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2028 |
0 |
0 |
T73 |
4361 |
9 |
0 |
0 |
T101 |
5533 |
7 |
0 |
0 |
T130 |
6432 |
11 |
0 |
0 |
T141 |
42031 |
245 |
0 |
0 |
T142 |
15381 |
20 |
0 |
0 |
T143 |
100628 |
142 |
0 |
0 |
T144 |
8718 |
7 |
0 |
0 |
T145 |
4874 |
16 |
0 |
0 |
T146 |
64735 |
61 |
0 |
0 |
T148 |
15212 |
34 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1911 |
0 |
0 |
T73 |
4361 |
10 |
0 |
0 |
T101 |
5533 |
9 |
0 |
0 |
T130 |
6432 |
4 |
0 |
0 |
T131 |
4188 |
2 |
0 |
0 |
T141 |
42031 |
256 |
0 |
0 |
T142 |
15381 |
21 |
0 |
0 |
T143 |
100628 |
131 |
0 |
0 |
T144 |
8718 |
9 |
0 |
0 |
T145 |
4874 |
7 |
0 |
0 |
T146 |
64735 |
88 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
3026 |
0 |
0 |
T73 |
4361 |
15 |
0 |
0 |
T101 |
5533 |
28 |
0 |
0 |
T130 |
6432 |
29 |
0 |
0 |
T131 |
4188 |
10 |
0 |
0 |
T141 |
42031 |
209 |
0 |
0 |
T142 |
15381 |
17 |
0 |
0 |
T143 |
100628 |
308 |
0 |
0 |
T144 |
8718 |
17 |
0 |
0 |
T145 |
4874 |
11 |
0 |
0 |
T147 |
4697 |
8 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1952 |
0 |
0 |
T73 |
4361 |
7 |
0 |
0 |
T101 |
5533 |
11 |
0 |
0 |
T130 |
6432 |
5 |
0 |
0 |
T131 |
4188 |
8 |
0 |
0 |
T141 |
42031 |
263 |
0 |
0 |
T142 |
15381 |
28 |
0 |
0 |
T143 |
100628 |
102 |
0 |
0 |
T144 |
8718 |
9 |
0 |
0 |
T145 |
4874 |
4 |
0 |
0 |
T147 |
4697 |
8 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
3493 |
0 |
0 |
T73 |
4361 |
16 |
0 |
0 |
T101 |
5533 |
27 |
0 |
0 |
T130 |
6432 |
17 |
0 |
0 |
T131 |
4188 |
27 |
0 |
0 |
T141 |
42031 |
238 |
0 |
0 |
T142 |
15381 |
22 |
0 |
0 |
T143 |
100628 |
404 |
0 |
0 |
T144 |
8718 |
15 |
0 |
0 |
T145 |
4874 |
5 |
0 |
0 |
T147 |
4697 |
20 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
2233 |
0 |
0 |
T73 |
4361 |
8 |
0 |
0 |
T101 |
5533 |
1 |
0 |
0 |
T130 |
6432 |
1 |
0 |
0 |
T131 |
4188 |
11 |
0 |
0 |
T141 |
42031 |
242 |
0 |
0 |
T142 |
15381 |
26 |
0 |
0 |
T143 |
100628 |
188 |
0 |
0 |
T144 |
8718 |
10 |
0 |
0 |
T145 |
4874 |
16 |
0 |
0 |
T147 |
4697 |
9 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1935 |
0 |
0 |
T73 |
4361 |
11 |
0 |
0 |
T101 |
5533 |
13 |
0 |
0 |
T131 |
4188 |
5 |
0 |
0 |
T141 |
42031 |
251 |
0 |
0 |
T142 |
15381 |
18 |
0 |
0 |
T143 |
100628 |
105 |
0 |
0 |
T144 |
8718 |
15 |
0 |
0 |
T145 |
4874 |
3 |
0 |
0 |
T146 |
64735 |
77 |
0 |
0 |
T147 |
4697 |
6 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1742 |
0 |
0 |
T73 |
4361 |
13 |
0 |
0 |
T85 |
14966 |
1 |
0 |
0 |
T101 |
5533 |
6 |
0 |
0 |
T141 |
42031 |
223 |
0 |
0 |
T142 |
15381 |
22 |
0 |
0 |
T143 |
100628 |
120 |
0 |
0 |
T144 |
8718 |
5 |
0 |
0 |
T145 |
4874 |
8 |
0 |
0 |
T146 |
64735 |
60 |
0 |
0 |
T147 |
4697 |
4 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1943 |
0 |
0 |
T73 |
4361 |
7 |
0 |
0 |
T101 |
5533 |
5 |
0 |
0 |
T130 |
6432 |
7 |
0 |
0 |
T131 |
4188 |
6 |
0 |
0 |
T141 |
42031 |
282 |
0 |
0 |
T142 |
15381 |
25 |
0 |
0 |
T143 |
100628 |
103 |
0 |
0 |
T144 |
8718 |
1 |
0 |
0 |
T145 |
4874 |
6 |
0 |
0 |
T146 |
64735 |
66 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1979 |
0 |
0 |
T73 |
4361 |
16 |
0 |
0 |
T101 |
5533 |
14 |
0 |
0 |
T130 |
6432 |
6 |
0 |
0 |
T131 |
4188 |
8 |
0 |
0 |
T141 |
42031 |
294 |
0 |
0 |
T142 |
15381 |
32 |
0 |
0 |
T143 |
100628 |
135 |
0 |
0 |
T144 |
8718 |
5 |
0 |
0 |
T145 |
4874 |
3 |
0 |
0 |
T147 |
4697 |
6 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1931 |
0 |
0 |
T73 |
4361 |
14 |
0 |
0 |
T101 |
5533 |
8 |
0 |
0 |
T130 |
6432 |
4 |
0 |
0 |
T131 |
4188 |
1 |
0 |
0 |
T141 |
42031 |
242 |
0 |
0 |
T142 |
15381 |
23 |
0 |
0 |
T143 |
100628 |
127 |
0 |
0 |
T144 |
8718 |
5 |
0 |
0 |
T145 |
4874 |
13 |
0 |
0 |
T146 |
64735 |
74 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
376052860 |
1915 |
0 |
0 |
T73 |
4361 |
17 |
0 |
0 |
T101 |
5533 |
10 |
0 |
0 |
T130 |
6432 |
9 |
0 |
0 |
T141 |
42031 |
229 |
0 |
0 |
T142 |
15381 |
22 |
0 |
0 |
T143 |
100628 |
123 |
0 |
0 |
T144 |
8718 |
16 |
0 |
0 |
T145 |
4874 |
5 |
0 |
0 |
T146 |
64735 |
67 |
0 |
0 |
T148 |
15212 |
15 |
0 |
0 |